camss-ispif.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * camss-ispif.c
   4 *
   5 * Qualcomm MSM Camera Subsystem - ISPIF (ISP Interface) Module
   6 *
   7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   8 * Copyright (C) 2015-2018 Linaro Ltd.
   9 */
  10#include <linux/clk.h>
  11#include <linux/completion.h>
  12#include <linux/interrupt.h>
  13#include <linux/io.h>
  14#include <linux/iopoll.h>
  15#include <linux/kernel.h>
  16#include <linux/mutex.h>
  17#include <linux/platform_device.h>
  18#include <linux/pm_runtime.h>
  19#include <media/media-entity.h>
  20#include <media/v4l2-device.h>
  21#include <media/v4l2-subdev.h>
  22
  23#include "camss-ispif.h"
  24#include "camss.h"
  25
  26#define MSM_ISPIF_NAME "msm_ispif"
  27
  28#define ISPIF_RST_CMD_0			0x008
  29#define ISPIF_RST_CMD_1			0x00c
  30#define ISPIF_RST_CMD_0_STROBED_RST_EN		(1 << 0)
  31#define ISPIF_RST_CMD_0_MISC_LOGIC_RST		(1 << 1)
  32#define ISPIF_RST_CMD_0_SW_REG_RST		(1 << 2)
  33#define ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST	(1 << 3)
  34#define ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST	(1 << 4)
  35#define ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST	(1 << 5)
  36#define ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST	(1 << 6)
  37#define ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST	(1 << 7)
  38#define ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST	(1 << 8)
  39#define ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST	(1 << 9)
  40#define ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST	(1 << 10)
  41#define ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST	(1 << 11)
  42#define ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST	(1 << 12)
  43#define ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST	(1 << 16)
  44#define ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST	(1 << 17)
  45#define ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST	(1 << 18)
  46#define ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST	(1 << 19)
  47#define ISPIF_IRQ_GLOBAL_CLEAR_CMD	0x01c
  48#define ISPIF_VFE_m_CTRL_0(m)		(0x200 + 0x200 * (m))
  49#define ISPIF_VFE_m_CTRL_0_PIX0_LINE_BUF_EN	(1 << 6)
  50#define ISPIF_VFE_m_IRQ_MASK_0(m)	(0x208 + 0x200 * (m))
  51#define ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE	0x00001249
  52#define ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK	0x00001fff
  53#define ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE	0x02492000
  54#define ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK	0x03ffe000
  55#define ISPIF_VFE_m_IRQ_MASK_1(m)	(0x20c + 0x200 * (m))
  56#define ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE	0x00001249
  57#define ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK	0x00001fff
  58#define ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE	0x02492000
  59#define ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK	0x03ffe000
  60#define ISPIF_VFE_m_IRQ_MASK_2(m)	(0x210 + 0x200 * (m))
  61#define ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE	0x00001249
  62#define ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK	0x00001fff
  63#define ISPIF_VFE_m_IRQ_STATUS_0(m)	(0x21c + 0x200 * (m))
  64#define ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW	(1 << 12)
  65#define ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW	(1 << 25)
  66#define ISPIF_VFE_m_IRQ_STATUS_1(m)	(0x220 + 0x200 * (m))
  67#define ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW	(1 << 12)
  68#define ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW	(1 << 25)
  69#define ISPIF_VFE_m_IRQ_STATUS_2(m)	(0x224 + 0x200 * (m))
  70#define ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW	(1 << 12)
  71#define ISPIF_VFE_m_IRQ_CLEAR_0(m)	(0x230 + 0x200 * (m))
  72#define ISPIF_VFE_m_IRQ_CLEAR_1(m)	(0x234 + 0x200 * (m))
  73#define ISPIF_VFE_m_IRQ_CLEAR_2(m)	(0x238 + 0x200 * (m))
  74#define ISPIF_VFE_m_INTF_INPUT_SEL(m)	(0x244 + 0x200 * (m))
  75#define ISPIF_VFE_m_INTF_CMD_0(m)	(0x248 + 0x200 * (m))
  76#define ISPIF_VFE_m_INTF_CMD_1(m)	(0x24c + 0x200 * (m))
  77#define ISPIF_VFE_m_PIX_INTF_n_CID_MASK(m, n)	\
  78					(0x254 + 0x200 * (m) + 0x4 * (n))
  79#define ISPIF_VFE_m_RDI_INTF_n_CID_MASK(m, n)	\
  80					(0x264 + 0x200 * (m) + 0x4 * (n))
  81/* PACK_CFG registers are 8x96 only */
  82#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(m, n)	\
  83					(0x270 + 0x200 * (m) + 0x4 * (n))
  84#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(m, n)	\
  85					(0x27c + 0x200 * (m) + 0x4 * (n))
  86#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(c)	\
  87					(1 << ((cid % 8) * 4))
  88#define ISPIF_VFE_m_PIX_INTF_n_STATUS(m, n)	\
  89					(0x2c0 + 0x200 * (m) + 0x4 * (n))
  90#define ISPIF_VFE_m_RDI_INTF_n_STATUS(m, n)	\
  91					(0x2d0 + 0x200 * (m) + 0x4 * (n))
  92
  93#define CSI_PIX_CLK_MUX_SEL		0x000
  94#define CSI_RDI_CLK_MUX_SEL		0x008
  95
  96#define ISPIF_TIMEOUT_SLEEP_US		1000
  97#define ISPIF_TIMEOUT_ALL_US		1000000
  98#define ISPIF_RESET_TIMEOUT_MS		500
  99
 100enum ispif_intf_cmd {
 101	CMD_DISABLE_FRAME_BOUNDARY = 0x0,
 102	CMD_ENABLE_FRAME_BOUNDARY = 0x1,
 103	CMD_DISABLE_IMMEDIATELY = 0x2,
 104	CMD_ALL_DISABLE_IMMEDIATELY = 0xaaaaaaaa,
 105	CMD_ALL_NO_CHANGE = 0xffffffff,
 106};
 107
 108static const u32 ispif_formats_8x16[] = {
 109	MEDIA_BUS_FMT_UYVY8_1X16,
 110	MEDIA_BUS_FMT_VYUY8_1X16,
 111	MEDIA_BUS_FMT_YUYV8_1X16,
 112	MEDIA_BUS_FMT_YVYU8_1X16,
 113	MEDIA_BUS_FMT_SBGGR8_1X8,
 114	MEDIA_BUS_FMT_SGBRG8_1X8,
 115	MEDIA_BUS_FMT_SGRBG8_1X8,
 116	MEDIA_BUS_FMT_SRGGB8_1X8,
 117	MEDIA_BUS_FMT_SBGGR10_1X10,
 118	MEDIA_BUS_FMT_SGBRG10_1X10,
 119	MEDIA_BUS_FMT_SGRBG10_1X10,
 120	MEDIA_BUS_FMT_SRGGB10_1X10,
 121	MEDIA_BUS_FMT_SBGGR12_1X12,
 122	MEDIA_BUS_FMT_SGBRG12_1X12,
 123	MEDIA_BUS_FMT_SGRBG12_1X12,
 124	MEDIA_BUS_FMT_SRGGB12_1X12,
 125	MEDIA_BUS_FMT_Y10_1X10,
 126};
 127
 128static const u32 ispif_formats_8x96[] = {
 129	MEDIA_BUS_FMT_UYVY8_1X16,
 130	MEDIA_BUS_FMT_VYUY8_1X16,
 131	MEDIA_BUS_FMT_YUYV8_1X16,
 132	MEDIA_BUS_FMT_YVYU8_1X16,
 133	MEDIA_BUS_FMT_SBGGR8_1X8,
 134	MEDIA_BUS_FMT_SGBRG8_1X8,
 135	MEDIA_BUS_FMT_SGRBG8_1X8,
 136	MEDIA_BUS_FMT_SRGGB8_1X8,
 137	MEDIA_BUS_FMT_SBGGR10_1X10,
 138	MEDIA_BUS_FMT_SGBRG10_1X10,
 139	MEDIA_BUS_FMT_SGRBG10_1X10,
 140	MEDIA_BUS_FMT_SRGGB10_1X10,
 141	MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
 142	MEDIA_BUS_FMT_SBGGR12_1X12,
 143	MEDIA_BUS_FMT_SGBRG12_1X12,
 144	MEDIA_BUS_FMT_SGRBG12_1X12,
 145	MEDIA_BUS_FMT_SRGGB12_1X12,
 146	MEDIA_BUS_FMT_SBGGR14_1X14,
 147	MEDIA_BUS_FMT_SGBRG14_1X14,
 148	MEDIA_BUS_FMT_SGRBG14_1X14,
 149	MEDIA_BUS_FMT_SRGGB14_1X14,
 150	MEDIA_BUS_FMT_Y10_1X10,
 151	MEDIA_BUS_FMT_Y10_2X8_PADHI_LE,
 152};
 153
 154/*
 155 * ispif_isr_8x96 - ISPIF module interrupt handler for 8x96
 156 * @irq: Interrupt line
 157 * @dev: ISPIF device
 158 *
 159 * Return IRQ_HANDLED on success
 160 */
 161static irqreturn_t ispif_isr_8x96(int irq, void *dev)
 162{
 163	struct ispif_device *ispif = dev;
 164	struct camss *camss = ispif->camss;
 165	u32 value0, value1, value2, value3, value4, value5;
 166
 167	value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0));
 168	value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0));
 169	value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0));
 170	value3 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(1));
 171	value4 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(1));
 172	value5 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(1));
 173
 174	writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
 175	writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
 176	writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
 177	writel_relaxed(value3, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(1));
 178	writel_relaxed(value4, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(1));
 179	writel_relaxed(value5, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(1));
 180
 181	writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
 182
 183	if ((value0 >> 27) & 0x1)
 184		complete(&ispif->reset_complete[0]);
 185
 186	if ((value3 >> 27) & 0x1)
 187		complete(&ispif->reset_complete[1]);
 188
 189	if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
 190		dev_err_ratelimited(camss->dev, "VFE0 pix0 overflow\n");
 191
 192	if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
 193		dev_err_ratelimited(camss->dev, "VFE0 rdi0 overflow\n");
 194
 195	if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
 196		dev_err_ratelimited(camss->dev, "VFE0 pix1 overflow\n");
 197
 198	if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
 199		dev_err_ratelimited(camss->dev, "VFE0 rdi1 overflow\n");
 200
 201	if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
 202		dev_err_ratelimited(camss->dev, "VFE0 rdi2 overflow\n");
 203
 204	if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
 205		dev_err_ratelimited(camss->dev, "VFE1 pix0 overflow\n");
 206
 207	if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
 208		dev_err_ratelimited(camss->dev, "VFE1 rdi0 overflow\n");
 209
 210	if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
 211		dev_err_ratelimited(camss->dev, "VFE1 pix1 overflow\n");
 212
 213	if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
 214		dev_err_ratelimited(camss->dev, "VFE1 rdi1 overflow\n");
 215
 216	if (unlikely(value5 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
 217		dev_err_ratelimited(camss->dev, "VFE1 rdi2 overflow\n");
 218
 219	return IRQ_HANDLED;
 220}
 221
 222/*
 223 * ispif_isr_8x16 - ISPIF module interrupt handler for 8x16
 224 * @irq: Interrupt line
 225 * @dev: ISPIF device
 226 *
 227 * Return IRQ_HANDLED on success
 228 */
 229static irqreturn_t ispif_isr_8x16(int irq, void *dev)
 230{
 231	struct ispif_device *ispif = dev;
 232	struct camss *camss = ispif->camss;
 233	u32 value0, value1, value2;
 234
 235	value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0));
 236	value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0));
 237	value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0));
 238
 239	writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
 240	writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
 241	writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
 242
 243	writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
 244
 245	if ((value0 >> 27) & 0x1)
 246		complete(&ispif->reset_complete[0]);
 247
 248	if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
 249		dev_err_ratelimited(camss->dev, "VFE0 pix0 overflow\n");
 250
 251	if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
 252		dev_err_ratelimited(camss->dev, "VFE0 rdi0 overflow\n");
 253
 254	if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
 255		dev_err_ratelimited(camss->dev, "VFE0 pix1 overflow\n");
 256
 257	if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
 258		dev_err_ratelimited(camss->dev, "VFE0 rdi1 overflow\n");
 259
 260	if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
 261		dev_err_ratelimited(camss->dev, "VFE0 rdi2 overflow\n");
 262
 263	return IRQ_HANDLED;
 264}
 265
 266static int ispif_vfe_reset(struct ispif_device *ispif, u8 vfe_id)
 267{
 268	struct camss *camss = ispif->camss;
 269
 270	unsigned long time;
 271	u32 val;
 272
 273	if (vfe_id >= camss->res->vfe_num) {
 274		dev_err(camss->dev,
 275			"Error: asked reset for invalid VFE%d\n", vfe_id);
 276		return -ENOENT;
 277	}
 278
 279	reinit_completion(&ispif->reset_complete[vfe_id]);
 280
 281	val = ISPIF_RST_CMD_0_STROBED_RST_EN |
 282		ISPIF_RST_CMD_0_MISC_LOGIC_RST |
 283		ISPIF_RST_CMD_0_SW_REG_RST |
 284		ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST |
 285		ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST |
 286		ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST |
 287		ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST |
 288		ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST |
 289		ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST |
 290		ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST |
 291		ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST |
 292		ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST |
 293		ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST |
 294		ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST |
 295		ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST |
 296		ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST |
 297		ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST;
 298
 299	if (vfe_id == 1)
 300		writel_relaxed(val, ispif->base + ISPIF_RST_CMD_1);
 301	else
 302		writel_relaxed(val, ispif->base + ISPIF_RST_CMD_0);
 303
 304	time = wait_for_completion_timeout(&ispif->reset_complete[vfe_id],
 305		msecs_to_jiffies(ISPIF_RESET_TIMEOUT_MS));
 306	if (!time) {
 307		dev_err(camss->dev,
 308			"ISPIF for VFE%d reset timeout\n", vfe_id);
 309		return -EIO;
 310	}
 311
 312	return 0;
 313}
 314
 315/*
 316 * ispif_reset - Trigger reset on ISPIF module and wait to complete
 317 * @ispif: ISPIF device
 318 *
 319 * Return 0 on success or a negative error code otherwise
 320 */
 321static int ispif_reset(struct ispif_device *ispif, u8 vfe_id)
 322{
 323	struct camss *camss = ispif->camss;
 324	int ret;
 325
 326	ret = camss_pm_domain_on(camss, PM_DOMAIN_VFE0);
 327	if (ret < 0)
 328		return ret;
 329
 330	ret = camss_pm_domain_on(camss, PM_DOMAIN_VFE1);
 331	if (ret < 0)
 332		return ret;
 333
 334	ret = camss_enable_clocks(ispif->nclocks_for_reset,
 335				  ispif->clock_for_reset,
 336				  camss->dev);
 337	if (ret < 0)
 338		return ret;
 339
 340	ret = ispif_vfe_reset(ispif, vfe_id);
 341	if (ret)
 342		dev_dbg(camss->dev, "ISPIF Reset failed\n");
 343
 344	camss_disable_clocks(ispif->nclocks_for_reset, ispif->clock_for_reset);
 345
 346	camss_pm_domain_off(camss, PM_DOMAIN_VFE0);
 347	camss_pm_domain_off(camss, PM_DOMAIN_VFE1);
 348
 349	return ret;
 350}
 351
 352/*
 353 * ispif_set_power - Power on/off ISPIF module
 354 * @sd: ISPIF V4L2 subdevice
 355 * @on: Requested power state
 356 *
 357 * Return 0 on success or a negative error code otherwise
 358 */
 359static int ispif_set_power(struct v4l2_subdev *sd, int on)
 360{
 361	struct ispif_line *line = v4l2_get_subdevdata(sd);
 362	struct ispif_device *ispif = line->ispif;
 363	struct device *dev = ispif->camss->dev;
 364	int ret = 0;
 365
 366	mutex_lock(&ispif->power_lock);
 367
 368	if (on) {
 369		if (ispif->power_count) {
 370			/* Power is already on */
 371			ispif->power_count++;
 372			goto exit;
 373		}
 374
 375		ret = pm_runtime_resume_and_get(dev);
 376		if (ret < 0)
 377			goto exit;
 378
 379		ret = camss_enable_clocks(ispif->nclocks, ispif->clock, dev);
 380		if (ret < 0) {
 381			pm_runtime_put_sync(dev);
 382			goto exit;
 383		}
 384
 385		ret = ispif_reset(ispif, line->vfe_id);
 386		if (ret < 0) {
 387			pm_runtime_put_sync(dev);
 388			camss_disable_clocks(ispif->nclocks, ispif->clock);
 389			goto exit;
 390		}
 391
 392		ispif->intf_cmd[line->vfe_id].cmd_0 = CMD_ALL_NO_CHANGE;
 393		ispif->intf_cmd[line->vfe_id].cmd_1 = CMD_ALL_NO_CHANGE;
 394
 395		ispif->power_count++;
 396	} else {
 397		if (ispif->power_count == 0) {
 398			dev_err(dev, "ispif power off on power_count == 0\n");
 399			goto exit;
 400		} else if (ispif->power_count == 1) {
 401			camss_disable_clocks(ispif->nclocks, ispif->clock);
 402			pm_runtime_put_sync(dev);
 403		}
 404
 405		ispif->power_count--;
 406	}
 407
 408exit:
 409	mutex_unlock(&ispif->power_lock);
 410
 411	return ret;
 412}
 413
 414/*
 415 * ispif_select_clk_mux - Select clock for PIX/RDI interface
 416 * @ispif: ISPIF device
 417 * @intf: VFE interface
 418 * @csid: CSID HW module id
 419 * @vfe: VFE HW module id
 420 * @enable: enable or disable the selected clock
 421 */
 422static void ispif_select_clk_mux(struct ispif_device *ispif,
 423				 enum ispif_intf intf, u8 csid,
 424				 u8 vfe, u8 enable)
 425{
 426	u32 val;
 427
 428	switch (intf) {
 429	case PIX0:
 430		val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
 431		val &= ~(0xf << (vfe * 8));
 432		if (enable)
 433			val |= (csid << (vfe * 8));
 434		writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
 435		break;
 436
 437	case RDI0:
 438		val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
 439		val &= ~(0xf << (vfe * 12));
 440		if (enable)
 441			val |= (csid << (vfe * 12));
 442		writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
 443		break;
 444
 445	case PIX1:
 446		val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
 447		val &= ~(0xf << (4 + (vfe * 8)));
 448		if (enable)
 449			val |= (csid << (4 + (vfe * 8)));
 450		writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
 451		break;
 452
 453	case RDI1:
 454		val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
 455		val &= ~(0xf << (4 + (vfe * 12)));
 456		if (enable)
 457			val |= (csid << (4 + (vfe * 12)));
 458		writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
 459		break;
 460
 461	case RDI2:
 462		val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
 463		val &= ~(0xf << (8 + (vfe * 12)));
 464		if (enable)
 465			val |= (csid << (8 + (vfe * 12)));
 466		writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
 467		break;
 468	}
 469
 470	mb();
 471}
 472
 473/*
 474 * ispif_validate_intf_status - Validate current status of PIX/RDI interface
 475 * @ispif: ISPIF device
 476 * @intf: VFE interface
 477 * @vfe: VFE HW module id
 478 *
 479 * Return 0 when interface is idle or -EBUSY otherwise
 480 */
 481static int ispif_validate_intf_status(struct ispif_device *ispif,
 482				      enum ispif_intf intf, u8 vfe)
 483{
 484	int ret = 0;
 485	u32 val = 0;
 486
 487	switch (intf) {
 488	case PIX0:
 489		val = readl_relaxed(ispif->base +
 490			ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0));
 491		break;
 492	case RDI0:
 493		val = readl_relaxed(ispif->base +
 494			ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0));
 495		break;
 496	case PIX1:
 497		val = readl_relaxed(ispif->base +
 498			ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1));
 499		break;
 500	case RDI1:
 501		val = readl_relaxed(ispif->base +
 502			ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1));
 503		break;
 504	case RDI2:
 505		val = readl_relaxed(ispif->base +
 506			ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2));
 507		break;
 508	}
 509
 510	if ((val & 0xf) != 0xf) {
 511		dev_err(ispif->camss->dev, "%s: ispif is busy: 0x%x\n",
 512			__func__, val);
 513		ret = -EBUSY;
 514	}
 515
 516	return ret;
 517}
 518
 519/*
 520 * ispif_wait_for_stop - Wait for PIX/RDI interface to stop
 521 * @ispif: ISPIF device
 522 * @intf: VFE interface
 523 * @vfe: VFE HW module id
 524 *
 525 * Return 0 on success or a negative error code otherwise
 526 */
 527static int ispif_wait_for_stop(struct ispif_device *ispif,
 528			       enum ispif_intf intf, u8 vfe)
 529{
 530	u32 addr = 0;
 531	u32 stop_flag = 0;
 532	int ret;
 533
 534	switch (intf) {
 535	case PIX0:
 536		addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0);
 537		break;
 538	case RDI0:
 539		addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0);
 540		break;
 541	case PIX1:
 542		addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1);
 543		break;
 544	case RDI1:
 545		addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1);
 546		break;
 547	case RDI2:
 548		addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2);
 549		break;
 550	}
 551
 552	ret = readl_poll_timeout(ispif->base + addr,
 553				 stop_flag,
 554				 (stop_flag & 0xf) == 0xf,
 555				 ISPIF_TIMEOUT_SLEEP_US,
 556				 ISPIF_TIMEOUT_ALL_US);
 557	if (ret < 0)
 558		dev_err(ispif->camss->dev, "%s: ispif stop timeout\n",
 559			__func__);
 560
 561	return ret;
 562}
 563
 564/*
 565 * ispif_select_csid - Select CSID HW module for input from
 566 * @ispif: ISPIF device
 567 * @intf: VFE interface
 568 * @csid: CSID HW module id
 569 * @vfe: VFE HW module id
 570 * @enable: enable or disable the selected input
 571 */
 572static void ispif_select_csid(struct ispif_device *ispif, enum ispif_intf intf,
 573			      u8 csid, u8 vfe, u8 enable)
 574{
 575	u32 val;
 576
 577	val = readl_relaxed(ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));
 578	switch (intf) {
 579	case PIX0:
 580		val &= ~(BIT(1) | BIT(0));
 581		if (enable)
 582			val |= csid;
 583		break;
 584	case RDI0:
 585		val &= ~(BIT(5) | BIT(4));
 586		if (enable)
 587			val |= (csid << 4);
 588		break;
 589	case PIX1:
 590		val &= ~(BIT(9) | BIT(8));
 591		if (enable)
 592			val |= (csid << 8);
 593		break;
 594	case RDI1:
 595		val &= ~(BIT(13) | BIT(12));
 596		if (enable)
 597			val |= (csid << 12);
 598		break;
 599	case RDI2:
 600		val &= ~(BIT(21) | BIT(20));
 601		if (enable)
 602			val |= (csid << 20);
 603		break;
 604	}
 605
 606	writel(val, ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));
 607}
 608
 609/*
 610 * ispif_select_cid - Enable/disable desired CID
 611 * @ispif: ISPIF device
 612 * @intf: VFE interface
 613 * @cid: desired CID to enable/disable
 614 * @vfe: VFE HW module id
 615 * @enable: enable or disable the desired CID
 616 */
 617static void ispif_select_cid(struct ispif_device *ispif, enum ispif_intf intf,
 618			     u8 cid, u8 vfe, u8 enable)
 619{
 620	u32 cid_mask = 1 << cid;
 621	u32 addr = 0;
 622	u32 val;
 623
 624	switch (intf) {
 625	case PIX0:
 626		addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 0);
 627		break;
 628	case RDI0:
 629		addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 0);
 630		break;
 631	case PIX1:
 632		addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 1);
 633		break;
 634	case RDI1:
 635		addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 1);
 636		break;
 637	case RDI2:
 638		addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 2);
 639		break;
 640	}
 641
 642	val = readl_relaxed(ispif->base + addr);
 643	if (enable)
 644		val |= cid_mask;
 645	else
 646		val &= ~cid_mask;
 647
 648	writel(val, ispif->base + addr);
 649}
 650
 651/*
 652 * ispif_config_irq - Enable/disable interrupts for PIX/RDI interface
 653 * @ispif: ISPIF device
 654 * @intf: VFE interface
 655 * @vfe: VFE HW module id
 656 * @enable: enable or disable
 657 */
 658static void ispif_config_irq(struct ispif_device *ispif, enum ispif_intf intf,
 659			     u8 vfe, u8 enable)
 660{
 661	u32 val;
 662
 663	switch (intf) {
 664	case PIX0:
 665		val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
 666		val &= ~ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK;
 667		if (enable)
 668			val |= ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE;
 669		writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
 670		writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE,
 671			       ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));
 672		break;
 673	case RDI0:
 674		val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
 675		val &= ~ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK;
 676		if (enable)
 677			val |= ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE;
 678		writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
 679		writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE,
 680			       ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));
 681		break;
 682	case PIX1:
 683		val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
 684		val &= ~ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK;
 685		if (enable)
 686			val |= ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE;
 687		writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
 688		writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE,
 689			       ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));
 690		break;
 691	case RDI1:
 692		val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
 693		val &= ~ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK;
 694		if (enable)
 695			val |= ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE;
 696		writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
 697		writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE,
 698			       ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));
 699		break;
 700	case RDI2:
 701		val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));
 702		val &= ~ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK;
 703		if (enable)
 704			val |= ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE;
 705		writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));
 706		writel_relaxed(ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE,
 707			       ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(vfe));
 708		break;
 709	}
 710
 711	writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
 712}
 713
 714/*
 715 * ispif_config_pack - Config packing for PRDI mode
 716 * @ispif: ISPIF device
 717 * @code: media bus format code
 718 * @intf: VFE interface
 719 * @cid: desired CID to handle
 720 * @vfe: VFE HW module id
 721 * @enable: enable or disable
 722 */
 723static void ispif_config_pack(struct ispif_device *ispif, u32 code,
 724			      enum ispif_intf intf, u8 cid, u8 vfe, u8 enable)
 725{
 726	u32 addr, val;
 727
 728	if (code != MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE &&
 729	    code != MEDIA_BUS_FMT_Y10_2X8_PADHI_LE)
 730		return;
 731
 732	switch (intf) {
 733	case RDI0:
 734		if (cid < 8)
 735			addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 0);
 736		else
 737			addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 0);
 738		break;
 739	case RDI1:
 740		if (cid < 8)
 741			addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 1);
 742		else
 743			addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 1);
 744		break;
 745	case RDI2:
 746		if (cid < 8)
 747			addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 2);
 748		else
 749			addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 2);
 750		break;
 751	default:
 752		return;
 753	}
 754
 755	if (enable)
 756		val = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(cid);
 757	else
 758		val = 0;
 759
 760	writel_relaxed(val, ispif->base + addr);
 761}
 762
 763/*
 764 * ispif_set_intf_cmd - Set command to enable/disable interface
 765 * @ispif: ISPIF device
 766 * @cmd: interface command
 767 * @intf: VFE interface
 768 * @vfe: VFE HW module id
 769 * @vc: virtual channel
 770 */
 771static void ispif_set_intf_cmd(struct ispif_device *ispif, u8 cmd,
 772			       enum ispif_intf intf, u8 vfe, u8 vc)
 773{
 774	u32 *val;
 775
 776	if (intf == RDI2) {
 777		val = &ispif->intf_cmd[vfe].cmd_1;
 778		*val &= ~(0x3 << (vc * 2 + 8));
 779		*val |= (cmd << (vc * 2 + 8));
 780		wmb();
 781		writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_1(vfe));
 782		wmb();
 783	} else {
 784		val = &ispif->intf_cmd[vfe].cmd_0;
 785		*val &= ~(0x3 << (vc * 2 + intf * 8));
 786		*val |= (cmd << (vc * 2 + intf * 8));
 787		wmb();
 788		writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_0(vfe));
 789		wmb();
 790	}
 791}
 792
 793/*
 794 * ispif_set_stream - Enable/disable streaming on ISPIF module
 795 * @sd: ISPIF V4L2 subdevice
 796 * @enable: Requested streaming state
 797 *
 798 * Main configuration of ISPIF module is also done here.
 799 *
 800 * Return 0 on success or a negative error code otherwise
 801 */
 802static int ispif_set_stream(struct v4l2_subdev *sd, int enable)
 803{
 804	struct ispif_line *line = v4l2_get_subdevdata(sd);
 805	struct ispif_device *ispif = line->ispif;
 806	struct camss *camss = ispif->camss;
 807	enum ispif_intf intf = line->interface;
 808	u8 csid = line->csid_id;
 809	u8 vfe = line->vfe_id;
 810	u8 vc = 0; /* Virtual Channel 0 */
 811	u8 cid = vc * 4; /* id of Virtual Channel and Data Type set */
 812	int ret;
 813
 814	if (enable) {
 815		if (!media_pad_remote_pad_first(&line->pads[MSM_ISPIF_PAD_SINK]))
 816			return -ENOLINK;
 817
 818		/* Config */
 819
 820		mutex_lock(&ispif->config_lock);
 821		ispif_select_clk_mux(ispif, intf, csid, vfe, 1);
 822
 823		ret = ispif_validate_intf_status(ispif, intf, vfe);
 824		if (ret < 0) {
 825			mutex_unlock(&ispif->config_lock);
 826			return ret;
 827		}
 828
 829		ispif_select_csid(ispif, intf, csid, vfe, 1);
 830		ispif_select_cid(ispif, intf, cid, vfe, 1);
 831		ispif_config_irq(ispif, intf, vfe, 1);
 832		if (camss->res->version == CAMSS_8x96 ||
 833		    camss->res->version == CAMSS_8x53 ||
 834		    camss->res->version == CAMSS_660)
 835			ispif_config_pack(ispif,
 836					  line->fmt[MSM_ISPIF_PAD_SINK].code,
 837					  intf, cid, vfe, 1);
 838		ispif_set_intf_cmd(ispif, CMD_ENABLE_FRAME_BOUNDARY,
 839				   intf, vfe, vc);
 840	} else {
 841		mutex_lock(&ispif->config_lock);
 842		ispif_set_intf_cmd(ispif, CMD_DISABLE_FRAME_BOUNDARY,
 843				   intf, vfe, vc);
 844		mutex_unlock(&ispif->config_lock);
 845
 846		ret = ispif_wait_for_stop(ispif, intf, vfe);
 847		if (ret < 0)
 848			return ret;
 849
 850		mutex_lock(&ispif->config_lock);
 851		if (camss->res->version == CAMSS_8x96 ||
 852		    camss->res->version == CAMSS_8x53 ||
 853		    camss->res->version == CAMSS_660)
 854			ispif_config_pack(ispif,
 855					  line->fmt[MSM_ISPIF_PAD_SINK].code,
 856					  intf, cid, vfe, 0);
 857		ispif_config_irq(ispif, intf, vfe, 0);
 858		ispif_select_cid(ispif, intf, cid, vfe, 0);
 859		ispif_select_csid(ispif, intf, csid, vfe, 0);
 860		ispif_select_clk_mux(ispif, intf, csid, vfe, 0);
 861	}
 862
 863	mutex_unlock(&ispif->config_lock);
 864
 865	return 0;
 866}
 867
 868/*
 869 * __ispif_get_format - Get pointer to format structure
 870 * @ispif: ISPIF line
 871 * @sd_state: V4L2 subdev state
 872 * @pad: pad from which format is requested
 873 * @which: TRY or ACTIVE format
 874 *
 875 * Return pointer to TRY or ACTIVE format structure
 876 */
 877static struct v4l2_mbus_framefmt *
 878__ispif_get_format(struct ispif_line *line,
 879		   struct v4l2_subdev_state *sd_state,
 880		   unsigned int pad,
 881		   enum v4l2_subdev_format_whence which)
 882{
 883	if (which == V4L2_SUBDEV_FORMAT_TRY)
 884		return v4l2_subdev_state_get_format(sd_state, pad);
 885
 886	return &line->fmt[pad];
 887}
 888
 889/*
 890 * ispif_try_format - Handle try format by pad subdev method
 891 * @ispif: ISPIF line
 892 * @sd_state: V4L2 subdev state
 893 * @pad: pad on which format is requested
 894 * @fmt: pointer to v4l2 format structure
 895 * @which: wanted subdev format
 896 */
 897static void ispif_try_format(struct ispif_line *line,
 898			     struct v4l2_subdev_state *sd_state,
 899			     unsigned int pad,
 900			     struct v4l2_mbus_framefmt *fmt,
 901			     enum v4l2_subdev_format_whence which)
 902{
 903	unsigned int i;
 904
 905	switch (pad) {
 906	case MSM_ISPIF_PAD_SINK:
 907		/* Set format on sink pad */
 908
 909		for (i = 0; i < line->nformats; i++)
 910			if (fmt->code == line->formats[i])
 911				break;
 912
 913		/* If not found, use UYVY as default */
 914		if (i >= line->nformats)
 915			fmt->code = MEDIA_BUS_FMT_UYVY8_1X16;
 916
 917		fmt->width = clamp_t(u32, fmt->width, 1, 8191);
 918		fmt->height = clamp_t(u32, fmt->height, 1, 8191);
 919
 920		fmt->field = V4L2_FIELD_NONE;
 921		fmt->colorspace = V4L2_COLORSPACE_SRGB;
 922
 923		break;
 924
 925	case MSM_ISPIF_PAD_SRC:
 926		/* Set and return a format same as sink pad */
 927
 928		*fmt = *__ispif_get_format(line, sd_state, MSM_ISPIF_PAD_SINK,
 929					   which);
 930
 931		break;
 932	}
 933
 934	fmt->colorspace = V4L2_COLORSPACE_SRGB;
 935}
 936
 937/*
 938 * ispif_enum_mbus_code - Handle pixel format enumeration
 939 * @sd: ISPIF V4L2 subdevice
 940 * @sd_state: V4L2 subdev state
 941 * @code: pointer to v4l2_subdev_mbus_code_enum structure
 942 * return -EINVAL or zero on success
 943 */
 944static int ispif_enum_mbus_code(struct v4l2_subdev *sd,
 945				struct v4l2_subdev_state *sd_state,
 946				struct v4l2_subdev_mbus_code_enum *code)
 947{
 948	struct ispif_line *line = v4l2_get_subdevdata(sd);
 949	struct v4l2_mbus_framefmt *format;
 950
 951	if (code->pad == MSM_ISPIF_PAD_SINK) {
 952		if (code->index >= line->nformats)
 953			return -EINVAL;
 954
 955		code->code = line->formats[code->index];
 956	} else {
 957		if (code->index > 0)
 958			return -EINVAL;
 959
 960		format = __ispif_get_format(line, sd_state,
 961					    MSM_ISPIF_PAD_SINK,
 962					    code->which);
 963
 964		code->code = format->code;
 965	}
 966
 967	return 0;
 968}
 969
 970/*
 971 * ispif_enum_frame_size - Handle frame size enumeration
 972 * @sd: ISPIF V4L2 subdevice
 973 * @sd_state: V4L2 subdev state
 974 * @fse: pointer to v4l2_subdev_frame_size_enum structure
 975 * return -EINVAL or zero on success
 976 */
 977static int ispif_enum_frame_size(struct v4l2_subdev *sd,
 978				 struct v4l2_subdev_state *sd_state,
 979				 struct v4l2_subdev_frame_size_enum *fse)
 980{
 981	struct ispif_line *line = v4l2_get_subdevdata(sd);
 982	struct v4l2_mbus_framefmt format;
 983
 984	if (fse->index != 0)
 985		return -EINVAL;
 986
 987	format.code = fse->code;
 988	format.width = 1;
 989	format.height = 1;
 990	ispif_try_format(line, sd_state, fse->pad, &format, fse->which);
 991	fse->min_width = format.width;
 992	fse->min_height = format.height;
 993
 994	if (format.code != fse->code)
 995		return -EINVAL;
 996
 997	format.code = fse->code;
 998	format.width = -1;
 999	format.height = -1;
1000	ispif_try_format(line, sd_state, fse->pad, &format, fse->which);
1001	fse->max_width = format.width;
1002	fse->max_height = format.height;
1003
1004	return 0;
1005}
1006
1007/*
1008 * ispif_get_format - Handle get format by pads subdev method
1009 * @sd: ISPIF V4L2 subdevice
1010 * @sd_state: V4L2 subdev state
1011 * @fmt: pointer to v4l2 subdev format structure
1012 *
1013 * Return -EINVAL or zero on success
1014 */
1015static int ispif_get_format(struct v4l2_subdev *sd,
1016			    struct v4l2_subdev_state *sd_state,
1017			    struct v4l2_subdev_format *fmt)
1018{
1019	struct ispif_line *line = v4l2_get_subdevdata(sd);
1020	struct v4l2_mbus_framefmt *format;
1021
1022	format = __ispif_get_format(line, sd_state, fmt->pad, fmt->which);
1023	if (format == NULL)
1024		return -EINVAL;
1025
1026	fmt->format = *format;
1027
1028	return 0;
1029}
1030
1031/*
1032 * ispif_set_format - Handle set format by pads subdev method
1033 * @sd: ISPIF V4L2 subdevice
1034 * @sd_state: V4L2 subdev state
1035 * @fmt: pointer to v4l2 subdev format structure
1036 *
1037 * Return -EINVAL or zero on success
1038 */
1039static int ispif_set_format(struct v4l2_subdev *sd,
1040			    struct v4l2_subdev_state *sd_state,
1041			    struct v4l2_subdev_format *fmt)
1042{
1043	struct ispif_line *line = v4l2_get_subdevdata(sd);
1044	struct v4l2_mbus_framefmt *format;
1045
1046	format = __ispif_get_format(line, sd_state, fmt->pad, fmt->which);
1047	if (format == NULL)
1048		return -EINVAL;
1049
1050	ispif_try_format(line, sd_state, fmt->pad, &fmt->format, fmt->which);
1051	*format = fmt->format;
1052
1053	/* Propagate the format from sink to source */
1054	if (fmt->pad == MSM_ISPIF_PAD_SINK) {
1055		format = __ispif_get_format(line, sd_state, MSM_ISPIF_PAD_SRC,
1056					    fmt->which);
1057
1058		*format = fmt->format;
1059		ispif_try_format(line, sd_state, MSM_ISPIF_PAD_SRC, format,
1060				 fmt->which);
1061	}
1062
1063	return 0;
1064}
1065
1066/*
1067 * ispif_init_formats - Initialize formats on all pads
1068 * @sd: ISPIF V4L2 subdevice
1069 * @fh: V4L2 subdev file handle
1070 *
1071 * Initialize all pad formats with default values.
1072 *
1073 * Return 0 on success or a negative error code otherwise
1074 */
1075static int ispif_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1076{
1077	struct v4l2_subdev_format format = {
1078		.pad = MSM_ISPIF_PAD_SINK,
1079		.which = fh ? V4L2_SUBDEV_FORMAT_TRY :
1080			      V4L2_SUBDEV_FORMAT_ACTIVE,
1081		.format = {
1082			.code = MEDIA_BUS_FMT_UYVY8_1X16,
1083			.width = 1920,
1084			.height = 1080
1085		}
1086	};
1087
1088	return ispif_set_format(sd, fh ? fh->state : NULL, &format);
1089}
1090
1091/*
1092 * msm_ispif_subdev_init - Initialize ISPIF device structure and resources
1093 * @ispif: ISPIF device
1094 * @res: ISPIF module resources table
1095 *
1096 * Return 0 on success or a negative error code otherwise
1097 */
1098int msm_ispif_subdev_init(struct camss *camss,
1099			  const struct camss_subdev_resources *res)
1100{
1101	struct device *dev = camss->dev;
1102	struct ispif_device *ispif = camss->ispif;
1103	struct platform_device *pdev = to_platform_device(dev);
1104	int i;
1105	int ret;
1106
1107	if (!camss->ispif)
1108		return 0;
1109
1110	ispif->camss = camss;
1111
1112	/* Number of ISPIF lines - same as number of CSID hardware modules */
1113	if (camss->res->version == CAMSS_8x16)
1114		ispif->line_num = 2;
1115	else if (camss->res->version == CAMSS_8x39)
1116		ispif->line_num = 3;
1117	else if (camss->res->version == CAMSS_8x96 ||
1118		 camss->res->version == CAMSS_8x53 ||
1119		 camss->res->version == CAMSS_660)
1120		ispif->line_num = 4;
1121	else
1122		return -EINVAL;
1123
1124	ispif->line = devm_kcalloc(dev, ispif->line_num,
1125				   sizeof(*ispif->line), GFP_KERNEL);
1126	if (!ispif->line)
1127		return -ENOMEM;
1128
1129	for (i = 0; i < ispif->line_num; i++) {
1130		ispif->line[i].ispif = ispif;
1131		ispif->line[i].id = i;
1132
1133		if (camss->res->version == CAMSS_8x16 ||
1134		    camss->res->version == CAMSS_8x39) {
1135			ispif->line[i].formats = ispif_formats_8x16;
1136			ispif->line[i].nformats =
1137					ARRAY_SIZE(ispif_formats_8x16);
1138		} else if (camss->res->version == CAMSS_8x96 ||
1139			   camss->res->version == CAMSS_8x53 ||
1140			   camss->res->version == CAMSS_660) {
1141			ispif->line[i].formats = ispif_formats_8x96;
1142			ispif->line[i].nformats =
1143					ARRAY_SIZE(ispif_formats_8x96);
1144		} else {
1145			return -EINVAL;
1146		}
1147	}
1148
1149	/* Memory */
1150
1151	ispif->base = devm_platform_ioremap_resource_byname(pdev, res->reg[0]);
1152	if (IS_ERR(ispif->base))
1153		return PTR_ERR(ispif->base);
1154
1155	ispif->base_clk_mux = devm_platform_ioremap_resource_byname(pdev, res->reg[1]);
1156	if (IS_ERR(ispif->base_clk_mux))
1157		return PTR_ERR(ispif->base_clk_mux);
1158
1159	/* Interrupt */
1160
1161	ret = platform_get_irq_byname(pdev, res->interrupt[0]);
1162	if (ret < 0)
1163		return ret;
1164
1165	ispif->irq = ret;
1166	snprintf(ispif->irq_name, sizeof(ispif->irq_name), "%s_%s",
1167		 dev_name(dev), MSM_ISPIF_NAME);
1168	if (camss->res->version == CAMSS_8x16 ||
1169	    camss->res->version == CAMSS_8x39)
1170		ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x16,
1171			       IRQF_TRIGGER_RISING, ispif->irq_name, ispif);
1172	else if (camss->res->version == CAMSS_8x96 ||
1173		 camss->res->version == CAMSS_8x53 ||
1174		 camss->res->version == CAMSS_660)
1175		ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x96,
1176			       IRQF_TRIGGER_RISING, ispif->irq_name, ispif);
1177	else
1178		ret = -EINVAL;
1179
1180	if (ret < 0) {
1181		dev_err(dev, "request_irq failed: %d\n", ret);
1182		return ret;
1183	}
1184
1185	/* Clocks */
1186
1187	ispif->nclocks = 0;
1188	while (res->clock[ispif->nclocks])
1189		ispif->nclocks++;
1190
1191	ispif->clock = devm_kcalloc(dev,
1192				    ispif->nclocks, sizeof(*ispif->clock),
1193				    GFP_KERNEL);
1194	if (!ispif->clock)
1195		return -ENOMEM;
1196
1197	for (i = 0; i < ispif->nclocks; i++) {
1198		struct camss_clock *clock = &ispif->clock[i];
1199
1200		clock->clk = devm_clk_get(dev, res->clock[i]);
1201		if (IS_ERR(clock->clk))
1202			return PTR_ERR(clock->clk);
1203
1204		clock->freq = NULL;
1205		clock->nfreqs = 0;
1206	}
1207
1208	ispif->nclocks_for_reset = 0;
1209	while (res->clock_for_reset[ispif->nclocks_for_reset])
1210		ispif->nclocks_for_reset++;
1211
1212	ispif->clock_for_reset = devm_kcalloc(dev,
1213					      ispif->nclocks_for_reset,
1214					      sizeof(*ispif->clock_for_reset),
1215					      GFP_KERNEL);
1216	if (!ispif->clock_for_reset)
1217		return -ENOMEM;
1218
1219	for (i = 0; i < ispif->nclocks_for_reset; i++) {
1220		struct camss_clock *clock = &ispif->clock_for_reset[i];
1221
1222		clock->clk = devm_clk_get(dev, res->clock_for_reset[i]);
1223		if (IS_ERR(clock->clk))
1224			return PTR_ERR(clock->clk);
1225
1226		clock->freq = NULL;
1227		clock->nfreqs = 0;
1228	}
1229
1230	mutex_init(&ispif->power_lock);
1231	ispif->power_count = 0;
1232
1233	mutex_init(&ispif->config_lock);
1234
1235	for (i = 0; i < MSM_ISPIF_VFE_NUM; i++)
1236		init_completion(&ispif->reset_complete[i]);
1237
1238	return 0;
1239}
1240
1241/*
1242 * ispif_get_intf - Get ISPIF interface to use by VFE line id
1243 * @line_id: VFE line id that the ISPIF line is connected to
1244 *
1245 * Return ISPIF interface to use
1246 */
1247static enum ispif_intf ispif_get_intf(enum vfe_line_id line_id)
1248{
1249	switch (line_id) {
1250	case (VFE_LINE_RDI0):
1251		return RDI0;
1252	case (VFE_LINE_RDI1):
1253		return RDI1;
1254	case (VFE_LINE_RDI2):
1255		return RDI2;
1256	case (VFE_LINE_PIX):
1257		return PIX0;
1258	default:
1259		return RDI0;
1260	}
1261}
1262
1263/*
1264 * ispif_get_vfe_id - Get VFE HW module id
1265 * @entity: Pointer to VFE media entity structure
1266 * @id: Return CSID HW module id here
1267 */
1268static void ispif_get_vfe_id(struct media_entity *entity, u8 *id)
1269{
1270	struct v4l2_subdev *sd;
1271	struct vfe_line *line;
1272	struct vfe_device *vfe;
1273
1274	sd = media_entity_to_v4l2_subdev(entity);
1275	line = v4l2_get_subdevdata(sd);
1276	vfe = to_vfe(line);
1277
1278	*id = vfe->id;
1279}
1280
1281/*
1282 * ispif_get_vfe_line_id - Get VFE line id by media entity
1283 * @entity: Pointer to VFE media entity structure
1284 * @id: Return VFE line id here
1285 */
1286static void ispif_get_vfe_line_id(struct media_entity *entity,
1287				  enum vfe_line_id *id)
1288{
1289	struct v4l2_subdev *sd;
1290	struct vfe_line *line;
1291
1292	sd = media_entity_to_v4l2_subdev(entity);
1293	line = v4l2_get_subdevdata(sd);
1294
1295	*id = line->id;
1296}
1297
1298/*
1299 * ispif_link_setup - Setup ISPIF connections
1300 * @entity: Pointer to media entity structure
1301 * @local: Pointer to local pad
1302 * @remote: Pointer to remote pad
1303 * @flags: Link flags
1304 *
1305 * Return 0 on success
1306 */
1307static int ispif_link_setup(struct media_entity *entity,
1308			    const struct media_pad *local,
1309			    const struct media_pad *remote, u32 flags)
1310{
1311	if (flags & MEDIA_LNK_FL_ENABLED) {
1312		if (media_pad_remote_pad_first(local))
1313			return -EBUSY;
1314
1315		if (local->flags & MEDIA_PAD_FL_SINK) {
1316			struct v4l2_subdev *sd;
1317			struct ispif_line *line;
1318
1319			sd = media_entity_to_v4l2_subdev(entity);
1320			line = v4l2_get_subdevdata(sd);
1321
1322			msm_csid_get_csid_id(remote->entity, &line->csid_id);
1323		} else { /* MEDIA_PAD_FL_SOURCE */
1324			struct v4l2_subdev *sd;
1325			struct ispif_line *line;
1326			enum vfe_line_id id;
1327
1328			sd = media_entity_to_v4l2_subdev(entity);
1329			line = v4l2_get_subdevdata(sd);
1330
1331			ispif_get_vfe_id(remote->entity, &line->vfe_id);
1332			ispif_get_vfe_line_id(remote->entity, &id);
1333			line->interface = ispif_get_intf(id);
1334		}
1335	}
1336
1337	return 0;
1338}
1339
1340static const struct v4l2_subdev_core_ops ispif_core_ops = {
1341	.s_power = ispif_set_power,
1342};
1343
1344static const struct v4l2_subdev_video_ops ispif_video_ops = {
1345	.s_stream = ispif_set_stream,
1346};
1347
1348static const struct v4l2_subdev_pad_ops ispif_pad_ops = {
1349	.enum_mbus_code = ispif_enum_mbus_code,
1350	.enum_frame_size = ispif_enum_frame_size,
1351	.get_fmt = ispif_get_format,
1352	.set_fmt = ispif_set_format,
1353};
1354
1355static const struct v4l2_subdev_ops ispif_v4l2_ops = {
1356	.core = &ispif_core_ops,
1357	.video = &ispif_video_ops,
1358	.pad = &ispif_pad_ops,
1359};
1360
1361static const struct v4l2_subdev_internal_ops ispif_v4l2_internal_ops = {
1362	.open = ispif_init_formats,
1363};
1364
1365static const struct media_entity_operations ispif_media_ops = {
1366	.link_setup = ispif_link_setup,
1367	.link_validate = v4l2_subdev_link_validate,
1368};
1369
1370/*
1371 * msm_ispif_register_entities - Register subdev node for ISPIF module
1372 * @ispif: ISPIF device
1373 * @v4l2_dev: V4L2 device
1374 *
1375 * Return 0 on success or a negative error code otherwise
1376 */
1377int msm_ispif_register_entities(struct ispif_device *ispif,
1378				struct v4l2_device *v4l2_dev)
1379{
1380	struct camss *camss;
1381	int ret;
1382	int i;
1383
1384	if (!ispif)
1385		return 0;
1386
1387	camss = ispif->camss;
1388
1389	for (i = 0; i < ispif->line_num; i++) {
1390		struct v4l2_subdev *sd = &ispif->line[i].subdev;
1391		struct media_pad *pads = ispif->line[i].pads;
1392
1393		v4l2_subdev_init(sd, &ispif_v4l2_ops);
1394		sd->internal_ops = &ispif_v4l2_internal_ops;
1395		sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1396		snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d",
1397			 MSM_ISPIF_NAME, i);
1398		v4l2_set_subdevdata(sd, &ispif->line[i]);
1399
1400		ret = ispif_init_formats(sd, NULL);
1401		if (ret < 0) {
1402			dev_err(camss->dev, "Failed to init format: %d\n", ret);
1403			goto error;
1404		}
1405
1406		pads[MSM_ISPIF_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1407		pads[MSM_ISPIF_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE;
1408
1409		sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
1410		sd->entity.ops = &ispif_media_ops;
1411		ret = media_entity_pads_init(&sd->entity, MSM_ISPIF_PADS_NUM,
1412					     pads);
1413		if (ret < 0) {
1414			dev_err(camss->dev, "Failed to init media entity: %d\n",
1415				ret);
1416			goto error;
1417		}
1418
1419		ret = v4l2_device_register_subdev(v4l2_dev, sd);
1420		if (ret < 0) {
1421			dev_err(camss->dev, "Failed to register subdev: %d\n",
1422				ret);
1423			media_entity_cleanup(&sd->entity);
1424			goto error;
1425		}
1426	}
1427
1428	return 0;
1429
1430error:
1431	for (i--; i >= 0; i--) {
1432		struct v4l2_subdev *sd = &ispif->line[i].subdev;
1433
1434		v4l2_device_unregister_subdev(sd);
1435		media_entity_cleanup(&sd->entity);
1436	}
1437
1438	return ret;
1439}
1440
1441/*
1442 * msm_ispif_unregister_entities - Unregister ISPIF module subdev node
1443 * @ispif: ISPIF device
1444 */
1445void msm_ispif_unregister_entities(struct ispif_device *ispif)
1446{
1447	int i;
1448
1449	if (!ispif)
1450		return;
1451
1452	mutex_destroy(&ispif->power_lock);
1453	mutex_destroy(&ispif->config_lock);
1454
1455	for (i = 0; i < ispif->line_num; i++) {
1456		struct v4l2_subdev *sd = &ispif->line[i].subdev;
1457
1458		v4l2_device_unregister_subdev(sd);
1459		media_entity_cleanup(&sd->entity);
1460	}
1461}