camss-csid-680.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module
  4 *
  5 * Copyright (C) 2020-2025 Linaro Ltd.
  6 */
  7#include <linux/completion.h>
  8#include <linux/interrupt.h>
  9#include <linux/io.h>
 10#include <linux/kernel.h>
 11
 12#include "camss.h"
 13#include "camss-csid.h"
 14#include "camss-csid-gen2.h"
 15
 16#define CSID_TOP_IO_PATH_CFG0(csid)				(0x4 * (csid))
 17#define		CSID_TOP_IO_PATH_CFG0_INTERNAL_CSID		BIT(0)
 18#define		CSID_TOP_IO_PATH_CFG0_SFE_0			BIT(1)
 19#define		CSID_TOP_IO_PATH_CFG0_SFE_1			GENMASK(1, 0)
 20#define		CSID_TOP_IO_PATH_CFG0_SBI_0			BIT(4)
 21#define		CSID_TOP_IO_PATH_CFG0_SBI_1			GENMASK(3, 0)
 22#define		CSID_TOP_IO_PATH_CFG0_SBI_2			GENMASK(3, 1)
 23#define		CSID_TOP_IO_PATH_CFG0_OUTPUT_IFE_EN		BIT(8)
 24#define		CSID_TOP_IO_PATH_CFG0_SFE_OFFLINE_EN		BIT(12)
 25
 26#define CSID_RESET_CMD						0x10
 27#define		CSID_RESET_CMD_HW_RESET				BIT(0)
 28#define		CSID_RESET_CMD_SW_RESET				BIT(1)
 29#define		CSID_RESET_CMD_IRQ_CTRL				BIT(2)
 30
 31#define CSID_IRQ_CMD						0x14
 32#define		CSID_IRQ_CMD_CLEAR				BIT(0)
 33#define		CSID_IRQ_CMD_SET				BIT(4)
 34
 35#define CSID_REG_UPDATE_CMD					0x18
 36
 37#define CSID_CSI2_RDIN_IRQ_STATUS(rdi)					(0xec + 0x10 * (rdi))
 38#define		CSID_CSI2_RDIN_CCIF_VIOLATION				BIT(29)
 39#define		CSID_CSI2_RDIN_SENSOR_SWITCH_OUT_OF_SYNC_FRAME_DROP	BIT(28)
 40#define		CSID_CSI2_RDIN_ERROR_REC_WIDTH_VIOLATION		BIT(27)
 41#define		CSID_CSI2_RDIN_ERROR_REC_HEIGHT_VIOLATION		BIT(26)
 42#define		CSID_CSI2_RDIN_BATCH_END_MISSING_VIOLATION		BIT(25)
 43#define		CSID_CSI2_RDIN_ILLEGAL_BATCH_ID_IRQ			BIT(24)
 44#define		CSID_CSI2_RDIN_RUP_DONE					BIT(23)
 45#define		CSID_CSI2_RDIN_CAMIF_EPOCH_1_IRQ			BIT(22)
 46#define		CSID_CSI2_RDIN_CAMIF_EPOCH_0_IRQ			BIT(21)
 47#define		CSID_CSI2_RDIN_ERROR_REC_OVERFLOW_IRQ			BIT(19)
 48#define		CSID_CSI2_RDIN_ERROR_REC_FRAME_DROP			BIT(18)
 49#define		CSID_CSI2_RDIN_VCDT_GRP_CHANG				BIT(17)
 50#define		CSID_CSI2_RDIN_VCDT_GRP_0_SEL				BIT(16)
 51#define		CSID_CSI2_RDIN_VCDT_GRP_1_SEL				BIT(15)
 52#define		CSID_CSI2_RDIN_ERROR_LINE_COUNT				BIT(14)
 53#define		CSID_CSI2_RDIN_ERROR_PIX_COUNT				BIT(13)
 54#define		CSID_CSI2_RDIN_INFO_INPUT_SOF				BIT(12)
 55#define		CSID_CSI2_RDIN_INFO_INPUT_SOL				BIT(11)
 56#define		CSID_CSI2_RDIN_INFO_INPUT_EOL				BIT(10)
 57#define		CSID_CSI2_RDIN_INFO_INPUT_EOF				BIT(9)
 58#define		CSID_CSI2_RDIN_INFO_FRAME_DROP_SOF			BIT(8)
 59#define		CSID_CSI2_RDIN_INFO_FRAME_DROP_SOL			BIT(7)
 60#define		CSID_CSI2_RDIN_INFO_FRAME_DROP_EOL			BIT(6)
 61#define		CSID_CSI2_RDIN_INFO_FRAME_DROP_EOF			BIT(5)
 62#define		CSID_CSI2_RDIN_INFO_CAMIF_SOF				BIT(4)
 63#define		CSID_CSI2_RDIN_INFO_CAMIF_EOF				BIT(3)
 64#define		CSID_CSI2_RDIN_INFO_FIFO_OVERFLOW			BIT(2)
 65#define		CSID_CSI2_RDIN_RES1					BIT(1)
 66#define		CSID_CSI2_RDIN_RES0					BIT(0)
 67
 68#define CSID_CSI2_RDIN_IRQ_MASK(rdi)				(0xf0 + 0x10 * (rdi))
 69#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi)				(0xf4 + 0x10 * (rdi))
 70#define CSID_CSI2_RDIN_IRQ_SET(rdi)				(0xf8 + 0x10 * (rdi))
 71
 72#define CSID_TOP_IRQ_STATUS					0x7c
 73#define CSID_TOP_IRQ_MASK					0x80
 74#define CSID_TOP_IRQ_CLEAR					0x84
 75#define		CSID_TOP_IRQ_RESET				BIT(0)
 76#define		CSID_TOP_IRQ_RX					BIT(2)
 77#define		CSID_TOP_IRQ_LONG_PKT(rdi)			(BIT(8) << (rdi))
 78#define		CSID_TOP_IRQ_BUF_DONE				BIT(13)
 79
 80#define CSID_BUF_DONE_IRQ_STATUS				0x8c
 81#define	BUF_DONE_IRQ_STATUS_RDI_OFFSET				(csid_is_lite(csid) ? 1 : 14)
 82#define CSID_BUF_DONE_IRQ_MASK					0x90
 83#define CSID_BUF_DONE_IRQ_CLEAR					0x94
 84
 85#define CSID_CSI2_RX_IRQ_STATUS					0x9c
 86#define CSID_CSI2_RX_IRQ_MASK					0xa0
 87#define CSID_CSI2_RX_IRQ_CLEAR					0xa4
 88
 89#define CSID_RESET_CFG						0xc
 90#define		CSID_RESET_CFG_MODE_IMMEDIATE			BIT(0)
 91#define		CSID_RESET_CFG_LOCATION_COMPLETE		BIT(4)
 92
 93#define CSID_CSI2_RDI_IRQ_STATUS(rdi)				(0xec + 0x10 * (rdi))
 94#define CSID_CSI2_RDI_IRQ_MASK(rdi)				(0xf0 + 0x10 * (rdi))
 95#define CSID_CSI2_RDI_IRQ_CLEAR(rdi)				(0xf4 + 0x10 * (rdi))
 96
 97#define CSID_CSI2_RX_CFG0					0x200
 98#define		CSI2_RX_CFG0_NUM_ACTIVE_LANES			0
 99#define		CSI2_RX_CFG0_DL0_INPUT_SEL			4
100#define		CSI2_RX_CFG0_DL1_INPUT_SEL			8
101#define		CSI2_RX_CFG0_DL2_INPUT_SEL			12
102#define		CSI2_RX_CFG0_DL3_INPUT_SEL			16
103#define		CSI2_RX_CFG0_PHY_NUM_SEL			20
104#define		CSI2_RX_CFG0_PHY_SEL_BASE_IDX			1
105#define		CSI2_RX_CFG0_PHY_TYPE_SEL			24
106
107#define CSID_CSI2_RX_CFG1					0x204
108#define		CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN		BIT(0)
109#define		CSI2_RX_CFG1_DE_SCRAMBLE_EN			BIT(1)
110#define		CSI2_RX_CFG1_VC_MODE				BIT(2)
111#define		CSI2_RX_CFG1_COMPLETE_STREAM_EN			BIT(4)
112#define		CSI2_RX_CFG1_COMPLETE_STREAM_FRAME_TIMING	BIT(5)
113#define		CSI2_RX_CFG1_MISR_EN				BIT(6)
114#define		CSI2_RX_CFG1_CGC_MODE				BIT(7)
115
116#define CSID_CSI2_RX_CAPTURE_CTRL				0x208
117#define		CSI2_RX_CAPTURE_CTRL_LONG_PKT_EN		BIT(0)
118#define		CSI2_RX_CAPTURE_CTRL_SHORT_PKT_EN		BIT(1)
119#define		CSI2_RX_CAPTURE_CTRL_CPHY_PKT_EN		BIT(2)
120#define		CSI2_RX_CAPTURE_CTRL_LONG_PKT_DT		GENMASK(9, 4)
121#define		CSI2_RX_CAPTURE_CTRL_LONG_PKT_VC		GENMASK(14, 10)
122#define		CSI2_RX_CAPTURE_CTRL_SHORT_PKT_VC		GENMASK(19, 15)
123#define		CSI2_RX_CAPTURE_CTRL_CPHY_PKT_DT		GENMASK(20, 25)
124#define		CSI2_RX_CAPTURE_CTRL_CPHY_PKT_VC		GENMASK(30, 26)
125
126#define CSID_CSI2_RX_TOTAL_PKTS_RCVD				0x240
127#define CSID_CSI2_RX_STATS_ECC					0x244
128#define CSID_CSI2_RX_CRC_ERRORS					0x248
129
130#define CSID_RDI_CFG0(rdi)					(0x500 + 0x100 * (rdi))
131#define		RDI_CFG0_DECODE_FORMAT				12
132#define		RDI_CFG0_DATA_TYPE				16
133#define		RDI_CFG0_VIRTUAL_CHANNEL			22
134#define		RDI_CFG0_DT_ID					27
135#define		RDI_CFG0_ENABLE					BIT(31)
136
137#define CSID_RDI_CTRL(rdi)					(0x504 + 0x100 * (rdi))
138#define		CSID_RDI_CTRL_HALT_CMD_HALT_AT_FRAME_BOUNDARY	0
139#define		CSID_RDI_CTRL_HALT_CMD_RESUME_AT_FRAME_BOUNDARY	1
140
141#define CSID_RDI_CFG1(rdi)					(0x510 + 0x100 * (rdi))
142#define		RDI_CFG1_TIMESTAMP_STB_FRAME			BIT(0)
143#define		RDI_CFG1_TIMESTAMP_STB_IRQ			BIT(1)
144#define		RDI_CFG1_BYTE_CNTR_EN				BIT(2)
145#define		RDI_CFG1_TIMESTAMP_EN				BIT(4)
146#define		RDI_CFG1_DROP_H_EN				BIT(5)
147#define		RDI_CFG1_DROP_V_EN				BIT(6)
148#define		RDI_CFG1_CROP_H_EN				BIT(7)
149#define		RDI_CFG1_CROP_V_EN				BIT(8)
150#define		RDI_CFG1_MISR_EN				BIT(9)
151#define		RDI_CFG1_PLAIN_ALIGN_MSB			BIT(11)
152#define		RDI_CFG1_EARLY_EOF_EN				BIT(14)
153#define		RDI_CFG1_PACKING_MIPI				BIT(15)
154
155#define CSID_RDI_ERR_RECOVERY_CFG0(rdi)				(0x514 + 0x100 * (rdi))
156#define CSID_RDI_EPOCH_IRQ_CFG(rdi)				(0x52c + 0x100 * (rdi))
157#define CSID_RDI_FRM_DROP_PATTERN(rdi)				(0x540 + 0x100 * (rdi))
158#define CSID_RDI_FRM_DROP_PERIOD(rdi)				(0x544 + 0x100 * (rdi))
159#define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi)			(0x548 + 0x100 * (rdi))
160#define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi)			(0x54c + 0x100 * (rdi))
161#define CSID_RDI_PIX_DROP_PATTERN(rdi)				(0x558 + 0x100 * (rdi))
162#define CSID_RDI_PIX_DROP_PERIOD(rdi)				(0x55c + 0x100 * (rdi))
163#define CSID_RDI_LINE_DROP_PATTERN(rdi)				(0x560 + 0x100 * (rdi))
164#define CSID_RDI_LINE_DROP_PERIOD(rdi)				(0x564 + 0x100 * (rdi))
165
166static inline int reg_update_rdi(struct csid_device *csid, int n)
167{
168	return BIT(4 + n) + BIT(20 + n);
169}
170
171static void csid_reg_update(struct csid_device *csid, int port_id)
172{
173	csid->reg_update |= reg_update_rdi(csid, port_id);
174	writel(csid->reg_update, csid->base + CSID_REG_UPDATE_CMD);
175}
176
177static inline void csid_reg_update_clear(struct csid_device *csid,
178					 int port_id)
179{
180	csid->reg_update &= ~reg_update_rdi(csid, port_id);
181	writel(csid->reg_update, csid->base + CSID_REG_UPDATE_CMD);
182}
183
184static void __csid_configure_rx(struct csid_device *csid,
185				struct csid_phy_config *phy, int vc)
186{
187	u32 val;
188
189	val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
190	val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
191	val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) << CSI2_RX_CFG0_PHY_NUM_SEL;
192
193	writel(val, csid->base + CSID_CSI2_RX_CFG0);
194
195	val = CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN;
196	if (vc > 3)
197		val |= CSI2_RX_CFG1_VC_MODE;
198	writel(val, csid->base + CSID_CSI2_RX_CFG1);
199}
200
201static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi)
202{
203	u32 val;
204
205	if (enable)
206		val = CSID_RDI_CTRL_HALT_CMD_RESUME_AT_FRAME_BOUNDARY;
207	else
208		val = CSID_RDI_CTRL_HALT_CMD_HALT_AT_FRAME_BOUNDARY;
209
210	writel(val, csid->base + CSID_RDI_CTRL(rdi));
211}
212
213static void __csid_configure_top(struct csid_device *csid)
214{
215	u32 val;
216
217	val = CSID_TOP_IO_PATH_CFG0_OUTPUT_IFE_EN | CSID_TOP_IO_PATH_CFG0_INTERNAL_CSID;
218	writel(val, csid->camss->csid_wrapper_base +
219	    CSID_TOP_IO_PATH_CFG0(csid->id));
220}
221
222static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 vc)
223{
224	struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc];
225	const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
226								   csid->res->formats->nformats,
227								   input_format->code);
228	u8 lane_cnt = csid->phy.lane_cnt;
229	u8 dt_id;
230	u32 val;
231
232	if (!lane_cnt)
233		lane_cnt = 4;
234
235	val = 0;
236	writel(val, csid->base + CSID_RDI_FRM_DROP_PERIOD(vc));
237
238	/*
239	 * DT_ID is a two bit bitfield that is concatenated with
240	 * the four least significant bits of the five bit VC
241	 * bitfield to generate an internal CID value.
242	 *
243	 * CSID_RDI_CFG0(vc)
244	 * DT_ID : 28:27
245	 * VC    : 26:22
246	 * DT    : 21:16
247	 *
248	 * CID   : VC 3:0 << 2 | DT_ID 1:0
249	 */
250	dt_id = vc & 0x03;
251
252	/* note: for non-RDI path, this should be format->decode_format */
253	val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
254	val |= format->data_type << RDI_CFG0_DATA_TYPE;
255	val |= vc << RDI_CFG0_VIRTUAL_CHANNEL;
256	val |= dt_id << RDI_CFG0_DT_ID;
257	writel(val, csid->base + CSID_RDI_CFG0(vc));
258
259	val = RDI_CFG1_TIMESTAMP_STB_FRAME;
260	val |= RDI_CFG1_BYTE_CNTR_EN;
261	val |= RDI_CFG1_TIMESTAMP_EN;
262	val |= RDI_CFG1_DROP_H_EN;
263	val |= RDI_CFG1_DROP_V_EN;
264	val |= RDI_CFG1_CROP_H_EN;
265	val |= RDI_CFG1_CROP_V_EN;
266	val |= RDI_CFG1_PACKING_MIPI;
267
268	writel(val, csid->base + CSID_RDI_CFG1(vc));
269
270	val = 0;
271	writel(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PERIOD(vc));
272
273	val = 1;
274	writel(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PATTERN(vc));
275
276	val = 0;
277	writel(val, csid->base + CSID_RDI_CTRL(vc));
278
279	val = readl(csid->base + CSID_RDI_CFG0(vc));
280	if (enable)
281		val |= RDI_CFG0_ENABLE;
282	else
283		val &= ~RDI_CFG0_ENABLE;
284	writel(val, csid->base + CSID_RDI_CFG0(vc));
285}
286
287static void csid_configure_stream(struct csid_device *csid, u8 enable)
288{
289	int i;
290
291	__csid_configure_top(csid);
292
293       /* Loop through all enabled VCs and configure stream for each */
294	for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++) {
295		if (csid->phy.en_vc & BIT(i)) {
296			__csid_configure_rdi_stream(csid, enable, i);
297			__csid_configure_rx(csid, &csid->phy, i);
298			__csid_ctrl_rdi(csid, enable, i);
299		}
300	}
301}
302
303/*
304 * csid_reset - Trigger reset on CSID module and wait to complete
305 * @csid: CSID device
306 *
307 * Return 0 on success or a negative error code otherwise
308 */
309static int csid_reset(struct csid_device *csid)
310{
311	unsigned long time;
312	u32 val;
313	int i;
314
315	reinit_completion(&csid->reset_complete);
316
317	writel(CSID_IRQ_CMD_CLEAR, csid->base + CSID_IRQ_CMD);
318
319	/* preserve registers */
320	val = CSID_RESET_CFG_MODE_IMMEDIATE | CSID_RESET_CFG_LOCATION_COMPLETE;
321	writel(val, csid->base + CSID_RESET_CFG);
322
323	val = CSID_RESET_CMD_HW_RESET | CSID_RESET_CMD_SW_RESET;
324	writel(val, csid->base + CSID_RESET_CMD);
325
326	time = wait_for_completion_timeout(&csid->reset_complete,
327					   msecs_to_jiffies(CSID_RESET_TIMEOUT_MS));
328	if (!time) {
329		dev_err(csid->camss->dev, "CSID reset timeout\n");
330		return -EIO;
331	}
332
333	for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++) {
334		/* Enable RUP done for the client port */
335		writel(CSID_CSI2_RDIN_RUP_DONE, csid->base + CSID_CSI2_RDIN_IRQ_MASK(i));
336	}
337
338	/* Clear RDI status */
339	writel(~0u, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
340
341	/* Enable BUF_DONE bit for all write-master client ports */
342	writel(~0u, csid->base + CSID_BUF_DONE_IRQ_MASK);
343
344	/* Unmask all TOP interrupts */
345	writel(~0u, csid->base + CSID_TOP_IRQ_MASK);
346
347	return 0;
348}
349
350static void csid_rup_complete(struct csid_device *csid, int rdi)
351{
352	csid_reg_update_clear(csid, rdi);
353}
354
355/*
356 * csid_isr - CSID module interrupt service routine
357 * @irq: Interrupt line
358 * @dev: CSID device
359 *
360 * Return IRQ_HANDLED on success
361 */
362static irqreturn_t csid_isr(int irq, void *dev)
363{
364	struct csid_device *csid = dev;
365	u32 buf_done_val, val, val_top;
366	int i;
367
368	/* Latch and clear TOP status */
369	val_top = readl(csid->base + CSID_TOP_IRQ_STATUS);
370	writel(val_top, csid->base + CSID_TOP_IRQ_CLEAR);
371
372	/* Latch and clear CSID_CSI2 status */
373	val = readl(csid->base + CSID_CSI2_RX_IRQ_STATUS);
374	writel(val, csid->base + CSID_CSI2_RX_IRQ_CLEAR);
375
376	/* Latch and clear top level BUF_DONE status */
377	buf_done_val = readl(csid->base + CSID_BUF_DONE_IRQ_STATUS);
378	writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
379
380	/* Process state for each RDI channel */
381	for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++) {
382		val = readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i));
383		if (val)
384			writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i));
385
386		if (val & CSID_CSI2_RDIN_RUP_DONE)
387			csid_rup_complete(csid, i);
388
389		if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i))
390			camss_buf_done(csid->camss, csid->id, i);
391	}
392
393	/* Issue clear command */
394	writel(CSID_IRQ_CMD_CLEAR, csid->base + CSID_IRQ_CMD);
395
396	/* Reset complete */
397	if (val_top & CSID_TOP_IRQ_RESET)
398		complete(&csid->reset_complete);
399
400	return IRQ_HANDLED;
401}
402
403static void csid_subdev_reg_update(struct csid_device *csid, int port_id, bool is_clear)
404{
405	if (is_clear)
406		csid_reg_update_clear(csid, port_id);
407	else
408		csid_reg_update(csid, port_id);
409}
410
411static void csid_subdev_init(struct csid_device *csid) {}
412
413const struct csid_hw_ops csid_ops_680 = {
414	.configure_testgen_pattern = NULL,
415	.configure_stream = csid_configure_stream,
416	.hw_version = csid_hw_version,
417	.isr = csid_isr,
418	.reset = csid_reset,
419	.src_pad_code = csid_src_pad_code,
420	.subdev_init = csid_subdev_init,
421	.reg_update = csid_subdev_reg_update,
422};