camss-csid-340.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module 340
  4 *
  5 * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
  6 */
  7
  8#include <linux/completion.h>
  9#include <linux/bitfield.h>
 10#include <linux/interrupt.h>
 11#include <linux/io.h>
 12#include <linux/kernel.h>
 13
 14#include "camss.h"
 15#include "camss-csid.h"
 16#include "camss-csid-gen2.h"
 17
 18#define CSID_RST_STROBES					(0x010)
 19#define		CSID_RST_SW_REGS			BIT(0)
 20#define		CSID_RST_IRQ				BIT(1)
 21#define CSID_RST_IFE_CLK				BIT(2)
 22#define		CSID_RST_PHY_CLK			BIT(3)
 23#define		CSID_RST_CSID_CLK			BIT(4)
 24
 25#define CSID_IRQ_STATUS						(0x070)
 26#define CSID_IRQ_MASK						(0x074)
 27#define		CSID_IRQ_MASK_RST_DONE			BIT(0)
 28#define CSID_IRQ_CLEAR						(0x078)
 29#define CSID_IRQ_CMD						(0x080)
 30#define		CSID_IRQ_CMD_CLEAR			BIT(0)
 31
 32#define CSID_CSI2_RX_CFG0					(0x100)
 33#define		CSI2_RX_CFG0_NUM_ACTIVE_LANES_MASK	GENMASK(1, 0)
 34#define		CSI2_RX_CFG0_DLX_INPUT_SEL_MASK		GENMASK(17, 4)
 35#define		CSI2_RX_CFG0_PHY_NUM_SEL_MASK		GENMASK(21, 20)
 36#define		CSI2_RX_CFG0_PHY_NUM_SEL_BASE_IDX	1
 37#define		CSI2_RX_CFG0_PHY_TYPE_SEL		BIT(24)
 38
 39#define CSID_CSI2_RX_CFG1					(0x104)
 40#define		CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN	BIT(0)
 41#define		CSI2_RX_CFG1_MISR_EN			BIT(6)
 42#define		CSI2_RX_CFG1_CGC_MODE			BIT(7)
 43
 44#define CSID_RDI_CFG0(rdi)					(0x300 + 0x100 * (rdi))
 45#define		CSID_RDI_CFG0_BYTE_CNTR_EN		BIT(0)
 46#define		CSID_RDI_CFG0_TIMESTAMP_EN		BIT(1)
 47#define		CSID_RDI_CFG0_DECODE_FORMAT_MASK	GENMASK(15, 12)
 48#define		CSID_RDI_CFG0_DECODE_FORMAT_NOP		CSID_RDI_CFG0_DECODE_FORMAT_MASK
 49#define		CSID_RDI_CFG0_DT_MASK			GENMASK(21, 16)
 50#define		CSID_RDI_CFG0_VC_MASK			GENMASK(23, 22)
 51#define		CSID_RDI_CFG0_DTID_MASK			GENMASK(28, 27)
 52#define		CSID_RDI_CFG0_ENABLE			BIT(31)
 53
 54#define CSID_RDI_CTRL(rdi)					(0x308 + 0x100 * (rdi))
 55#define CSID_RDI_CTRL_HALT_AT_FRAME_BOUNDARY		0
 56#define CSID_RDI_CTRL_RESUME_AT_FRAME_BOUNDARY		1
 57
 58static void __csid_configure_rx(struct csid_device *csid,
 59				struct csid_phy_config *phy, int vc)
 60{
 61	u32 val;
 62
 63	val = FIELD_PREP(CSI2_RX_CFG0_NUM_ACTIVE_LANES_MASK, phy->lane_cnt - 1);
 64	val |= FIELD_PREP(CSI2_RX_CFG0_DLX_INPUT_SEL_MASK, phy->lane_assign);
 65	val |= FIELD_PREP(CSI2_RX_CFG0_PHY_NUM_SEL_MASK,
 66			  phy->csiphy_id + CSI2_RX_CFG0_PHY_NUM_SEL_BASE_IDX);
 67	writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0);
 68
 69	val = CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN;
 70	writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG1);
 71}
 72
 73static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi)
 74{
 75	writel_relaxed(!!enable, csid->base + CSID_RDI_CTRL(rdi));
 76}
 77
 78static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 vc)
 79{
 80	struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc];
 81	const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
 82								   csid->res->formats->nformats,
 83								   input_format->code);
 84	u8 lane_cnt = csid->phy.lane_cnt;
 85	u8 dt_id;
 86	u32 val;
 87
 88	if (!lane_cnt)
 89		lane_cnt = 4;
 90
 91	/*
 92	 * DT_ID is a two bit bitfield that is concatenated with
 93	 * the four least significant bits of the five bit VC
 94	 * bitfield to generate an internal CID value.
 95	 *
 96	 * CSID_RDI_CFG0(vc)
 97	 * DT_ID : 28:27
 98	 * VC    : 26:22
 99	 * DT    : 21:16
100	 *
101	 * CID   : VC 3:0 << 2 | DT_ID 1:0
102	 */
103	dt_id = vc & 0x03;
104
105	val = CSID_RDI_CFG0_DECODE_FORMAT_NOP; /* only for RDI path */
106	val |= FIELD_PREP(CSID_RDI_CFG0_DT_MASK, format->data_type);
107	val |= FIELD_PREP(CSID_RDI_CFG0_VC_MASK, vc);
108	val |= FIELD_PREP(CSID_RDI_CFG0_DTID_MASK, dt_id);
109
110	if (enable)
111		val |= CSID_RDI_CFG0_ENABLE;
112
113	dev_dbg(csid->camss->dev, "CSID%u: Stream %s (dt:0x%x vc=%u)\n",
114		csid->id, enable ? "enable" : "disable", format->data_type, vc);
115
116	writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc));
117}
118
119static void csid_configure_stream(struct csid_device *csid, u8 enable)
120{
121	int i;
122
123	for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++) {
124		if (csid->phy.en_vc & BIT(i)) {
125			__csid_configure_rdi_stream(csid, enable, i);
126			__csid_configure_rx(csid, &csid->phy, i);
127			__csid_ctrl_rdi(csid, enable, i);
128		}
129	}
130}
131
132static int csid_reset(struct csid_device *csid)
133{
134	unsigned long time;
135
136	writel_relaxed(CSID_IRQ_MASK_RST_DONE, csid->base + CSID_IRQ_MASK);
137	writel_relaxed(CSID_IRQ_MASK_RST_DONE, csid->base + CSID_IRQ_CLEAR);
138	writel_relaxed(CSID_IRQ_CMD_CLEAR, csid->base + CSID_IRQ_CMD);
139
140	reinit_completion(&csid->reset_complete);
141
142	/* Reset with registers preserved */
143	writel(CSID_RST_IRQ | CSID_RST_IFE_CLK | CSID_RST_PHY_CLK | CSID_RST_CSID_CLK,
144	       csid->base + CSID_RST_STROBES);
145
146	time = wait_for_completion_timeout(&csid->reset_complete,
147					   msecs_to_jiffies(CSID_RESET_TIMEOUT_MS));
148	if (!time) {
149		dev_err(csid->camss->dev, "CSID%u: reset timeout\n", csid->id);
150		return -EIO;
151	}
152
153	dev_dbg(csid->camss->dev, "CSID%u: reset done\n", csid->id);
154
155	return 0;
156}
157
158static irqreturn_t csid_isr(int irq, void *dev)
159{
160	struct csid_device *csid = dev;
161	u32 val;
162
163	val = readl_relaxed(csid->base + CSID_IRQ_STATUS);
164	writel_relaxed(val, csid->base + CSID_IRQ_CLEAR);
165	writel_relaxed(CSID_IRQ_CMD_CLEAR, csid->base + CSID_IRQ_CMD);
166
167	if (val & CSID_IRQ_MASK_RST_DONE)
168		complete(&csid->reset_complete);
169	else
170		dev_warn_ratelimited(csid->camss->dev, "Spurious CSID interrupt\n");
171
172	return IRQ_HANDLED;
173}
174
175static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val)
176{
177	return -EOPNOTSUPP; /* Not part of CSID */
178}
179
180static void csid_subdev_init(struct csid_device *csid) {}
181
182const struct csid_hw_ops csid_ops_340 = {
183	.configure_testgen_pattern = csid_configure_testgen_pattern,
184	.configure_stream = csid_configure_stream,
185	.hw_version = csid_hw_version,
186	.isr = csid_isr,
187	.reset = csid_reset,
188	.src_pad_code = csid_src_pad_code,
189	.subdev_init = csid_subdev_init,
190};