imx-pxp.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Freescale PXP Register Definitions
   4 *
   5 * based on pxp_dma_v3.h, Xml Revision: 1.77, Template Revision: 1.3
   6 *
   7 * Copyright 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
   8 */
   9
  10#ifndef __IMX_PXP_H__
  11#define __IMX_PXP_H__
  12
  13#define HW_PXP_CTRL	(0x00000000)
  14#define HW_PXP_CTRL_SET	(0x00000004)
  15#define HW_PXP_CTRL_CLR	(0x00000008)
  16#define HW_PXP_CTRL_TOG	(0x0000000c)
  17
  18#define BM_PXP_CTRL_SFTRST 0x80000000
  19#define BF_PXP_CTRL_SFTRST(v) \
  20	(((v) << 31) & BM_PXP_CTRL_SFTRST)
  21#define BM_PXP_CTRL_CLKGATE 0x40000000
  22#define BF_PXP_CTRL_CLKGATE(v)  \
  23	(((v) << 30) & BM_PXP_CTRL_CLKGATE)
  24#define BM_PXP_CTRL_RSVD4 0x20000000
  25#define BF_PXP_CTRL_RSVD4(v)  \
  26	(((v) << 29) & BM_PXP_CTRL_RSVD4)
  27#define BM_PXP_CTRL_EN_REPEAT 0x10000000
  28#define BF_PXP_CTRL_EN_REPEAT(v)  \
  29	(((v) << 28) & BM_PXP_CTRL_EN_REPEAT)
  30#define BM_PXP_CTRL_ENABLE_ROTATE1 0x08000000
  31#define BF_PXP_CTRL_ENABLE_ROTATE1(v)  \
  32	(((v) << 27) & BM_PXP_CTRL_ENABLE_ROTATE1)
  33#define BM_PXP_CTRL_ENABLE_ROTATE0 0x04000000
  34#define BF_PXP_CTRL_ENABLE_ROTATE0(v)  \
  35	(((v) << 26) & BM_PXP_CTRL_ENABLE_ROTATE0)
  36#define BM_PXP_CTRL_ENABLE_LUT 0x02000000
  37#define BF_PXP_CTRL_ENABLE_LUT(v)  \
  38	(((v) << 25) & BM_PXP_CTRL_ENABLE_LUT)
  39#define BM_PXP_CTRL_ENABLE_CSC2 0x01000000
  40#define BF_PXP_CTRL_ENABLE_CSC2(v)  \
  41	(((v) << 24) & BM_PXP_CTRL_ENABLE_CSC2)
  42#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000
  43#define BF_PXP_CTRL_BLOCK_SIZE(v)  \
  44	(((v) << 23) & BM_PXP_CTRL_BLOCK_SIZE)
  45#define BV_PXP_CTRL_BLOCK_SIZE__8X8   0x0
  46#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1
  47#define BM_PXP_CTRL_RSVD1 0x00400000
  48#define BF_PXP_CTRL_RSVD1(v)  \
  49	(((v) << 22) & BM_PXP_CTRL_RSVD1)
  50#define BM_PXP_CTRL_ENABLE_ALPHA_B 0x00200000
  51#define BF_PXP_CTRL_ENABLE_ALPHA_B(v)  \
  52	(((v) << 21) & BM_PXP_CTRL_ENABLE_ALPHA_B)
  53#define BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE 0x00100000
  54#define BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(v)  \
  55	(((v) << 20) & BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE)
  56#define BM_PXP_CTRL_ENABLE_WFE_B 0x00080000
  57#define BF_PXP_CTRL_ENABLE_WFE_B(v)  \
  58	(((v) << 19) & BM_PXP_CTRL_ENABLE_WFE_B)
  59#define BM_PXP_CTRL_ENABLE_WFE_A 0x00040000
  60#define BF_PXP_CTRL_ENABLE_WFE_A(v)  \
  61	(((v) << 18) & BM_PXP_CTRL_ENABLE_WFE_A)
  62#define BM_PXP_CTRL_ENABLE_DITHER 0x00020000
  63#define BF_PXP_CTRL_ENABLE_DITHER(v)  \
  64	(((v) << 17) & BM_PXP_CTRL_ENABLE_DITHER)
  65#define BM_PXP_CTRL_ENABLE_PS_AS_OUT 0x00010000
  66#define BF_PXP_CTRL_ENABLE_PS_AS_OUT(v)  \
  67	(((v) << 16) & BM_PXP_CTRL_ENABLE_PS_AS_OUT)
  68#define BM_PXP_CTRL_VFLIP1 0x00008000
  69#define BF_PXP_CTRL_VFLIP1(v)  \
  70	(((v) << 15) & BM_PXP_CTRL_VFLIP1)
  71#define BM_PXP_CTRL_HFLIP1 0x00004000
  72#define BF_PXP_CTRL_HFLIP1(v)  \
  73	(((v) << 14) & BM_PXP_CTRL_HFLIP1)
  74#define BP_PXP_CTRL_ROTATE1      12
  75#define BM_PXP_CTRL_ROTATE1 0x00003000
  76#define BF_PXP_CTRL_ROTATE1(v)  \
  77	(((v) << 12) & BM_PXP_CTRL_ROTATE1)
  78#define BV_PXP_CTRL_ROTATE1__ROT_0   0x0
  79#define BV_PXP_CTRL_ROTATE1__ROT_90  0x1
  80#define BV_PXP_CTRL_ROTATE1__ROT_180 0x2
  81#define BV_PXP_CTRL_ROTATE1__ROT_270 0x3
  82#define BM_PXP_CTRL_VFLIP0 0x00000800
  83#define BF_PXP_CTRL_VFLIP0(v)  \
  84	(((v) << 11) & BM_PXP_CTRL_VFLIP0)
  85#define BM_PXP_CTRL_HFLIP0 0x00000400
  86#define BF_PXP_CTRL_HFLIP0(v)  \
  87	(((v) << 10) & BM_PXP_CTRL_HFLIP0)
  88#define BP_PXP_CTRL_ROTATE0      8
  89#define BM_PXP_CTRL_ROTATE0 0x00000300
  90#define BF_PXP_CTRL_ROTATE0(v)  \
  91	(((v) << 8) & BM_PXP_CTRL_ROTATE0)
  92#define BV_PXP_CTRL_ROTATE0__ROT_0   0x0
  93#define BV_PXP_CTRL_ROTATE0__ROT_90  0x1
  94#define BV_PXP_CTRL_ROTATE0__ROT_180 0x2
  95#define BV_PXP_CTRL_ROTATE0__ROT_270 0x3
  96#define BP_PXP_CTRL_RSVD0      6
  97#define BM_PXP_CTRL_RSVD0 0x000000C0
  98#define BF_PXP_CTRL_RSVD0(v)  \
  99	(((v) << 6) & BM_PXP_CTRL_RSVD0)
 100#define BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP 0x00000020
 101#define BF_PXP_CTRL_HANDSHAKE_ABORT_SKIP(v)  \
 102	(((v) << 5) & BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP)
 103#define BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE 0x00000010
 104#define BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE(v)  \
 105	(((v) << 4) & BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE)
 106#define BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE 0x00000008
 107#define BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE(v)  \
 108	(((v) << 3) & BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE)
 109#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004
 110#define BF_PXP_CTRL_NEXT_IRQ_ENABLE(v)  \
 111	(((v) << 2) & BM_PXP_CTRL_NEXT_IRQ_ENABLE)
 112#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002
 113#define BF_PXP_CTRL_IRQ_ENABLE(v)  \
 114	(((v) << 1) & BM_PXP_CTRL_IRQ_ENABLE)
 115#define BM_PXP_CTRL_ENABLE 0x00000001
 116#define BF_PXP_CTRL_ENABLE(v)  \
 117	(((v) << 0) & BM_PXP_CTRL_ENABLE)
 118
 119#define HW_PXP_STAT	(0x00000010)
 120#define HW_PXP_STAT_SET	(0x00000014)
 121#define HW_PXP_STAT_CLR	(0x00000018)
 122#define HW_PXP_STAT_TOG	(0x0000001c)
 123
 124#define BP_PXP_STAT_BLOCKX      24
 125#define BM_PXP_STAT_BLOCKX 0xFF000000
 126#define BF_PXP_STAT_BLOCKX(v) \
 127	(((v) << 24) & BM_PXP_STAT_BLOCKX)
 128#define BP_PXP_STAT_BLOCKY      16
 129#define BM_PXP_STAT_BLOCKY 0x00FF0000
 130#define BF_PXP_STAT_BLOCKY(v)  \
 131	(((v) << 16) & BM_PXP_STAT_BLOCKY)
 132#define BP_PXP_STAT_AXI_ERROR_ID_1      12
 133#define BM_PXP_STAT_AXI_ERROR_ID_1 0x0000F000
 134#define BF_PXP_STAT_AXI_ERROR_ID_1(v)  \
 135	(((v) << 12) & BM_PXP_STAT_AXI_ERROR_ID_1)
 136#define BM_PXP_STAT_RSVD2 0x00000800
 137#define BF_PXP_STAT_RSVD2(v)  \
 138	(((v) << 11) & BM_PXP_STAT_RSVD2)
 139#define BM_PXP_STAT_AXI_READ_ERROR_1 0x00000400
 140#define BF_PXP_STAT_AXI_READ_ERROR_1(v)  \
 141	(((v) << 10) & BM_PXP_STAT_AXI_READ_ERROR_1)
 142#define BM_PXP_STAT_AXI_WRITE_ERROR_1 0x00000200
 143#define BF_PXP_STAT_AXI_WRITE_ERROR_1(v)  \
 144	(((v) << 9) & BM_PXP_STAT_AXI_WRITE_ERROR_1)
 145#define BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ 0x00000100
 146#define BF_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(v)  \
 147	(((v) << 8) & BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ)
 148#define BP_PXP_STAT_AXI_ERROR_ID_0      4
 149#define BM_PXP_STAT_AXI_ERROR_ID_0 0x000000F0
 150#define BF_PXP_STAT_AXI_ERROR_ID_0(v)  \
 151	(((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID_0)
 152#define BM_PXP_STAT_NEXT_IRQ 0x00000008
 153#define BF_PXP_STAT_NEXT_IRQ(v)  \
 154	(((v) << 3) & BM_PXP_STAT_NEXT_IRQ)
 155#define BM_PXP_STAT_AXI_READ_ERROR_0 0x00000004
 156#define BF_PXP_STAT_AXI_READ_ERROR_0(v)  \
 157	(((v) << 2) & BM_PXP_STAT_AXI_READ_ERROR_0)
 158#define BM_PXP_STAT_AXI_WRITE_ERROR_0 0x00000002
 159#define BF_PXP_STAT_AXI_WRITE_ERROR_0(v)  \
 160	(((v) << 1) & BM_PXP_STAT_AXI_WRITE_ERROR_0)
 161#define BM_PXP_STAT_IRQ0 0x00000001
 162#define BF_PXP_STAT_IRQ0(v)  \
 163	(((v) << 0) & BM_PXP_STAT_IRQ0)
 164
 165#define HW_PXP_OUT_CTRL	(0x00000020)
 166#define HW_PXP_OUT_CTRL_SET	(0x00000024)
 167#define HW_PXP_OUT_CTRL_CLR	(0x00000028)
 168#define HW_PXP_OUT_CTRL_TOG	(0x0000002c)
 169
 170#define BP_PXP_OUT_CTRL_ALPHA      24
 171#define BM_PXP_OUT_CTRL_ALPHA 0xFF000000
 172#define BF_PXP_OUT_CTRL_ALPHA(v) \
 173	(((v) << 24) & BM_PXP_OUT_CTRL_ALPHA)
 174#define BM_PXP_OUT_CTRL_ALPHA_OUTPUT 0x00800000
 175#define BF_PXP_OUT_CTRL_ALPHA_OUTPUT(v)  \
 176	(((v) << 23) & BM_PXP_OUT_CTRL_ALPHA_OUTPUT)
 177#define BP_PXP_OUT_CTRL_RSVD1      10
 178#define BM_PXP_OUT_CTRL_RSVD1 0x007FFC00
 179#define BF_PXP_OUT_CTRL_RSVD1(v)  \
 180	(((v) << 10) & BM_PXP_OUT_CTRL_RSVD1)
 181#define BP_PXP_OUT_CTRL_INTERLACED_OUTPUT      8
 182#define BM_PXP_OUT_CTRL_INTERLACED_OUTPUT 0x00000300
 183#define BF_PXP_OUT_CTRL_INTERLACED_OUTPUT(v)  \
 184	(((v) << 8) & BM_PXP_OUT_CTRL_INTERLACED_OUTPUT)
 185#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0
 186#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD0      0x1
 187#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD1      0x2
 188#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__INTERLACED  0x3
 189#define BP_PXP_OUT_CTRL_RSVD0      5
 190#define BM_PXP_OUT_CTRL_RSVD0 0x000000E0
 191#define BF_PXP_OUT_CTRL_RSVD0(v)  \
 192	(((v) << 5) & BM_PXP_OUT_CTRL_RSVD0)
 193#define BP_PXP_OUT_CTRL_FORMAT      0
 194#define BM_PXP_OUT_CTRL_FORMAT 0x0000001F
 195#define BF_PXP_OUT_CTRL_FORMAT(v)  \
 196	(((v) << 0) & BM_PXP_OUT_CTRL_FORMAT)
 197#define BV_PXP_OUT_CTRL_FORMAT__ARGB8888  0x0
 198#define BV_PXP_OUT_CTRL_FORMAT__RGB888    0x4
 199#define BV_PXP_OUT_CTRL_FORMAT__RGB888P   0x5
 200#define BV_PXP_OUT_CTRL_FORMAT__ARGB1555  0x8
 201#define BV_PXP_OUT_CTRL_FORMAT__ARGB4444  0x9
 202#define BV_PXP_OUT_CTRL_FORMAT__RGB555    0xC
 203#define BV_PXP_OUT_CTRL_FORMAT__RGB444    0xD
 204#define BV_PXP_OUT_CTRL_FORMAT__RGB565    0xE
 205#define BV_PXP_OUT_CTRL_FORMAT__YUV1P444  0x10
 206#define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12
 207#define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13
 208#define BV_PXP_OUT_CTRL_FORMAT__Y8	0x14
 209#define BV_PXP_OUT_CTRL_FORMAT__Y4	0x15
 210#define BV_PXP_OUT_CTRL_FORMAT__YUV2P422  0x18
 211#define BV_PXP_OUT_CTRL_FORMAT__YUV2P420  0x19
 212#define BV_PXP_OUT_CTRL_FORMAT__YVU2P422  0x1A
 213#define BV_PXP_OUT_CTRL_FORMAT__YVU2P420  0x1B
 214
 215#define HW_PXP_OUT_BUF	(0x00000030)
 216
 217#define BP_PXP_OUT_BUF_ADDR      0
 218#define BM_PXP_OUT_BUF_ADDR 0xFFFFFFFF
 219#define BF_PXP_OUT_BUF_ADDR(v)   (v)
 220
 221#define HW_PXP_OUT_BUF2	(0x00000040)
 222
 223#define BP_PXP_OUT_BUF2_ADDR      0
 224#define BM_PXP_OUT_BUF2_ADDR 0xFFFFFFFF
 225#define BF_PXP_OUT_BUF2_ADDR(v)   (v)
 226
 227#define HW_PXP_OUT_PITCH	(0x00000050)
 228
 229#define BP_PXP_OUT_PITCH_RSVD      16
 230#define BM_PXP_OUT_PITCH_RSVD 0xFFFF0000
 231#define BF_PXP_OUT_PITCH_RSVD(v) \
 232	(((v) << 16) & BM_PXP_OUT_PITCH_RSVD)
 233#define BP_PXP_OUT_PITCH_PITCH      0
 234#define BM_PXP_OUT_PITCH_PITCH 0x0000FFFF
 235#define BF_PXP_OUT_PITCH_PITCH(v)  \
 236	(((v) << 0) & BM_PXP_OUT_PITCH_PITCH)
 237
 238#define HW_PXP_OUT_LRC	(0x00000060)
 239
 240#define BP_PXP_OUT_LRC_RSVD1      30
 241#define BM_PXP_OUT_LRC_RSVD1 0xC0000000
 242#define BF_PXP_OUT_LRC_RSVD1(v) \
 243	(((v) << 30) & BM_PXP_OUT_LRC_RSVD1)
 244#define BP_PXP_OUT_LRC_X      16
 245#define BM_PXP_OUT_LRC_X 0x3FFF0000
 246#define BF_PXP_OUT_LRC_X(v)  \
 247	(((v) << 16) & BM_PXP_OUT_LRC_X)
 248#define BP_PXP_OUT_LRC_RSVD0      14
 249#define BM_PXP_OUT_LRC_RSVD0 0x0000C000
 250#define BF_PXP_OUT_LRC_RSVD0(v)  \
 251	(((v) << 14) & BM_PXP_OUT_LRC_RSVD0)
 252#define BP_PXP_OUT_LRC_Y      0
 253#define BM_PXP_OUT_LRC_Y 0x00003FFF
 254#define BF_PXP_OUT_LRC_Y(v)  \
 255	(((v) << 0) & BM_PXP_OUT_LRC_Y)
 256
 257#define HW_PXP_OUT_PS_ULC	(0x00000070)
 258
 259#define BP_PXP_OUT_PS_ULC_RSVD1      30
 260#define BM_PXP_OUT_PS_ULC_RSVD1 0xC0000000
 261#define BF_PXP_OUT_PS_ULC_RSVD1(v) \
 262	(((v) << 30) & BM_PXP_OUT_PS_ULC_RSVD1)
 263#define BP_PXP_OUT_PS_ULC_X      16
 264#define BM_PXP_OUT_PS_ULC_X 0x3FFF0000
 265#define BF_PXP_OUT_PS_ULC_X(v)  \
 266	(((v) << 16) & BM_PXP_OUT_PS_ULC_X)
 267#define BP_PXP_OUT_PS_ULC_RSVD0      14
 268#define BM_PXP_OUT_PS_ULC_RSVD0 0x0000C000
 269#define BF_PXP_OUT_PS_ULC_RSVD0(v)  \
 270	(((v) << 14) & BM_PXP_OUT_PS_ULC_RSVD0)
 271#define BP_PXP_OUT_PS_ULC_Y      0
 272#define BM_PXP_OUT_PS_ULC_Y 0x00003FFF
 273#define BF_PXP_OUT_PS_ULC_Y(v)  \
 274	(((v) << 0) & BM_PXP_OUT_PS_ULC_Y)
 275
 276#define HW_PXP_OUT_PS_LRC	(0x00000080)
 277
 278#define BP_PXP_OUT_PS_LRC_RSVD1      30
 279#define BM_PXP_OUT_PS_LRC_RSVD1 0xC0000000
 280#define BF_PXP_OUT_PS_LRC_RSVD1(v) \
 281	(((v) << 30) & BM_PXP_OUT_PS_LRC_RSVD1)
 282#define BP_PXP_OUT_PS_LRC_X      16
 283#define BM_PXP_OUT_PS_LRC_X 0x3FFF0000
 284#define BF_PXP_OUT_PS_LRC_X(v)  \
 285	(((v) << 16) & BM_PXP_OUT_PS_LRC_X)
 286#define BP_PXP_OUT_PS_LRC_RSVD0      14
 287#define BM_PXP_OUT_PS_LRC_RSVD0 0x0000C000
 288#define BF_PXP_OUT_PS_LRC_RSVD0(v)  \
 289	(((v) << 14) & BM_PXP_OUT_PS_LRC_RSVD0)
 290#define BP_PXP_OUT_PS_LRC_Y      0
 291#define BM_PXP_OUT_PS_LRC_Y 0x00003FFF
 292#define BF_PXP_OUT_PS_LRC_Y(v)  \
 293	(((v) << 0) & BM_PXP_OUT_PS_LRC_Y)
 294
 295#define HW_PXP_OUT_AS_ULC	(0x00000090)
 296
 297#define BP_PXP_OUT_AS_ULC_RSVD1      30
 298#define BM_PXP_OUT_AS_ULC_RSVD1 0xC0000000
 299#define BF_PXP_OUT_AS_ULC_RSVD1(v) \
 300	(((v) << 30) & BM_PXP_OUT_AS_ULC_RSVD1)
 301#define BP_PXP_OUT_AS_ULC_X      16
 302#define BM_PXP_OUT_AS_ULC_X 0x3FFF0000
 303#define BF_PXP_OUT_AS_ULC_X(v)  \
 304	(((v) << 16) & BM_PXP_OUT_AS_ULC_X)
 305#define BP_PXP_OUT_AS_ULC_RSVD0      14
 306#define BM_PXP_OUT_AS_ULC_RSVD0 0x0000C000
 307#define BF_PXP_OUT_AS_ULC_RSVD0(v)  \
 308	(((v) << 14) & BM_PXP_OUT_AS_ULC_RSVD0)
 309#define BP_PXP_OUT_AS_ULC_Y      0
 310#define BM_PXP_OUT_AS_ULC_Y 0x00003FFF
 311#define BF_PXP_OUT_AS_ULC_Y(v)  \
 312	(((v) << 0) & BM_PXP_OUT_AS_ULC_Y)
 313
 314#define HW_PXP_OUT_AS_LRC	(0x000000a0)
 315
 316#define BP_PXP_OUT_AS_LRC_RSVD1      30
 317#define BM_PXP_OUT_AS_LRC_RSVD1 0xC0000000
 318#define BF_PXP_OUT_AS_LRC_RSVD1(v) \
 319	(((v) << 30) & BM_PXP_OUT_AS_LRC_RSVD1)
 320#define BP_PXP_OUT_AS_LRC_X      16
 321#define BM_PXP_OUT_AS_LRC_X 0x3FFF0000
 322#define BF_PXP_OUT_AS_LRC_X(v)  \
 323	(((v) << 16) & BM_PXP_OUT_AS_LRC_X)
 324#define BP_PXP_OUT_AS_LRC_RSVD0      14
 325#define BM_PXP_OUT_AS_LRC_RSVD0 0x0000C000
 326#define BF_PXP_OUT_AS_LRC_RSVD0(v)  \
 327	(((v) << 14) & BM_PXP_OUT_AS_LRC_RSVD0)
 328#define BP_PXP_OUT_AS_LRC_Y      0
 329#define BM_PXP_OUT_AS_LRC_Y 0x00003FFF
 330#define BF_PXP_OUT_AS_LRC_Y(v)  \
 331	(((v) << 0) & BM_PXP_OUT_AS_LRC_Y)
 332
 333#define HW_PXP_PS_CTRL	(0x000000b0)
 334#define HW_PXP_PS_CTRL_SET	(0x000000b4)
 335#define HW_PXP_PS_CTRL_CLR	(0x000000b8)
 336#define HW_PXP_PS_CTRL_TOG	(0x000000bc)
 337
 338#define BP_PXP_PS_CTRL_RSVD1      12
 339#define BM_PXP_PS_CTRL_RSVD1 0xFFFFF000
 340#define BF_PXP_PS_CTRL_RSVD1(v) \
 341	(((v) << 12) & BM_PXP_PS_CTRL_RSVD1)
 342#define BP_PXP_PS_CTRL_DECX      10
 343#define BM_PXP_PS_CTRL_DECX 0x00000C00
 344#define BF_PXP_PS_CTRL_DECX(v)  \
 345	(((v) << 10) & BM_PXP_PS_CTRL_DECX)
 346#define BV_PXP_PS_CTRL_DECX__DISABLE 0x0
 347#define BV_PXP_PS_CTRL_DECX__DECX2   0x1
 348#define BV_PXP_PS_CTRL_DECX__DECX4   0x2
 349#define BV_PXP_PS_CTRL_DECX__DECX8   0x3
 350#define BP_PXP_PS_CTRL_DECY      8
 351#define BM_PXP_PS_CTRL_DECY 0x00000300
 352#define BF_PXP_PS_CTRL_DECY(v)  \
 353	(((v) << 8) & BM_PXP_PS_CTRL_DECY)
 354#define BV_PXP_PS_CTRL_DECY__DISABLE 0x0
 355#define BV_PXP_PS_CTRL_DECY__DECY2   0x1
 356#define BV_PXP_PS_CTRL_DECY__DECY4   0x2
 357#define BV_PXP_PS_CTRL_DECY__DECY8   0x3
 358#define BM_PXP_PS_CTRL_RSVD0 0x00000080
 359#define BF_PXP_PS_CTRL_RSVD0(v)  \
 360	(((v) << 7) & BM_PXP_PS_CTRL_RSVD0)
 361#define BM_PXP_PS_CTRL_WB_SWAP 0x00000040
 362#define BF_PXP_PS_CTRL_WB_SWAP(v)  \
 363	(((v) << 6) & BM_PXP_PS_CTRL_WB_SWAP)
 364#define BP_PXP_PS_CTRL_FORMAT      0
 365#define BM_PXP_PS_CTRL_FORMAT 0x0000003F
 366#define BF_PXP_PS_CTRL_FORMAT(v)  \
 367	(((v) << 0) & BM_PXP_PS_CTRL_FORMAT)
 368#define BV_PXP_PS_CTRL_FORMAT__RGB888    0x4
 369#define BV_PXP_PS_CTRL_FORMAT__RGB555    0xC
 370#define BV_PXP_PS_CTRL_FORMAT__RGB444    0xD
 371#define BV_PXP_PS_CTRL_FORMAT__RGB565    0xE
 372#define BV_PXP_PS_CTRL_FORMAT__YUV1P444  0x10
 373#define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12
 374#define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13
 375#define BV_PXP_PS_CTRL_FORMAT__Y8	0x14
 376#define BV_PXP_PS_CTRL_FORMAT__Y4	0x15
 377#define BV_PXP_PS_CTRL_FORMAT__YUV2P422  0x18
 378#define BV_PXP_PS_CTRL_FORMAT__YUV2P420  0x19
 379#define BV_PXP_PS_CTRL_FORMAT__YVU2P422  0x1A
 380#define BV_PXP_PS_CTRL_FORMAT__YVU2P420  0x1B
 381#define BV_PXP_PS_CTRL_FORMAT__YUV422    0x1E
 382#define BV_PXP_PS_CTRL_FORMAT__YUV420    0x1F
 383
 384#define HW_PXP_PS_BUF	(0x000000c0)
 385
 386#define BP_PXP_PS_BUF_ADDR      0
 387#define BM_PXP_PS_BUF_ADDR 0xFFFFFFFF
 388#define BF_PXP_PS_BUF_ADDR(v)   (v)
 389
 390#define HW_PXP_PS_UBUF	(0x000000d0)
 391
 392#define BP_PXP_PS_UBUF_ADDR      0
 393#define BM_PXP_PS_UBUF_ADDR 0xFFFFFFFF
 394#define BF_PXP_PS_UBUF_ADDR(v)   (v)
 395
 396#define HW_PXP_PS_VBUF	(0x000000e0)
 397
 398#define BP_PXP_PS_VBUF_ADDR      0
 399#define BM_PXP_PS_VBUF_ADDR 0xFFFFFFFF
 400#define BF_PXP_PS_VBUF_ADDR(v)   (v)
 401
 402#define HW_PXP_PS_PITCH	(0x000000f0)
 403
 404#define BP_PXP_PS_PITCH_RSVD      16
 405#define BM_PXP_PS_PITCH_RSVD 0xFFFF0000
 406#define BF_PXP_PS_PITCH_RSVD(v) \
 407	(((v) << 16) & BM_PXP_PS_PITCH_RSVD)
 408#define BP_PXP_PS_PITCH_PITCH      0
 409#define BM_PXP_PS_PITCH_PITCH 0x0000FFFF
 410#define BF_PXP_PS_PITCH_PITCH(v)  \
 411	(((v) << 0) & BM_PXP_PS_PITCH_PITCH)
 412
 413#define HW_PXP_PS_BACKGROUND_0	(0x00000100)
 414
 415#define BP_PXP_PS_BACKGROUND_0_RSVD      24
 416#define BM_PXP_PS_BACKGROUND_0_RSVD 0xFF000000
 417#define BF_PXP_PS_BACKGROUND_0_RSVD(v) \
 418	(((v) << 24) & BM_PXP_PS_BACKGROUND_0_RSVD)
 419#define BP_PXP_PS_BACKGROUND_0_COLOR      0
 420#define BM_PXP_PS_BACKGROUND_0_COLOR 0x00FFFFFF
 421#define BF_PXP_PS_BACKGROUND_0_COLOR(v)  \
 422	(((v) << 0) & BM_PXP_PS_BACKGROUND_0_COLOR)
 423
 424#define HW_PXP_PS_SCALE	(0x00000110)
 425
 426#define BM_PXP_PS_SCALE_RSVD2 0x80000000
 427#define BF_PXP_PS_SCALE_RSVD2(v) \
 428	(((v) << 31) & BM_PXP_PS_SCALE_RSVD2)
 429#define BP_PXP_PS_SCALE_YSCALE      16
 430#define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000
 431#define BF_PXP_PS_SCALE_YSCALE(v)  \
 432	(((v) << 16) & BM_PXP_PS_SCALE_YSCALE)
 433#define BM_PXP_PS_SCALE_RSVD1 0x00008000
 434#define BF_PXP_PS_SCALE_RSVD1(v)  \
 435	(((v) << 15) & BM_PXP_PS_SCALE_RSVD1)
 436#define BP_PXP_PS_SCALE_XSCALE      0
 437#define BM_PXP_PS_SCALE_XSCALE 0x00007FFF
 438#define BF_PXP_PS_SCALE_XSCALE(v)  \
 439	(((v) << 0) & BM_PXP_PS_SCALE_XSCALE)
 440
 441#define HW_PXP_PS_OFFSET	(0x00000120)
 442
 443#define BP_PXP_PS_OFFSET_RSVD2      28
 444#define BM_PXP_PS_OFFSET_RSVD2 0xF0000000
 445#define BF_PXP_PS_OFFSET_RSVD2(v) \
 446	(((v) << 28) & BM_PXP_PS_OFFSET_RSVD2)
 447#define BP_PXP_PS_OFFSET_YOFFSET      16
 448#define BM_PXP_PS_OFFSET_YOFFSET 0x0FFF0000
 449#define BF_PXP_PS_OFFSET_YOFFSET(v)  \
 450	(((v) << 16) & BM_PXP_PS_OFFSET_YOFFSET)
 451#define BP_PXP_PS_OFFSET_RSVD1      12
 452#define BM_PXP_PS_OFFSET_RSVD1 0x0000F000
 453#define BF_PXP_PS_OFFSET_RSVD1(v)  \
 454	(((v) << 12) & BM_PXP_PS_OFFSET_RSVD1)
 455#define BP_PXP_PS_OFFSET_XOFFSET      0
 456#define BM_PXP_PS_OFFSET_XOFFSET 0x00000FFF
 457#define BF_PXP_PS_OFFSET_XOFFSET(v)  \
 458	(((v) << 0) & BM_PXP_PS_OFFSET_XOFFSET)
 459
 460#define HW_PXP_PS_CLRKEYLOW_0	(0x00000130)
 461
 462#define BP_PXP_PS_CLRKEYLOW_0_RSVD1      24
 463#define BM_PXP_PS_CLRKEYLOW_0_RSVD1 0xFF000000
 464#define BF_PXP_PS_CLRKEYLOW_0_RSVD1(v) \
 465	(((v) << 24) & BM_PXP_PS_CLRKEYLOW_0_RSVD1)
 466#define BP_PXP_PS_CLRKEYLOW_0_PIXEL      0
 467#define BM_PXP_PS_CLRKEYLOW_0_PIXEL 0x00FFFFFF
 468#define BF_PXP_PS_CLRKEYLOW_0_PIXEL(v)  \
 469	(((v) << 0) & BM_PXP_PS_CLRKEYLOW_0_PIXEL)
 470
 471#define HW_PXP_PS_CLRKEYHIGH_0	(0x00000140)
 472
 473#define BP_PXP_PS_CLRKEYHIGH_0_RSVD1      24
 474#define BM_PXP_PS_CLRKEYHIGH_0_RSVD1 0xFF000000
 475#define BF_PXP_PS_CLRKEYHIGH_0_RSVD1(v) \
 476	(((v) << 24) & BM_PXP_PS_CLRKEYHIGH_0_RSVD1)
 477#define BP_PXP_PS_CLRKEYHIGH_0_PIXEL      0
 478#define BM_PXP_PS_CLRKEYHIGH_0_PIXEL 0x00FFFFFF
 479#define BF_PXP_PS_CLRKEYHIGH_0_PIXEL(v)  \
 480	(((v) << 0) & BM_PXP_PS_CLRKEYHIGH_0_PIXEL)
 481
 482#define HW_PXP_AS_CTRL	(0x00000150)
 483
 484#define BP_PXP_AS_CTRL_RSVD1      22
 485#define BM_PXP_AS_CTRL_RSVD1 0xFFC00000
 486#define BF_PXP_AS_CTRL_RSVD1(v) \
 487	(((v) << 22) & BM_PXP_AS_CTRL_RSVD1)
 488#define BM_PXP_AS_CTRL_ALPHA1_INVERT 0x00200000
 489#define BF_PXP_AS_CTRL_ALPHA1_INVERT(v)  \
 490	(((v) << 21) & BM_PXP_AS_CTRL_ALPHA1_INVERT)
 491#define BM_PXP_AS_CTRL_ALPHA0_INVERT 0x00100000
 492#define BF_PXP_AS_CTRL_ALPHA0_INVERT(v)  \
 493	(((v) << 20) & BM_PXP_AS_CTRL_ALPHA0_INVERT)
 494#define BP_PXP_AS_CTRL_ROP      16
 495#define BM_PXP_AS_CTRL_ROP 0x000F0000
 496#define BF_PXP_AS_CTRL_ROP(v)  \
 497	(((v) << 16) & BM_PXP_AS_CTRL_ROP)
 498#define BV_PXP_AS_CTRL_ROP__MASKAS     0x0
 499#define BV_PXP_AS_CTRL_ROP__MASKNOTAS  0x1
 500#define BV_PXP_AS_CTRL_ROP__MASKASNOT  0x2
 501#define BV_PXP_AS_CTRL_ROP__MERGEAS    0x3
 502#define BV_PXP_AS_CTRL_ROP__MERGENOTAS 0x4
 503#define BV_PXP_AS_CTRL_ROP__MERGEASNOT 0x5
 504#define BV_PXP_AS_CTRL_ROP__NOTCOPYAS  0x6
 505#define BV_PXP_AS_CTRL_ROP__NOT	0x7
 506#define BV_PXP_AS_CTRL_ROP__NOTMASKAS  0x8
 507#define BV_PXP_AS_CTRL_ROP__NOTMERGEAS 0x9
 508#define BV_PXP_AS_CTRL_ROP__XORAS      0xA
 509#define BV_PXP_AS_CTRL_ROP__NOTXORAS   0xB
 510#define BP_PXP_AS_CTRL_ALPHA      8
 511#define BM_PXP_AS_CTRL_ALPHA 0x0000FF00
 512#define BF_PXP_AS_CTRL_ALPHA(v)  \
 513	(((v) << 8) & BM_PXP_AS_CTRL_ALPHA)
 514#define BP_PXP_AS_CTRL_FORMAT      4
 515#define BM_PXP_AS_CTRL_FORMAT 0x000000F0
 516#define BF_PXP_AS_CTRL_FORMAT(v)  \
 517	(((v) << 4) & BM_PXP_AS_CTRL_FORMAT)
 518#define BV_PXP_AS_CTRL_FORMAT__ARGB8888 0x0
 519#define BV_PXP_AS_CTRL_FORMAT__RGBA8888 0x1
 520#define BV_PXP_AS_CTRL_FORMAT__RGB888   0x4
 521#define BV_PXP_AS_CTRL_FORMAT__ARGB1555 0x8
 522#define BV_PXP_AS_CTRL_FORMAT__ARGB4444 0x9
 523#define BV_PXP_AS_CTRL_FORMAT__RGB555   0xC
 524#define BV_PXP_AS_CTRL_FORMAT__RGB444   0xD
 525#define BV_PXP_AS_CTRL_FORMAT__RGB565   0xE
 526#define BM_PXP_AS_CTRL_ENABLE_COLORKEY 0x00000008
 527#define BF_PXP_AS_CTRL_ENABLE_COLORKEY(v)  \
 528	(((v) << 3) & BM_PXP_AS_CTRL_ENABLE_COLORKEY)
 529#define BP_PXP_AS_CTRL_ALPHA_CTRL      1
 530#define BM_PXP_AS_CTRL_ALPHA_CTRL 0x00000006
 531#define BF_PXP_AS_CTRL_ALPHA_CTRL(v)  \
 532	(((v) << 1) & BM_PXP_AS_CTRL_ALPHA_CTRL)
 533#define BV_PXP_AS_CTRL_ALPHA_CTRL__Embedded 0x0
 534#define BV_PXP_AS_CTRL_ALPHA_CTRL__Override 0x1
 535#define BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply 0x2
 536#define BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs     0x3
 537#define BM_PXP_AS_CTRL_RSVD0 0x00000001
 538#define BF_PXP_AS_CTRL_RSVD0(v)  \
 539	(((v) << 0) & BM_PXP_AS_CTRL_RSVD0)
 540
 541#define HW_PXP_AS_BUF	(0x00000160)
 542
 543#define BP_PXP_AS_BUF_ADDR      0
 544#define BM_PXP_AS_BUF_ADDR 0xFFFFFFFF
 545#define BF_PXP_AS_BUF_ADDR(v)   (v)
 546
 547#define HW_PXP_AS_PITCH	(0x00000170)
 548
 549#define BP_PXP_AS_PITCH_RSVD      16
 550#define BM_PXP_AS_PITCH_RSVD 0xFFFF0000
 551#define BF_PXP_AS_PITCH_RSVD(v) \
 552	(((v) << 16) & BM_PXP_AS_PITCH_RSVD)
 553#define BP_PXP_AS_PITCH_PITCH      0
 554#define BM_PXP_AS_PITCH_PITCH 0x0000FFFF
 555#define BF_PXP_AS_PITCH_PITCH(v)  \
 556	(((v) << 0) & BM_PXP_AS_PITCH_PITCH)
 557
 558#define HW_PXP_AS_CLRKEYLOW_0	(0x00000180)
 559
 560#define BP_PXP_AS_CLRKEYLOW_0_RSVD1      24
 561#define BM_PXP_AS_CLRKEYLOW_0_RSVD1 0xFF000000
 562#define BF_PXP_AS_CLRKEYLOW_0_RSVD1(v) \
 563	(((v) << 24) & BM_PXP_AS_CLRKEYLOW_0_RSVD1)
 564#define BP_PXP_AS_CLRKEYLOW_0_PIXEL      0
 565#define BM_PXP_AS_CLRKEYLOW_0_PIXEL 0x00FFFFFF
 566#define BF_PXP_AS_CLRKEYLOW_0_PIXEL(v)  \
 567	(((v) << 0) & BM_PXP_AS_CLRKEYLOW_0_PIXEL)
 568
 569#define HW_PXP_AS_CLRKEYHIGH_0	(0x00000190)
 570
 571#define BP_PXP_AS_CLRKEYHIGH_0_RSVD1      24
 572#define BM_PXP_AS_CLRKEYHIGH_0_RSVD1 0xFF000000
 573#define BF_PXP_AS_CLRKEYHIGH_0_RSVD1(v) \
 574	(((v) << 24) & BM_PXP_AS_CLRKEYHIGH_0_RSVD1)
 575#define BP_PXP_AS_CLRKEYHIGH_0_PIXEL      0
 576#define BM_PXP_AS_CLRKEYHIGH_0_PIXEL 0x00FFFFFF
 577#define BF_PXP_AS_CLRKEYHIGH_0_PIXEL(v)  \
 578	(((v) << 0) & BM_PXP_AS_CLRKEYHIGH_0_PIXEL)
 579
 580#define HW_PXP_CSC1_COEF0	(0x000001a0)
 581
 582#define BM_PXP_CSC1_COEF0_YCBCR_MODE 0x80000000
 583#define BF_PXP_CSC1_COEF0_YCBCR_MODE(v) \
 584	(((v) << 31) & BM_PXP_CSC1_COEF0_YCBCR_MODE)
 585#define BM_PXP_CSC1_COEF0_BYPASS 0x40000000
 586#define BF_PXP_CSC1_COEF0_BYPASS(v)  \
 587	(((v) << 30) & BM_PXP_CSC1_COEF0_BYPASS)
 588#define BM_PXP_CSC1_COEF0_RSVD1 0x20000000
 589#define BF_PXP_CSC1_COEF0_RSVD1(v)  \
 590	(((v) << 29) & BM_PXP_CSC1_COEF0_RSVD1)
 591#define BP_PXP_CSC1_COEF0_C0      18
 592#define BM_PXP_CSC1_COEF0_C0 0x1FFC0000
 593#define BF_PXP_CSC1_COEF0_C0(v)  \
 594	(((v) << 18) & BM_PXP_CSC1_COEF0_C0)
 595#define BP_PXP_CSC1_COEF0_UV_OFFSET      9
 596#define BM_PXP_CSC1_COEF0_UV_OFFSET 0x0003FE00
 597
 598/*
 599 * We use v * (1 << 9) instead of v << 9, to workaround a gcc5 bug.
 600 * The compiler cannot understand that the expression is constant.
 601 */
 602#define BF_PXP_CSC1_COEF0_UV_OFFSET(v)  \
 603	(((v) * (1 << 9)) & BM_PXP_CSC1_COEF0_UV_OFFSET)
 604#define BP_PXP_CSC1_COEF0_Y_OFFSET      0
 605#define BM_PXP_CSC1_COEF0_Y_OFFSET 0x000001FF
 606#define BF_PXP_CSC1_COEF0_Y_OFFSET(v)  \
 607	((v) & BM_PXP_CSC1_COEF0_Y_OFFSET)
 608
 609#define HW_PXP_CSC1_COEF1	(0x000001b0)
 610
 611#define BP_PXP_CSC1_COEF1_RSVD1      27
 612#define BM_PXP_CSC1_COEF1_RSVD1 0xF8000000
 613#define BF_PXP_CSC1_COEF1_RSVD1(v) \
 614	(((v) << 27) & BM_PXP_CSC1_COEF1_RSVD1)
 615#define BP_PXP_CSC1_COEF1_C1      16
 616#define BM_PXP_CSC1_COEF1_C1 0x07FF0000
 617#define BF_PXP_CSC1_COEF1_C1(v)  \
 618	(((v) << 16) & BM_PXP_CSC1_COEF1_C1)
 619#define BP_PXP_CSC1_COEF1_RSVD0      11
 620#define BM_PXP_CSC1_COEF1_RSVD0 0x0000F800
 621#define BF_PXP_CSC1_COEF1_RSVD0(v)  \
 622	(((v) << 11) & BM_PXP_CSC1_COEF1_RSVD0)
 623#define BP_PXP_CSC1_COEF1_C4      0
 624#define BM_PXP_CSC1_COEF1_C4 0x000007FF
 625#define BF_PXP_CSC1_COEF1_C4(v)  \
 626	(((v) << 0) & BM_PXP_CSC1_COEF1_C4)
 627
 628#define HW_PXP_CSC1_COEF2	(0x000001c0)
 629
 630#define BP_PXP_CSC1_COEF2_RSVD1      27
 631#define BM_PXP_CSC1_COEF2_RSVD1 0xF8000000
 632#define BF_PXP_CSC1_COEF2_RSVD1(v) \
 633	(((v) << 27) & BM_PXP_CSC1_COEF2_RSVD1)
 634#define BP_PXP_CSC1_COEF2_C2      16
 635#define BM_PXP_CSC1_COEF2_C2 0x07FF0000
 636#define BF_PXP_CSC1_COEF2_C2(v)  \
 637	(((v) << 16) & BM_PXP_CSC1_COEF2_C2)
 638#define BP_PXP_CSC1_COEF2_RSVD0      11
 639#define BM_PXP_CSC1_COEF2_RSVD0 0x0000F800
 640#define BF_PXP_CSC1_COEF2_RSVD0(v)  \
 641	(((v) << 11) & BM_PXP_CSC1_COEF2_RSVD0)
 642#define BP_PXP_CSC1_COEF2_C3      0
 643#define BM_PXP_CSC1_COEF2_C3 0x000007FF
 644#define BF_PXP_CSC1_COEF2_C3(v)  \
 645	(((v) << 0) & BM_PXP_CSC1_COEF2_C3)
 646
 647#define HW_PXP_CSC2_CTRL	(0x000001d0)
 648
 649#define BP_PXP_CSC2_CTRL_RSVD      3
 650#define BM_PXP_CSC2_CTRL_RSVD 0xFFFFFFF8
 651#define BF_PXP_CSC2_CTRL_RSVD(v) \
 652	(((v) << 3) & BM_PXP_CSC2_CTRL_RSVD)
 653#define BP_PXP_CSC2_CTRL_CSC_MODE      1
 654#define BM_PXP_CSC2_CTRL_CSC_MODE 0x00000006
 655#define BF_PXP_CSC2_CTRL_CSC_MODE(v)  \
 656	(((v) << 1) & BM_PXP_CSC2_CTRL_CSC_MODE)
 657#define BV_PXP_CSC2_CTRL_CSC_MODE__YUV2RGB   0x0
 658#define BV_PXP_CSC2_CTRL_CSC_MODE__YCbCr2RGB 0x1
 659#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV   0x2
 660#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr 0x3
 661#define BM_PXP_CSC2_CTRL_BYPASS 0x00000001
 662#define BF_PXP_CSC2_CTRL_BYPASS(v)  \
 663	(((v) << 0) & BM_PXP_CSC2_CTRL_BYPASS)
 664
 665#define HW_PXP_CSC2_COEF0	(0x000001e0)
 666
 667#define BP_PXP_CSC2_COEF0_RSVD1      27
 668#define BM_PXP_CSC2_COEF0_RSVD1 0xF8000000
 669#define BF_PXP_CSC2_COEF0_RSVD1(v) \
 670	(((v) << 27) & BM_PXP_CSC2_COEF0_RSVD1)
 671#define BP_PXP_CSC2_COEF0_A2      16
 672#define BM_PXP_CSC2_COEF0_A2 0x07FF0000
 673#define BF_PXP_CSC2_COEF0_A2(v)  \
 674	(((v) << 16) & BM_PXP_CSC2_COEF0_A2)
 675#define BP_PXP_CSC2_COEF0_RSVD0      11
 676#define BM_PXP_CSC2_COEF0_RSVD0 0x0000F800
 677#define BF_PXP_CSC2_COEF0_RSVD0(v)  \
 678	(((v) << 11) & BM_PXP_CSC2_COEF0_RSVD0)
 679#define BP_PXP_CSC2_COEF0_A1      0
 680#define BM_PXP_CSC2_COEF0_A1 0x000007FF
 681#define BF_PXP_CSC2_COEF0_A1(v)  \
 682	(((v) << 0) & BM_PXP_CSC2_COEF0_A1)
 683
 684#define HW_PXP_CSC2_COEF1	(0x000001f0)
 685
 686#define BP_PXP_CSC2_COEF1_RSVD1      27
 687#define BM_PXP_CSC2_COEF1_RSVD1 0xF8000000
 688#define BF_PXP_CSC2_COEF1_RSVD1(v) \
 689	(((v) << 27) & BM_PXP_CSC2_COEF1_RSVD1)
 690#define BP_PXP_CSC2_COEF1_B1      16
 691#define BM_PXP_CSC2_COEF1_B1 0x07FF0000
 692#define BF_PXP_CSC2_COEF1_B1(v)  \
 693	(((v) << 16) & BM_PXP_CSC2_COEF1_B1)
 694#define BP_PXP_CSC2_COEF1_RSVD0      11
 695#define BM_PXP_CSC2_COEF1_RSVD0 0x0000F800
 696#define BF_PXP_CSC2_COEF1_RSVD0(v)  \
 697	(((v) << 11) & BM_PXP_CSC2_COEF1_RSVD0)
 698#define BP_PXP_CSC2_COEF1_A3      0
 699#define BM_PXP_CSC2_COEF1_A3 0x000007FF
 700#define BF_PXP_CSC2_COEF1_A3(v)  \
 701	(((v) << 0) & BM_PXP_CSC2_COEF1_A3)
 702
 703#define HW_PXP_CSC2_COEF2	(0x00000200)
 704
 705#define BP_PXP_CSC2_COEF2_RSVD1      27
 706#define BM_PXP_CSC2_COEF2_RSVD1 0xF8000000
 707#define BF_PXP_CSC2_COEF2_RSVD1(v) \
 708	(((v) << 27) & BM_PXP_CSC2_COEF2_RSVD1)
 709#define BP_PXP_CSC2_COEF2_B3      16
 710#define BM_PXP_CSC2_COEF2_B3 0x07FF0000
 711#define BF_PXP_CSC2_COEF2_B3(v)  \
 712	(((v) << 16) & BM_PXP_CSC2_COEF2_B3)
 713#define BP_PXP_CSC2_COEF2_RSVD0      11
 714#define BM_PXP_CSC2_COEF2_RSVD0 0x0000F800
 715#define BF_PXP_CSC2_COEF2_RSVD0(v)  \
 716	(((v) << 11) & BM_PXP_CSC2_COEF2_RSVD0)
 717#define BP_PXP_CSC2_COEF2_B2      0
 718#define BM_PXP_CSC2_COEF2_B2 0x000007FF
 719#define BF_PXP_CSC2_COEF2_B2(v)  \
 720	(((v) << 0) & BM_PXP_CSC2_COEF2_B2)
 721
 722#define HW_PXP_CSC2_COEF3	(0x00000210)
 723
 724#define BP_PXP_CSC2_COEF3_RSVD1      27
 725#define BM_PXP_CSC2_COEF3_RSVD1 0xF8000000
 726#define BF_PXP_CSC2_COEF3_RSVD1(v) \
 727	(((v) << 27) & BM_PXP_CSC2_COEF3_RSVD1)
 728#define BP_PXP_CSC2_COEF3_C2      16
 729#define BM_PXP_CSC2_COEF3_C2 0x07FF0000
 730#define BF_PXP_CSC2_COEF3_C2(v)  \
 731	(((v) << 16) & BM_PXP_CSC2_COEF3_C2)
 732#define BP_PXP_CSC2_COEF3_RSVD0      11
 733#define BM_PXP_CSC2_COEF3_RSVD0 0x0000F800
 734#define BF_PXP_CSC2_COEF3_RSVD0(v)  \
 735	(((v) << 11) & BM_PXP_CSC2_COEF3_RSVD0)
 736#define BP_PXP_CSC2_COEF3_C1      0
 737#define BM_PXP_CSC2_COEF3_C1 0x000007FF
 738#define BF_PXP_CSC2_COEF3_C1(v)  \
 739	(((v) << 0) & BM_PXP_CSC2_COEF3_C1)
 740
 741#define HW_PXP_CSC2_COEF4	(0x00000220)
 742
 743#define BP_PXP_CSC2_COEF4_RSVD1      25
 744#define BM_PXP_CSC2_COEF4_RSVD1 0xFE000000
 745#define BF_PXP_CSC2_COEF4_RSVD1(v) \
 746	(((v) << 25) & BM_PXP_CSC2_COEF4_RSVD1)
 747#define BP_PXP_CSC2_COEF4_D1      16
 748#define BM_PXP_CSC2_COEF4_D1 0x01FF0000
 749#define BF_PXP_CSC2_COEF4_D1(v)  \
 750	(((v) << 16) & BM_PXP_CSC2_COEF4_D1)
 751#define BP_PXP_CSC2_COEF4_RSVD0      11
 752#define BM_PXP_CSC2_COEF4_RSVD0 0x0000F800
 753#define BF_PXP_CSC2_COEF4_RSVD0(v)  \
 754	(((v) << 11) & BM_PXP_CSC2_COEF4_RSVD0)
 755#define BP_PXP_CSC2_COEF4_C3      0
 756#define BM_PXP_CSC2_COEF4_C3 0x000007FF
 757#define BF_PXP_CSC2_COEF4_C3(v)  \
 758	(((v) << 0) & BM_PXP_CSC2_COEF4_C3)
 759
 760#define HW_PXP_CSC2_COEF5	(0x00000230)
 761
 762#define BP_PXP_CSC2_COEF5_RSVD1      25
 763#define BM_PXP_CSC2_COEF5_RSVD1 0xFE000000
 764#define BF_PXP_CSC2_COEF5_RSVD1(v) \
 765	(((v) << 25) & BM_PXP_CSC2_COEF5_RSVD1)
 766#define BP_PXP_CSC2_COEF5_D3      16
 767#define BM_PXP_CSC2_COEF5_D3 0x01FF0000
 768#define BF_PXP_CSC2_COEF5_D3(v)  \
 769	(((v) << 16) & BM_PXP_CSC2_COEF5_D3)
 770#define BP_PXP_CSC2_COEF5_RSVD0      9
 771#define BM_PXP_CSC2_COEF5_RSVD0 0x0000FE00
 772#define BF_PXP_CSC2_COEF5_RSVD0(v)  \
 773	(((v) << 9) & BM_PXP_CSC2_COEF5_RSVD0)
 774#define BP_PXP_CSC2_COEF5_D2      0
 775#define BM_PXP_CSC2_COEF5_D2 0x000001FF
 776#define BF_PXP_CSC2_COEF5_D2(v)  \
 777	(((v) << 0) & BM_PXP_CSC2_COEF5_D2)
 778
 779#define HW_PXP_LUT_CTRL	(0x00000240)
 780
 781#define BM_PXP_LUT_CTRL_BYPASS 0x80000000
 782#define BF_PXP_LUT_CTRL_BYPASS(v) \
 783	(((v) << 31) & BM_PXP_LUT_CTRL_BYPASS)
 784#define BP_PXP_LUT_CTRL_RSVD3      26
 785#define BM_PXP_LUT_CTRL_RSVD3 0x7C000000
 786#define BF_PXP_LUT_CTRL_RSVD3(v)  \
 787	(((v) << 26) & BM_PXP_LUT_CTRL_RSVD3)
 788#define BP_PXP_LUT_CTRL_LOOKUP_MODE      24
 789#define BM_PXP_LUT_CTRL_LOOKUP_MODE 0x03000000
 790#define BF_PXP_LUT_CTRL_LOOKUP_MODE(v)  \
 791	(((v) << 24) & BM_PXP_LUT_CTRL_LOOKUP_MODE)
 792#define BV_PXP_LUT_CTRL_LOOKUP_MODE__CACHE_RGB565  0x0
 793#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8     0x1
 794#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB444 0x2
 795#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB454 0x3
 796#define BP_PXP_LUT_CTRL_RSVD2      18
 797#define BM_PXP_LUT_CTRL_RSVD2 0x00FC0000
 798#define BF_PXP_LUT_CTRL_RSVD2(v)  \
 799	(((v) << 18) & BM_PXP_LUT_CTRL_RSVD2)
 800#define BP_PXP_LUT_CTRL_OUT_MODE      16
 801#define BM_PXP_LUT_CTRL_OUT_MODE 0x00030000
 802#define BF_PXP_LUT_CTRL_OUT_MODE(v)  \
 803	(((v) << 16) & BM_PXP_LUT_CTRL_OUT_MODE)
 804#define BV_PXP_LUT_CTRL_OUT_MODE__RESERVED    0x0
 805#define BV_PXP_LUT_CTRL_OUT_MODE__Y8	  0x1
 806#define BV_PXP_LUT_CTRL_OUT_MODE__RGBW4444CFA 0x2
 807#define BV_PXP_LUT_CTRL_OUT_MODE__RGB888      0x3
 808#define BP_PXP_LUT_CTRL_RSVD1      11
 809#define BM_PXP_LUT_CTRL_RSVD1 0x0000F800
 810#define BF_PXP_LUT_CTRL_RSVD1(v)  \
 811	(((v) << 11) & BM_PXP_LUT_CTRL_RSVD1)
 812#define BM_PXP_LUT_CTRL_SEL_8KB 0x00000400
 813#define BF_PXP_LUT_CTRL_SEL_8KB(v)  \
 814	(((v) << 10) & BM_PXP_LUT_CTRL_SEL_8KB)
 815#define BM_PXP_LUT_CTRL_LRU_UPD 0x00000200
 816#define BF_PXP_LUT_CTRL_LRU_UPD(v)  \
 817	(((v) << 9) & BM_PXP_LUT_CTRL_LRU_UPD)
 818#define BM_PXP_LUT_CTRL_INVALID 0x00000100
 819#define BF_PXP_LUT_CTRL_INVALID(v)  \
 820	(((v) << 8) & BM_PXP_LUT_CTRL_INVALID)
 821#define BP_PXP_LUT_CTRL_RSVD0      1
 822#define BM_PXP_LUT_CTRL_RSVD0 0x000000FE
 823#define BF_PXP_LUT_CTRL_RSVD0(v)  \
 824	(((v) << 1) & BM_PXP_LUT_CTRL_RSVD0)
 825#define BM_PXP_LUT_CTRL_DMA_START 0x00000001
 826#define BF_PXP_LUT_CTRL_DMA_START(v)  \
 827	(((v) << 0) & BM_PXP_LUT_CTRL_DMA_START)
 828
 829#define HW_PXP_LUT_ADDR	(0x00000250)
 830
 831#define BM_PXP_LUT_ADDR_RSVD2 0x80000000
 832#define BF_PXP_LUT_ADDR_RSVD2(v) \
 833	(((v) << 31) & BM_PXP_LUT_ADDR_RSVD2)
 834#define BP_PXP_LUT_ADDR_NUM_BYTES      16
 835#define BM_PXP_LUT_ADDR_NUM_BYTES 0x7FFF0000
 836#define BF_PXP_LUT_ADDR_NUM_BYTES(v)  \
 837	(((v) << 16) & BM_PXP_LUT_ADDR_NUM_BYTES)
 838#define BP_PXP_LUT_ADDR_RSVD1      14
 839#define BM_PXP_LUT_ADDR_RSVD1 0x0000C000
 840#define BF_PXP_LUT_ADDR_RSVD1(v)  \
 841	(((v) << 14) & BM_PXP_LUT_ADDR_RSVD1)
 842#define BP_PXP_LUT_ADDR_ADDR      0
 843#define BM_PXP_LUT_ADDR_ADDR 0x00003FFF
 844#define BF_PXP_LUT_ADDR_ADDR(v)  \
 845	(((v) << 0) & BM_PXP_LUT_ADDR_ADDR)
 846
 847#define HW_PXP_LUT_DATA	(0x00000260)
 848
 849#define BP_PXP_LUT_DATA_DATA      0
 850#define BM_PXP_LUT_DATA_DATA 0xFFFFFFFF
 851#define BF_PXP_LUT_DATA_DATA(v)   (v)
 852
 853#define HW_PXP_LUT_EXTMEM	(0x00000270)
 854
 855#define BP_PXP_LUT_EXTMEM_ADDR      0
 856#define BM_PXP_LUT_EXTMEM_ADDR 0xFFFFFFFF
 857#define BF_PXP_LUT_EXTMEM_ADDR(v)   (v)
 858
 859#define HW_PXP_CFA	(0x00000280)
 860
 861#define BP_PXP_CFA_DATA      0
 862#define BM_PXP_CFA_DATA 0xFFFFFFFF
 863#define BF_PXP_CFA_DATA(v)   (v)
 864
 865#define HW_PXP_ALPHA_A_CTRL	(0x00000290)
 866
 867#define BP_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA      24
 868#define BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA 0xFF000000
 869#define BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA(v) \
 870	(((v) << 24) & BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA)
 871#define BP_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA      16
 872#define BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA 0x00FF0000
 873#define BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA(v)  \
 874	(((v) << 16) & BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA)
 875#define BP_PXP_ALPHA_A_CTRL_RSVD0      14
 876#define BM_PXP_ALPHA_A_CTRL_RSVD0 0x0000C000
 877#define BF_PXP_ALPHA_A_CTRL_RSVD0(v)  \
 878	(((v) << 14) & BM_PXP_ALPHA_A_CTRL_RSVD0)
 879#define BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE 0x00002000
 880#define BF_PXP_ALPHA_A_CTRL_S1_COLOR_MODE(v)  \
 881	(((v) << 13) & BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE)
 882#define BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__0 0x0
 883#define BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__1 0x1
 884#define BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE 0x00001000
 885#define BF_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE(v)  \
 886	(((v) << 12) & BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE)
 887#define BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__0 0x0
 888#define BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__1 0x1
 889#define BP_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE      10
 890#define BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE 0x00000C00
 891#define BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE(v)  \
 892	(((v) << 10) & BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE)
 893#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__0 0x0
 894#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__1 0x0
 895#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__2 0x0
 896#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__3 0x0
 897#define BP_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE      8
 898#define BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE 0x00000300
 899#define BF_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE(v)  \
 900	(((v) << 8) & BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE)
 901#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__0 0x0
 902#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__1 0x1
 903#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__2 0x2
 904#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__3 0x3
 905#define BM_PXP_ALPHA_A_CTRL_RSVD1 0x00000080
 906#define BF_PXP_ALPHA_A_CTRL_RSVD1(v)  \
 907	(((v) << 7) & BM_PXP_ALPHA_A_CTRL_RSVD1)
 908#define BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE 0x00000040
 909#define BF_PXP_ALPHA_A_CTRL_S0_COLOR_MODE(v)  \
 910	(((v) << 6) & BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE)
 911#define BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__0 0x0
 912#define BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__1 0x1
 913#define BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE 0x00000020
 914#define BF_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE(v)  \
 915	(((v) << 5) & BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE)
 916#define BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__0 0x0
 917#define BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__1 0x1
 918#define BP_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE      3
 919#define BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE 0x00000018
 920#define BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE(v)  \
 921	(((v) << 3) & BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE)
 922#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__0 0x0
 923#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__1 0x1
 924#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__2 0x2
 925#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__3 0x3
 926#define BP_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE      1
 927#define BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE 0x00000006
 928#define BF_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE(v)  \
 929	(((v) << 1) & BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE)
 930#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__0 0x0
 931#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__1 0x1
 932#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__2 0x2
 933#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__3 0x3
 934#define BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE 0x00000001
 935#define BF_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE(v)  \
 936	(((v) << 0) & BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE)
 937#define BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__0 0x0
 938#define BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__1 0x1
 939
 940#define HW_PXP_ALPHA_B_CTRL	(0x000002a0)
 941
 942#define BP_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA      24
 943#define BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA 0xFF000000
 944#define BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA(v) \
 945	(((v) << 24) & BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA)
 946#define BP_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA      16
 947#define BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA 0x00FF0000
 948#define BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA(v)  \
 949	(((v) << 16) & BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA)
 950#define BP_PXP_ALPHA_B_CTRL_RSVD0      14
 951#define BM_PXP_ALPHA_B_CTRL_RSVD0 0x0000C000
 952#define BF_PXP_ALPHA_B_CTRL_RSVD0(v)  \
 953	(((v) << 14) & BM_PXP_ALPHA_B_CTRL_RSVD0)
 954#define BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE 0x00002000
 955#define BF_PXP_ALPHA_B_CTRL_S1_COLOR_MODE(v)  \
 956	(((v) << 13) & BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE)
 957#define BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__0 0x0
 958#define BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__1 0x1
 959#define BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE 0x00001000
 960#define BF_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE(v)  \
 961	(((v) << 12) & BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE)
 962#define BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__0 0x0
 963#define BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__1 0x1
 964#define BP_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE      10
 965#define BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE 0x00000C00
 966#define BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE(v)  \
 967	(((v) << 10) & BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE)
 968#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__0 0x0
 969#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__1 0x1
 970#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__2 0x2
 971#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__3 0x3
 972#define BP_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE      8
 973#define BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE 0x00000300
 974#define BF_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE(v)  \
 975	(((v) << 8) & BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE)
 976#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__0 0x0
 977#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__1 0x1
 978#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__2 0x2
 979#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__3 0x3
 980#define BM_PXP_ALPHA_B_CTRL_RSVD1 0x00000080
 981#define BF_PXP_ALPHA_B_CTRL_RSVD1(v)  \
 982	(((v) << 7) & BM_PXP_ALPHA_B_CTRL_RSVD1)
 983#define BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE 0x00000040
 984#define BF_PXP_ALPHA_B_CTRL_S0_COLOR_MODE(v)  \
 985	(((v) << 6) & BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE)
 986#define BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__0 0x0
 987#define BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__1 0x1
 988#define BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE 0x00000020
 989#define BF_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE(v)  \
 990	(((v) << 5) & BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE)
 991#define BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__0 0x0
 992#define BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__1 0x1
 993#define BP_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE      3
 994#define BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE 0x00000018
 995#define BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE(v)  \
 996	(((v) << 3) & BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE)
 997#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__0 0x0
 998#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__1 0x1
 999#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__2 0x2
1000#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__3 0x3
1001#define BP_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE      1
1002#define BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE 0x00000006
1003#define BF_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE(v)  \
1004	(((v) << 1) & BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE)
1005#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__0 0x0
1006#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__1 0x1
1007#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__2 0x2
1008#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__3 0x3
1009#define BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE 0x00000001
1010#define BF_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE(v)  \
1011	(((v) << 0) & BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE)
1012#define BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__0 0x0
1013#define BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__1 0x1
1014
1015#define HW_PXP_ALPHA_B_CTRL_1	(0x000002b0)
1016
1017#define BP_PXP_ALPHA_B_CTRL_1_RSVD0      8
1018#define BM_PXP_ALPHA_B_CTRL_1_RSVD0 0xFFFFFF00
1019#define BF_PXP_ALPHA_B_CTRL_1_RSVD0(v) \
1020	(((v) << 8) & BM_PXP_ALPHA_B_CTRL_1_RSVD0)
1021#define BP_PXP_ALPHA_B_CTRL_1_ROP      4
1022#define BM_PXP_ALPHA_B_CTRL_1_ROP 0x000000F0
1023#define BF_PXP_ALPHA_B_CTRL_1_ROP(v)  \
1024	(((v) << 4) & BM_PXP_ALPHA_B_CTRL_1_ROP)
1025#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKAS     0x0
1026#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKNOTAS  0x1
1027#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKASNOT  0x2
1028#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEAS    0x3
1029#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGENOTAS 0x4
1030#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEASNOT 0x5
1031#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTCOPYAS  0x6
1032#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOT	0x7
1033#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMASKAS  0x8
1034#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMERGEAS 0x9
1035#define BV_PXP_ALPHA_B_CTRL_1_ROP__XORAS      0xA
1036#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTXORAS   0xB
1037#define BP_PXP_ALPHA_B_CTRL_1_RSVD1      2
1038#define BM_PXP_ALPHA_B_CTRL_1_RSVD1 0x0000000C
1039#define BF_PXP_ALPHA_B_CTRL_1_RSVD1(v)  \
1040	(((v) << 2) & BM_PXP_ALPHA_B_CTRL_1_RSVD1)
1041#define BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE 0x00000002
1042#define BF_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE(v)  \
1043	(((v) << 1) & BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE)
1044#define BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE 0x00000001
1045#define BF_PXP_ALPHA_B_CTRL_1_ROP_ENABLE(v)  \
1046	(((v) << 0) & BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE)
1047
1048#define HW_PXP_PS_BACKGROUND_1	(0x000002c0)
1049
1050#define BP_PXP_PS_BACKGROUND_1_RSVD      24
1051#define BM_PXP_PS_BACKGROUND_1_RSVD 0xFF000000
1052#define BF_PXP_PS_BACKGROUND_1_RSVD(v) \
1053	(((v) << 24) & BM_PXP_PS_BACKGROUND_1_RSVD)
1054#define BP_PXP_PS_BACKGROUND_1_COLOR      0
1055#define BM_PXP_PS_BACKGROUND_1_COLOR 0x00FFFFFF
1056#define BF_PXP_PS_BACKGROUND_1_COLOR(v)  \
1057	(((v) << 0) & BM_PXP_PS_BACKGROUND_1_COLOR)
1058
1059#define HW_PXP_PS_CLRKEYLOW_1	(0x000002d0)
1060
1061#define BP_PXP_PS_CLRKEYLOW_1_RSVD1      24
1062#define BM_PXP_PS_CLRKEYLOW_1_RSVD1 0xFF000000
1063#define BF_PXP_PS_CLRKEYLOW_1_RSVD1(v) \
1064	(((v) << 24) & BM_PXP_PS_CLRKEYLOW_1_RSVD1)
1065#define BP_PXP_PS_CLRKEYLOW_1_PIXEL      0
1066#define BM_PXP_PS_CLRKEYLOW_1_PIXEL 0x00FFFFFF
1067#define BF_PXP_PS_CLRKEYLOW_1_PIXEL(v)  \
1068	(((v) << 0) & BM_PXP_PS_CLRKEYLOW_1_PIXEL)
1069
1070#define HW_PXP_PS_CLRKEYHIGH_1	(0x000002e0)
1071
1072#define BP_PXP_PS_CLRKEYHIGH_1_RSVD1      24
1073#define BM_PXP_PS_CLRKEYHIGH_1_RSVD1 0xFF000000
1074#define BF_PXP_PS_CLRKEYHIGH_1_RSVD1(v) \
1075	(((v) << 24) & BM_PXP_PS_CLRKEYHIGH_1_RSVD1)
1076#define BP_PXP_PS_CLRKEYHIGH_1_PIXEL      0
1077#define BM_PXP_PS_CLRKEYHIGH_1_PIXEL 0x00FFFFFF
1078#define BF_PXP_PS_CLRKEYHIGH_1_PIXEL(v)  \
1079	(((v) << 0) & BM_PXP_PS_CLRKEYHIGH_1_PIXEL)
1080
1081#define HW_PXP_AS_CLRKEYLOW_1	(0x000002f0)
1082
1083#define BP_PXP_AS_CLRKEYLOW_1_RSVD1      24
1084#define BM_PXP_AS_CLRKEYLOW_1_RSVD1 0xFF000000
1085#define BF_PXP_AS_CLRKEYLOW_1_RSVD1(v) \
1086	(((v) << 24) & BM_PXP_AS_CLRKEYLOW_1_RSVD1)
1087#define BP_PXP_AS_CLRKEYLOW_1_PIXEL      0
1088#define BM_PXP_AS_CLRKEYLOW_1_PIXEL 0x00FFFFFF
1089#define BF_PXP_AS_CLRKEYLOW_1_PIXEL(v)  \
1090	(((v) << 0) & BM_PXP_AS_CLRKEYLOW_1_PIXEL)
1091
1092#define HW_PXP_AS_CLRKEYHIGH_1	(0x00000300)
1093
1094#define BP_PXP_AS_CLRKEYHIGH_1_RSVD1      24
1095#define BM_PXP_AS_CLRKEYHIGH_1_RSVD1 0xFF000000
1096#define BF_PXP_AS_CLRKEYHIGH_1_RSVD1(v) \
1097	(((v) << 24) & BM_PXP_AS_CLRKEYHIGH_1_RSVD1)
1098#define BP_PXP_AS_CLRKEYHIGH_1_PIXEL      0
1099#define BM_PXP_AS_CLRKEYHIGH_1_PIXEL 0x00FFFFFF
1100#define BF_PXP_AS_CLRKEYHIGH_1_PIXEL(v)  \
1101	(((v) << 0) & BM_PXP_AS_CLRKEYHIGH_1_PIXEL)
1102
1103#define HW_PXP_CTRL2	(0x00000310)
1104#define HW_PXP_CTRL2_SET	(0x00000314)
1105#define HW_PXP_CTRL2_CLR	(0x00000318)
1106#define HW_PXP_CTRL2_TOG	(0x0000031c)
1107
1108#define BP_PXP_CTRL2_RSVD3      28
1109#define BM_PXP_CTRL2_RSVD3 0xF0000000
1110#define BF_PXP_CTRL2_RSVD3(v) \
1111	(((v) << 28) & BM_PXP_CTRL2_RSVD3)
1112#define BM_PXP_CTRL2_ENABLE_ROTATE1 0x08000000
1113#define BF_PXP_CTRL2_ENABLE_ROTATE1(v)  \
1114	(((v) << 27) & BM_PXP_CTRL2_ENABLE_ROTATE1)
1115#define BM_PXP_CTRL2_ENABLE_ROTATE0 0x04000000
1116#define BF_PXP_CTRL2_ENABLE_ROTATE0(v)  \
1117	(((v) << 26) & BM_PXP_CTRL2_ENABLE_ROTATE0)
1118#define BM_PXP_CTRL2_ENABLE_LUT 0x02000000
1119#define BF_PXP_CTRL2_ENABLE_LUT(v)  \
1120	(((v) << 25) & BM_PXP_CTRL2_ENABLE_LUT)
1121#define BM_PXP_CTRL2_ENABLE_CSC2 0x01000000
1122#define BF_PXP_CTRL2_ENABLE_CSC2(v)  \
1123	(((v) << 24) & BM_PXP_CTRL2_ENABLE_CSC2)
1124#define BM_PXP_CTRL2_BLOCK_SIZE 0x00800000
1125#define BF_PXP_CTRL2_BLOCK_SIZE(v)  \
1126	(((v) << 23) & BM_PXP_CTRL2_BLOCK_SIZE)
1127#define BV_PXP_CTRL2_BLOCK_SIZE__8X8   0x0
1128#define BV_PXP_CTRL2_BLOCK_SIZE__16X16 0x1
1129#define BM_PXP_CTRL2_RSVD2 0x00400000
1130#define BF_PXP_CTRL2_RSVD2(v)  \
1131	(((v) << 22) & BM_PXP_CTRL2_RSVD2)
1132#define BM_PXP_CTRL2_ENABLE_ALPHA_B 0x00200000
1133#define BF_PXP_CTRL2_ENABLE_ALPHA_B(v)  \
1134	(((v) << 21) & BM_PXP_CTRL2_ENABLE_ALPHA_B)
1135#define BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE 0x00100000
1136#define BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE(v)  \
1137	(((v) << 20) & BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE)
1138#define BM_PXP_CTRL2_ENABLE_WFE_B 0x00080000
1139#define BF_PXP_CTRL2_ENABLE_WFE_B(v)  \
1140	(((v) << 19) & BM_PXP_CTRL2_ENABLE_WFE_B)
1141#define BM_PXP_CTRL2_ENABLE_WFE_A 0x00040000
1142#define BF_PXP_CTRL2_ENABLE_WFE_A(v)  \
1143	(((v) << 18) & BM_PXP_CTRL2_ENABLE_WFE_A)
1144#define BM_PXP_CTRL2_ENABLE_DITHER 0x00020000
1145#define BF_PXP_CTRL2_ENABLE_DITHER(v)  \
1146	(((v) << 17) & BM_PXP_CTRL2_ENABLE_DITHER)
1147#define BM_PXP_CTRL2_RSVD1 0x00010000
1148#define BF_PXP_CTRL2_RSVD1(v)  \
1149	(((v) << 16) & BM_PXP_CTRL2_RSVD1)
1150#define BM_PXP_CTRL2_VFLIP1 0x00008000
1151#define BF_PXP_CTRL2_VFLIP1(v)  \
1152	(((v) << 15) & BM_PXP_CTRL2_VFLIP1)
1153#define BM_PXP_CTRL2_HFLIP1 0x00004000
1154#define BF_PXP_CTRL2_HFLIP1(v)  \
1155	(((v) << 14) & BM_PXP_CTRL2_HFLIP1)
1156#define BP_PXP_CTRL2_ROTATE1      12
1157#define BM_PXP_CTRL2_ROTATE1 0x00003000
1158#define BF_PXP_CTRL2_ROTATE1(v)  \
1159	(((v) << 12) & BM_PXP_CTRL2_ROTATE1)
1160#define BV_PXP_CTRL2_ROTATE1__ROT_0   0x0
1161#define BV_PXP_CTRL2_ROTATE1__ROT_90  0x1
1162#define BV_PXP_CTRL2_ROTATE1__ROT_180 0x2
1163#define BV_PXP_CTRL2_ROTATE1__ROT_270 0x3
1164#define BM_PXP_CTRL2_VFLIP0 0x00000800
1165#define BF_PXP_CTRL2_VFLIP0(v)  \
1166	(((v) << 11) & BM_PXP_CTRL2_VFLIP0)
1167#define BM_PXP_CTRL2_HFLIP0 0x00000400
1168#define BF_PXP_CTRL2_HFLIP0(v)  \
1169	(((v) << 10) & BM_PXP_CTRL2_HFLIP0)
1170#define BP_PXP_CTRL2_ROTATE0      8
1171#define BM_PXP_CTRL2_ROTATE0 0x00000300
1172#define BF_PXP_CTRL2_ROTATE0(v)  \
1173	(((v) << 8) & BM_PXP_CTRL2_ROTATE0)
1174#define BV_PXP_CTRL2_ROTATE0__ROT_0   0x0
1175#define BV_PXP_CTRL2_ROTATE0__ROT_90  0x1
1176#define BV_PXP_CTRL2_ROTATE0__ROT_180 0x2
1177#define BV_PXP_CTRL2_ROTATE0__ROT_270 0x3
1178#define BP_PXP_CTRL2_RSVD0      1
1179#define BM_PXP_CTRL2_RSVD0 0x000000FE
1180#define BF_PXP_CTRL2_RSVD0(v)  \
1181	(((v) << 1) & BM_PXP_CTRL2_RSVD0)
1182#define BM_PXP_CTRL2_ENABLE 0x00000001
1183#define BF_PXP_CTRL2_ENABLE(v)  \
1184	(((v) << 0) & BM_PXP_CTRL2_ENABLE)
1185
1186#define HW_PXP_POWER_REG0	(0x00000320)
1187
1188#define BP_PXP_POWER_REG0_CTRL      12
1189#define BM_PXP_POWER_REG0_CTRL 0xFFFFF000
1190#define BF_PXP_POWER_REG0_CTRL(v) \
1191	(((v) << 12) & BM_PXP_POWER_REG0_CTRL)
1192#define BP_PXP_POWER_REG0_ROT0_MEM_LP_STATE      9
1193#define BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE 0x00000E00
1194#define BF_PXP_POWER_REG0_ROT0_MEM_LP_STATE(v)  \
1195	(((v) << 9) & BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE)
1196#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__NONE 0x0
1197#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__LS   0x1
1198#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__DS   0x2
1199#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__SD   0x4
1200#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN      6
1201#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN 0x000001C0
1202#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN(v)  \
1203	(((v) << 6) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN)
1204#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__NONE 0x0
1205#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__LS   0x1
1206#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__DS   0x2
1207#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__SD   0x4
1208#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN      3
1209#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN 0x00000038
1210#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN(v)  \
1211	(((v) << 3) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN)
1212#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__NONE 0x0
1213#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__LS   0x1
1214#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__DS   0x2
1215#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__SD   0x4
1216#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0      0
1217#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0 0x00000007
1218#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0(v)  \
1219	(((v) << 0) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0)
1220#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__NONE 0x0
1221#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__LS   0x1
1222#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__DS   0x2
1223#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__SD   0x4
1224
1225#define HW_PXP_POWER_REG1	(0x00000330)
1226
1227#define BP_PXP_POWER_REG1_RSVD0      24
1228#define BM_PXP_POWER_REG1_RSVD0 0xFF000000
1229#define BF_PXP_POWER_REG1_RSVD0(v) \
1230	(((v) << 24) & BM_PXP_POWER_REG1_RSVD0)
1231#define BP_PXP_POWER_REG1_ALU_B_MEM_LP_STATE      21
1232#define BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE 0x00E00000
1233#define BF_PXP_POWER_REG1_ALU_B_MEM_LP_STATE(v)  \
1234	(((v) << 21) & BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE)
1235#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__NONE 0x0
1236#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__LS   0x1
1237#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__DS   0x2
1238#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__SD   0x4
1239#define BP_PXP_POWER_REG1_ALU_A_MEM_LP_STATE      18
1240#define BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE 0x001C0000
1241#define BF_PXP_POWER_REG1_ALU_A_MEM_LP_STATE(v)  \
1242	(((v) << 18) & BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE)
1243#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__NONE 0x0
1244#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__LS   0x1
1245#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__DS   0x2
1246#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__SD   0x4
1247#define BP_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE      15
1248#define BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE 0x00038000
1249#define BF_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE(v)  \
1250	(((v) << 15) & BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE)
1251#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__NONE 0x0
1252#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__LS   0x1
1253#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__DS   0x2
1254#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__SD   0x4
1255#define BP_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE      12
1256#define BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE 0x00007000
1257#define BF_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE(v)  \
1258	(((v) << 12) & BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE)
1259#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__NONE 0x0
1260#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__LS   0x1
1261#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__DS   0x2
1262#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__SD   0x4
1263#define BP_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE      9
1264#define BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE 0x00000E00
1265#define BF_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE(v)  \
1266	(((v) << 9) & BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE)
1267#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__NONE 0x0
1268#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__LS   0x1
1269#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__DS   0x2
1270#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__SD   0x4
1271#define BP_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE      6
1272#define BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE 0x000001C0
1273#define BF_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE(v)  \
1274	(((v) << 6) & BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE)
1275#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__NONE 0x0
1276#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__LS   0x1
1277#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__DS   0x2
1278#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__SD   0x4
1279#define BP_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE      3
1280#define BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE 0x00000038
1281#define BF_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE(v)  \
1282	(((v) << 3) & BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE)
1283#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__NONE 0x0
1284#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__LS   0x1
1285#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__DS   0x2
1286#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__SD   0x4
1287#define BP_PXP_POWER_REG1_ROT1_MEM_LP_STATE      0
1288#define BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE 0x00000007
1289#define BF_PXP_POWER_REG1_ROT1_MEM_LP_STATE(v)  \
1290	(((v) << 0) & BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE)
1291#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__NONE 0x0
1292#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__LS   0x1
1293#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__DS   0x2
1294#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__SD   0x4
1295
1296#define HW_PXP_DATA_PATH_CTRL0	(0x00000340)
1297#define HW_PXP_DATA_PATH_CTRL0_SET	(0x00000344)
1298#define HW_PXP_DATA_PATH_CTRL0_CLR	(0x00000348)
1299#define HW_PXP_DATA_PATH_CTRL0_TOG	(0x0000034c)
1300
1301#define BP_PXP_DATA_PATH_CTRL0_MUX15_SEL      30
1302#define BM_PXP_DATA_PATH_CTRL0_MUX15_SEL 0xC0000000
1303#define BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(v) \
1304	(((v) << 30) & BM_PXP_DATA_PATH_CTRL0_MUX15_SEL)
1305#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__0 0x0
1306#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__1 0x1
1307#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__2 0x2
1308#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__3 0x3
1309#define BP_PXP_DATA_PATH_CTRL0_MUX14_SEL      28
1310#define BM_PXP_DATA_PATH_CTRL0_MUX14_SEL 0x30000000
1311#define BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(v)  \
1312	(((v) << 28) & BM_PXP_DATA_PATH_CTRL0_MUX14_SEL)
1313#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__0 0x0
1314#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__1 0x1
1315#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__2 0x2
1316#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__3 0x3
1317#define BP_PXP_DATA_PATH_CTRL0_MUX13_SEL      26
1318#define BM_PXP_DATA_PATH_CTRL0_MUX13_SEL 0x0C000000
1319#define BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(v)  \
1320	(((v) << 26) & BM_PXP_DATA_PATH_CTRL0_MUX13_SEL)
1321#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__0 0x0
1322#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__1 0x1
1323#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__2 0x2
1324#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__3 0x3
1325#define BP_PXP_DATA_PATH_CTRL0_MUX12_SEL      24
1326#define BM_PXP_DATA_PATH_CTRL0_MUX12_SEL 0x03000000
1327#define BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(v)  \
1328	(((v) << 24) & BM_PXP_DATA_PATH_CTRL0_MUX12_SEL)
1329#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__0 0x0
1330#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__1 0x1
1331#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__2 0x2
1332#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__3 0x3
1333#define BP_PXP_DATA_PATH_CTRL0_MUX11_SEL      22
1334#define BM_PXP_DATA_PATH_CTRL0_MUX11_SEL 0x00C00000
1335#define BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(v)  \
1336	(((v) << 22) & BM_PXP_DATA_PATH_CTRL0_MUX11_SEL)
1337#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__0 0x0
1338#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__1 0x1
1339#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__2 0x2
1340#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__3 0x3
1341#define BP_PXP_DATA_PATH_CTRL0_MUX10_SEL      20
1342#define BM_PXP_DATA_PATH_CTRL0_MUX10_SEL 0x00300000
1343#define BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(v)  \
1344	(((v) << 20) & BM_PXP_DATA_PATH_CTRL0_MUX10_SEL)
1345#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__0 0x0
1346#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__1 0x1
1347#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__2 0x2
1348#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__3 0x3
1349#define BP_PXP_DATA_PATH_CTRL0_MUX9_SEL      18
1350#define BM_PXP_DATA_PATH_CTRL0_MUX9_SEL 0x000C0000
1351#define BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(v)  \
1352	(((v) << 18) & BM_PXP_DATA_PATH_CTRL0_MUX9_SEL)
1353#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__0 0x0
1354#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__1 0x1
1355#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__2 0x2
1356#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__3 0x3
1357#define BP_PXP_DATA_PATH_CTRL0_MUX8_SEL      16
1358#define BM_PXP_DATA_PATH_CTRL0_MUX8_SEL 0x00030000
1359#define BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(v)  \
1360	(((v) << 16) & BM_PXP_DATA_PATH_CTRL0_MUX8_SEL)
1361#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__0 0x0
1362#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__1 0x1
1363#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__2 0x2
1364#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__3 0x3
1365#define BP_PXP_DATA_PATH_CTRL0_MUX7_SEL      14
1366#define BM_PXP_DATA_PATH_CTRL0_MUX7_SEL 0x0000C000
1367#define BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(v)  \
1368	(((v) << 14) & BM_PXP_DATA_PATH_CTRL0_MUX7_SEL)
1369#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__0 0x0
1370#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__1 0x1
1371#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__2 0x2
1372#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__3 0x3
1373#define BP_PXP_DATA_PATH_CTRL0_MUX6_SEL      12
1374#define BM_PXP_DATA_PATH_CTRL0_MUX6_SEL 0x00003000
1375#define BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(v)  \
1376	(((v) << 12) & BM_PXP_DATA_PATH_CTRL0_MUX6_SEL)
1377#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__0 0x0
1378#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__1 0x1
1379#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__2 0x2
1380#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__3 0x3
1381#define BP_PXP_DATA_PATH_CTRL0_MUX5_SEL      10
1382#define BM_PXP_DATA_PATH_CTRL0_MUX5_SEL 0x00000C00
1383#define BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(v)  \
1384	(((v) << 10) & BM_PXP_DATA_PATH_CTRL0_MUX5_SEL)
1385#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__0 0x0
1386#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__1 0x1
1387#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__2 0x2
1388#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__3 0x3
1389#define BP_PXP_DATA_PATH_CTRL0_MUX4_SEL      8
1390#define BM_PXP_DATA_PATH_CTRL0_MUX4_SEL 0x00000300
1391#define BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(v)  \
1392	(((v) << 8) & BM_PXP_DATA_PATH_CTRL0_MUX4_SEL)
1393#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__0 0x0
1394#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__1 0x1
1395#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__2 0x2
1396#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__3 0x3
1397#define BP_PXP_DATA_PATH_CTRL0_MUX3_SEL      6
1398#define BM_PXP_DATA_PATH_CTRL0_MUX3_SEL 0x000000C0
1399#define BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(v)  \
1400	(((v) << 6) & BM_PXP_DATA_PATH_CTRL0_MUX3_SEL)
1401#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__0 0x0
1402#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__1 0x1
1403#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__2 0x2
1404#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__3 0x3
1405#define BP_PXP_DATA_PATH_CTRL0_MUX2_SEL      4
1406#define BM_PXP_DATA_PATH_CTRL0_MUX2_SEL 0x00000030
1407#define BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(v)  \
1408	(((v) << 4) & BM_PXP_DATA_PATH_CTRL0_MUX2_SEL)
1409#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__0 0x0
1410#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__1 0x1
1411#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__2 0x2
1412#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__3 0x3
1413#define BP_PXP_DATA_PATH_CTRL0_MUX1_SEL      2
1414#define BM_PXP_DATA_PATH_CTRL0_MUX1_SEL 0x0000000C
1415#define BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(v)  \
1416	(((v) << 2) & BM_PXP_DATA_PATH_CTRL0_MUX1_SEL)
1417#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__0 0x0
1418#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__1 0x1
1419#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__2 0x2
1420#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__3 0x3
1421#define BP_PXP_DATA_PATH_CTRL0_MUX0_SEL      0
1422#define BM_PXP_DATA_PATH_CTRL0_MUX0_SEL 0x00000003
1423#define BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(v)  \
1424	(((v) << 0) & BM_PXP_DATA_PATH_CTRL0_MUX0_SEL)
1425#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__0 0x0
1426#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__1 0x1
1427#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__2 0x2
1428#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__3 0x3
1429
1430#define HW_PXP_DATA_PATH_CTRL1	(0x00000350)
1431#define HW_PXP_DATA_PATH_CTRL1_SET	(0x00000354)
1432#define HW_PXP_DATA_PATH_CTRL1_CLR	(0x00000358)
1433#define HW_PXP_DATA_PATH_CTRL1_TOG	(0x0000035c)
1434
1435#define BP_PXP_DATA_PATH_CTRL1_RSVD0      4
1436#define BM_PXP_DATA_PATH_CTRL1_RSVD0 0xFFFFFFF0
1437#define BF_PXP_DATA_PATH_CTRL1_RSVD0(v) \
1438	(((v) << 4) & BM_PXP_DATA_PATH_CTRL1_RSVD0)
1439#define BP_PXP_DATA_PATH_CTRL1_MUX17_SEL      2
1440#define BM_PXP_DATA_PATH_CTRL1_MUX17_SEL 0x0000000C
1441#define BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(v)  \
1442	(((v) << 2) & BM_PXP_DATA_PATH_CTRL1_MUX17_SEL)
1443#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__0 0x0
1444#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__1 0x1
1445#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__2 0x2
1446#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__3 0x3
1447#define BP_PXP_DATA_PATH_CTRL1_MUX16_SEL      0
1448#define BM_PXP_DATA_PATH_CTRL1_MUX16_SEL 0x00000003
1449#define BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(v)  \
1450	(((v) << 0) & BM_PXP_DATA_PATH_CTRL1_MUX16_SEL)
1451#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__0 0x0
1452#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__1 0x1
1453#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__2 0x2
1454#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__3 0x3
1455
1456#define HW_PXP_INIT_MEM_CTRL	(0x00000360)
1457#define HW_PXP_INIT_MEM_CTRL_SET	(0x00000364)
1458#define HW_PXP_INIT_MEM_CTRL_CLR	(0x00000368)
1459#define HW_PXP_INIT_MEM_CTRL_TOG	(0x0000036c)
1460
1461#define BM_PXP_INIT_MEM_CTRL_START 0x80000000
1462#define BF_PXP_INIT_MEM_CTRL_START(v) \
1463	(((v) << 31) & BM_PXP_INIT_MEM_CTRL_START)
1464#define BP_PXP_INIT_MEM_CTRL_SELECT      27
1465#define BM_PXP_INIT_MEM_CTRL_SELECT 0x78000000
1466#define BF_PXP_INIT_MEM_CTRL_SELECT(v)  \
1467	(((v) << 27) & BM_PXP_INIT_MEM_CTRL_SELECT)
1468#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_LUT  0x0
1469#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR0 0x1
1470#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR1 0x2
1471#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER1_LUT  0x3
1472#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER2_LUT  0x4
1473#define BV_PXP_INIT_MEM_CTRL_SELECT__ALU_A	0x5
1474#define BV_PXP_INIT_MEM_CTRL_SELECT__ALU_B	0x6
1475#define BV_PXP_INIT_MEM_CTRL_SELECT__WFE_A_FETCH  0x7
1476#define BV_PXP_INIT_MEM_CTRL_SELECT__WFE_B_FETCH  0x8
1477#define BV_PXP_INIT_MEM_CTRL_SELECT__RESERVED     0x15
1478#define BP_PXP_INIT_MEM_CTRL_RSVD0      16
1479#define BM_PXP_INIT_MEM_CTRL_RSVD0 0x07FF0000
1480#define BF_PXP_INIT_MEM_CTRL_RSVD0(v)  \
1481	(((v) << 16) & BM_PXP_INIT_MEM_CTRL_RSVD0)
1482#define BP_PXP_INIT_MEM_CTRL_ADDR      0
1483#define BM_PXP_INIT_MEM_CTRL_ADDR 0x0000FFFF
1484#define BF_PXP_INIT_MEM_CTRL_ADDR(v)  \
1485	(((v) << 0) & BM_PXP_INIT_MEM_CTRL_ADDR)
1486
1487#define HW_PXP_INIT_MEM_DATA	(0x00000370)
1488
1489#define BP_PXP_INIT_MEM_DATA_DATA      0
1490#define BM_PXP_INIT_MEM_DATA_DATA 0xFFFFFFFF
1491#define BF_PXP_INIT_MEM_DATA_DATA(v)   (v)
1492
1493#define HW_PXP_INIT_MEM_DATA_HIGH	(0x00000380)
1494
1495#define BP_PXP_INIT_MEM_DATA_HIGH_DATA      0
1496#define BM_PXP_INIT_MEM_DATA_HIGH_DATA 0xFFFFFFFF
1497#define BF_PXP_INIT_MEM_DATA_HIGH_DATA(v)   (v)
1498
1499#define HW_PXP_IRQ_MASK	(0x00000390)
1500#define HW_PXP_IRQ_MASK_SET	(0x00000394)
1501#define HW_PXP_IRQ_MASK_CLR	(0x00000398)
1502#define HW_PXP_IRQ_MASK_TOG	(0x0000039c)
1503
1504#define BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN 0x80000000
1505#define BF_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN(v) \
1506	(((v) << 31) & BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN)
1507#define BP_PXP_IRQ_MASK_RSVD1      16
1508#define BM_PXP_IRQ_MASK_RSVD1 0x7FFF0000
1509#define BF_PXP_IRQ_MASK_RSVD1(v)  \
1510	(((v) << 16) & BM_PXP_IRQ_MASK_RSVD1)
1511#define BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN 0x00008000
1512#define BF_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN(v)  \
1513	(((v) << 15) & BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN)
1514#define BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN 0x00004000
1515#define BF_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN(v)  \
1516	(((v) << 14) & BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN)
1517#define BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN 0x00002000
1518#define BF_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN(v)  \
1519	(((v) << 13) & BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN)
1520#define BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN 0x00001000
1521#define BF_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN(v)  \
1522	(((v) << 12) & BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN)
1523#define BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN 0x00000800
1524#define BF_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN(v)  \
1525	(((v) << 11) & BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN)
1526#define BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN 0x00000400
1527#define BF_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN(v)  \
1528	(((v) << 10) & BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN)
1529#define BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN 0x00000200
1530#define BF_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN(v)  \
1531	(((v) << 9) & BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN)
1532#define BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN 0x00000100
1533#define BF_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN(v)  \
1534	(((v) << 8) & BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN)
1535#define BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN 0x00000080
1536#define BF_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN(v)  \
1537	(((v) << 7) & BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN)
1538#define BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN 0x00000040
1539#define BF_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN(v)  \
1540	(((v) << 6) & BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN)
1541#define BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN 0x00000020
1542#define BF_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN(v)  \
1543	(((v) << 5) & BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN)
1544#define BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN 0x00000010
1545#define BF_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN(v)  \
1546	(((v) << 4) & BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN)
1547#define BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN 0x00000008
1548#define BF_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN(v)  \
1549	(((v) << 3) & BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN)
1550#define BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN 0x00000004
1551#define BF_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN(v)  \
1552	(((v) << 2) & BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN)
1553#define BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN 0x00000002
1554#define BF_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN(v)  \
1555	(((v) << 1) & BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN)
1556#define BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN 0x00000001
1557#define BF_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN(v)  \
1558	(((v) << 0) & BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN)
1559
1560#define HW_PXP_IRQ	(0x000003a0)
1561#define HW_PXP_IRQ_SET	(0x000003a4)
1562#define HW_PXP_IRQ_CLR	(0x000003a8)
1563#define HW_PXP_IRQ_TOG	(0x000003ac)
1564
1565#define BM_PXP_IRQ_COMPRESS_DONE_IRQ 0x80000000
1566#define BF_PXP_IRQ_COMPRESS_DONE_IRQ(v) \
1567	(((v) << 31) & BM_PXP_IRQ_COMPRESS_DONE_IRQ)
1568#define BP_PXP_IRQ_RSVD1      16
1569#define BM_PXP_IRQ_RSVD1 0x7FFF0000
1570#define BF_PXP_IRQ_RSVD1(v)  \
1571	(((v) << 16) & BM_PXP_IRQ_RSVD1)
1572#define BM_PXP_IRQ_WFE_B_STORE_IRQ 0x00008000
1573#define BF_PXP_IRQ_WFE_B_STORE_IRQ(v)  \
1574	(((v) << 15) & BM_PXP_IRQ_WFE_B_STORE_IRQ)
1575#define BM_PXP_IRQ_WFE_A_STORE_IRQ 0x00004000
1576#define BF_PXP_IRQ_WFE_A_STORE_IRQ(v)  \
1577	(((v) << 14) & BM_PXP_IRQ_WFE_A_STORE_IRQ)
1578#define BM_PXP_IRQ_DITHER_STORE_IRQ 0x00002000
1579#define BF_PXP_IRQ_DITHER_STORE_IRQ(v)  \
1580	(((v) << 13) & BM_PXP_IRQ_DITHER_STORE_IRQ)
1581#define BM_PXP_IRQ_FIRST_STORE_IRQ 0x00001000
1582#define BF_PXP_IRQ_FIRST_STORE_IRQ(v)  \
1583	(((v) << 12) & BM_PXP_IRQ_FIRST_STORE_IRQ)
1584#define BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ 0x00000800
1585#define BF_PXP_IRQ_WFE_B_CH1_STORE_IRQ(v)  \
1586	(((v) << 11) & BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ)
1587#define BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ 0x00000400
1588#define BF_PXP_IRQ_WFE_B_CH0_STORE_IRQ(v)  \
1589	(((v) << 10) & BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ)
1590#define BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ 0x00000200
1591#define BF_PXP_IRQ_WFE_A_CH1_STORE_IRQ(v)  \
1592	(((v) << 9) & BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ)
1593#define BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ 0x00000100
1594#define BF_PXP_IRQ_WFE_A_CH0_STORE_IRQ(v)  \
1595	(((v) << 8) & BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ)
1596#define BM_PXP_IRQ_DITHER_CH1_STORE_IRQ 0x00000080
1597#define BF_PXP_IRQ_DITHER_CH1_STORE_IRQ(v)  \
1598	(((v) << 7) & BM_PXP_IRQ_DITHER_CH1_STORE_IRQ)
1599#define BM_PXP_IRQ_DITHER_CH0_STORE_IRQ 0x00000040
1600#define BF_PXP_IRQ_DITHER_CH0_STORE_IRQ(v)  \
1601	(((v) << 6) & BM_PXP_IRQ_DITHER_CH0_STORE_IRQ)
1602#define BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ 0x00000020
1603#define BF_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ(v)  \
1604	(((v) << 5) & BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ)
1605#define BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ 0x00000010
1606#define BF_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ(v)  \
1607	(((v) << 4) & BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ)
1608#define BM_PXP_IRQ_FIRST_CH1_STORE_IRQ 0x00000008
1609#define BF_PXP_IRQ_FIRST_CH1_STORE_IRQ(v)  \
1610	(((v) << 3) & BM_PXP_IRQ_FIRST_CH1_STORE_IRQ)
1611#define BM_PXP_IRQ_FIRST_CH0_STORE_IRQ 0x00000004
1612#define BF_PXP_IRQ_FIRST_CH0_STORE_IRQ(v)  \
1613	(((v) << 2) & BM_PXP_IRQ_FIRST_CH0_STORE_IRQ)
1614#define BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ 0x00000002
1615#define BF_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ(v)  \
1616	(((v) << 1) & BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ)
1617#define BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ 0x00000001
1618#define BF_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ(v)  \
1619	(((v) << 0) & BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ)
1620
1621#define HW_PXP_NEXT	(0x00000400)
1622
1623#define BP_PXP_NEXT_POINTER      2
1624#define BM_PXP_NEXT_POINTER 0xFFFFFFFC
1625#define BF_PXP_NEXT_POINTER(v) \
1626	(((v) << 2) & BM_PXP_NEXT_POINTER)
1627#define BM_PXP_NEXT_RSVD 0x00000002
1628#define BF_PXP_NEXT_RSVD(v)  \
1629	(((v) << 1) & BM_PXP_NEXT_RSVD)
1630#define BM_PXP_NEXT_ENABLED 0x00000001
1631#define BF_PXP_NEXT_ENABLED(v)  \
1632	(((v) << 0) & BM_PXP_NEXT_ENABLED)
1633
1634#define HW_PXP_DEBUGCTRL	(0x00000410)
1635
1636#define BP_PXP_DEBUGCTRL_RSVD      12
1637#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFF000
1638#define BF_PXP_DEBUGCTRL_RSVD(v) \
1639	(((v) << 12) & BM_PXP_DEBUGCTRL_RSVD)
1640#define BP_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT      8
1641#define BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 0x00000F00
1642#define BF_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(v)  \
1643	(((v) << 8) & BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT)
1644#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__NONE     0x0
1645#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MISS_CNT 0x1
1646#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__HIT_CNT  0x2
1647#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__LAT_CNT  0x4
1648#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MAX_LAT  0x8
1649#define BP_PXP_DEBUGCTRL_SELECT      0
1650#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF
1651#define BF_PXP_DEBUGCTRL_SELECT(v)  \
1652	(((v) << 0) & BM_PXP_DEBUGCTRL_SELECT)
1653#define BV_PXP_DEBUGCTRL_SELECT__NONE	0x0
1654#define BV_PXP_DEBUGCTRL_SELECT__CTRL	0x1
1655#define BV_PXP_DEBUGCTRL_SELECT__PSBUF       0x2
1656#define BV_PXP_DEBUGCTRL_SELECT__PSBAX       0x3
1657#define BV_PXP_DEBUGCTRL_SELECT__PSBAY       0x4
1658#define BV_PXP_DEBUGCTRL_SELECT__ASBUF       0x5
1659#define BV_PXP_DEBUGCTRL_SELECT__ROTATION    0x6
1660#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF0     0x7
1661#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF1     0x8
1662#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF2     0x9
1663#define BV_PXP_DEBUGCTRL_SELECT__LUT_STAT    0x10
1664#define BV_PXP_DEBUGCTRL_SELECT__LUT_MISS    0x11
1665#define BV_PXP_DEBUGCTRL_SELECT__LUT_HIT     0x12
1666#define BV_PXP_DEBUGCTRL_SELECT__LUT_LAT     0x13
1667#define BV_PXP_DEBUGCTRL_SELECT__LUT_MAX_LAT 0x14
1668
1669#define HW_PXP_DEBUG	(0x00000420)
1670
1671#define BP_PXP_DEBUG_DATA      0
1672#define BM_PXP_DEBUG_DATA 0xFFFFFFFF
1673#define BF_PXP_DEBUG_DATA(v)   (v)
1674
1675#define HW_PXP_VERSION	(0x00000430)
1676
1677#define BP_PXP_VERSION_MAJOR      24
1678#define BM_PXP_VERSION_MAJOR 0xFF000000
1679#define BF_PXP_VERSION_MAJOR(v) \
1680	(((v) << 24) & BM_PXP_VERSION_MAJOR)
1681#define BP_PXP_VERSION_MINOR      16
1682#define BM_PXP_VERSION_MINOR 0x00FF0000
1683#define BF_PXP_VERSION_MINOR(v)  \
1684	(((v) << 16) & BM_PXP_VERSION_MINOR)
1685#define BP_PXP_VERSION_STEP      0
1686#define BM_PXP_VERSION_STEP 0x0000FFFF
1687#define BF_PXP_VERSION_STEP(v)  \
1688	(((v) << 0) & BM_PXP_VERSION_STEP)
1689
1690#endif /* __IMX_PXP_H__ */