imx-mipi-csis.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Samsung CSIS MIPI CSI-2 receiver driver.
   4 *
   5 * The Samsung CSIS IP is a MIPI CSI-2 receiver found in various NXP i.MX7 and
   6 * i.MX8 SoCs. The i.MX7 features version 3.3 of the IP, while i.MX8 features
   7 * version 3.6.3.
   8 *
   9 * Copyright (C) 2019 Linaro Ltd
  10 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved.
  11 * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
  12 *
  13 */
  14
  15#include <linux/clk.h>
  16#include <linux/debugfs.h>
  17#include <linux/delay.h>
  18#include <linux/errno.h>
  19#include <linux/interrupt.h>
  20#include <linux/io.h>
  21#include <linux/kernel.h>
  22#include <linux/module.h>
  23#include <linux/mutex.h>
  24#include <linux/of.h>
  25#include <linux/platform_device.h>
  26#include <linux/pm_runtime.h>
  27#include <linux/regulator/consumer.h>
  28#include <linux/reset.h>
  29#include <linux/spinlock.h>
  30
  31#include <media/mipi-csi2.h>
  32#include <media/v4l2-common.h>
  33#include <media/v4l2-device.h>
  34#include <media/v4l2-event.h>
  35#include <media/v4l2-fwnode.h>
  36#include <media/v4l2-mc.h>
  37#include <media/v4l2-subdev.h>
  38
  39#define CSIS_DRIVER_NAME			"imx-mipi-csis"
  40
  41#define CSIS_PAD_SINK				0
  42#define CSIS_PAD_SOURCE				1
  43#define CSIS_PADS_NUM				2
  44
  45#define MIPI_CSIS_DEF_PIX_WIDTH			640
  46#define MIPI_CSIS_DEF_PIX_HEIGHT		480
  47
  48/* Register map definition */
  49
  50/* CSIS version */
  51#define MIPI_CSIS_VERSION			0x00
  52#define MIPI_CSIS_VERSION_IMX7D			0x03030505
  53#define MIPI_CSIS_VERSION_IMX8MP		0x03060301
  54
  55/* CSIS common control */
  56#define MIPI_CSIS_CMN_CTRL			0x04
  57#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW(n)	BIT((n) + 16)
  58#define MIPI_CSIS_CMN_CTRL_INTERLEAVE_MODE_DT	BIT(10)
  59#define MIPI_CSIS_CMN_CTRL_LANE_NUMBER(n)	((n) << 8)
  60#define MIPI_CSIS_CMN_CTRL_LANE_NUMBER_MASK	GENMASK(9, 8)
  61#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL	BIT(2)
  62#define MIPI_CSIS_CMN_CTRL_SW_RESET		BIT(1)
  63#define MIPI_CSIS_CMN_CTRL_CSI_EN		BIT(0)
  64
  65/* CSIS clock control */
  66#define MIPI_CSIS_CLK_CTRL			0x08
  67#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL(n, x)	((x) << ((n) * 4 + 16))
  68#define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MASK	GENMASK(7, 4)
  69#define MIPI_CSIS_CLK_CTRL_WCLK_SRC(n)		BIT(n)
  70
  71/* CSIS Interrupt mask */
  72#define MIPI_CSIS_INT_MSK			0x10
  73#define MIPI_CSIS_INT_MSK_EVEN_BEFORE		BIT(31)
  74#define MIPI_CSIS_INT_MSK_EVEN_AFTER		BIT(30)
  75#define MIPI_CSIS_INT_MSK_ODD_BEFORE		BIT(29)
  76#define MIPI_CSIS_INT_MSK_ODD_AFTER		BIT(28)
  77#define MIPI_CSIS_INT_MSK_FRAME_START		BIT(24)
  78#define MIPI_CSIS_INT_MSK_FRAME_END		BIT(20)
  79#define MIPI_CSIS_INT_MSK_ERR_SOT_HS		BIT(16)
  80#define MIPI_CSIS_INT_MSK_ERR_LOST_FS		BIT(12)
  81#define MIPI_CSIS_INT_MSK_ERR_LOST_FE		BIT(8)
  82#define MIPI_CSIS_INT_MSK_ERR_OVER		BIT(4)
  83#define MIPI_CSIS_INT_MSK_ERR_WRONG_CFG		BIT(3)
  84#define MIPI_CSIS_INT_MSK_ERR_ECC		BIT(2)
  85#define MIPI_CSIS_INT_MSK_ERR_CRC		BIT(1)
  86#define MIPI_CSIS_INT_MSK_ERR_ID		BIT(0)
  87
  88/* CSIS Interrupt source */
  89#define MIPI_CSIS_INT_SRC			0x14
  90#define MIPI_CSIS_INT_SRC_EVEN_BEFORE		BIT(31)
  91#define MIPI_CSIS_INT_SRC_EVEN_AFTER		BIT(30)
  92#define MIPI_CSIS_INT_SRC_EVEN			BIT(30)
  93#define MIPI_CSIS_INT_SRC_ODD_BEFORE		BIT(29)
  94#define MIPI_CSIS_INT_SRC_ODD_AFTER		BIT(28)
  95#define MIPI_CSIS_INT_SRC_ODD			(0x3 << 28)
  96#define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA	(0xf << 28)
  97#define MIPI_CSIS_INT_SRC_FRAME_START(n)	BIT((n) + 24)
  98#define MIPI_CSIS_INT_SRC_FRAME_END(n)		BIT((n) + 20)
  99#define MIPI_CSIS_INT_SRC_ERR_SOT_HS(n)		BIT((n) + 16)
 100#define MIPI_CSIS_INT_SRC_ERR_LOST_FS(n)	BIT((n) + 12)
 101#define MIPI_CSIS_INT_SRC_ERR_LOST_FE(n)	BIT((n) + 8)
 102#define MIPI_CSIS_INT_SRC_ERR_OVER(n)		BIT((n) + 4)
 103#define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG		BIT(3)
 104#define MIPI_CSIS_INT_SRC_ERR_ECC		BIT(2)
 105#define MIPI_CSIS_INT_SRC_ERR_CRC		BIT(1)
 106#define MIPI_CSIS_INT_SRC_ERR_ID		BIT(0)
 107#define MIPI_CSIS_INT_SRC_ERRORS		0xfffff
 108
 109/* D-PHY status control */
 110#define MIPI_CSIS_DPHY_STATUS			0x20
 111#define MIPI_CSIS_DPHY_STATUS_ULPS_DAT		BIT(8)
 112#define MIPI_CSIS_DPHY_STATUS_STOPSTATE_DAT	BIT(4)
 113#define MIPI_CSIS_DPHY_STATUS_ULPS_CLK		BIT(1)
 114#define MIPI_CSIS_DPHY_STATUS_STOPSTATE_CLK	BIT(0)
 115
 116/* D-PHY common control */
 117#define MIPI_CSIS_DPHY_CMN_CTRL			0x24
 118#define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(n)	((n) << 24)
 119#define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK	GENMASK(31, 24)
 120#define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n)	((n) << 22)
 121#define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK	GENMASK(23, 22)
 122#define MIPI_CSIS_DPHY_CMN_CTRL_S_DPDN_SWAP_CLK	BIT(6)
 123#define MIPI_CSIS_DPHY_CMN_CTRL_S_DPDN_SWAP_DAT	BIT(5)
 124#define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT	BIT(1)
 125#define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_CLK	BIT(0)
 126#define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE		(0x1f << 0)
 127
 128/* D-PHY Master and Slave Control register Low */
 129#define MIPI_CSIS_DPHY_BCTRL_L			0x30
 130#define MIPI_CSIS_DPHY_BCTRL_L_USER_DATA_PATTERN_LOW(n)		(((n) & 3U) << 30)
 131#define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV		(0 << 28)
 132#define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_724MV		(1 << 28)
 133#define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_733MV		(2 << 28)
 134#define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_706MV		(3 << 28)
 135#define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ		(0 << 27)
 136#define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_1_5MHZ		(1 << 27)
 137#define MIPI_CSIS_DPHY_BCTRL_L_VREG12_EXTPWR_EN_CTL		BIT(26)
 138#define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V		(0 << 24)
 139#define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_23V		(1 << 24)
 140#define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_17V		(2 << 24)
 141#define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_26V		(3 << 24)
 142#define MIPI_CSIS_DPHY_BCTRL_L_REG_1P2_LVL_SEL			BIT(23)
 143#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV		(0 << 21)
 144#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_100MV		(1 << 21)
 145#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_120MV		(2 << 21)
 146#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_140MV		(3 << 21)
 147#define MIPI_CSIS_DPHY_BCTRL_L_VREF_SRC_SEL			BIT(20)
 148#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV		(0 << 18)
 149#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_743MV		(1 << 18)
 150#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_650MV		(2 << 18)
 151#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_682MV		(3 << 18)
 152#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_PULSE_REJECT		BIT(17)
 153#define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_0	(0 << 15)
 154#define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_15P	(1 << 15)
 155#define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_30P	(3 << 15)
 156#define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_UP		BIT(14)
 157#define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV			(0 << 13)
 158#define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_70MV			(1 << 13)
 159#define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_EN			BIT(12)
 160#define MIPI_CSIS_DPHY_BCTRL_L_ERRCONTENTION_LP_EN		BIT(11)
 161#define MIPI_CSIS_DPHY_BCTRL_L_TXTRIGGER_CLK_EN			BIT(10)
 162#define MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(n)			(((n) * 25 / 1000000) << 0)
 163
 164/* D-PHY Master and Slave Control register High */
 165#define MIPI_CSIS_DPHY_BCTRL_H			0x34
 166/* D-PHY Slave Control register Low */
 167#define MIPI_CSIS_DPHY_SCTRL_L			0x38
 168/* D-PHY Slave Control register High */
 169#define MIPI_CSIS_DPHY_SCTRL_H			0x3c
 170
 171/* ISP Configuration register */
 172#define MIPI_CSIS_ISP_CONFIG_CH(n)		(0x40 + (n) * 0x10)
 173#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MASK	GENMASK(31, 24)
 174#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x)	((x) << 24)
 175#define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE	(0 << 12)
 176#define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL	(1 << 12)
 177#define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD	(2 << 12)	/* i.MX8M[MNP] only */
 178#define MIPI_CSIS_ISPCFG_PIXEL_MODE_MASK	GENMASK(13, 12)
 179#define MIPI_CSIS_ISPCFG_PARALLEL		BIT(11)
 180#define MIPI_CSIS_ISPCFG_DATAFORMAT(fmt)	((fmt) << 2)
 181#define MIPI_CSIS_ISPCFG_DATAFORMAT_MASK	GENMASK(7, 2)
 182
 183/* ISP Image Resolution register */
 184#define MIPI_CSIS_ISP_RESOL_CH(n)		(0x44 + (n) * 0x10)
 185#define MIPI_CSIS_ISP_RESOL_VRESOL(n)		((n) << 16)
 186#define MIPI_CSIS_ISP_RESOL_HRESOL(n)		((n) << 0)
 187#define CSIS_MAX_PIX_WIDTH			0xffff
 188#define CSIS_MAX_PIX_HEIGHT			0xffff
 189
 190/* ISP SYNC register */
 191#define MIPI_CSIS_ISP_SYNC_CH(n)		(0x48 + (n) * 0x10)
 192#define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV(n)	((n) << 18)
 193#define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV(n)	((n) << 12)
 194#define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV(n)	((n) << 0)
 195
 196/* ISP shadow registers */
 197#define MIPI_CSIS_SDW_CONFIG_CH(n)		(0x80 + (n) * 0x10)
 198#define MIPI_CSIS_SDW_RESOL_CH(n)		(0x84 + (n) * 0x10)
 199#define MIPI_CSIS_SDW_SYNC_CH(n)		(0x88 + (n) * 0x10)
 200
 201/* Debug control register */
 202#define MIPI_CSIS_DBG_CTRL			0xc0
 203#define MIPI_CSIS_DBG_INTR_MSK			0xc4
 204#define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT		BIT(25)
 205#define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE		BIT(24)
 206#define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE(n)	BIT((n) + 20)
 207#define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME(n)	BIT((n) + 16)
 208#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE(n)		BIT((n) + 12)
 209#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS(n)		BIT((n) + 8)
 210#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL(n)	BIT((n) + 4)
 211#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE(n)	BIT((n) + 0)
 212#define MIPI_CSIS_DBG_INTR_SRC			0xc8
 213#define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT		BIT(25)
 214#define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE		BIT(24)
 215#define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(n)	BIT((n) + 20)
 216#define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(n)	BIT((n) + 16)
 217#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(n)		BIT((n) + 12)
 218#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(n)		BIT((n) + 8)
 219#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(n)	BIT((n) + 4)
 220#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(n)	BIT((n) + 0)
 221
 222#define MIPI_CSIS_FRAME_COUNTER_CH(n)		(0x0100 + (n) * 4)
 223
 224/* Non-image packet data buffers */
 225#define MIPI_CSIS_PKTDATA_ODD			0x2000
 226#define MIPI_CSIS_PKTDATA_EVEN			0x3000
 227#define MIPI_CSIS_PKTDATA_SIZE			SZ_4K
 228
 229#define MIPI_CSIS_MAX_CHANNELS			4
 230
 231struct mipi_csis_event {
 232	bool debug;
 233	unsigned int channel;
 234	u32 mask;
 235	const char * const name;
 236	unsigned int counter;
 237};
 238
 239static const struct mipi_csis_event mipi_csis_events[] = {
 240	/* Errors */
 241	{ false, 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS(0),		"SOT 0 Error" },
 242	{ false, 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS(1),		"SOT 1 Error" },
 243	{ false, 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS(2),		"SOT 2 Error" },
 244	{ false, 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS(3),		"SOT 3 Error" },
 245	{ false, 0, MIPI_CSIS_INT_SRC_ERR_LOST_FS(0),		"Lost Frame Start Error 0" },
 246	{ false, 1, MIPI_CSIS_INT_SRC_ERR_LOST_FS(1),		"Lost Frame Start Error 1" },
 247	{ false, 2, MIPI_CSIS_INT_SRC_ERR_LOST_FS(2),		"Lost Frame Start Error 2" },
 248	{ false, 3, MIPI_CSIS_INT_SRC_ERR_LOST_FS(3),		"Lost Frame Start Error 3" },
 249	{ false, 0, MIPI_CSIS_INT_SRC_ERR_LOST_FE(0),		"Lost Frame End Error 0" },
 250	{ false, 1, MIPI_CSIS_INT_SRC_ERR_LOST_FE(1),		"Lost Frame End Error 1" },
 251	{ false, 2, MIPI_CSIS_INT_SRC_ERR_LOST_FE(2),		"Lost Frame End Error 2" },
 252	{ false, 3, MIPI_CSIS_INT_SRC_ERR_LOST_FE(3),		"Lost Frame End Error 3" },
 253	{ false, 0, MIPI_CSIS_INT_SRC_ERR_OVER(0),		"FIFO Overflow Error 0" },
 254	{ false, 1, MIPI_CSIS_INT_SRC_ERR_OVER(1),		"FIFO Overflow Error 1" },
 255	{ false, 2, MIPI_CSIS_INT_SRC_ERR_OVER(2),		"FIFO Overflow Error 2" },
 256	{ false, 3, MIPI_CSIS_INT_SRC_ERR_OVER(3),		"FIFO Overflow Error 3" },
 257	{ false, 0, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG,		"Wrong Configuration Error" },
 258	{ false, 0, MIPI_CSIS_INT_SRC_ERR_ECC,			"ECC Error" },
 259	{ false, 0, MIPI_CSIS_INT_SRC_ERR_CRC,			"CRC Error" },
 260	{ false, 0, MIPI_CSIS_INT_SRC_ERR_ID,			"Unknown ID Error" },
 261	{ true, 0, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT,	"Data Type Not Supported" },
 262	{ true, 0, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE,		"Data Type Ignored" },
 263	{ true, 0, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(0),	"Frame Size Error 0" },
 264	{ true, 1, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(1),	"Frame Size Error 1" },
 265	{ true, 2, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(2),	"Frame Size Error 2" },
 266	{ true, 3, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(3),	"Frame Size Error 3" },
 267	{ true, 0, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(0),	"Truncated Frame 0" },
 268	{ true, 1, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(1),	"Truncated Frame 1" },
 269	{ true, 2, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(2),	"Truncated Frame 2" },
 270	{ true, 3, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(3),	"Truncated Frame 3" },
 271	{ true, 0, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(0),		"Early Frame End 0" },
 272	{ true, 1, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(1),		"Early Frame End 1" },
 273	{ true, 2, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(2),		"Early Frame End 2" },
 274	{ true, 3, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(3),		"Early Frame End 3" },
 275	{ true, 0, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(0),		"Early Frame Start 0" },
 276	{ true, 1, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(1),		"Early Frame Start 1" },
 277	{ true, 2, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(2),		"Early Frame Start 2" },
 278	{ true, 3, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(3),		"Early Frame Start 3" },
 279	/* Non-image data receive events */
 280	{ false, 0, MIPI_CSIS_INT_SRC_EVEN_BEFORE,		"Non-image data before even frame" },
 281	{ false, 0, MIPI_CSIS_INT_SRC_EVEN_AFTER,		"Non-image data after even frame" },
 282	{ false, 0, MIPI_CSIS_INT_SRC_ODD_BEFORE,		"Non-image data before odd frame" },
 283	{ false, 0, MIPI_CSIS_INT_SRC_ODD_AFTER,		"Non-image data after odd frame" },
 284	/* Frame start/end */
 285	{ false, 0, MIPI_CSIS_INT_SRC_FRAME_START(0),		"Frame Start 0" },
 286	{ false, 1, MIPI_CSIS_INT_SRC_FRAME_START(1),		"Frame Start 1" },
 287	{ false, 2, MIPI_CSIS_INT_SRC_FRAME_START(2),		"Frame Start 2" },
 288	{ false, 3, MIPI_CSIS_INT_SRC_FRAME_START(3),		"Frame Start 3" },
 289	{ false, 0, MIPI_CSIS_INT_SRC_FRAME_END(0),		"Frame End 0" },
 290	{ false, 1, MIPI_CSIS_INT_SRC_FRAME_END(1),		"Frame End 1" },
 291	{ false, 2, MIPI_CSIS_INT_SRC_FRAME_END(2),		"Frame End 2" },
 292	{ false, 3, MIPI_CSIS_INT_SRC_FRAME_END(3),		"Frame End 3" },
 293	{ true, 0, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(0),	"VSYNC Falling Edge 0" },
 294	{ true, 1, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(1),	"VSYNC Falling Edge 1" },
 295	{ true, 2, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(2),	"VSYNC Falling Edge 2" },
 296	{ true, 3, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(3),	"VSYNC Falling Edge 3" },
 297	{ true, 0, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(0),	"VSYNC Rising Edge 0" },
 298	{ true, 1, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(1),	"VSYNC Rising Edge 1" },
 299	{ true, 2, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(2),	"VSYNC Rising Edge 2" },
 300	{ true, 3, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(3),	"VSYNC Rising Edge 3" },
 301};
 302
 303#define MIPI_CSIS_NUM_EVENTS		ARRAY_SIZE(mipi_csis_events)
 304#define MIPI_CSIS_NUM_ERROR_EVENTS	38
 305
 306enum mipi_csis_clk {
 307	MIPI_CSIS_CLK_PCLK,
 308	MIPI_CSIS_CLK_WRAP,
 309	MIPI_CSIS_CLK_PHY,
 310	MIPI_CSIS_CLK_AXI,
 311};
 312
 313static const char * const mipi_csis_clk_id[] = {
 314	"pclk",
 315	"wrap",
 316	"phy",
 317	"axi",
 318};
 319
 320enum mipi_csis_version {
 321	MIPI_CSIS_V3_3,
 322	MIPI_CSIS_V3_6_3,
 323};
 324
 325struct mipi_csis_info {
 326	enum mipi_csis_version version;
 327	unsigned int num_clocks;
 328};
 329
 330struct mipi_csis_device {
 331	struct device *dev;
 332	void __iomem *regs;
 333	struct clk_bulk_data *clks;
 334	struct reset_control *mrst;
 335	struct regulator *mipi_phy_regulator;
 336
 337	const struct mipi_csis_info *info;
 338	unsigned int num_channels;
 339
 340	struct v4l2_subdev sd;
 341	struct media_pad pads[CSIS_PADS_NUM];
 342	struct v4l2_async_notifier notifier;
 343
 344	struct {
 345		struct v4l2_subdev *sd;
 346		const struct media_pad *pad;
 347	} source;
 348
 349	struct v4l2_mbus_config_mipi_csi2 bus;
 350	u32 clk_frequency;
 351	u32 hs_settle;
 352	u32 clk_settle;
 353
 354	unsigned int num_data_lanes;
 355
 356	spinlock_t slock;	/* Protect events */
 357	struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS];
 358	struct dentry *debugfs_root;
 359	struct {
 360		bool enable;
 361		u32 hs_settle;
 362		u32 clk_settle;
 363	} debug;
 364};
 365
 366/* -----------------------------------------------------------------------------
 367 * Format helpers
 368 */
 369
 370struct csis_pix_format {
 371	u32 code;
 372	u32 output;
 373	u32 data_type;
 374	u8 width;
 375};
 376
 377static const struct csis_pix_format mipi_csis_formats[] = {
 378	/* YUV formats. */
 379	{
 380		.code = MEDIA_BUS_FMT_UYVY8_1X16,
 381		.output = MEDIA_BUS_FMT_UYVY8_1X16,
 382		.data_type = MIPI_CSI2_DT_YUV422_8B,
 383		.width = 16,
 384	},
 385	/* RGB formats. */
 386	{
 387		.code = MEDIA_BUS_FMT_RGB565_1X16,
 388		.output = MEDIA_BUS_FMT_RGB565_1X16,
 389		.data_type = MIPI_CSI2_DT_RGB565,
 390		.width = 16,
 391	}, {
 392		.code = MEDIA_BUS_FMT_BGR888_1X24,
 393		.output = MEDIA_BUS_FMT_RGB888_1X24,
 394		.data_type = MIPI_CSI2_DT_RGB888,
 395		.width = 24,
 396	},
 397	/* RAW (Bayer and greyscale) formats. */
 398	{
 399		.code = MEDIA_BUS_FMT_SBGGR8_1X8,
 400		.output = MEDIA_BUS_FMT_SBGGR8_1X8,
 401		.data_type = MIPI_CSI2_DT_RAW8,
 402		.width = 8,
 403	}, {
 404		.code = MEDIA_BUS_FMT_SGBRG8_1X8,
 405		.output = MEDIA_BUS_FMT_SGBRG8_1X8,
 406		.data_type = MIPI_CSI2_DT_RAW8,
 407		.width = 8,
 408	}, {
 409		.code = MEDIA_BUS_FMT_SGRBG8_1X8,
 410		.output = MEDIA_BUS_FMT_SGRBG8_1X8,
 411		.data_type = MIPI_CSI2_DT_RAW8,
 412		.width = 8,
 413	}, {
 414		.code = MEDIA_BUS_FMT_SRGGB8_1X8,
 415		.output = MEDIA_BUS_FMT_SRGGB8_1X8,
 416		.data_type = MIPI_CSI2_DT_RAW8,
 417		.width = 8,
 418	}, {
 419		.code = MEDIA_BUS_FMT_Y8_1X8,
 420		.output = MEDIA_BUS_FMT_Y8_1X8,
 421		.data_type = MIPI_CSI2_DT_RAW8,
 422		.width = 8,
 423	}, {
 424		.code = MEDIA_BUS_FMT_SBGGR10_1X10,
 425		.output = MEDIA_BUS_FMT_SBGGR10_1X10,
 426		.data_type = MIPI_CSI2_DT_RAW10,
 427		.width = 10,
 428	}, {
 429		.code = MEDIA_BUS_FMT_SGBRG10_1X10,
 430		.output = MEDIA_BUS_FMT_SGBRG10_1X10,
 431		.data_type = MIPI_CSI2_DT_RAW10,
 432		.width = 10,
 433	}, {
 434		.code = MEDIA_BUS_FMT_SGRBG10_1X10,
 435		.output = MEDIA_BUS_FMT_SGRBG10_1X10,
 436		.data_type = MIPI_CSI2_DT_RAW10,
 437		.width = 10,
 438	}, {
 439		.code = MEDIA_BUS_FMT_SRGGB10_1X10,
 440		.output = MEDIA_BUS_FMT_SRGGB10_1X10,
 441		.data_type = MIPI_CSI2_DT_RAW10,
 442		.width = 10,
 443	}, {
 444		.code = MEDIA_BUS_FMT_Y10_1X10,
 445		.output = MEDIA_BUS_FMT_Y10_1X10,
 446		.data_type = MIPI_CSI2_DT_RAW10,
 447		.width = 10,
 448	}, {
 449		.code = MEDIA_BUS_FMT_SBGGR12_1X12,
 450		.output = MEDIA_BUS_FMT_SBGGR12_1X12,
 451		.data_type = MIPI_CSI2_DT_RAW12,
 452		.width = 12,
 453	}, {
 454		.code = MEDIA_BUS_FMT_SGBRG12_1X12,
 455		.output = MEDIA_BUS_FMT_SGBRG12_1X12,
 456		.data_type = MIPI_CSI2_DT_RAW12,
 457		.width = 12,
 458	}, {
 459		.code = MEDIA_BUS_FMT_SGRBG12_1X12,
 460		.output = MEDIA_BUS_FMT_SGRBG12_1X12,
 461		.data_type = MIPI_CSI2_DT_RAW12,
 462		.width = 12,
 463	}, {
 464		.code = MEDIA_BUS_FMT_SRGGB12_1X12,
 465		.output = MEDIA_BUS_FMT_SRGGB12_1X12,
 466		.data_type = MIPI_CSI2_DT_RAW12,
 467		.width = 12,
 468	}, {
 469		.code = MEDIA_BUS_FMT_Y12_1X12,
 470		.output = MEDIA_BUS_FMT_Y12_1X12,
 471		.data_type = MIPI_CSI2_DT_RAW12,
 472		.width = 12,
 473	}, {
 474		.code = MEDIA_BUS_FMT_SBGGR14_1X14,
 475		.output = MEDIA_BUS_FMT_SBGGR14_1X14,
 476		.data_type = MIPI_CSI2_DT_RAW14,
 477		.width = 14,
 478	}, {
 479		.code = MEDIA_BUS_FMT_SGBRG14_1X14,
 480		.output = MEDIA_BUS_FMT_SGBRG14_1X14,
 481		.data_type = MIPI_CSI2_DT_RAW14,
 482		.width = 14,
 483	}, {
 484		.code = MEDIA_BUS_FMT_SGRBG14_1X14,
 485		.output = MEDIA_BUS_FMT_SGRBG14_1X14,
 486		.data_type = MIPI_CSI2_DT_RAW14,
 487		.width = 14,
 488	}, {
 489		.code = MEDIA_BUS_FMT_SRGGB14_1X14,
 490		.output = MEDIA_BUS_FMT_SRGGB14_1X14,
 491		.data_type = MIPI_CSI2_DT_RAW14,
 492		.width = 14,
 493	},
 494	/* JPEG */
 495	{
 496		.code = MEDIA_BUS_FMT_JPEG_1X8,
 497		.output = MEDIA_BUS_FMT_JPEG_1X8,
 498		/*
 499		 * Map JPEG_1X8 to the RAW8 datatype.
 500		 *
 501		 * The CSI-2 specification suggests in Annex A "JPEG8 Data
 502		 * Format (informative)" to transmit JPEG data using one of the
 503		 * Data Types aimed to represent arbitrary data, such as the
 504		 * "User Defined Data Type 1" (0x30).
 505		 *
 506		 * However, when configured with a User Defined Data Type, the
 507		 * CSIS outputs data in quad pixel mode regardless of the mode
 508		 * selected in the MIPI_CSIS_ISP_CONFIG_CH register. Neither of
 509		 * the IP cores connected to the CSIS in i.MX SoCs (CSI bridge
 510		 * or ISI) support quad pixel mode, so this will never work in
 511		 * practice.
 512		 *
 513		 * Some sensors (such as the OV5640) send JPEG data using the
 514		 * RAW8 data type. This is usable and works, so map the JPEG
 515		 * format to RAW8. If the CSIS ends up being integrated in an
 516		 * SoC that can support quad pixel mode, this will have to be
 517		 * revisited.
 518		 */
 519		.data_type = MIPI_CSI2_DT_RAW8,
 520		.width = 8,
 521	}
 522};
 523
 524static const struct csis_pix_format *find_csis_format(u32 code)
 525{
 526	unsigned int i;
 527
 528	for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++)
 529		if (code == mipi_csis_formats[i].code)
 530			return &mipi_csis_formats[i];
 531	return NULL;
 532}
 533
 534/* -----------------------------------------------------------------------------
 535 * Hardware configuration
 536 */
 537
 538static inline u32 mipi_csis_read(struct mipi_csis_device *csis, u32 reg)
 539{
 540	return readl(csis->regs + reg);
 541}
 542
 543static inline void mipi_csis_write(struct mipi_csis_device *csis, u32 reg,
 544				   u32 val)
 545{
 546	writel(val, csis->regs + reg);
 547}
 548
 549static void mipi_csis_enable_interrupts(struct mipi_csis_device *csis, bool on)
 550{
 551	mipi_csis_write(csis, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0);
 552	mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0);
 553}
 554
 555static void mipi_csis_sw_reset(struct mipi_csis_device *csis)
 556{
 557	u32 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
 558
 559	mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL,
 560			val | MIPI_CSIS_CMN_CTRL_SW_RESET);
 561	usleep_range(10, 20);
 562}
 563
 564static void mipi_csis_system_enable(struct mipi_csis_device *csis, int on)
 565{
 566	u32 val, mask;
 567
 568	val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
 569	if (on)
 570		val |= MIPI_CSIS_CMN_CTRL_CSI_EN;
 571	else
 572		val &= ~MIPI_CSIS_CMN_CTRL_CSI_EN;
 573	mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val);
 574
 575	val = mipi_csis_read(csis, MIPI_CSIS_DPHY_CMN_CTRL);
 576	val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE;
 577	if (on) {
 578		mask = (1 << (csis->num_data_lanes + 1)) - 1;
 579		val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE);
 580	}
 581	mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, val);
 582}
 583
 584static void __mipi_csis_set_format(struct mipi_csis_device *csis,
 585				   const struct v4l2_mbus_framefmt *format,
 586				   const struct csis_pix_format *csis_fmt)
 587{
 588	u32 val;
 589
 590	/* Color format */
 591	val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(0));
 592	val &= ~(MIPI_CSIS_ISPCFG_PARALLEL | MIPI_CSIS_ISPCFG_PIXEL_MODE_MASK |
 593		 MIPI_CSIS_ISPCFG_DATAFORMAT_MASK);
 594
 595	/*
 596	 * YUV 4:2:2 can be transferred with 8 or 16 bits per clock sample
 597	 * (referred to in the documentation as single and dual pixel modes
 598	 * respectively, although the 8-bit mode transfers half a pixel per
 599	 * clock sample and the 16-bit mode one pixel). While both mode work
 600	 * when the CSIS is connected to a receiver that supports either option,
 601	 * single pixel mode requires clock rates twice as high. As all SoCs
 602	 * that integrate the CSIS can operate in 16-bit bit mode, and some do
 603	 * not support 8-bit mode (this is the case of the i.MX8MP), use dual
 604	 * pixel mode unconditionally.
 605	 *
 606	 * TODO: Verify which other formats require DUAL (or QUAD) modes.
 607	 */
 608	if (csis_fmt->data_type == MIPI_CSI2_DT_YUV422_8B)
 609		val |= MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL;
 610
 611	val |= MIPI_CSIS_ISPCFG_DATAFORMAT(csis_fmt->data_type);
 612	mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(0), val);
 613
 614	/* Pixel resolution */
 615	mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0),
 616			MIPI_CSIS_ISP_RESOL_VRESOL(format->height) |
 617			MIPI_CSIS_ISP_RESOL_HRESOL(format->width));
 618}
 619
 620static int mipi_csis_calculate_params(struct mipi_csis_device *csis,
 621				      const struct csis_pix_format *csis_fmt)
 622{
 623	s64 link_freq;
 624	u32 lane_rate;
 625
 626	/* Calculate the line rate from the pixel rate. */
 627	link_freq = v4l2_get_link_freq(csis->source.pad, csis_fmt->width,
 628				       csis->num_data_lanes * 2);
 629	if (link_freq < 0) {
 630		dev_err(csis->dev, "Unable to obtain link frequency: %d\n",
 631			(int)link_freq);
 632		return link_freq;
 633	}
 634
 635	lane_rate = link_freq * 2;
 636
 637	if (lane_rate < 80000000 || lane_rate > 1500000000) {
 638		dev_dbg(csis->dev, "Out-of-bound lane rate %u\n", lane_rate);
 639		return -EINVAL;
 640	}
 641
 642	/*
 643	 * The HSSETTLE counter value is document in a table, but can also
 644	 * easily be calculated. Hardcode the CLKSETTLE value to 0 for now
 645	 * (which is documented as corresponding to CSI-2 v0.87 to v1.00) until
 646	 * we figure out how to compute it correctly.
 647	 */
 648	csis->hs_settle = (lane_rate - 5000000) / 45000000;
 649	csis->clk_settle = 0;
 650
 651	dev_dbg(csis->dev, "lane rate %u, Tclk_settle %u, Ths_settle %u\n",
 652		lane_rate, csis->clk_settle, csis->hs_settle);
 653
 654	if (csis->debug.hs_settle < 0xff) {
 655		dev_dbg(csis->dev, "overriding Ths_settle with %u\n",
 656			csis->debug.hs_settle);
 657		csis->hs_settle = csis->debug.hs_settle;
 658	}
 659
 660	if (csis->debug.clk_settle < 4) {
 661		dev_dbg(csis->dev, "overriding Tclk_settle with %u\n",
 662			csis->debug.clk_settle);
 663		csis->clk_settle = csis->debug.clk_settle;
 664	}
 665
 666	return 0;
 667}
 668
 669static void mipi_csis_set_params(struct mipi_csis_device *csis,
 670				 const struct v4l2_mbus_framefmt *format,
 671				 const struct csis_pix_format *csis_fmt)
 672{
 673	int lanes = csis->num_data_lanes;
 674	u32 val;
 675
 676	val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
 677	val &= ~MIPI_CSIS_CMN_CTRL_LANE_NUMBER_MASK;
 678	val |= MIPI_CSIS_CMN_CTRL_LANE_NUMBER(lanes - 1);
 679	if (csis->info->version == MIPI_CSIS_V3_3)
 680		val |= MIPI_CSIS_CMN_CTRL_INTERLEAVE_MODE_DT;
 681	mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val);
 682
 683	__mipi_csis_set_format(csis, format, csis_fmt);
 684
 685	mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL,
 686			MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(csis->hs_settle) |
 687			MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(csis->clk_settle));
 688
 689	mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0),
 690			MIPI_CSIS_ISP_SYNC_HSYNC_LINTV(0) |
 691			MIPI_CSIS_ISP_SYNC_VSYNC_SINTV(0) |
 692			MIPI_CSIS_ISP_SYNC_VSYNC_EINTV(0));
 693
 694	val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL);
 695	val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC(0);
 696	val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL(0, 15);
 697	val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MASK;
 698	mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val);
 699
 700	mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_L,
 701			MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV |
 702			MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ |
 703			MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V |
 704			MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV |
 705			MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV |
 706			MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV |
 707			MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(20000000));
 708	mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_H, 0);
 709
 710	/* Update the shadow register. */
 711	val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
 712	mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL,
 713			val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW(0) |
 714			MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL);
 715}
 716
 717static int mipi_csis_clk_enable(struct mipi_csis_device *csis)
 718{
 719	return clk_bulk_prepare_enable(csis->info->num_clocks, csis->clks);
 720}
 721
 722static void mipi_csis_clk_disable(struct mipi_csis_device *csis)
 723{
 724	clk_bulk_disable_unprepare(csis->info->num_clocks, csis->clks);
 725}
 726
 727static int mipi_csis_clk_get(struct mipi_csis_device *csis)
 728{
 729	unsigned int i;
 730	int ret;
 731
 732	csis->clks = devm_kcalloc(csis->dev, csis->info->num_clocks,
 733				  sizeof(*csis->clks), GFP_KERNEL);
 734
 735	if (!csis->clks)
 736		return -ENOMEM;
 737
 738	for (i = 0; i < csis->info->num_clocks; i++)
 739		csis->clks[i].id = mipi_csis_clk_id[i];
 740
 741	ret = devm_clk_bulk_get(csis->dev, csis->info->num_clocks,
 742				csis->clks);
 743	if (ret < 0)
 744		return ret;
 745
 746	if (csis->clk_frequency) {
 747		/*
 748		 * Set the clock rate. This is deprecated, for backward
 749		 * compatibility with old device trees.
 750		 */
 751		ret = clk_set_rate(csis->clks[MIPI_CSIS_CLK_WRAP].clk,
 752				   csis->clk_frequency);
 753		if (ret < 0)
 754			dev_err(csis->dev, "set rate=%d failed: %d\n",
 755				csis->clk_frequency, ret);
 756	}
 757
 758	return ret;
 759}
 760
 761static void mipi_csis_start_stream(struct mipi_csis_device *csis,
 762				   const struct v4l2_mbus_framefmt *format,
 763				   const struct csis_pix_format *csis_fmt)
 764{
 765	mipi_csis_sw_reset(csis);
 766	mipi_csis_set_params(csis, format, csis_fmt);
 767	mipi_csis_system_enable(csis, true);
 768	mipi_csis_enable_interrupts(csis, true);
 769}
 770
 771static void mipi_csis_stop_stream(struct mipi_csis_device *csis)
 772{
 773	mipi_csis_enable_interrupts(csis, false);
 774	mipi_csis_system_enable(csis, false);
 775}
 776
 777static void mipi_csis_queue_event_sof(struct mipi_csis_device *csis)
 778{
 779	struct v4l2_event event = {
 780		.type = V4L2_EVENT_FRAME_SYNC,
 781	};
 782	u32 frame;
 783
 784	frame = mipi_csis_read(csis, MIPI_CSIS_FRAME_COUNTER_CH(0));
 785	event.u.frame_sync.frame_sequence = frame;
 786	v4l2_event_queue(csis->sd.devnode, &event);
 787}
 788
 789static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id)
 790{
 791	struct mipi_csis_device *csis = dev_id;
 792	unsigned long flags;
 793	unsigned int i;
 794	u32 status;
 795	u32 dbg_status;
 796
 797	status = mipi_csis_read(csis, MIPI_CSIS_INT_SRC);
 798	dbg_status = mipi_csis_read(csis, MIPI_CSIS_DBG_INTR_SRC);
 799
 800	spin_lock_irqsave(&csis->slock, flags);
 801
 802	/* Update the event/error counters */
 803	if ((status & MIPI_CSIS_INT_SRC_ERRORS) || csis->debug.enable) {
 804		for (i = 0; i < ARRAY_SIZE(csis->events); i++) {
 805			struct mipi_csis_event *event = &csis->events[i];
 806
 807			if (event->channel >= csis->num_channels)
 808				continue;
 809
 810			if ((!event->debug && (status & event->mask)) ||
 811			    (event->debug && (dbg_status & event->mask)))
 812				event->counter++;
 813		}
 814	}
 815
 816	if (status & MIPI_CSIS_INT_SRC_FRAME_START(0))
 817		mipi_csis_queue_event_sof(csis);
 818
 819	spin_unlock_irqrestore(&csis->slock, flags);
 820
 821	mipi_csis_write(csis, MIPI_CSIS_INT_SRC, status);
 822	mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_SRC, dbg_status);
 823
 824	return IRQ_HANDLED;
 825}
 826
 827/* -----------------------------------------------------------------------------
 828 * PHY regulator and reset
 829 */
 830
 831static int mipi_csis_phy_enable(struct mipi_csis_device *csis)
 832{
 833	if (csis->info->version != MIPI_CSIS_V3_3)
 834		return 0;
 835
 836	return regulator_enable(csis->mipi_phy_regulator);
 837}
 838
 839static int mipi_csis_phy_disable(struct mipi_csis_device *csis)
 840{
 841	if (csis->info->version != MIPI_CSIS_V3_3)
 842		return 0;
 843
 844	return regulator_disable(csis->mipi_phy_regulator);
 845}
 846
 847static void mipi_csis_phy_reset(struct mipi_csis_device *csis)
 848{
 849	if (csis->info->version != MIPI_CSIS_V3_3)
 850		return;
 851
 852	reset_control_assert(csis->mrst);
 853	msleep(20);
 854	reset_control_deassert(csis->mrst);
 855}
 856
 857static int mipi_csis_phy_init(struct mipi_csis_device *csis)
 858{
 859	if (csis->info->version != MIPI_CSIS_V3_3)
 860		return 0;
 861
 862	/* Get MIPI PHY reset and regulator. */
 863	csis->mrst = devm_reset_control_get_exclusive(csis->dev, NULL);
 864	if (IS_ERR(csis->mrst))
 865		return PTR_ERR(csis->mrst);
 866
 867	csis->mipi_phy_regulator = devm_regulator_get(csis->dev, "phy");
 868	if (IS_ERR(csis->mipi_phy_regulator))
 869		return PTR_ERR(csis->mipi_phy_regulator);
 870
 871	return regulator_set_voltage(csis->mipi_phy_regulator, 1000000,
 872				     1000000);
 873}
 874
 875/* -----------------------------------------------------------------------------
 876 * Debug
 877 */
 878
 879static void mipi_csis_clear_counters(struct mipi_csis_device *csis)
 880{
 881	unsigned long flags;
 882	unsigned int i;
 883
 884	spin_lock_irqsave(&csis->slock, flags);
 885	for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++)
 886		csis->events[i].counter = 0;
 887	spin_unlock_irqrestore(&csis->slock, flags);
 888}
 889
 890static void mipi_csis_log_counters(struct mipi_csis_device *csis, bool non_errors)
 891{
 892	unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS
 893				: MIPI_CSIS_NUM_ERROR_EVENTS;
 894	unsigned int counters[MIPI_CSIS_NUM_EVENTS];
 895	unsigned long flags;
 896	unsigned int i;
 897
 898	spin_lock_irqsave(&csis->slock, flags);
 899	for (i = 0; i < num_events; ++i)
 900		counters[i] =  csis->events[i].counter;
 901	spin_unlock_irqrestore(&csis->slock, flags);
 902
 903	for (i = 0; i < num_events; ++i) {
 904		const struct mipi_csis_event *event = &csis->events[i];
 905
 906		if (event->channel >= csis->num_channels)
 907			continue;
 908
 909		if (counters[i] > 0 || csis->debug.enable)
 910			dev_info(csis->dev, "%s events: %d\n",
 911				 event->name, counters[i]);
 912	}
 913}
 914
 915struct mipi_csis_reg_info {
 916	u32 addr;
 917	unsigned int offset;
 918	const char * const name;
 919};
 920
 921static void mipi_csis_dump_channel_reg(struct mipi_csis_device *csis,
 922				       const struct mipi_csis_reg_info *reg,
 923				       unsigned int channel)
 924{
 925	dev_info(csis->dev, "%16s%u: 0x%08x\n", reg->name, channel,
 926		 mipi_csis_read(csis, reg->addr + channel * reg->offset));
 927}
 928
 929static int mipi_csis_dump_regs(struct mipi_csis_device *csis)
 930{
 931	static const struct mipi_csis_reg_info common_registers[] = {
 932		{ MIPI_CSIS_CMN_CTRL, 0, "CMN_CTRL" },
 933		{ MIPI_CSIS_CLK_CTRL, 0, "CLK_CTRL" },
 934		{ MIPI_CSIS_INT_MSK, 0, "INT_MSK" },
 935		{ MIPI_CSIS_DPHY_STATUS, 0, "DPHY_STATUS" },
 936		{ MIPI_CSIS_DPHY_CMN_CTRL, 0, "DPHY_CMN_CTRL" },
 937		{ MIPI_CSIS_DPHY_SCTRL_L, 0, "DPHY_SCTRL_L" },
 938		{ MIPI_CSIS_DPHY_SCTRL_H, 0, "DPHY_SCTRL_H" },
 939		{ MIPI_CSIS_DBG_CTRL, 0, "DBG_CTRL" },
 940	};
 941	static const struct mipi_csis_reg_info channel_registers[] = {
 942		{ MIPI_CSIS_ISP_CONFIG_CH(0), 0x10, "ISP_CONFIG_CH" },
 943		{ MIPI_CSIS_ISP_RESOL_CH(0), 0x10, "ISP_RESOL_CH" },
 944		{ MIPI_CSIS_SDW_CONFIG_CH(0), 0x10, "SDW_CONFIG_CH" },
 945		{ MIPI_CSIS_SDW_RESOL_CH(0), 0x10, "SDW_RESOL_CH" },
 946		{ MIPI_CSIS_FRAME_COUNTER_CH(0), 4, "FRAME_COUNTER_CH" },
 947	};
 948
 949	if (!pm_runtime_get_if_in_use(csis->dev))
 950		return 0;
 951
 952	dev_info(csis->dev, "--- REGISTERS ---\n");
 953
 954	for (unsigned int i = 0; i < ARRAY_SIZE(common_registers); i++) {
 955		const struct mipi_csis_reg_info *reg = &common_registers[i];
 956
 957		dev_info(csis->dev, "%17s: 0x%08x\n", reg->name,
 958			 mipi_csis_read(csis, reg->addr));
 959	}
 960
 961	for (unsigned int chan = 0; chan < csis->num_channels; chan++) {
 962		for (unsigned int i = 0; i < ARRAY_SIZE(channel_registers); ++i)
 963			mipi_csis_dump_channel_reg(csis, &channel_registers[i],
 964						   chan);
 965	}
 966
 967	pm_runtime_put(csis->dev);
 968
 969	return 0;
 970}
 971
 972static int mipi_csis_dump_regs_show(struct seq_file *m, void *private)
 973{
 974	struct mipi_csis_device *csis = m->private;
 975
 976	return mipi_csis_dump_regs(csis);
 977}
 978DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs);
 979
 980static void mipi_csis_debugfs_init(struct mipi_csis_device *csis)
 981{
 982	csis->debug.hs_settle = UINT_MAX;
 983	csis->debug.clk_settle = UINT_MAX;
 984
 985	csis->debugfs_root = debugfs_create_dir(dev_name(csis->dev), NULL);
 986
 987	debugfs_create_bool("debug_enable", 0600, csis->debugfs_root,
 988			    &csis->debug.enable);
 989	debugfs_create_file("dump_regs", 0600, csis->debugfs_root, csis,
 990			    &mipi_csis_dump_regs_fops);
 991	debugfs_create_u32("tclk_settle", 0600, csis->debugfs_root,
 992			   &csis->debug.clk_settle);
 993	debugfs_create_u32("ths_settle", 0600, csis->debugfs_root,
 994			   &csis->debug.hs_settle);
 995}
 996
 997static void mipi_csis_debugfs_exit(struct mipi_csis_device *csis)
 998{
 999	debugfs_remove_recursive(csis->debugfs_root);
1000}
1001
1002/* -----------------------------------------------------------------------------
1003 * V4L2 subdev operations
1004 */
1005
1006static struct mipi_csis_device *sd_to_mipi_csis_device(struct v4l2_subdev *sdev)
1007{
1008	return container_of(sdev, struct mipi_csis_device, sd);
1009}
1010
1011static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable)
1012{
1013	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1014	const struct v4l2_mbus_framefmt *format;
1015	const struct csis_pix_format *csis_fmt;
1016	struct v4l2_subdev_state *state;
1017	int ret;
1018
1019	if (!enable) {
1020		v4l2_subdev_disable_streams(csis->source.sd,
1021					    csis->source.pad->index, BIT(0));
1022
1023		mipi_csis_stop_stream(csis);
1024		if (csis->debug.enable)
1025			mipi_csis_log_counters(csis, true);
1026
1027		pm_runtime_put(csis->dev);
1028
1029		return 0;
1030	}
1031
1032	state = v4l2_subdev_lock_and_get_active_state(sd);
1033
1034	format = v4l2_subdev_state_get_format(state, CSIS_PAD_SINK);
1035	csis_fmt = find_csis_format(format->code);
1036
1037	ret = v4l2_get_active_data_lanes(csis->source.pad, csis->bus.num_data_lanes);
1038	if (ret < 0)
1039		goto err_unlock;
1040
1041	csis->num_data_lanes = ret;
1042
1043	ret = mipi_csis_calculate_params(csis, csis_fmt);
1044	if (ret < 0)
1045		goto err_unlock;
1046
1047	mipi_csis_clear_counters(csis);
1048
1049	ret = pm_runtime_resume_and_get(csis->dev);
1050	if (ret < 0)
1051		goto err_unlock;
1052
1053	mipi_csis_start_stream(csis, format, csis_fmt);
1054
1055	ret = v4l2_subdev_enable_streams(csis->source.sd,
1056					 csis->source.pad->index, BIT(0));
1057	if (ret < 0)
1058		goto err_stop;
1059
1060	mipi_csis_log_counters(csis, true);
1061
1062	v4l2_subdev_unlock_state(state);
1063
1064	return 0;
1065
1066err_stop:
1067	mipi_csis_stop_stream(csis);
1068	pm_runtime_put(csis->dev);
1069err_unlock:
1070	v4l2_subdev_unlock_state(state);
1071
1072	return ret;
1073}
1074
1075static int mipi_csis_enum_mbus_code(struct v4l2_subdev *sd,
1076				    struct v4l2_subdev_state *state,
1077				    struct v4l2_subdev_mbus_code_enum *code)
1078{
1079	/*
1080	 * The CSIS can't transcode in any way, the source format is identical
1081	 * to the sink format.
1082	 */
1083	if (code->pad == CSIS_PAD_SOURCE) {
1084		struct v4l2_mbus_framefmt *fmt;
1085
1086		if (code->index > 0)
1087			return -EINVAL;
1088
1089		fmt = v4l2_subdev_state_get_format(state, code->pad);
1090		code->code = fmt->code;
1091		return 0;
1092	}
1093
1094	if (code->pad != CSIS_PAD_SINK)
1095		return -EINVAL;
1096
1097	if (code->index >= ARRAY_SIZE(mipi_csis_formats))
1098		return -EINVAL;
1099
1100	code->code = mipi_csis_formats[code->index].code;
1101
1102	return 0;
1103}
1104
1105static int mipi_csis_set_fmt(struct v4l2_subdev *sd,
1106			     struct v4l2_subdev_state *state,
1107			     struct v4l2_subdev_format *sdformat)
1108{
1109	const struct csis_pix_format *csis_fmt;
1110	struct v4l2_mbus_framefmt *fmt;
1111	unsigned int align;
1112
1113	/*
1114	 * The CSIS can't transcode in any way, the source format can't be
1115	 * modified.
1116	 */
1117	if (sdformat->pad == CSIS_PAD_SOURCE)
1118		return v4l2_subdev_get_fmt(sd, state, sdformat);
1119
1120	if (sdformat->pad != CSIS_PAD_SINK)
1121		return -EINVAL;
1122
1123	/*
1124	 * Validate the media bus code and clamp and align the size.
1125	 *
1126	 * The total number of bits per line must be a multiple of 8. We thus
1127	 * need to align the width for formats that are not multiples of 8
1128	 * bits.
1129	 */
1130	csis_fmt = find_csis_format(sdformat->format.code);
1131	if (!csis_fmt)
1132		csis_fmt = &mipi_csis_formats[0];
1133
1134	switch (csis_fmt->width % 8) {
1135	case 0:
1136		align = 0;
1137		break;
1138	case 4:
1139		align = 1;
1140		break;
1141	case 2:
1142	case 6:
1143		align = 2;
1144		break;
1145	default:
1146		/* 1, 3, 5, 7 */
1147		align = 3;
1148		break;
1149	}
1150
1151	v4l_bound_align_image(&sdformat->format.width, 1,
1152			      CSIS_MAX_PIX_WIDTH, align,
1153			      &sdformat->format.height, 1,
1154			      CSIS_MAX_PIX_HEIGHT, 0, 0);
1155
1156	fmt = v4l2_subdev_state_get_format(state, sdformat->pad);
1157
1158	fmt->code = csis_fmt->code;
1159	fmt->width = sdformat->format.width;
1160	fmt->height = sdformat->format.height;
1161	fmt->field = V4L2_FIELD_NONE;
1162	fmt->colorspace = sdformat->format.colorspace;
1163	fmt->quantization = sdformat->format.quantization;
1164	fmt->xfer_func = sdformat->format.xfer_func;
1165	fmt->ycbcr_enc = sdformat->format.ycbcr_enc;
1166
1167	sdformat->format = *fmt;
1168
1169	/* Propagate the format from sink to source. */
1170	fmt = v4l2_subdev_state_get_format(state, CSIS_PAD_SOURCE);
1171	*fmt = sdformat->format;
1172
1173	/* The format on the source pad might change due to unpacking. */
1174	fmt->code = csis_fmt->output;
1175
1176	return 0;
1177}
1178
1179static int mipi_csis_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
1180				    struct v4l2_mbus_frame_desc *fd)
1181{
1182	struct v4l2_mbus_frame_desc_entry *entry = &fd->entry[0];
1183	const struct csis_pix_format *csis_fmt;
1184	const struct v4l2_mbus_framefmt *fmt;
1185	struct v4l2_subdev_state *state;
1186
1187	if (pad != CSIS_PAD_SOURCE)
1188		return -EINVAL;
1189
1190	state = v4l2_subdev_lock_and_get_active_state(sd);
1191	fmt = v4l2_subdev_state_get_format(state, CSIS_PAD_SOURCE);
1192	csis_fmt = find_csis_format(fmt->code);
1193	v4l2_subdev_unlock_state(state);
1194
1195	if (!csis_fmt)
1196		return -EPIPE;
1197
1198	fd->type = V4L2_MBUS_FRAME_DESC_TYPE_PARALLEL;
1199	fd->num_entries = 1;
1200
1201	entry->flags = 0;
1202	entry->pixelcode = csis_fmt->code;
1203	entry->bus.csi2.vc = 0;
1204	entry->bus.csi2.dt = csis_fmt->data_type;
1205
1206	return 0;
1207}
1208
1209static int mipi_csis_init_state(struct v4l2_subdev *sd,
1210				struct v4l2_subdev_state *state)
1211{
1212	struct v4l2_subdev_format fmt = {
1213		.pad = CSIS_PAD_SINK,
1214	};
1215
1216	fmt.format.code = mipi_csis_formats[0].code;
1217	fmt.format.width = MIPI_CSIS_DEF_PIX_WIDTH;
1218	fmt.format.height = MIPI_CSIS_DEF_PIX_HEIGHT;
1219
1220	fmt.format.colorspace = V4L2_COLORSPACE_SMPTE170M;
1221	fmt.format.xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt.format.colorspace);
1222	fmt.format.ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt.format.colorspace);
1223	fmt.format.quantization =
1224		V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt.format.colorspace,
1225					      fmt.format.ycbcr_enc);
1226
1227	return mipi_csis_set_fmt(sd, state, &fmt);
1228}
1229
1230static int mipi_csis_log_status(struct v4l2_subdev *sd)
1231{
1232	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1233
1234	mipi_csis_log_counters(csis, true);
1235	if (csis->debug.enable)
1236		mipi_csis_dump_regs(csis);
1237
1238	return 0;
1239}
1240
1241static int mipi_csis_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1242				     struct v4l2_event_subscription *sub)
1243{
1244	if (sub->type != V4L2_EVENT_FRAME_SYNC)
1245		return -EINVAL;
1246
1247	/* V4L2_EVENT_FRAME_SYNC doesn't require an id, so zero should be set */
1248	if (sub->id != 0)
1249		return -EINVAL;
1250
1251	return v4l2_event_subscribe(fh, sub, 0, NULL);
1252}
1253
1254static const struct v4l2_subdev_core_ops mipi_csis_core_ops = {
1255	.log_status	= mipi_csis_log_status,
1256	.subscribe_event =  mipi_csis_subscribe_event,
1257	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
1258};
1259
1260static const struct v4l2_subdev_video_ops mipi_csis_video_ops = {
1261	.s_stream	= mipi_csis_s_stream,
1262};
1263
1264static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = {
1265	.enum_mbus_code		= mipi_csis_enum_mbus_code,
1266	.get_fmt		= v4l2_subdev_get_fmt,
1267	.set_fmt		= mipi_csis_set_fmt,
1268	.get_frame_desc		= mipi_csis_get_frame_desc,
1269};
1270
1271static const struct v4l2_subdev_ops mipi_csis_subdev_ops = {
1272	.core	= &mipi_csis_core_ops,
1273	.video	= &mipi_csis_video_ops,
1274	.pad	= &mipi_csis_pad_ops,
1275};
1276
1277static const struct v4l2_subdev_internal_ops mipi_csis_internal_ops = {
1278	.init_state		= mipi_csis_init_state,
1279};
1280
1281/* -----------------------------------------------------------------------------
1282 * Media entity operations
1283 */
1284
1285static int mipi_csis_link_setup(struct media_entity *entity,
1286				const struct media_pad *local_pad,
1287				const struct media_pad *remote_pad, u32 flags)
1288{
1289	struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1290	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1291	struct v4l2_subdev *remote_sd;
1292
1293	dev_dbg(csis->dev, "link setup %s -> %s", remote_pad->entity->name,
1294		local_pad->entity->name);
1295
1296	/* We only care about the link to the source. */
1297	if (!(local_pad->flags & MEDIA_PAD_FL_SINK))
1298		return 0;
1299
1300	remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity);
1301
1302	if (flags & MEDIA_LNK_FL_ENABLED) {
1303		if (csis->source.sd)
1304			return -EBUSY;
1305
1306		csis->source.sd = remote_sd;
1307		csis->source.pad = remote_pad;
1308	} else {
1309		csis->source.sd = NULL;
1310		csis->source.pad = NULL;
1311	}
1312
1313	return 0;
1314}
1315
1316static const struct media_entity_operations mipi_csis_entity_ops = {
1317	.link_setup	= mipi_csis_link_setup,
1318	.link_validate	= v4l2_subdev_link_validate,
1319	.get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
1320};
1321
1322/* -----------------------------------------------------------------------------
1323 * Async subdev notifier
1324 */
1325
1326static struct mipi_csis_device *
1327mipi_notifier_to_csis_state(struct v4l2_async_notifier *n)
1328{
1329	return container_of(n, struct mipi_csis_device, notifier);
1330}
1331
1332static int mipi_csis_notify_bound(struct v4l2_async_notifier *notifier,
1333				  struct v4l2_subdev *sd,
1334				  struct v4l2_async_connection *asd)
1335{
1336	struct mipi_csis_device *csis = mipi_notifier_to_csis_state(notifier);
1337	struct media_pad *sink = &csis->sd.entity.pads[CSIS_PAD_SINK];
1338
1339	return v4l2_create_fwnode_links_to_pad(sd, sink, 0);
1340}
1341
1342static const struct v4l2_async_notifier_operations mipi_csis_notify_ops = {
1343	.bound = mipi_csis_notify_bound,
1344};
1345
1346static int mipi_csis_async_register(struct mipi_csis_device *csis)
1347{
1348	struct v4l2_fwnode_endpoint vep = {
1349		.bus_type = V4L2_MBUS_CSI2_DPHY,
1350	};
1351	struct v4l2_async_connection *asd;
1352	struct fwnode_handle *ep;
1353	unsigned int i;
1354	int ret;
1355
1356	v4l2_async_subdev_nf_init(&csis->notifier, &csis->sd);
1357
1358	ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csis->dev), 0, 0,
1359					     FWNODE_GRAPH_ENDPOINT_NEXT);
1360	if (!ep)
1361		return -ENOTCONN;
1362
1363	ret = v4l2_fwnode_endpoint_parse(ep, &vep);
1364	if (ret)
1365		goto err_parse;
1366
1367	for (i = 0; i < vep.bus.mipi_csi2.num_data_lanes; ++i) {
1368		if (vep.bus.mipi_csi2.data_lanes[i] != i + 1) {
1369			dev_err(csis->dev,
1370				"data lanes reordering is not supported");
1371			ret = -EINVAL;
1372			goto err_parse;
1373		}
1374	}
1375
1376	csis->bus = vep.bus.mipi_csi2;
1377	csis->num_data_lanes = csis->bus.num_data_lanes;
1378
1379	dev_dbg(csis->dev, "max data lanes: %d\n", csis->bus.num_data_lanes);
1380	dev_dbg(csis->dev, "flags: 0x%08x\n", csis->bus.flags);
1381
1382	asd = v4l2_async_nf_add_fwnode_remote(&csis->notifier, ep,
1383					      struct v4l2_async_connection);
1384	if (IS_ERR(asd)) {
1385		ret = PTR_ERR(asd);
1386		goto err_parse;
1387	}
1388
1389	fwnode_handle_put(ep);
1390
1391	csis->notifier.ops = &mipi_csis_notify_ops;
1392
1393	ret = v4l2_async_nf_register(&csis->notifier);
1394	if (ret)
1395		return ret;
1396
1397	return v4l2_async_register_subdev(&csis->sd);
1398
1399err_parse:
1400	fwnode_handle_put(ep);
1401
1402	return ret;
1403}
1404
1405/* -----------------------------------------------------------------------------
1406 * Suspend/resume
1407 */
1408
1409static int mipi_csis_runtime_suspend(struct device *dev)
1410{
1411	struct v4l2_subdev *sd = dev_get_drvdata(dev);
1412	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1413	int ret;
1414
1415	ret = mipi_csis_phy_disable(csis);
1416	if (ret)
1417		return -EAGAIN;
1418
1419	mipi_csis_clk_disable(csis);
1420
1421	return 0;
1422}
1423
1424static int mipi_csis_runtime_resume(struct device *dev)
1425{
1426	struct v4l2_subdev *sd = dev_get_drvdata(dev);
1427	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1428	int ret;
1429
1430	ret = mipi_csis_phy_enable(csis);
1431	if (ret)
1432		return -EAGAIN;
1433
1434	ret = mipi_csis_clk_enable(csis);
1435	if (ret) {
1436		mipi_csis_phy_disable(csis);
1437		return ret;
1438	}
1439
1440	return 0;
1441}
1442
1443static const struct dev_pm_ops mipi_csis_pm_ops = {
1444	RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume,
1445		       NULL)
1446};
1447
1448/* -----------------------------------------------------------------------------
1449 * Probe/remove & platform driver
1450 */
1451
1452static int mipi_csis_subdev_init(struct mipi_csis_device *csis)
1453{
1454	struct v4l2_subdev *sd = &csis->sd;
1455	int ret;
1456
1457	v4l2_subdev_init(sd, &mipi_csis_subdev_ops);
1458	sd->internal_ops = &mipi_csis_internal_ops;
1459	sd->owner = THIS_MODULE;
1460	snprintf(sd->name, sizeof(sd->name), "csis-%s",
1461		 dev_name(csis->dev));
1462
1463	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1464	sd->ctrl_handler = NULL;
1465
1466	sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
1467	sd->entity.ops = &mipi_csis_entity_ops;
1468
1469	sd->dev = csis->dev;
1470
1471	csis->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK
1472					 | MEDIA_PAD_FL_MUST_CONNECT;
1473	csis->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE
1474					   | MEDIA_PAD_FL_MUST_CONNECT;
1475	ret = media_entity_pads_init(&sd->entity, CSIS_PADS_NUM, csis->pads);
1476	if (ret)
1477		return ret;
1478
1479	ret = v4l2_subdev_init_finalize(sd);
1480	if (ret) {
1481		media_entity_cleanup(&sd->entity);
1482		return ret;
1483	}
1484
1485	return 0;
1486}
1487
1488static int mipi_csis_parse_dt(struct mipi_csis_device *csis)
1489{
1490	struct device_node *node = csis->dev->of_node;
1491
1492	of_property_read_u32(node, "clock-frequency", &csis->clk_frequency);
1493	dev_dbg(csis->dev, "clock frequency: %u\n", csis->clk_frequency);
1494
1495	csis->num_channels = 1;
1496	of_property_read_u32(node, "fsl,num-channels", &csis->num_channels);
1497	if (csis->num_channels < 1 || csis->num_channels > MIPI_CSIS_MAX_CHANNELS)
1498		return dev_err_probe(csis->dev, -EINVAL,
1499				     "Invalid fsl,num-channels value\n");
1500
1501	return 0;
1502}
1503
1504static int mipi_csis_probe(struct platform_device *pdev)
1505{
1506	struct device *dev = &pdev->dev;
1507	struct mipi_csis_device *csis;
1508	int irq;
1509	int ret;
1510
1511	csis = devm_kzalloc(dev, sizeof(*csis), GFP_KERNEL);
1512	if (!csis)
1513		return -ENOMEM;
1514
1515	spin_lock_init(&csis->slock);
1516
1517	csis->dev = dev;
1518	csis->info = of_device_get_match_data(dev);
1519
1520	memcpy(csis->events, mipi_csis_events, sizeof(csis->events));
1521
1522	/* Parse DT properties. */
1523	ret = mipi_csis_parse_dt(csis);
1524	if (ret < 0)
1525		return ret;
1526
1527	/* Acquire resources. */
1528	csis->regs = devm_platform_ioremap_resource(pdev, 0);
1529	if (IS_ERR(csis->regs))
1530		return PTR_ERR(csis->regs);
1531
1532	irq = platform_get_irq(pdev, 0);
1533	if (irq < 0)
1534		return irq;
1535
1536	ret = mipi_csis_phy_init(csis);
1537	if (ret < 0)
1538		return ret;
1539
1540	ret = mipi_csis_clk_get(csis);
1541	if (ret < 0)
1542		return ret;
1543
1544	/* Reset PHY and enable the clocks. */
1545	mipi_csis_phy_reset(csis);
1546
1547	/* Now that the hardware is initialized, request the interrupt. */
1548	ret = devm_request_irq(dev, irq, mipi_csis_irq_handler, 0,
1549			       dev_name(dev), csis);
1550	if (ret) {
1551		dev_err(dev, "Interrupt request failed\n");
1552		return ret;
1553	}
1554
1555	/* Initialize and register the subdev. */
1556	ret = mipi_csis_subdev_init(csis);
1557	if (ret < 0)
1558		return ret;
1559
1560	platform_set_drvdata(pdev, &csis->sd);
1561
1562	ret = mipi_csis_async_register(csis);
1563	if (ret < 0) {
1564		dev_err(dev, "async register failed: %d\n", ret);
1565		goto err_cleanup;
1566	}
1567
1568	/* Initialize debugfs. */
1569	mipi_csis_debugfs_init(csis);
1570
1571	/* Enable runtime PM. */
1572	pm_runtime_enable(dev);
1573	if (!pm_runtime_enabled(dev)) {
1574		ret = mipi_csis_runtime_resume(dev);
1575		if (ret < 0)
1576			goto err_unregister_all;
1577	}
1578
1579	return 0;
1580
1581err_unregister_all:
1582	mipi_csis_debugfs_exit(csis);
1583err_cleanup:
1584	v4l2_subdev_cleanup(&csis->sd);
1585	media_entity_cleanup(&csis->sd.entity);
1586	v4l2_async_nf_unregister(&csis->notifier);
1587	v4l2_async_nf_cleanup(&csis->notifier);
1588	v4l2_async_unregister_subdev(&csis->sd);
1589
1590	return ret;
1591}
1592
1593static void mipi_csis_remove(struct platform_device *pdev)
1594{
1595	struct v4l2_subdev *sd = platform_get_drvdata(pdev);
1596	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1597
1598	mipi_csis_debugfs_exit(csis);
1599	v4l2_async_nf_unregister(&csis->notifier);
1600	v4l2_async_nf_cleanup(&csis->notifier);
1601	v4l2_async_unregister_subdev(&csis->sd);
1602
1603	if (!pm_runtime_enabled(&pdev->dev))
1604		mipi_csis_runtime_suspend(&pdev->dev);
1605
1606	pm_runtime_disable(&pdev->dev);
1607	v4l2_subdev_cleanup(&csis->sd);
1608	media_entity_cleanup(&csis->sd.entity);
1609	pm_runtime_set_suspended(&pdev->dev);
1610}
1611
1612static const struct of_device_id mipi_csis_of_match[] = {
1613	{
1614		.compatible = "fsl,imx7-mipi-csi2",
1615		.data = &(const struct mipi_csis_info){
1616			.version = MIPI_CSIS_V3_3,
1617			.num_clocks = 3,
1618		},
1619	}, {
1620		.compatible = "fsl,imx8mm-mipi-csi2",
1621		.data = &(const struct mipi_csis_info){
1622			.version = MIPI_CSIS_V3_6_3,
1623			.num_clocks = 4,
1624		},
1625	},
1626	{ /* sentinel */ },
1627};
1628MODULE_DEVICE_TABLE(of, mipi_csis_of_match);
1629
1630static struct platform_driver mipi_csis_driver = {
1631	.probe		= mipi_csis_probe,
1632	.remove		= mipi_csis_remove,
1633	.driver		= {
1634		.of_match_table = mipi_csis_of_match,
1635		.name		= CSIS_DRIVER_NAME,
1636		.pm		= pm_ptr(&mipi_csis_pm_ops),
1637	},
1638};
1639
1640module_platform_driver(mipi_csis_driver);
1641
1642MODULE_DESCRIPTION("i.MX7 & i.MX8 MIPI CSI-2 receiver driver");
1643MODULE_LICENSE("GPL v2");