dw100_regs.h

  1/* SPDX-License-Identifier: GPL-2.0+ */
  2/*
  3 * DW100 Hardware dewarper
  4 *
  5 * Copyright 2022 NXP
  6 * Author: Xavier Roumegue (xavier.roumegue@oss.nxp.com)
  7 */
  8
  9#ifndef _DW100_REGS_H_
 10#define _DW100_REGS_H_
 11
 12/* AHB register offset */
 13#define DW100_DEWARP_ID			0x00
 14#define DW100_DEWARP_CTRL		0x04
 15#define DW100_DEWARP_CTRL_ENABLE			BIT(0)
 16#define DW100_DEWARP_CTRL_START				BIT(1)
 17#define DW100_DEWARP_CTRL_SOFT_RESET			BIT(2)
 18#define DW100_DEWARP_CTRL_FORMAT_YUV422_SP		0UL
 19#define DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED		1UL
 20#define DW100_DEWARP_CTRL_FORMAT_YUV420_SP		2UL
 21#define DW100_DEWARP_CTRL_INPUT_FORMAT_MASK		GENMASK(5, 4)
 22#define DW100_DEWARP_CTRL_INPUT_FORMAT(x)		((x) << 4)
 23#define DW100_DEWARP_CTRL_OUTPUT_FORMAT(x)		((x) << 6)
 24#define DW100_DEWARP_CTRL_OUTPUT_FORMAT_MASK		GENMASK(7, 6)
 25#define DW100_DEWARP_CTRL_SRC_AUTO_SHADOW		BIT(8)
 26#define DW100_DEWARP_CTRL_HW_HANDSHAKE			BIT(9)
 27#define DW100_DEWARP_CTRL_DST_AUTO_SHADOW		BIT(10)
 28#define DW100_DEWARP_CTRL_SPLIT_LINE			BIT(11)
 29#define DW100_DEWARP_CTRL_PREFETCH_MODE_MASK		GENMASK(17, 16)
 30#define DW100_DEWARP_CTRL_PREFETCH_MODE_TRAVERSAL	(0UL << 16)
 31#define DW100_DEWARP_CTRL_PREFETCH_MODE_CALCULATION	(1UL << 16)
 32#define DW100_DEWARP_CTRL_PREFETCH_MODE_AUTO		(2UL << 16)
 33#define DW100_DEWARP_CTRL_PREFETCH_THRESHOLD_MASK	GENMASK(24, 18)
 34#define DW100_DEWARP_CTRL_PREFETCH_THRESHOLD(x)		((x) << 18)
 35
 36#define DW100_MAP_LUT_ADDR		0x08
 37#define DW100_MAP_LUT_ADDR_ADDR(addr)	(((addr) >> 4) & GENMASK(29, 0))
 38#define DW100_MAP_LUT_SIZE		0x0c
 39#define DW100_MAP_LUT_SIZE_WIDTH(w)	(((w) & GENMASK(10, 0)) << 0)
 40#define DW100_MAP_LUT_SIZE_HEIGHT(h)	(((h) & GENMASK(10, 0)) << 16)
 41#define DW100_SRC_IMG_Y_BASE		0x10
 42#define DW100_IMG_Y_BASE(base)		(((base) >> 4) & GENMASK(29, 0))
 43#define DW100_SRC_IMG_UV_BASE		0x14
 44#define DW100_IMG_UV_BASE(base)		(((base) >> 4) & GENMASK(29, 0))
 45#define DW100_SRC_IMG_SIZE		0x18
 46#define DW100_IMG_SIZE_WIDTH(w)		(((w) & GENMASK(12, 0)) << 0)
 47#define DW100_IMG_SIZE_HEIGHT(h)	(((h) & GENMASK(12, 0)) << 16)
 48
 49#define DW100_SRC_IMG_STRIDE		0x1c
 50#define DW100_MAP_LUT_ADDR2		0x20
 51#define DW100_MAP_LUT_SIZE2		0x24
 52#define DW100_SRC_IMG_Y_BASE2		0x28
 53#define DW100_SRC_IMG_UV_BASE2		0x2c
 54#define DW100_SRC_IMG_SIZE2		0x30
 55#define DW100_SRC_IMG_STRIDE2		0x34
 56#define DW100_DST_IMG_Y_BASE		0x38
 57#define DW100_DST_IMG_UV_BASE		0x3c
 58#define DW100_DST_IMG_SIZE		0x40
 59#define DW100_DST_IMG_STRIDE		0x44
 60#define DW100_DST_IMG_Y_BASE2		0x48
 61#define DW100_DST_IMG_UV_BASE2		0x4c
 62#define DW100_DST_IMG_SIZE2		0x50
 63#define DW100_DST_IMG_STRIDE2		0x54
 64#define DW100_SWAP_CONTROL		0x58
 65#define DW100_SWAP_CONTROL_BYTE		BIT(0)
 66#define DW100_SWAP_CONTROL_SHORT	BIT(1)
 67#define DW100_SWAP_CONTROL_WORD		BIT(2)
 68#define DW100_SWAP_CONTROL_LONG		BIT(3)
 69#define DW100_SWAP_CONTROL_Y(x)		(((x) & GENMASK(3, 0)) << 0)
 70#define DW100_SWAP_CONTROL_UV(x)	(((x) & GENMASK(3, 0)) << 4)
 71#define DW100_SWAP_CONTROL_SRC(x)	(((x) & GENMASK(7, 0)) << 0)
 72#define DW100_SWAP_CONTROL_DST(x)	(((x) & GENMASK(7, 0)) << 8)
 73#define DW100_SWAP_CONTROL_SRC2(x)	(((x) & GENMASK(7, 0)) << 16)
 74#define DW100_SWAP_CONTROL_DST2(x)	(((x) & GENMASK(7, 0)) << 24)
 75#define DW100_SWAP_CONTROL_SRC_MASK	GENMASK(7, 0)
 76#define DW100_SWAP_CONTROL_DST_MASK	GENMASK(15, 8)
 77#define DW100_SWAP_CONTROL_SRC2_MASK	GENMASK(23, 16)
 78#define DW100_SWAP_CONTROL_DST2_MASK	GENMASK(31, 24)
 79#define DW100_VERTICAL_SPLIT_LINE	0x5c
 80#define DW100_HORIZON_SPLIT_LINE	0x60
 81#define DW100_SCALE_FACTOR		0x64
 82#define DW100_ROI_START			0x68
 83#define DW100_ROI_START_X(x)		(((x) & GENMASK(12, 0)) << 0)
 84#define DW100_ROI_START_Y(y)		(((y) & GENMASK(12, 0)) << 16)
 85#define DW100_BOUNDARY_PIXEL		0x6c
 86#define DW100_BOUNDARY_PIXEL_V(v)	(((v) & GENMASK(7, 0)) << 0)
 87#define DW100_BOUNDARY_PIXEL_U(u)	(((u) & GENMASK(7, 0)) << 8)
 88#define DW100_BOUNDARY_PIXEL_Y(y)	(((y) & GENMASK(7, 0)) << 16)
 89
 90#define DW100_INTERRUPT_STATUS		0x70
 91#define DW100_INTERRUPT_STATUS_INT_FRAME_DONE		BIT(0)
 92#define DW100_INTERRUPT_STATUS_INT_ERR_TIME_OUT		BIT(1)
 93#define DW100_INTERRUPT_STATUS_INT_ERR_AXI_RESP		BIT(2)
 94#define DW100_INTERRUPT_STATUS_INT_ERR_X		BIT(3)
 95#define DW100_INTERRUPT_STATUS_INT_ERR_MB_FETCH		BIT(4)
 96#define DW100_INTERRUPT_STATUS_INT_ERR_FRAME2		BIT(5)
 97#define DW100_INTERRUPT_STATUS_INT_ERR_FRAME3		BIT(6)
 98#define DW100_INTERRUPT_STATUS_INT_ERR_FRAME_DONE	BIT(7)
 99#define DW100_INTERRUPT_STATUS_INT_ERR_STATUS(x)	(((x) >> 1) & 0x7f)
100#define DW100_INTERRUPT_STATUS_INT_STATUS(x)		((x) & 0xff)
101
102#define DW100_INTERRUPT_STATUS_INT_ENABLE_MASK		GENMASK(15, 8)
103#define DW100_INTERRUPT_STATUS_INT_ENABLE(x)		(((x) & GENMASK(7, 0)) << 8)
104#define DW100_INTERRUPT_STATUS_FRAME_BUSY		BIT(16)
105#define DW100_INTERRUPT_STATUS_INT_CLEAR(x)		(((x) & GENMASK(7, 0)) << 24)
106#define DW100_BUS_CTRL			0x74
107#define DW100_BUS_CTRL_AXI_MASTER_ENABLE	BIT(31)
108#define DW100_BUS_CTRL1			0x78
109#define DW100_BUS_TIME_OUT_CYCLE	0x7c
110#define DW100_DST_IMG_Y_SIZE1		0x80
111#define DW100_DST_IMG_Y_SIZE(sz)	(((sz) >> 4) & GENMASK(29, 0))
112#define DW100_DST_IMG_UV_SIZE(sz)	(((sz) >> 4) & GENMASK(29, 0))
113#define DW100_DST_IMG_UV_SIZE1		0x84
114#define DW100_DST_IMG_Y_SIZE2		0x88
115#define DW100_DST_IMG_UV_SIZE2		0x8c
116
117#endif /* _DW100_REGS_H_ */