dw100.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * DW100 Hardware dewarper
   4 *
   5 * Copyright 2022 NXP
   6 * Author: Xavier Roumegue (xavier.roumegue@oss.nxp.com)
   7 *
   8 */
   9
  10#include <linux/clk.h>
  11#include <linux/debugfs.h>
  12#include <linux/interrupt.h>
  13#include <linux/io.h>
  14#include <linux/minmax.h>
  15#include <linux/module.h>
  16#include <linux/of.h>
  17#include <linux/platform_device.h>
  18#include <linux/pm_runtime.h>
  19
  20#include <media/v4l2-ctrls.h>
  21#include <media/v4l2-device.h>
  22#include <media/v4l2-event.h>
  23#include <media/v4l2-ioctl.h>
  24#include <media/v4l2-mem2mem.h>
  25#include <media/videobuf2-dma-contig.h>
  26
  27#include <uapi/linux/dw100.h>
  28
  29#include "dw100_regs.h"
  30
  31#define DRV_NAME "dw100"
  32
  33#define DW100_MIN_W		176u
  34#define DW100_MIN_H		144u
  35#define DW100_MAX_W		4096u
  36#define DW100_MAX_H		3072u
  37#define DW100_ALIGN_W		3
  38#define DW100_ALIGN_H		3
  39
  40#define DW100_BLOCK_SIZE	16
  41
  42#define DW100_DEF_W		640u
  43#define DW100_DEF_H		480u
  44#define DW100_DEF_LUT_W		(DIV_ROUND_UP(DW100_DEF_W, DW100_BLOCK_SIZE) + 1)
  45#define DW100_DEF_LUT_H		(DIV_ROUND_UP(DW100_DEF_H, DW100_BLOCK_SIZE) + 1)
  46
  47/*
  48 * 16 controls have been reserved for this driver for future extension, but
  49 * let's limit the related driver allocation to the effective number of controls
  50 * in use.
  51 */
  52#define DW100_MAX_CTRLS			1
  53#define DW100_CTRL_DEWARPING_MAP	0
  54
  55enum {
  56	DW100_QUEUE_SRC = 0,
  57	DW100_QUEUE_DST = 1,
  58};
  59
  60enum {
  61	DW100_FMT_CAPTURE = BIT(0),
  62	DW100_FMT_OUTPUT = BIT(1),
  63};
  64
  65struct dw100_device {
  66	struct platform_device		*pdev;
  67	struct v4l2_m2m_dev		*m2m_dev;
  68	struct v4l2_device		v4l2_dev;
  69	struct video_device		vfd;
  70	struct media_device		mdev;
  71	/* Video device lock */
  72	struct mutex			vfd_mutex;
  73	void __iomem			*mmio;
  74	struct clk_bulk_data		*clks;
  75	int				num_clks;
  76	struct dentry			*debugfs_root;
  77};
  78
  79struct dw100_q_data {
  80	struct v4l2_pix_format_mplane	pix_fmt;
  81	unsigned int			sequence;
  82	const struct dw100_fmt		*fmt;
  83	struct v4l2_rect		crop;
  84};
  85
  86struct dw100_ctx {
  87	struct v4l2_fh			fh;
  88	struct dw100_device		*dw_dev;
  89	struct v4l2_ctrl_handler	hdl;
  90	struct v4l2_ctrl		*ctrls[DW100_MAX_CTRLS];
  91	/* per context m2m queue lock */
  92	struct mutex			vq_mutex;
  93
  94	/* Look Up Table for pixel remapping */
  95	unsigned int			*map;
  96	dma_addr_t			map_dma;
  97	size_t				map_size;
  98	unsigned int			map_width;
  99	unsigned int			map_height;
 100	bool				user_map_is_set;
 101
 102	/* Source and destination queue data */
 103	struct dw100_q_data		q_data[2];
 104};
 105
 106static const struct v4l2_frmsize_stepwise dw100_frmsize_stepwise = {
 107	.min_width = DW100_MIN_W,
 108	.min_height = DW100_MIN_H,
 109	.max_width = DW100_MAX_W,
 110	.max_height = DW100_MAX_H,
 111	.step_width = 1UL << DW100_ALIGN_W,
 112	.step_height = 1UL << DW100_ALIGN_H,
 113};
 114
 115static const struct dw100_fmt {
 116	u32 fourcc;
 117	u32 types;
 118	u32 reg_format;
 119	bool reg_swap_uv;
 120} formats[] = {
 121	{
 122		.fourcc = V4L2_PIX_FMT_NV16,
 123		.types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE,
 124		.reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP,
 125		.reg_swap_uv = false,
 126	}, {
 127		.fourcc = V4L2_PIX_FMT_NV16M,
 128		.types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE,
 129		.reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP,
 130		.reg_swap_uv = false,
 131	}, {
 132		.fourcc = V4L2_PIX_FMT_NV61,
 133		.types = DW100_FMT_CAPTURE,
 134		.reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP,
 135		.reg_swap_uv = true,
 136	}, {
 137		.fourcc = V4L2_PIX_FMT_NV61M,
 138		.types = DW100_FMT_CAPTURE,
 139		.reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP,
 140		.reg_swap_uv = true,
 141	}, {
 142		.fourcc = V4L2_PIX_FMT_YUYV,
 143		.types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE,
 144		.reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED,
 145		.reg_swap_uv = false,
 146	}, {
 147		.fourcc = V4L2_PIX_FMT_UYVY,
 148		.types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE,
 149		.reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED,
 150		.reg_swap_uv = true,
 151	}, {
 152		.fourcc = V4L2_PIX_FMT_NV12,
 153		.types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE,
 154		.reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP,
 155		.reg_swap_uv = false,
 156	}, {
 157		.fourcc = V4L2_PIX_FMT_NV12M,
 158		.types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE,
 159		.reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP,
 160		.reg_swap_uv = false,
 161	}, {
 162		.fourcc = V4L2_PIX_FMT_NV21,
 163		.types = DW100_FMT_CAPTURE,
 164		.reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP,
 165		.reg_swap_uv = true,
 166	}, {
 167		.fourcc = V4L2_PIX_FMT_NV21M,
 168		.types = DW100_FMT_CAPTURE,
 169		.reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP,
 170		.reg_swap_uv = true,
 171	},
 172};
 173
 174static inline int to_dw100_fmt_type(enum v4l2_buf_type type)
 175{
 176	if (V4L2_TYPE_IS_OUTPUT(type))
 177		return DW100_FMT_OUTPUT;
 178	else
 179		return DW100_FMT_CAPTURE;
 180}
 181
 182static const struct dw100_fmt *dw100_find_pixel_format(u32 pixel_format,
 183						       int fmt_type)
 184{
 185	unsigned int i;
 186
 187	for (i = 0; i < ARRAY_SIZE(formats); i++) {
 188		const struct dw100_fmt *fmt = &formats[i];
 189
 190		if (fmt->fourcc == pixel_format && fmt->types & fmt_type)
 191			return fmt;
 192	}
 193
 194	return NULL;
 195}
 196
 197static const struct dw100_fmt *dw100_find_format(struct v4l2_format *f)
 198{
 199	return dw100_find_pixel_format(f->fmt.pix_mp.pixelformat,
 200				       to_dw100_fmt_type(f->type));
 201}
 202
 203static inline u32 dw100_read(struct dw100_device *dw_dev, u32 reg)
 204{
 205	return readl(dw_dev->mmio + reg);
 206}
 207
 208static inline void dw100_write(struct dw100_device *dw_dev, u32 reg, u32 val)
 209{
 210	writel(val, dw_dev->mmio + reg);
 211}
 212
 213static inline int dw100_dump_regs(struct seq_file *m)
 214{
 215	struct dw100_device *dw_dev = m->private;
 216#define __DECLARE_REG(x) { #x, x }
 217	unsigned int i;
 218	static const struct reg_desc {
 219		const char * const name;
 220		unsigned int addr;
 221	} dw100_regs[] = {
 222		__DECLARE_REG(DW100_DEWARP_ID),
 223		__DECLARE_REG(DW100_DEWARP_CTRL),
 224		__DECLARE_REG(DW100_MAP_LUT_ADDR),
 225		__DECLARE_REG(DW100_MAP_LUT_SIZE),
 226		__DECLARE_REG(DW100_MAP_LUT_ADDR2),
 227		__DECLARE_REG(DW100_MAP_LUT_SIZE2),
 228		__DECLARE_REG(DW100_SRC_IMG_Y_BASE),
 229		__DECLARE_REG(DW100_SRC_IMG_UV_BASE),
 230		__DECLARE_REG(DW100_SRC_IMG_SIZE),
 231		__DECLARE_REG(DW100_SRC_IMG_STRIDE),
 232		__DECLARE_REG(DW100_DST_IMG_Y_BASE),
 233		__DECLARE_REG(DW100_DST_IMG_UV_BASE),
 234		__DECLARE_REG(DW100_DST_IMG_SIZE),
 235		__DECLARE_REG(DW100_DST_IMG_STRIDE),
 236		__DECLARE_REG(DW100_DST_IMG_Y_SIZE1),
 237		__DECLARE_REG(DW100_DST_IMG_UV_SIZE1),
 238		__DECLARE_REG(DW100_SRC_IMG_Y_BASE2),
 239		__DECLARE_REG(DW100_SRC_IMG_UV_BASE2),
 240		__DECLARE_REG(DW100_SRC_IMG_SIZE2),
 241		__DECLARE_REG(DW100_SRC_IMG_STRIDE2),
 242		__DECLARE_REG(DW100_DST_IMG_Y_BASE2),
 243		__DECLARE_REG(DW100_DST_IMG_UV_BASE2),
 244		__DECLARE_REG(DW100_DST_IMG_SIZE2),
 245		__DECLARE_REG(DW100_DST_IMG_STRIDE2),
 246		__DECLARE_REG(DW100_DST_IMG_Y_SIZE2),
 247		__DECLARE_REG(DW100_DST_IMG_UV_SIZE2),
 248		__DECLARE_REG(DW100_SWAP_CONTROL),
 249		__DECLARE_REG(DW100_VERTICAL_SPLIT_LINE),
 250		__DECLARE_REG(DW100_HORIZON_SPLIT_LINE),
 251		__DECLARE_REG(DW100_SCALE_FACTOR),
 252		__DECLARE_REG(DW100_ROI_START),
 253		__DECLARE_REG(DW100_BOUNDARY_PIXEL),
 254		__DECLARE_REG(DW100_INTERRUPT_STATUS),
 255		__DECLARE_REG(DW100_BUS_CTRL),
 256		__DECLARE_REG(DW100_BUS_CTRL1),
 257		__DECLARE_REG(DW100_BUS_TIME_OUT_CYCLE),
 258	};
 259
 260	for (i = 0; i < ARRAY_SIZE(dw100_regs); i++)
 261		seq_printf(m, "%s: %#x\n", dw100_regs[i].name,
 262			   dw100_read(dw_dev, dw100_regs[i].addr));
 263
 264	return 0;
 265}
 266
 267static inline struct dw100_ctx *dw100_file2ctx(struct file *file)
 268{
 269	return container_of(file_to_v4l2_fh(file), struct dw100_ctx, fh);
 270}
 271
 272static struct dw100_q_data *dw100_get_q_data(struct dw100_ctx *ctx,
 273					     enum v4l2_buf_type type)
 274{
 275	if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
 276		return &ctx->q_data[DW100_QUEUE_SRC];
 277	else
 278		return &ctx->q_data[DW100_QUEUE_DST];
 279}
 280
 281static u32 dw100_get_n_vertices_from_length(u32 length)
 282{
 283	return DIV_ROUND_UP(length, DW100_BLOCK_SIZE) + 1;
 284}
 285
 286static u16 dw100_map_convert_to_uq12_4(u32 a)
 287{
 288	return (u16)((a & 0xfff) << 4);
 289}
 290
 291static u32 dw100_map_format_coordinates(u16 xq, u16 yq)
 292{
 293	return (u32)((yq << 16) | xq);
 294}
 295
 296static u32 *dw100_get_user_map(struct dw100_ctx *ctx)
 297{
 298	struct v4l2_ctrl *ctrl = ctx->ctrls[DW100_CTRL_DEWARPING_MAP];
 299
 300	return ctrl->p_cur.p_u32;
 301}
 302
 303/*
 304 * Create the dewarp map used by the hardware from the V4L2 control values which
 305 * have been initialized with an identity map or set by the application.
 306 */
 307static int dw100_create_mapping(struct dw100_ctx *ctx)
 308{
 309	u32 *user_map;
 310
 311	if (ctx->map)
 312		dma_free_coherent(&ctx->dw_dev->pdev->dev, ctx->map_size,
 313				  ctx->map, ctx->map_dma);
 314
 315	ctx->map = dma_alloc_coherent(&ctx->dw_dev->pdev->dev, ctx->map_size,
 316				      &ctx->map_dma, GFP_KERNEL);
 317
 318	if (!ctx->map)
 319		return -ENOMEM;
 320
 321	user_map = dw100_get_user_map(ctx);
 322	memcpy(ctx->map, user_map, ctx->map_size);
 323
 324	dev_dbg(&ctx->dw_dev->pdev->dev,
 325		"%ux%u %s mapping created (d:%pad-c:%p) for stream %ux%u->%ux%u\n",
 326		ctx->map_width, ctx->map_height,
 327		ctx->user_map_is_set ? "user" : "identity",
 328		&ctx->map_dma, ctx->map,
 329		ctx->q_data[DW100_QUEUE_SRC].pix_fmt.width,
 330		ctx->q_data[DW100_QUEUE_DST].pix_fmt.height,
 331		ctx->q_data[DW100_QUEUE_SRC].pix_fmt.width,
 332		ctx->q_data[DW100_QUEUE_DST].pix_fmt.height);
 333
 334	return 0;
 335}
 336
 337static void dw100_destroy_mapping(struct dw100_ctx *ctx)
 338{
 339	if (ctx->map) {
 340		dma_free_coherent(&ctx->dw_dev->pdev->dev, ctx->map_size,
 341				  ctx->map, ctx->map_dma);
 342		ctx->map = NULL;
 343	}
 344}
 345
 346static int dw100_s_ctrl(struct v4l2_ctrl *ctrl)
 347{
 348	struct dw100_ctx *ctx =
 349		container_of(ctrl->handler, struct dw100_ctx, hdl);
 350
 351	switch (ctrl->id) {
 352	case V4L2_CID_DW100_DEWARPING_16x16_VERTEX_MAP:
 353		ctx->user_map_is_set = true;
 354		break;
 355	}
 356
 357	return 0;
 358}
 359
 360static const struct v4l2_ctrl_ops dw100_ctrl_ops = {
 361	.s_ctrl = dw100_s_ctrl,
 362};
 363
 364/*
 365 * Initialize the dewarping map with an identity mapping.
 366 *
 367 * A 16 pixels cell size grid is mapped on the destination image.
 368 * The last cells width/height might be lesser than 16 if the destination image
 369 * width/height is not divisible by 16. This dewarping grid map specifies the
 370 * source image pixel location (x, y) on each grid intersection point.
 371 * Bilinear interpolation is used to compute inner cell points locations.
 372 *
 373 * The coordinates are saved in UQ12.4 fixed point format.
 374 */
 375static void dw100_ctrl_dewarping_map_init(const struct v4l2_ctrl *ctrl,
 376					  u32 from_idx,
 377					  union v4l2_ctrl_ptr ptr)
 378{
 379	struct dw100_ctx *ctx =
 380		container_of(ctrl->handler, struct dw100_ctx, hdl);
 381
 382	u32 sw, sh, mw, mh, idx;
 383	u16 qx, qy, qdx, qdy, qsh, qsw;
 384	u32 *map = ctrl->p_cur.p_u32;
 385
 386	sw = ctx->q_data[DW100_QUEUE_SRC].pix_fmt.width;
 387	sh = ctx->q_data[DW100_QUEUE_SRC].pix_fmt.height;
 388
 389	mw = ctrl->dims[0];
 390	mh = ctrl->dims[1];
 391
 392	qsw = dw100_map_convert_to_uq12_4(sw);
 393	qsh = dw100_map_convert_to_uq12_4(sh);
 394	qdx = qsw / (mw - 1);
 395	qdy = qsh / (mh - 1);
 396
 397	ctx->map_width = mw;
 398	ctx->map_height = mh;
 399	ctx->map_size = mh * mw * sizeof(u32);
 400
 401	for (idx = from_idx; idx < ctrl->elems; idx++) {
 402		qy = min_t(u32, (idx / mw) * qdy, qsh);
 403		qx = min_t(u32, (idx % mw) * qdx, qsw);
 404		map[idx] = dw100_map_format_coordinates(qx, qy);
 405	}
 406
 407	ctx->user_map_is_set = false;
 408}
 409
 410static const struct v4l2_ctrl_type_ops dw100_ctrl_type_ops = {
 411	.init = dw100_ctrl_dewarping_map_init,
 412	.validate = v4l2_ctrl_type_op_validate,
 413	.log = v4l2_ctrl_type_op_log,
 414	.equal = v4l2_ctrl_type_op_equal,
 415};
 416
 417static const struct v4l2_ctrl_config controls[] = {
 418	[DW100_CTRL_DEWARPING_MAP] = {
 419		.ops = &dw100_ctrl_ops,
 420		.type_ops = &dw100_ctrl_type_ops,
 421		.id = V4L2_CID_DW100_DEWARPING_16x16_VERTEX_MAP,
 422		.name = "Dewarping Vertex Map",
 423		.type = V4L2_CTRL_TYPE_U32,
 424		.min = 0x00000000,
 425		.max = 0xffffffff,
 426		.step = 1,
 427		.def = 0,
 428		.dims = { DW100_DEF_LUT_W, DW100_DEF_LUT_H },
 429	},
 430};
 431
 432static int dw100_queue_setup(struct vb2_queue *vq,
 433			     unsigned int *nbuffers, unsigned int *nplanes,
 434			     unsigned int sizes[], struct device *alloc_devs[])
 435{
 436	struct dw100_ctx *ctx = vb2_get_drv_priv(vq);
 437	const struct v4l2_pix_format_mplane *format;
 438	unsigned int i;
 439
 440	format = &dw100_get_q_data(ctx, vq->type)->pix_fmt;
 441
 442	if (*nplanes) {
 443		if (*nplanes != format->num_planes)
 444			return -EINVAL;
 445
 446		for (i = 0; i < *nplanes; ++i) {
 447			if (sizes[i] < format->plane_fmt[i].sizeimage)
 448				return -EINVAL;
 449		}
 450
 451		return 0;
 452	}
 453
 454	*nplanes = format->num_planes;
 455
 456	for (i = 0; i < format->num_planes; ++i)
 457		sizes[i] = format->plane_fmt[i].sizeimage;
 458
 459	return 0;
 460}
 461
 462static int dw100_buf_prepare(struct vb2_buffer *vb)
 463{
 464	unsigned int i;
 465	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 466	struct dw100_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
 467	struct dw100_device *dw_dev = ctx->dw_dev;
 468	const struct v4l2_pix_format_mplane *pix_fmt =
 469		&dw100_get_q_data(ctx, vb->vb2_queue->type)->pix_fmt;
 470
 471	if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
 472		if (vbuf->field != V4L2_FIELD_NONE) {
 473			dev_dbg(&dw_dev->pdev->dev, "%x field isn't supported\n",
 474				vbuf->field);
 475			return -EINVAL;
 476		}
 477	}
 478
 479	for (i = 0; i < pix_fmt->num_planes; i++) {
 480		unsigned long size = pix_fmt->plane_fmt[i].sizeimage;
 481
 482		if (vb2_plane_size(vb, i) < size) {
 483			dev_dbg(&dw_dev->pdev->dev,
 484				"User buffer too small (%lu < %lu)\n",
 485				vb2_plane_size(vb, i), size);
 486			return -EINVAL;
 487		}
 488
 489		vb2_set_plane_payload(vb, i, size);
 490	}
 491
 492	return 0;
 493}
 494
 495static void dw100_buf_queue(struct vb2_buffer *vb)
 496{
 497	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 498	struct dw100_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
 499
 500	v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
 501}
 502
 503static void dw100_return_all_buffers(struct vb2_queue *q,
 504				     enum vb2_buffer_state state)
 505{
 506	struct dw100_ctx *ctx = vb2_get_drv_priv(q);
 507	struct vb2_v4l2_buffer *vbuf;
 508
 509	for (;;) {
 510		if (V4L2_TYPE_IS_OUTPUT(q->type))
 511			vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
 512		else
 513			vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
 514		if (!vbuf)
 515			return;
 516		v4l2_m2m_buf_done(vbuf, state);
 517	}
 518}
 519
 520static int dw100_start_streaming(struct vb2_queue *q, unsigned int count)
 521{
 522	struct dw100_ctx *ctx = vb2_get_drv_priv(q);
 523	struct dw100_q_data *q_data = dw100_get_q_data(ctx, q->type);
 524	int ret;
 525
 526	q_data->sequence = 0;
 527
 528	ret = dw100_create_mapping(ctx);
 529	if (ret)
 530		goto err;
 531
 532	ret = pm_runtime_resume_and_get(&ctx->dw_dev->pdev->dev);
 533	if (ret) {
 534		dw100_destroy_mapping(ctx);
 535		goto err;
 536	}
 537
 538	return 0;
 539err:
 540	dw100_return_all_buffers(q, VB2_BUF_STATE_QUEUED);
 541	return ret;
 542}
 543
 544static void dw100_stop_streaming(struct vb2_queue *q)
 545{
 546	struct dw100_ctx *ctx = vb2_get_drv_priv(q);
 547
 548	dw100_return_all_buffers(q, VB2_BUF_STATE_ERROR);
 549
 550	pm_runtime_put_sync(&ctx->dw_dev->pdev->dev);
 551
 552	dw100_destroy_mapping(ctx);
 553}
 554
 555static const struct vb2_ops dw100_qops = {
 556	.queue_setup	 = dw100_queue_setup,
 557	.buf_prepare	 = dw100_buf_prepare,
 558	.buf_queue	 = dw100_buf_queue,
 559	.start_streaming = dw100_start_streaming,
 560	.stop_streaming  = dw100_stop_streaming,
 561};
 562
 563static int dw100_m2m_queue_init(void *priv, struct vb2_queue *src_vq,
 564				struct vb2_queue *dst_vq)
 565{
 566	struct dw100_ctx *ctx = priv;
 567	int ret;
 568
 569	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
 570	src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
 571	src_vq->drv_priv = ctx;
 572	src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
 573	src_vq->ops = &dw100_qops;
 574	src_vq->mem_ops = &vb2_dma_contig_memops;
 575	src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
 576	src_vq->lock = &ctx->vq_mutex;
 577	src_vq->dev = ctx->dw_dev->v4l2_dev.dev;
 578
 579	ret = vb2_queue_init(src_vq);
 580	if (ret)
 581		return ret;
 582
 583	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
 584	dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
 585	dst_vq->drv_priv = ctx;
 586	dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
 587	dst_vq->ops = &dw100_qops;
 588	dst_vq->mem_ops = &vb2_dma_contig_memops;
 589	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
 590	dst_vq->lock = &ctx->vq_mutex;
 591	dst_vq->dev = ctx->dw_dev->v4l2_dev.dev;
 592
 593	return vb2_queue_init(dst_vq);
 594}
 595
 596static int dw100_open(struct file *file)
 597{
 598	struct dw100_device *dw_dev = video_drvdata(file);
 599	struct dw100_ctx *ctx;
 600	struct v4l2_ctrl_handler *hdl;
 601	struct v4l2_pix_format_mplane *pix_fmt;
 602	int ret, i;
 603
 604	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
 605	if (!ctx)
 606		return -ENOMEM;
 607
 608	mutex_init(&ctx->vq_mutex);
 609	v4l2_fh_init(&ctx->fh, video_devdata(file));
 610	ctx->dw_dev = dw_dev;
 611
 612	ctx->q_data[DW100_QUEUE_SRC].fmt = &formats[0];
 613
 614	pix_fmt = &ctx->q_data[DW100_QUEUE_SRC].pix_fmt;
 615	pix_fmt->field = V4L2_FIELD_NONE;
 616	pix_fmt->colorspace = V4L2_COLORSPACE_REC709;
 617	pix_fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(pix_fmt->colorspace);
 618	pix_fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(pix_fmt->colorspace);
 619	pix_fmt->quantization =
 620		V4L2_MAP_QUANTIZATION_DEFAULT(false, pix_fmt->colorspace,
 621					      pix_fmt->ycbcr_enc);
 622
 623	v4l2_fill_pixfmt_mp(pix_fmt, formats[0].fourcc, DW100_DEF_W, DW100_DEF_H);
 624
 625	ctx->q_data[DW100_QUEUE_SRC].crop.top = 0;
 626	ctx->q_data[DW100_QUEUE_SRC].crop.left = 0;
 627	ctx->q_data[DW100_QUEUE_SRC].crop.width = DW100_DEF_W;
 628	ctx->q_data[DW100_QUEUE_SRC].crop.height = DW100_DEF_H;
 629
 630	ctx->q_data[DW100_QUEUE_DST] = ctx->q_data[DW100_QUEUE_SRC];
 631
 632	hdl = &ctx->hdl;
 633	v4l2_ctrl_handler_init(hdl, ARRAY_SIZE(controls));
 634	for (i = 0; i < ARRAY_SIZE(controls); i++) {
 635		ctx->ctrls[i] = v4l2_ctrl_new_custom(hdl, &controls[i], NULL);
 636		if (hdl->error) {
 637			dev_err(&ctx->dw_dev->pdev->dev,
 638				"Adding control (%d) failed\n", i);
 639			ret = hdl->error;
 640			goto err;
 641		}
 642	}
 643	ctx->fh.ctrl_handler = hdl;
 644
 645	ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dw_dev->m2m_dev,
 646					    ctx, &dw100_m2m_queue_init);
 647
 648	if (IS_ERR(ctx->fh.m2m_ctx)) {
 649		ret = PTR_ERR(ctx->fh.m2m_ctx);
 650		goto err;
 651	}
 652
 653	v4l2_fh_add(&ctx->fh, file);
 654
 655	return 0;
 656
 657err:
 658	v4l2_ctrl_handler_free(hdl);
 659	v4l2_fh_exit(&ctx->fh);
 660	mutex_destroy(&ctx->vq_mutex);
 661	kfree(ctx);
 662
 663	return ret;
 664}
 665
 666static int dw100_release(struct file *file)
 667{
 668	struct dw100_ctx *ctx = dw100_file2ctx(file);
 669
 670	v4l2_fh_del(&ctx->fh, file);
 671	v4l2_fh_exit(&ctx->fh);
 672	v4l2_ctrl_handler_free(&ctx->hdl);
 673	v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
 674	mutex_destroy(&ctx->vq_mutex);
 675	kfree(ctx);
 676
 677	return 0;
 678}
 679
 680static const struct v4l2_file_operations dw100_fops = {
 681	.owner		= THIS_MODULE,
 682	.open		= dw100_open,
 683	.release	= dw100_release,
 684	.poll		= v4l2_m2m_fop_poll,
 685	.unlocked_ioctl	= video_ioctl2,
 686	.mmap		= v4l2_m2m_fop_mmap,
 687};
 688
 689static int dw100_querycap(struct file *file, void *priv,
 690			  struct v4l2_capability *cap)
 691{
 692	strscpy(cap->driver, DRV_NAME, sizeof(cap->driver));
 693	strscpy(cap->card, "DW100 dewarper", sizeof(cap->card));
 694
 695	return 0;
 696}
 697
 698static int dw100_enum_fmt_vid(struct file *file, void *priv,
 699			      struct v4l2_fmtdesc *f)
 700{
 701	int i, num = 0;
 702
 703	for (i = 0; i < ARRAY_SIZE(formats); i++) {
 704		if (formats[i].types & to_dw100_fmt_type(f->type)) {
 705			if (num == f->index) {
 706				f->pixelformat = formats[i].fourcc;
 707				return 0;
 708			}
 709			++num;
 710		}
 711	}
 712
 713	return -EINVAL;
 714}
 715
 716static int dw100_enum_framesizes(struct file *file, void *priv,
 717				 struct v4l2_frmsizeenum *fsize)
 718{
 719	const struct dw100_fmt *fmt;
 720
 721	if (fsize->index)
 722		return -EINVAL;
 723
 724	fmt = dw100_find_pixel_format(fsize->pixel_format,
 725				      DW100_FMT_OUTPUT | DW100_FMT_CAPTURE);
 726	if (!fmt)
 727		return -EINVAL;
 728
 729	fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
 730	fsize->stepwise = dw100_frmsize_stepwise;
 731
 732	return 0;
 733}
 734
 735static int dw100_g_fmt_vid(struct file *file, void *priv, struct v4l2_format *f)
 736{
 737	struct dw100_ctx *ctx = dw100_file2ctx(file);
 738	struct dw100_q_data *q_data;
 739
 740	q_data = dw100_get_q_data(ctx, f->type);
 741
 742	f->fmt.pix_mp = q_data->pix_fmt;
 743
 744	return 0;
 745}
 746
 747static int dw100_try_fmt(struct file *file, struct v4l2_format *f)
 748{
 749	struct dw100_ctx *ctx = dw100_file2ctx(file);
 750	struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
 751	const struct dw100_fmt *fmt;
 752
 753	fmt = dw100_find_format(f);
 754	if (!fmt) {
 755		fmt = &formats[0];
 756		pix->pixelformat = fmt->fourcc;
 757	}
 758
 759	v4l2_apply_frmsize_constraints(&pix->width, &pix->height,
 760				       &dw100_frmsize_stepwise);
 761
 762	v4l2_fill_pixfmt_mp(pix, fmt->fourcc, pix->width, pix->height);
 763
 764	pix->field = V4L2_FIELD_NONE;
 765
 766	if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
 767		if (pix->colorspace == V4L2_COLORSPACE_DEFAULT)
 768			pix->colorspace = V4L2_COLORSPACE_REC709;
 769		if (pix->xfer_func == V4L2_XFER_FUNC_DEFAULT)
 770			pix->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(pix->colorspace);
 771		if (pix->ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT)
 772			pix->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(pix->colorspace);
 773		if (pix->quantization == V4L2_QUANTIZATION_DEFAULT)
 774			pix->quantization =
 775				V4L2_MAP_QUANTIZATION_DEFAULT(false,
 776							      pix->colorspace,
 777							      pix->ycbcr_enc);
 778	} else {
 779		/*
 780		 * The DW100 can't perform colorspace conversion, the colorspace
 781		 * on the capture queue must be identical to the output queue.
 782		 */
 783		const struct dw100_q_data *q_data =
 784			dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
 785
 786		pix->colorspace = q_data->pix_fmt.colorspace;
 787		pix->xfer_func = q_data->pix_fmt.xfer_func;
 788		pix->ycbcr_enc = q_data->pix_fmt.ycbcr_enc;
 789		pix->quantization = q_data->pix_fmt.quantization;
 790	}
 791
 792	return 0;
 793}
 794
 795static int dw100_s_fmt(struct dw100_ctx *ctx, struct v4l2_format *f)
 796{
 797	struct dw100_q_data *q_data;
 798	struct vb2_queue *vq;
 799
 800	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
 801
 802	q_data = dw100_get_q_data(ctx, f->type);
 803	if (!q_data)
 804		return -EINVAL;
 805
 806	if (vb2_is_busy(vq)) {
 807		dev_dbg(&ctx->dw_dev->pdev->dev, "%s queue busy\n", __func__);
 808		return -EBUSY;
 809	}
 810
 811	q_data->fmt = dw100_find_format(f);
 812	q_data->pix_fmt = f->fmt.pix_mp;
 813	q_data->crop.top = 0;
 814	q_data->crop.left = 0;
 815	q_data->crop.width = f->fmt.pix_mp.width;
 816	q_data->crop.height = f->fmt.pix_mp.height;
 817
 818	/* Propagate buffers encoding */
 819
 820	if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
 821		struct dw100_q_data *dst_q_data =
 822			dw100_get_q_data(ctx,
 823					 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
 824
 825		dst_q_data->pix_fmt.colorspace = q_data->pix_fmt.colorspace;
 826		dst_q_data->pix_fmt.ycbcr_enc = q_data->pix_fmt.ycbcr_enc;
 827		dst_q_data->pix_fmt.quantization = q_data->pix_fmt.quantization;
 828		dst_q_data->pix_fmt.xfer_func = q_data->pix_fmt.xfer_func;
 829	}
 830
 831	dev_dbg(&ctx->dw_dev->pdev->dev,
 832		"Setting format for type %u, wxh: %ux%u, fmt: %p4cc\n",
 833		f->type, q_data->pix_fmt.width, q_data->pix_fmt.height,
 834		&q_data->pix_fmt.pixelformat);
 835
 836	if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
 837		int ret;
 838		u32 dims[V4L2_CTRL_MAX_DIMS] = {};
 839		struct v4l2_ctrl *ctrl = ctx->ctrls[DW100_CTRL_DEWARPING_MAP];
 840
 841		dims[0] = dw100_get_n_vertices_from_length(q_data->pix_fmt.width);
 842		dims[1] = dw100_get_n_vertices_from_length(q_data->pix_fmt.height);
 843
 844		ret = v4l2_ctrl_modify_dimensions(ctrl, dims);
 845
 846		if (ret) {
 847			dev_err(&ctx->dw_dev->pdev->dev,
 848				"Modifying LUT dimensions failed with error %d\n",
 849				ret);
 850			return ret;
 851		}
 852	}
 853
 854	return 0;
 855}
 856
 857static int dw100_try_fmt_vid_cap(struct file *file, void *priv,
 858				 struct v4l2_format *f)
 859{
 860	if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
 861		return -EINVAL;
 862
 863	return dw100_try_fmt(file, f);
 864}
 865
 866static int dw100_s_fmt_vid_cap(struct file *file, void *priv,
 867			       struct v4l2_format *f)
 868{
 869	struct dw100_ctx *ctx = dw100_file2ctx(file);
 870	int ret;
 871
 872	ret = dw100_try_fmt_vid_cap(file, priv, f);
 873	if (ret)
 874		return ret;
 875
 876	ret = dw100_s_fmt(ctx, f);
 877	if (ret)
 878		return ret;
 879
 880	return 0;
 881}
 882
 883static int dw100_try_fmt_vid_out(struct file *file, void *priv,
 884				 struct v4l2_format *f)
 885{
 886	if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
 887		return -EINVAL;
 888
 889	return dw100_try_fmt(file, f);
 890}
 891
 892static int dw100_s_fmt_vid_out(struct file *file, void *priv,
 893			       struct v4l2_format *f)
 894{
 895	struct dw100_ctx *ctx = dw100_file2ctx(file);
 896	int ret;
 897
 898	ret = dw100_try_fmt_vid_out(file, priv, f);
 899	if (ret)
 900		return ret;
 901
 902	ret = dw100_s_fmt(ctx, f);
 903	if (ret)
 904		return ret;
 905
 906	return 0;
 907}
 908
 909static int dw100_g_selection(struct file *file, void *fh,
 910			     struct v4l2_selection *sel)
 911{
 912	struct dw100_ctx *ctx = dw100_file2ctx(file);
 913	struct dw100_q_data *src_q_data;
 914
 915	if (sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
 916		return -EINVAL;
 917
 918	src_q_data = dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
 919
 920	switch (sel->target) {
 921	case V4L2_SEL_TGT_CROP_DEFAULT:
 922	case V4L2_SEL_TGT_CROP_BOUNDS:
 923		sel->r.top = 0;
 924		sel->r.left = 0;
 925		sel->r.width = src_q_data->pix_fmt.width;
 926		sel->r.height = src_q_data->pix_fmt.height;
 927		break;
 928	case V4L2_SEL_TGT_CROP:
 929		sel->r.top = src_q_data->crop.top;
 930		sel->r.left = src_q_data->crop.left;
 931		sel->r.width = src_q_data->crop.width;
 932		sel->r.height = src_q_data->crop.height;
 933		break;
 934	default:
 935		return -EINVAL;
 936	}
 937
 938	return 0;
 939}
 940
 941static int dw100_s_selection(struct file *file, void *fh,
 942			     struct v4l2_selection *sel)
 943{
 944	struct dw100_ctx *ctx = dw100_file2ctx(file);
 945	struct dw100_q_data *src_q_data;
 946	u32 qscalex, qscaley, qscale;
 947	int x, y, w, h;
 948	unsigned int wframe, hframe;
 949
 950	if (sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
 951		return -EINVAL;
 952
 953	src_q_data = dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
 954
 955	dev_dbg(&ctx->dw_dev->pdev->dev,
 956		">>> Buffer Type: %u Target: %u Rect: (%d,%d)/%ux%u\n",
 957		sel->type, sel->target,
 958		sel->r.left, sel->r.top, sel->r.width, sel->r.height);
 959
 960	switch (sel->target) {
 961	case V4L2_SEL_TGT_CROP:
 962		wframe = src_q_data->pix_fmt.width;
 963		hframe = src_q_data->pix_fmt.height;
 964
 965		sel->r.top = clamp_t(int, sel->r.top, 0, hframe - DW100_MIN_H);
 966		sel->r.left = clamp_t(int, sel->r.left, 0, wframe - DW100_MIN_W);
 967		sel->r.height =
 968			clamp(sel->r.height, DW100_MIN_H, hframe - sel->r.top);
 969		sel->r.width =
 970			clamp(sel->r.width, DW100_MIN_W, wframe - sel->r.left);
 971
 972		/* UQ16.16 for float operations */
 973		qscalex = (sel->r.width << 16) / wframe;
 974		qscaley = (sel->r.height << 16) / hframe;
 975		y = sel->r.top;
 976		x = sel->r.left;
 977		if (qscalex == qscaley) {
 978			qscale = qscalex;
 979		} else {
 980			switch (sel->flags) {
 981			case 0:
 982				qscale = (qscalex + qscaley) / 2;
 983				break;
 984			case V4L2_SEL_FLAG_GE:
 985				qscale = max(qscaley, qscalex);
 986				break;
 987			case V4L2_SEL_FLAG_LE:
 988				qscale = min(qscaley, qscalex);
 989				break;
 990			case V4L2_SEL_FLAG_LE | V4L2_SEL_FLAG_GE:
 991				return -ERANGE;
 992			default:
 993				return -EINVAL;
 994			}
 995		}
 996
 997		w = (u32)((((u64)wframe << 16) * qscale) >> 32);
 998		h = (u32)((((u64)hframe << 16) * qscale) >> 32);
 999		x = x + (sel->r.width  - w) / 2;
1000		y = y + (sel->r.height  - h) / 2;
1001		x = min(wframe - w, (unsigned int)max(0, x));
1002		y = min(hframe - h, (unsigned int)max(0, y));
1003
1004		sel->r.top = y;
1005		sel->r.left = x;
1006		sel->r.width = w;
1007		sel->r.height = h;
1008
1009		src_q_data->crop.top = sel->r.top;
1010		src_q_data->crop.left = sel->r.left;
1011		src_q_data->crop.width = sel->r.width;
1012		src_q_data->crop.height = sel->r.height;
1013		break;
1014
1015	default:
1016		return -EINVAL;
1017	}
1018
1019	dev_dbg(&ctx->dw_dev->pdev->dev,
1020		"<<< Buffer Type: %u Target: %u Rect: (%d,%d)/%ux%u\n",
1021		sel->type, sel->target,
1022		sel->r.left, sel->r.top, sel->r.width, sel->r.height);
1023
1024	return 0;
1025}
1026
1027static const struct v4l2_ioctl_ops dw100_ioctl_ops = {
1028	.vidioc_querycap		= dw100_querycap,
1029
1030	.vidioc_enum_fmt_vid_cap	= dw100_enum_fmt_vid,
1031	.vidioc_enum_framesizes		= dw100_enum_framesizes,
1032	.vidioc_g_fmt_vid_cap_mplane	= dw100_g_fmt_vid,
1033	.vidioc_try_fmt_vid_cap_mplane	= dw100_try_fmt_vid_cap,
1034	.vidioc_s_fmt_vid_cap_mplane	= dw100_s_fmt_vid_cap,
1035
1036	.vidioc_enum_fmt_vid_out	= dw100_enum_fmt_vid,
1037	.vidioc_g_fmt_vid_out_mplane	= dw100_g_fmt_vid,
1038	.vidioc_try_fmt_vid_out_mplane	= dw100_try_fmt_vid_out,
1039	.vidioc_s_fmt_vid_out_mplane	= dw100_s_fmt_vid_out,
1040
1041	.vidioc_g_selection		= dw100_g_selection,
1042	.vidioc_s_selection		= dw100_s_selection,
1043	.vidioc_reqbufs			= v4l2_m2m_ioctl_reqbufs,
1044	.vidioc_querybuf		= v4l2_m2m_ioctl_querybuf,
1045	.vidioc_qbuf			= v4l2_m2m_ioctl_qbuf,
1046	.vidioc_dqbuf			= v4l2_m2m_ioctl_dqbuf,
1047	.vidioc_prepare_buf		= v4l2_m2m_ioctl_prepare_buf,
1048	.vidioc_create_bufs		= v4l2_m2m_ioctl_create_bufs,
1049	.vidioc_expbuf			= v4l2_m2m_ioctl_expbuf,
1050
1051	.vidioc_streamon		= v4l2_m2m_ioctl_streamon,
1052	.vidioc_streamoff		= v4l2_m2m_ioctl_streamoff,
1053
1054	.vidioc_subscribe_event		= v4l2_ctrl_subscribe_event,
1055	.vidioc_unsubscribe_event	= v4l2_event_unsubscribe,
1056};
1057
1058static void dw100_job_finish(struct dw100_device *dw_dev, bool with_error)
1059{
1060	struct dw100_ctx *curr_ctx;
1061	struct vb2_v4l2_buffer *src_vb, *dst_vb;
1062	enum vb2_buffer_state buf_state;
1063
1064	curr_ctx = v4l2_m2m_get_curr_priv(dw_dev->m2m_dev);
1065
1066	if (!curr_ctx) {
1067		dev_err(&dw_dev->pdev->dev,
1068			"Instance released before the end of transaction\n");
1069		return;
1070	}
1071
1072	src_vb = v4l2_m2m_src_buf_remove(curr_ctx->fh.m2m_ctx);
1073	dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->fh.m2m_ctx);
1074
1075	if (likely(!with_error))
1076		buf_state = VB2_BUF_STATE_DONE;
1077	else
1078		buf_state = VB2_BUF_STATE_ERROR;
1079
1080	v4l2_m2m_buf_done(src_vb, buf_state);
1081	v4l2_m2m_buf_done(dst_vb, buf_state);
1082
1083	dev_dbg(&dw_dev->pdev->dev, "Finishing transaction with%s error(s)\n",
1084		with_error ? "" : "out");
1085
1086	v4l2_m2m_job_finish(dw_dev->m2m_dev, curr_ctx->fh.m2m_ctx);
1087}
1088
1089static void dw100_hw_reset(struct dw100_device *dw_dev)
1090{
1091	u32 val;
1092
1093	val = dw100_read(dw_dev, DW100_DEWARP_CTRL);
1094	val |= DW100_DEWARP_CTRL_ENABLE;
1095	val |= DW100_DEWARP_CTRL_SOFT_RESET;
1096	dw100_write(dw_dev, DW100_DEWARP_CTRL, val);
1097	val &= ~DW100_DEWARP_CTRL_SOFT_RESET;
1098	dw100_write(dw_dev, DW100_DEWARP_CTRL, val);
1099}
1100
1101static void _dw100_hw_set_master_bus_enable(struct dw100_device *dw_dev,
1102					    unsigned int enable)
1103{
1104	u32 val;
1105
1106	dev_dbg(&dw_dev->pdev->dev, "%sable master bus\n",
1107		enable ? "En" : "Dis");
1108
1109	val = dw100_read(dw_dev, DW100_BUS_CTRL);
1110
1111	if (enable)
1112		val |= DW100_BUS_CTRL_AXI_MASTER_ENABLE;
1113	else
1114		val &= ~DW100_BUS_CTRL_AXI_MASTER_ENABLE;
1115
1116	dw100_write(dw_dev, DW100_BUS_CTRL, val);
1117}
1118
1119static void dw100_hw_master_bus_enable(struct dw100_device *dw_dev)
1120{
1121	_dw100_hw_set_master_bus_enable(dw_dev, 1);
1122}
1123
1124static void dw100_hw_master_bus_disable(struct dw100_device *dw_dev)
1125{
1126	_dw100_hw_set_master_bus_enable(dw_dev, 0);
1127}
1128
1129static void dw100_hw_dewarp_start(struct dw100_device *dw_dev)
1130{
1131	u32 val;
1132
1133	val = dw100_read(dw_dev, DW100_DEWARP_CTRL);
1134
1135	dev_dbg(&dw_dev->pdev->dev, "Starting Hardware CTRL:0x%08x\n", val);
1136	dw100_write(dw_dev, DW100_DEWARP_CTRL, val | DW100_DEWARP_CTRL_START);
1137	dw100_write(dw_dev, DW100_DEWARP_CTRL, val);
1138}
1139
1140static void dw100_hw_init_ctrl(struct dw100_device *dw_dev)
1141{
1142	u32 val;
1143	/*
1144	 * Input format YUV422_SP
1145	 * Output format YUV422_SP
1146	 * No hardware handshake (SW)
1147	 * No automatic double src buffering (Single)
1148	 * No automatic double dst buffering (Single)
1149	 * No Black Line
1150	 * Prefetch image pixel traversal
1151	 */
1152
1153	val = DW100_DEWARP_CTRL_ENABLE
1154	    /* Valid only for auto prefetch mode*/
1155	    | DW100_DEWARP_CTRL_PREFETCH_THRESHOLD(32);
1156
1157	/*
1158	 * Calculation mode required to support any scaling factor,
1159	 * but x4 slower than traversal mode.
1160	 *
1161	 * DW100_DEWARP_CTRL_PREFETCH_MODE_TRAVERSAL
1162	 * DW100_DEWARP_CTRL_PREFETCH_MODE_CALCULATION
1163	 * DW100_DEWARP_CTRL_PREFETCH_MODE_AUTO
1164	 *
1165	 * TODO: Find heuristics requiring calculation mode
1166	 */
1167	val |= DW100_DEWARP_CTRL_PREFETCH_MODE_CALCULATION;
1168
1169	dw100_write(dw_dev, DW100_DEWARP_CTRL, val);
1170}
1171
1172static void dw100_hw_set_pixel_boundary(struct dw100_device *dw_dev)
1173{
1174	u32 val;
1175
1176	val = DW100_BOUNDARY_PIXEL_V(128)
1177		| DW100_BOUNDARY_PIXEL_U(128)
1178		| DW100_BOUNDARY_PIXEL_Y(0);
1179
1180	dw100_write(dw_dev, DW100_BOUNDARY_PIXEL, val);
1181}
1182
1183static void dw100_hw_set_scale(struct dw100_device *dw_dev, u8 scale)
1184{
1185	dev_dbg(&dw_dev->pdev->dev, "Setting scale factor to %u\n", scale);
1186
1187	dw100_write(dw_dev, DW100_SCALE_FACTOR, scale);
1188}
1189
1190static void dw100_hw_set_roi(struct dw100_device *dw_dev, u32 x, u32 y)
1191{
1192	u32 val;
1193
1194	dev_dbg(&dw_dev->pdev->dev, "Setting ROI region to %u.%u\n", x, y);
1195
1196	val = DW100_ROI_START_X(x) | DW100_ROI_START_Y(y);
1197
1198	dw100_write(dw_dev, DW100_ROI_START, val);
1199}
1200
1201static void dw100_hw_set_src_crop(struct dw100_device *dw_dev,
1202				  const struct dw100_q_data *src_q_data,
1203				  const struct dw100_q_data *dst_q_data)
1204{
1205	const struct v4l2_rect *rect = &src_q_data->crop;
1206	u32 src_scale, qscale, left_scale, top_scale;
1207
1208	/* HW Scale is UQ1.7 encoded */
1209	src_scale = (rect->width << 7) / src_q_data->pix_fmt.width;
1210	dw100_hw_set_scale(dw_dev, src_scale);
1211
1212	qscale = (dst_q_data->pix_fmt.width << 7)  / src_q_data->pix_fmt.width;
1213
1214	left_scale = ((rect->left << 7) * qscale) >> 14;
1215	top_scale = ((rect->top << 7) * qscale) >> 14;
1216
1217	dw100_hw_set_roi(dw_dev, left_scale, top_scale);
1218}
1219
1220static void dw100_hw_set_source(struct dw100_device *dw_dev,
1221				const struct dw100_q_data *q_data,
1222				struct vb2_buffer *buffer)
1223{
1224	u32 width, height, stride, fourcc, val;
1225	const struct dw100_fmt *fmt = q_data->fmt;
1226	dma_addr_t addr_y = vb2_dma_contig_plane_dma_addr(buffer, 0);
1227	dma_addr_t addr_uv;
1228
1229	width =  q_data->pix_fmt.width;
1230	height = q_data->pix_fmt.height;
1231	stride = q_data->pix_fmt.plane_fmt[0].bytesperline;
1232	fourcc = q_data->fmt->fourcc;
1233
1234	if (q_data->pix_fmt.num_planes == 2)
1235		addr_uv = vb2_dma_contig_plane_dma_addr(buffer, 1);
1236	else
1237		addr_uv = addr_y + (stride * height);
1238
1239	dev_dbg(&dw_dev->pdev->dev,
1240		"Set HW source registers for %ux%u - stride %u, pixfmt: %p4cc, dma:%pad\n",
1241		width, height, stride, &fourcc, &addr_y);
1242
1243	/* Pixel Format */
1244	val = dw100_read(dw_dev, DW100_DEWARP_CTRL);
1245
1246	val &= ~DW100_DEWARP_CTRL_INPUT_FORMAT_MASK;
1247	val |= DW100_DEWARP_CTRL_INPUT_FORMAT(fmt->reg_format);
1248
1249	dw100_write(dw_dev, DW100_DEWARP_CTRL, val);
1250
1251	/* Swap */
1252	val = dw100_read(dw_dev, DW100_SWAP_CONTROL);
1253
1254	val &= ~DW100_SWAP_CONTROL_SRC_MASK;
1255	/*
1256	 * Data swapping is performed only on Y plane for source image.
1257	 */
1258	if (fmt->reg_swap_uv &&
1259	    fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED)
1260		val |= DW100_SWAP_CONTROL_SRC(DW100_SWAP_CONTROL_Y
1261					      (DW100_SWAP_CONTROL_BYTE));
1262
1263	dw100_write(dw_dev, DW100_SWAP_CONTROL, val);
1264
1265	/* Image resolution */
1266	dw100_write(dw_dev, DW100_SRC_IMG_SIZE,
1267		    DW100_IMG_SIZE_WIDTH(width) | DW100_IMG_SIZE_HEIGHT(height));
1268
1269	dw100_write(dw_dev,  DW100_SRC_IMG_STRIDE, stride);
1270
1271	/* Buffers */
1272	dw100_write(dw_dev, DW100_SRC_IMG_Y_BASE, DW100_IMG_Y_BASE(addr_y));
1273	dw100_write(dw_dev, DW100_SRC_IMG_UV_BASE, DW100_IMG_UV_BASE(addr_uv));
1274}
1275
1276static void dw100_hw_set_destination(struct dw100_device *dw_dev,
1277				     const struct dw100_q_data *q_data,
1278				     const struct dw100_fmt *ifmt,
1279				     struct vb2_buffer *buffer)
1280{
1281	u32 width, height, stride, fourcc, val, size_y, size_uv;
1282	const struct dw100_fmt *fmt = q_data->fmt;
1283	dma_addr_t addr_y, addr_uv;
1284
1285	width =  q_data->pix_fmt.width;
1286	height = q_data->pix_fmt.height;
1287	stride = q_data->pix_fmt.plane_fmt[0].bytesperline;
1288	fourcc = fmt->fourcc;
1289
1290	addr_y = vb2_dma_contig_plane_dma_addr(buffer, 0);
1291	size_y = q_data->pix_fmt.plane_fmt[0].sizeimage;
1292
1293	if (q_data->pix_fmt.num_planes == 2) {
1294		addr_uv = vb2_dma_contig_plane_dma_addr(buffer, 1);
1295		size_uv = q_data->pix_fmt.plane_fmt[1].sizeimage;
1296	} else {
1297		addr_uv = addr_y + ALIGN(stride * height, 16);
1298		size_uv = size_y;
1299		if (fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV420_SP)
1300			size_uv /= 2;
1301	}
1302
1303	dev_dbg(&dw_dev->pdev->dev,
1304		"Set HW destination registers for %ux%u - stride %u, pixfmt: %p4cc, dma:%pad\n",
1305		width, height, stride, &fourcc, &addr_y);
1306
1307	/* Pixel Format */
1308	val = dw100_read(dw_dev, DW100_DEWARP_CTRL);
1309
1310	val &= ~DW100_DEWARP_CTRL_OUTPUT_FORMAT_MASK;
1311	val |= DW100_DEWARP_CTRL_OUTPUT_FORMAT(fmt->reg_format);
1312
1313	dw100_write(dw_dev, DW100_DEWARP_CTRL, val);
1314
1315	/* Swap */
1316	val = dw100_read(dw_dev, DW100_SWAP_CONTROL);
1317
1318	val &= ~DW100_SWAP_CONTROL_DST_MASK;
1319
1320	/*
1321	 * Avoid to swap twice
1322	 */
1323	if (fmt->reg_swap_uv ^
1324	    (ifmt->reg_swap_uv && ifmt->reg_format !=
1325	     DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED)) {
1326		if (fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED)
1327			val |= DW100_SWAP_CONTROL_DST(DW100_SWAP_CONTROL_Y
1328						      (DW100_SWAP_CONTROL_BYTE));
1329		else
1330			val |= DW100_SWAP_CONTROL_DST(DW100_SWAP_CONTROL_UV
1331						      (DW100_SWAP_CONTROL_BYTE));
1332	}
1333
1334	dw100_write(dw_dev, DW100_SWAP_CONTROL, val);
1335
1336	/* Image resolution */
1337	dw100_write(dw_dev, DW100_DST_IMG_SIZE,
1338		    DW100_IMG_SIZE_WIDTH(width) | DW100_IMG_SIZE_HEIGHT(height));
1339	dw100_write(dw_dev, DW100_DST_IMG_STRIDE, stride);
1340	dw100_write(dw_dev, DW100_DST_IMG_Y_BASE, DW100_IMG_Y_BASE(addr_y));
1341	dw100_write(dw_dev, DW100_DST_IMG_UV_BASE, DW100_IMG_UV_BASE(addr_uv));
1342	dw100_write(dw_dev, DW100_DST_IMG_Y_SIZE1, DW100_DST_IMG_Y_SIZE(size_y));
1343	dw100_write(dw_dev, DW100_DST_IMG_UV_SIZE1,
1344		    DW100_DST_IMG_UV_SIZE(size_uv));
1345}
1346
1347static void dw100_hw_set_mapping(struct dw100_device *dw_dev, dma_addr_t addr,
1348				 u32 width, u32 height)
1349{
1350	dev_dbg(&dw_dev->pdev->dev,
1351		"Set HW mapping registers for %ux%u addr:%pad",
1352		width, height, &addr);
1353
1354	dw100_write(dw_dev, DW100_MAP_LUT_ADDR, DW100_MAP_LUT_ADDR_ADDR(addr));
1355	dw100_write(dw_dev, DW100_MAP_LUT_SIZE, DW100_MAP_LUT_SIZE_WIDTH(width)
1356		    | DW100_MAP_LUT_SIZE_HEIGHT(height));
1357}
1358
1359static void dw100_hw_clear_irq(struct dw100_device *dw_dev, unsigned int irq)
1360{
1361	dw100_write(dw_dev, DW100_INTERRUPT_STATUS,
1362		    DW100_INTERRUPT_STATUS_INT_CLEAR(irq));
1363}
1364
1365static void dw100_hw_enable_irq(struct dw100_device *dw_dev)
1366{
1367	dw100_write(dw_dev, DW100_INTERRUPT_STATUS,
1368		    DW100_INTERRUPT_STATUS_INT_ENABLE_MASK);
1369}
1370
1371static void dw100_hw_disable_irq(struct dw100_device *dw_dev)
1372{
1373	dw100_write(dw_dev, DW100_INTERRUPT_STATUS, 0);
1374}
1375
1376static u32 dw_hw_get_pending_irqs(struct dw100_device *dw_dev)
1377{
1378	u32 val;
1379
1380	val = dw100_read(dw_dev, DW100_INTERRUPT_STATUS);
1381
1382	return DW100_INTERRUPT_STATUS_INT_STATUS(val);
1383}
1384
1385static irqreturn_t dw100_irq_handler(int irq, void *dev_id)
1386{
1387	struct dw100_device *dw_dev = dev_id;
1388	u32 pending_irqs, err_irqs, frame_done_irq;
1389	bool with_error = true;
1390
1391	pending_irqs = dw_hw_get_pending_irqs(dw_dev);
1392	frame_done_irq = pending_irqs & DW100_INTERRUPT_STATUS_INT_FRAME_DONE;
1393	err_irqs = DW100_INTERRUPT_STATUS_INT_ERR_STATUS(pending_irqs);
1394
1395	if (frame_done_irq) {
1396		dev_dbg(&dw_dev->pdev->dev, "Frame done interrupt\n");
1397		with_error = false;
1398		err_irqs &= ~DW100_INTERRUPT_STATUS_INT_ERR_STATUS
1399			(DW100_INTERRUPT_STATUS_INT_ERR_FRAME_DONE);
1400	}
1401
1402	if (err_irqs)
1403		dev_err(&dw_dev->pdev->dev, "Interrupt error: %#x\n", err_irqs);
1404
1405	dw100_hw_disable_irq(dw_dev);
1406	dw100_hw_master_bus_disable(dw_dev);
1407	dw100_hw_clear_irq(dw_dev, pending_irqs |
1408			   DW100_INTERRUPT_STATUS_INT_ERR_TIME_OUT);
1409
1410	dw100_job_finish(dw_dev, with_error);
1411
1412	return IRQ_HANDLED;
1413}
1414
1415static void dw100_start(struct dw100_ctx *ctx, struct vb2_v4l2_buffer *in_vb,
1416			struct vb2_v4l2_buffer *out_vb)
1417{
1418	struct dw100_device *dw_dev = ctx->dw_dev;
1419
1420	out_vb->sequence =
1421		dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)->sequence++;
1422	in_vb->sequence =
1423		dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)->sequence++;
1424
1425	dev_dbg(&ctx->dw_dev->pdev->dev,
1426		"Starting queues %p->%p, sequence %u->%u\n",
1427		v4l2_m2m_get_vq(ctx->fh.m2m_ctx,
1428				V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE),
1429		v4l2_m2m_get_vq(ctx->fh.m2m_ctx,
1430				V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE),
1431		in_vb->sequence, out_vb->sequence);
1432
1433	v4l2_m2m_buf_copy_metadata(in_vb, out_vb);
1434
1435	/* Now, let's deal with hardware ... */
1436	dw100_hw_master_bus_disable(dw_dev);
1437	dw100_hw_init_ctrl(dw_dev);
1438	dw100_hw_set_pixel_boundary(dw_dev);
1439	dw100_hw_set_src_crop(dw_dev, &ctx->q_data[DW100_QUEUE_SRC],
1440			      &ctx->q_data[DW100_QUEUE_DST]);
1441	dw100_hw_set_source(dw_dev, &ctx->q_data[DW100_QUEUE_SRC],
1442			    &in_vb->vb2_buf);
1443	dw100_hw_set_destination(dw_dev, &ctx->q_data[DW100_QUEUE_DST],
1444				 ctx->q_data[DW100_QUEUE_SRC].fmt,
1445				 &out_vb->vb2_buf);
1446	dw100_hw_set_mapping(dw_dev, ctx->map_dma,
1447			     ctx->map_width, ctx->map_height);
1448	dw100_hw_enable_irq(dw_dev);
1449	dw100_hw_dewarp_start(dw_dev);
1450
1451	/* Enable Bus */
1452	dw100_hw_master_bus_enable(dw_dev);
1453}
1454
1455static void dw100_device_run(void *priv)
1456{
1457	struct dw100_ctx *ctx = priv;
1458	struct vb2_v4l2_buffer *src_buf, *dst_buf;
1459
1460	src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1461	dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1462
1463	dw100_start(ctx, src_buf, dst_buf);
1464}
1465
1466static const struct v4l2_m2m_ops dw100_m2m_ops = {
1467	.device_run	= dw100_device_run,
1468};
1469
1470static struct video_device *dw100_init_video_device(struct dw100_device *dw_dev)
1471{
1472	struct video_device *vfd = &dw_dev->vfd;
1473
1474	vfd->vfl_dir = VFL_DIR_M2M;
1475	vfd->fops = &dw100_fops;
1476	vfd->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
1477	vfd->ioctl_ops = &dw100_ioctl_ops;
1478	vfd->minor = -1;
1479	vfd->release = video_device_release_empty;
1480	vfd->v4l2_dev = &dw_dev->v4l2_dev;
1481	vfd->lock = &dw_dev->vfd_mutex;
1482
1483	strscpy(vfd->name, DRV_NAME, sizeof(vfd->name));
1484	mutex_init(vfd->lock);
1485	video_set_drvdata(vfd, dw_dev);
1486
1487	return vfd;
1488}
1489
1490static int dw100_dump_regs_show(struct seq_file *m, void *private)
1491{
1492	struct dw100_device *dw_dev = m->private;
1493	int ret;
1494
1495	ret = pm_runtime_resume_and_get(&dw_dev->pdev->dev);
1496	if (ret < 0)
1497		return ret;
1498
1499	ret = dw100_dump_regs(m);
1500
1501	pm_runtime_put_sync(&dw_dev->pdev->dev);
1502
1503	return ret;
1504}
1505DEFINE_SHOW_ATTRIBUTE(dw100_dump_regs);
1506
1507static void dw100_debugfs_init(struct dw100_device *dw_dev)
1508{
1509	dw_dev->debugfs_root =
1510		debugfs_create_dir(dev_name(&dw_dev->pdev->dev), NULL);
1511
1512	debugfs_create_file("dump_regs", 0600, dw_dev->debugfs_root, dw_dev,
1513			    &dw100_dump_regs_fops);
1514}
1515
1516static void dw100_debugfs_exit(struct dw100_device *dw_dev)
1517{
1518	debugfs_remove_recursive(dw_dev->debugfs_root);
1519}
1520
1521static int dw100_probe(struct platform_device *pdev)
1522{
1523	struct dw100_device *dw_dev;
1524	struct video_device *vfd;
1525	int ret, irq;
1526
1527	dw_dev = devm_kzalloc(&pdev->dev, sizeof(*dw_dev), GFP_KERNEL);
1528	if (!dw_dev)
1529		return -ENOMEM;
1530	dw_dev->pdev = pdev;
1531
1532	ret = devm_clk_bulk_get_all(&pdev->dev, &dw_dev->clks);
1533	if (ret < 0) {
1534		dev_err(&pdev->dev, "Unable to get clocks: %d\n", ret);
1535		return ret;
1536	}
1537	dw_dev->num_clks = ret;
1538
1539	dw_dev->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1540	if (IS_ERR(dw_dev->mmio))
1541		return PTR_ERR(dw_dev->mmio);
1542
1543	irq = platform_get_irq(pdev, 0);
1544	if (irq < 0)
1545		return irq;
1546
1547	platform_set_drvdata(pdev, dw_dev);
1548
1549	pm_runtime_enable(&pdev->dev);
1550	ret = pm_runtime_resume_and_get(&pdev->dev);
1551	if (ret < 0) {
1552		dev_err(&pdev->dev, "Unable to resume the device: %d\n", ret);
1553		goto err_pm;
1554	}
1555
1556	pm_runtime_put_sync(&pdev->dev);
1557
1558	ret = devm_request_irq(&pdev->dev, irq, dw100_irq_handler, IRQF_ONESHOT,
1559			       dev_name(&pdev->dev), dw_dev);
1560	if (ret < 0) {
1561		dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
1562		goto err_pm;
1563	}
1564
1565	ret = v4l2_device_register(&pdev->dev, &dw_dev->v4l2_dev);
1566	if (ret)
1567		goto err_pm;
1568
1569	vfd = dw100_init_video_device(dw_dev);
1570
1571	dw_dev->m2m_dev = v4l2_m2m_init(&dw100_m2m_ops);
1572	if (IS_ERR(dw_dev->m2m_dev)) {
1573		dev_err(&pdev->dev, "Failed to init mem2mem device\n");
1574		ret = PTR_ERR(dw_dev->m2m_dev);
1575		goto err_v4l2;
1576	}
1577
1578	dw_dev->mdev.dev = &pdev->dev;
1579	strscpy(dw_dev->mdev.model, "dw100", sizeof(dw_dev->mdev.model));
1580	media_device_init(&dw_dev->mdev);
1581	dw_dev->v4l2_dev.mdev = &dw_dev->mdev;
1582
1583	ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1);
1584	if (ret) {
1585		dev_err(&pdev->dev, "Failed to register video device\n");
1586		goto err_m2m;
1587	}
1588
1589	ret = v4l2_m2m_register_media_controller(dw_dev->m2m_dev, vfd,
1590						 MEDIA_ENT_F_PROC_VIDEO_SCALER);
1591	if (ret) {
1592		dev_err(&pdev->dev, "Failed to init mem2mem media controller\n");
1593		goto error_v4l2;
1594	}
1595
1596	ret = media_device_register(&dw_dev->mdev);
1597	if (ret) {
1598		dev_err(&pdev->dev, "Failed to register mem2mem media device\n");
1599		goto error_m2m_mc;
1600	}
1601
1602	dw100_debugfs_init(dw_dev);
1603
1604	dev_info(&pdev->dev,
1605		 "dw100 v4l2 m2m registered as /dev/video%u\n", vfd->num);
1606
1607	return 0;
1608
1609error_m2m_mc:
1610	v4l2_m2m_unregister_media_controller(dw_dev->m2m_dev);
1611error_v4l2:
1612	video_unregister_device(vfd);
1613err_m2m:
1614	media_device_cleanup(&dw_dev->mdev);
1615	v4l2_m2m_release(dw_dev->m2m_dev);
1616err_v4l2:
1617	v4l2_device_unregister(&dw_dev->v4l2_dev);
1618err_pm:
1619	pm_runtime_disable(&pdev->dev);
1620
1621	return ret;
1622}
1623
1624static void dw100_remove(struct platform_device *pdev)
1625{
1626	struct dw100_device *dw_dev = platform_get_drvdata(pdev);
1627
1628	dw100_debugfs_exit(dw_dev);
1629
1630	pm_runtime_disable(&pdev->dev);
1631
1632	media_device_unregister(&dw_dev->mdev);
1633	v4l2_m2m_unregister_media_controller(dw_dev->m2m_dev);
1634	media_device_cleanup(&dw_dev->mdev);
1635
1636	video_unregister_device(&dw_dev->vfd);
1637	mutex_destroy(dw_dev->vfd.lock);
1638	v4l2_m2m_release(dw_dev->m2m_dev);
1639	v4l2_device_unregister(&dw_dev->v4l2_dev);
1640}
1641
1642static int __maybe_unused dw100_runtime_suspend(struct device *dev)
1643{
1644	struct dw100_device *dw_dev = dev_get_drvdata(dev);
1645
1646	clk_bulk_disable_unprepare(dw_dev->num_clks, dw_dev->clks);
1647
1648	return 0;
1649}
1650
1651static int __maybe_unused dw100_runtime_resume(struct device *dev)
1652{
1653	int ret;
1654	struct dw100_device *dw_dev = dev_get_drvdata(dev);
1655
1656	ret = clk_bulk_prepare_enable(dw_dev->num_clks, dw_dev->clks);
1657
1658	if (ret)
1659		return ret;
1660
1661	dw100_hw_reset(dw_dev);
1662
1663	return 0;
1664}
1665
1666static const struct dev_pm_ops dw100_pm = {
1667	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1668				pm_runtime_force_resume)
1669	SET_RUNTIME_PM_OPS(dw100_runtime_suspend,
1670			   dw100_runtime_resume, NULL)
1671};
1672
1673static const struct of_device_id dw100_dt_ids[] = {
1674	{ .compatible = "nxp,imx8mp-dw100", .data = NULL },
1675	{ },
1676};
1677MODULE_DEVICE_TABLE(of, dw100_dt_ids);
1678
1679static struct platform_driver dw100_driver = {
1680	.probe		= dw100_probe,
1681	.remove		= dw100_remove,
1682	.driver		= {
1683		.name	= DRV_NAME,
1684		.pm = &dw100_pm,
1685		.of_match_table = dw100_dt_ids,
1686	},
1687};
1688
1689module_platform_driver(dw100_driver);
1690
1691MODULE_DESCRIPTION("DW100 Hardware dewarper");
1692MODULE_AUTHOR("Xavier Roumegue <Xavier.Roumegue@oss.nxp.com>");
1693MODULE_LICENSE("GPL");