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h264.c
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linux-6.19.14/drivers/media/platform/nvidia/tegra-vde/h264.c
1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * NVIDIA Tegra Video decoder driver 4 * 5 * Copyright (C) 2016-2022 Dmitry Osipenko <digetx@gmail.com> 6 * 7 */ 8 9#include <linux/iopoll.h> 10#include <linux/pm_runtime.h> 11#include <linux/reset.h> 12#include <linux/slab.h> 13 14#include <media/v4l2-h264.h> 15 16#include "trace.h" 17#include "vde.h" 18 19#define FLAG_B_FRAME 0x1 20#define FLAG_REFERENCE 0x2 21 22struct tegra_vde_h264_decoder_ctx { 23 unsigned int dpb_frames_nb; 24 unsigned int dpb_ref_frames_with_earlier_poc_nb; 25 unsigned int baseline_profile; 26 unsigned int level_idc; 27 unsigned int log2_max_pic_order_cnt_lsb; 28 unsigned int log2_max_frame_num; 29 unsigned int pic_order_cnt_type; 30 unsigned int direct_8x8_inference_flag; 31 unsigned int pic_width_in_mbs; 32 unsigned int pic_height_in_mbs; 33 unsigned int pic_init_qp; 34 unsigned int deblocking_filter_control_present_flag; 35 unsigned int constrained_intra_pred_flag; 36 unsigned int chroma_qp_index_offset; 37 unsigned int pic_order_present_flag; 38 unsigned int num_ref_idx_l0_active_minus1; 39 unsigned int num_ref_idx_l1_active_minus1; 40}; 41 42struct h264_reflists { 43 struct v4l2_h264_reference p[V4L2_H264_NUM_DPB_ENTRIES]; 44 struct v4l2_h264_reference b0[V4L2_H264_NUM_DPB_ENTRIES]; 45 struct v4l2_h264_reference b1[V4L2_H264_NUM_DPB_ENTRIES]; 46}; 47 48static int tegra_vde_wait_mbe(struct tegra_vde *vde) 49{ 50 u32 tmp; 51 52 return readl_relaxed_poll_timeout(vde->mbe + 0x8C, tmp, 53 tmp >= 0x10, 1, 100); 54} 55 56static int tegra_vde_setup_mbe_frame_idx(struct tegra_vde *vde, 57 unsigned int refs_nb, 58 bool setup_refs) 59{ 60 u32 value, frame_idx_enb_mask = 0; 61 unsigned int frame_idx; 62 unsigned int idx; 63 int err; 64 65 tegra_vde_writel(vde, 0xD0000000 | (0 << 23), vde->mbe, 0x80); 66 tegra_vde_writel(vde, 0xD0200000 | (0 << 23), vde->mbe, 0x80); 67 68 err = tegra_vde_wait_mbe(vde); 69 if (err) 70 return err; 71 72 if (!setup_refs) 73 return 0; 74 75 for (idx = 0, frame_idx = 1; idx < refs_nb; idx++, frame_idx++) { 76 tegra_vde_writel(vde, 0xD0000000 | (frame_idx << 23), 77 vde->mbe, 0x80); 78 tegra_vde_writel(vde, 0xD0200000 | (frame_idx << 23), 79 vde->mbe, 0x80); 80 81 frame_idx_enb_mask |= frame_idx << (6 * (idx % 4)); 82 83 if (idx % 4 == 3 || idx == refs_nb - 1) { 84 value = 0xC0000000; 85 value |= (idx >> 2) << 24; 86 value |= frame_idx_enb_mask; 87 88 tegra_vde_writel(vde, value, vde->mbe, 0x80); 89 90 err = tegra_vde_wait_mbe(vde); 91 if (err) 92 return err; 93 94 frame_idx_enb_mask = 0; 95 } 96 } 97 98 return 0; 99} 100 101static void tegra_vde_mbe_set_0xa_reg(struct tegra_vde *vde, int reg, u32 val) 102{ 103 tegra_vde_writel(vde, 0xA0000000 | (reg << 24) | (val & 0xFFFF), 104 vde->mbe, 0x80); 105 tegra_vde_writel(vde, 0xA0000000 | ((reg + 1) << 24) | (val >> 16), 106 vde->mbe, 0x80); 107} 108 109static int tegra_vde_wait_bsev(struct tegra_vde *vde, bool wait_dma) 110{ 111 struct device *dev = vde->dev; 112 u32 value; 113 int err; 114 115 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, 116 !(value & BIT(2)), 1, 100); 117 if (err) { 118 dev_err(dev, "BSEV unknown bit timeout\n"); 119 return err; 120 } 121 122 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, 123 (value & BSE_ICMDQUE_EMPTY), 1, 100); 124 if (err) { 125 dev_err(dev, "BSEV ICMDQUE flush timeout\n"); 126 return err; 127 } 128 129 if (!wait_dma) 130 return 0; 131 132 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, 133 !(value & BSE_DMA_BUSY), 1, 1000); 134 if (err) { 135 dev_err(dev, "BSEV DMA timeout\n"); 136 return err; 137 } 138 139 return 0; 140} 141 142static int tegra_vde_push_to_bsev_icmdqueue(struct tegra_vde *vde, 143 u32 value, bool wait_dma) 144{ 145 tegra_vde_writel(vde, value, vde->bsev, ICMDQUE_WR); 146 147 return tegra_vde_wait_bsev(vde, wait_dma); 148} 149 150static void tegra_vde_setup_frameid(struct tegra_vde *vde, 151 struct tegra_video_frame *frame, 152 unsigned int frameid, 153 u32 mbs_width, u32 mbs_height) 154{ 155 u32 y_addr = frame ? frame->y_addr : 0x6CDEAD00; 156 u32 cb_addr = frame ? frame->cb_addr : 0x6CDEAD00; 157 u32 cr_addr = frame ? frame->cr_addr : 0x6CDEAD00; 158 u32 value1 = frame ? ((frame->luma_atoms_pitch << 16) | mbs_height) : 0; 159 u32 value2 = frame ? ((frame->chroma_atoms_pitch << 6) | 1) : 0; 160 161 tegra_vde_writel(vde, y_addr >> 8, vde->frameid, 0x000 + frameid * 4); 162 tegra_vde_writel(vde, cb_addr >> 8, vde->frameid, 0x100 + frameid * 4); 163 tegra_vde_writel(vde, cr_addr >> 8, vde->frameid, 0x180 + frameid * 4); 164 tegra_vde_writel(vde, value1, vde->frameid, 0x080 + frameid * 4); 165 tegra_vde_writel(vde, value2, vde->frameid, 0x280 + frameid * 4); 166} 167 168static void tegra_setup_frameidx(struct tegra_vde *vde, 169 struct tegra_video_frame *frames, 170 unsigned int frames_nb, 171 u32 mbs_width, u32 mbs_height) 172{ 173 unsigned int idx; 174 175 for (idx = 0; idx < frames_nb; idx++) 176 tegra_vde_setup_frameid(vde, &frames[idx], idx, 177 mbs_width, mbs_height); 178 179 for (; idx < 17; idx++) 180 tegra_vde_setup_frameid(vde, NULL, idx, 0, 0); 181} 182 183static void tegra_vde_setup_iram_entry(struct tegra_vde *vde, 184 unsigned int table, 185 unsigned int row, 186 u32 value1, u32 value2) 187{ 188 u32 *iram_tables = vde->iram; 189 190 trace_vde_setup_iram_entry(table, row, value1, value2); 191 192 iram_tables[0x20 * table + row * 2 + 0] = value1; 193 iram_tables[0x20 * table + row * 2 + 1] = value2; 194} 195 196static void tegra_vde_setup_iram_tables(struct tegra_vde *vde, 197 struct tegra_video_frame *dpb_frames, 198 unsigned int ref_frames_nb, 199 unsigned int with_earlier_poc_nb) 200{ 201 struct tegra_video_frame *frame; 202 int with_later_poc_nb; 203 u32 value, aux_addr; 204 unsigned int i, k; 205 206 trace_vde_ref_l0(dpb_frames[0].frame_num); 207 208 for (i = 0; i < 16; i++) { 209 if (i < ref_frames_nb) { 210 frame = &dpb_frames[i + 1]; 211 212 aux_addr = frame->aux_addr; 213 214 value = (i + 1) << 26; 215 value |= !(frame->flags & FLAG_B_FRAME) << 25; 216 value |= 1 << 24; 217 value |= frame->frame_num; 218 } else { 219 aux_addr = 0x6ADEAD00; 220 value = 0x3f; 221 } 222 223 tegra_vde_setup_iram_entry(vde, 0, i, value, aux_addr); 224 tegra_vde_setup_iram_entry(vde, 1, i, value, aux_addr); 225 tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr); 226 tegra_vde_setup_iram_entry(vde, 3, i, value, aux_addr); 227 } 228 229 if (!(dpb_frames[0].flags & FLAG_B_FRAME)) 230 return; 231 232 if (with_earlier_poc_nb >= ref_frames_nb) 233 return; 234 235 with_later_poc_nb = ref_frames_nb - with_earlier_poc_nb; 236 237 trace_vde_ref_l1(with_later_poc_nb, with_earlier_poc_nb); 238 239 for (i = 0, k = with_earlier_poc_nb; i < with_later_poc_nb; i++, k++) { 240 frame = &dpb_frames[k + 1]; 241 242 aux_addr = frame->aux_addr; 243 244 value = (k + 1) << 26; 245 value |= !(frame->flags & FLAG_B_FRAME) << 25; 246 value |= 1 << 24; 247 value |= frame->frame_num; 248 249 tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr); 250 } 251 252 for (k = 0; i < ref_frames_nb; i++, k++) { 253 frame = &dpb_frames[k + 1]; 254 255 aux_addr = frame->aux_addr; 256 257 value = (k + 1) << 26; 258 value |= !(frame->flags & FLAG_B_FRAME) << 25; 259 value |= 1 << 24; 260 value |= frame->frame_num; 261 262 tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr); 263 } 264} 265 266static int tegra_vde_setup_hw_context(struct tegra_vde *vde, 267 struct tegra_vde_h264_decoder_ctx *ctx, 268 struct tegra_video_frame *dpb_frames, 269 dma_addr_t bitstream_data_addr, 270 size_t bitstream_data_size, 271 unsigned int macroblocks_nb) 272{ 273 struct device *dev = vde->dev; 274 u32 value; 275 int err; 276 277 tegra_vde_set_bits(vde, 0x000A, vde->sxe, 0xF0); 278 tegra_vde_set_bits(vde, 0x000B, vde->bsev, CMDQUE_CONTROL); 279 tegra_vde_set_bits(vde, 0x8002, vde->mbe, 0x50); 280 tegra_vde_set_bits(vde, 0x000A, vde->mbe, 0xA0); 281 tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x14); 282 tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x28); 283 tegra_vde_set_bits(vde, 0x0A00, vde->mce, 0x08); 284 tegra_vde_set_bits(vde, 0x000A, vde->tfe, 0x00); 285 tegra_vde_set_bits(vde, 0x0005, vde->vdma, 0x04); 286 287 tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x1C); 288 tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x00); 289 tegra_vde_writel(vde, 0x00000007, vde->vdma, 0x04); 290 tegra_vde_writel(vde, 0x00000007, vde->frameid, 0x200); 291 tegra_vde_writel(vde, 0x00000005, vde->tfe, 0x04); 292 tegra_vde_writel(vde, 0x00000000, vde->mbe, 0x84); 293 tegra_vde_writel(vde, 0x00000010, vde->sxe, 0x08); 294 tegra_vde_writel(vde, 0x00000150, vde->sxe, 0x54); 295 tegra_vde_writel(vde, 0x0000054C, vde->sxe, 0x58); 296 tegra_vde_writel(vde, 0x00000E34, vde->sxe, 0x5C); 297 tegra_vde_writel(vde, 0x063C063C, vde->mce, 0x10); 298 tegra_vde_writel(vde, 0x0003FC00, vde->bsev, INTR_STATUS); 299 tegra_vde_writel(vde, 0x0000150D, vde->bsev, BSE_CONFIG); 300 tegra_vde_writel(vde, 0x00000100, vde->bsev, BSE_INT_ENB); 301 tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x98); 302 tegra_vde_writel(vde, 0x00000060, vde->bsev, 0x9C); 303 304 memset(vde->iram + 128, 0, macroblocks_nb / 2); 305 306 tegra_setup_frameidx(vde, dpb_frames, ctx->dpb_frames_nb, 307 ctx->pic_width_in_mbs, ctx->pic_height_in_mbs); 308 309 tegra_vde_setup_iram_tables(vde, dpb_frames, 310 ctx->dpb_frames_nb - 1, 311 ctx->dpb_ref_frames_with_earlier_poc_nb); 312 313 /* 314 * The IRAM mapping is write-combine, ensure that CPU buffers have 315 * been flushed at this point. 316 */ 317 wmb(); 318 319 tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x8C); 320 tegra_vde_writel(vde, bitstream_data_addr + bitstream_data_size, 321 vde->bsev, 0x54); 322 323 vde->bitstream_data_addr = bitstream_data_addr; 324 325 value = ctx->pic_width_in_mbs << 11 | ctx->pic_height_in_mbs << 3; 326 327 tegra_vde_writel(vde, value, vde->bsev, 0x88); 328 329 err = tegra_vde_wait_bsev(vde, false); 330 if (err) 331 return err; 332 333 err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x800003FC, false); 334 if (err) 335 return err; 336 337 value = 0x01500000; 338 value |= ((vde->iram_lists_addr + 512) >> 2) & 0xFFFF; 339 340 err = tegra_vde_push_to_bsev_icmdqueue(vde, value, true); 341 if (err) 342 return err; 343 344 err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x840F054C, false); 345 if (err) 346 return err; 347 348 err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x80000080, false); 349 if (err) 350 return err; 351 352 value = 0x0E340000 | ((vde->iram_lists_addr >> 2) & 0xFFFF); 353 354 err = tegra_vde_push_to_bsev_icmdqueue(vde, value, true); 355 if (err) 356 return err; 357 358 value = 0x00800005; 359 value |= ctx->pic_width_in_mbs << 11; 360 value |= ctx->pic_height_in_mbs << 3; 361 362 tegra_vde_writel(vde, value, vde->sxe, 0x10); 363 364 value = !ctx->baseline_profile << 17; 365 value |= ctx->level_idc << 13; 366 value |= ctx->log2_max_pic_order_cnt_lsb << 7; 367 value |= ctx->pic_order_cnt_type << 5; 368 value |= ctx->log2_max_frame_num; 369 370 tegra_vde_writel(vde, value, vde->sxe, 0x40); 371 372 value = ctx->pic_init_qp << 25; 373 value |= !!(ctx->deblocking_filter_control_present_flag) << 2; 374 value |= !!ctx->pic_order_present_flag; 375 376 tegra_vde_writel(vde, value, vde->sxe, 0x44); 377 378 value = ctx->chroma_qp_index_offset; 379 value |= ctx->num_ref_idx_l0_active_minus1 << 5; 380 value |= ctx->num_ref_idx_l1_active_minus1 << 10; 381 value |= !!ctx->constrained_intra_pred_flag << 15; 382 383 tegra_vde_writel(vde, value, vde->sxe, 0x48); 384 385 value = 0x0C000000; 386 value |= !!(dpb_frames[0].flags & FLAG_B_FRAME) << 24; 387 388 tegra_vde_writel(vde, value, vde->sxe, 0x4C); 389 390 value = 0x03800000; 391 value |= bitstream_data_size & GENMASK(19, 15); 392 393 tegra_vde_writel(vde, value, vde->sxe, 0x68); 394 395 tegra_vde_writel(vde, bitstream_data_addr, vde->sxe, 0x6C); 396 397 if (vde->soc->supports_ref_pic_marking) 398 tegra_vde_writel(vde, vde->secure_bo->dma_addr, vde->sxe, 0x7c); 399 400 value = 0x10000005; 401 value |= ctx->pic_width_in_mbs << 11; 402 value |= ctx->pic_height_in_mbs << 3; 403 404 tegra_vde_writel(vde, value, vde->mbe, 0x80); 405 406 value = 0x26800000; 407 value |= ctx->level_idc << 4; 408 value |= !ctx->baseline_profile << 1; 409 value |= !!ctx->direct_8x8_inference_flag; 410 411 tegra_vde_writel(vde, value, vde->mbe, 0x80); 412 413 tegra_vde_writel(vde, 0xF4000001, vde->mbe, 0x80); 414 tegra_vde_writel(vde, 0x20000000, vde->mbe, 0x80); 415 tegra_vde_writel(vde, 0xF4000101, vde->mbe, 0x80); 416 417 value = 0x20000000; 418 value |= ctx->chroma_qp_index_offset << 8; 419 420 tegra_vde_writel(vde, value, vde->mbe, 0x80); 421 422 err = tegra_vde_setup_mbe_frame_idx(vde, 423 ctx->dpb_frames_nb - 1, 424 ctx->pic_order_cnt_type == 0); 425 if (err) { 426 dev_err(dev, "MBE frames setup failed %d\n", err); 427 return err; 428 } 429 430 tegra_vde_mbe_set_0xa_reg(vde, 0, 0x000009FC); 431 tegra_vde_mbe_set_0xa_reg(vde, 2, 0x61DEAD00); 432 tegra_vde_mbe_set_0xa_reg(vde, 4, 0x62DEAD00); 433 tegra_vde_mbe_set_0xa_reg(vde, 6, 0x63DEAD00); 434 tegra_vde_mbe_set_0xa_reg(vde, 8, dpb_frames[0].aux_addr); 435 436 value = 0xFC000000; 437 value |= !!(dpb_frames[0].flags & FLAG_B_FRAME) << 2; 438 439 if (!ctx->baseline_profile) 440 value |= !!(dpb_frames[0].flags & FLAG_REFERENCE) << 1; 441 442 tegra_vde_writel(vde, value, vde->mbe, 0x80); 443 444 err = tegra_vde_wait_mbe(vde); 445 if (err) { 446 dev_err(dev, "MBE programming failed %d\n", err); 447 return err; 448 } 449 450 return 0; 451} 452 453static void tegra_vde_decode_frame(struct tegra_vde *vde, 454 unsigned int macroblocks_nb) 455{ 456 reinit_completion(&vde->decode_completion); 457 458 tegra_vde_writel(vde, 0x00000001, vde->bsev, 0x8C); 459 tegra_vde_writel(vde, 0x20000000 | (macroblocks_nb - 1), 460 vde->sxe, 0x00); 461} 462 463static int tegra_vde_validate_h264_ctx(struct device *dev, 464 struct tegra_vde_h264_decoder_ctx *ctx) 465{ 466 if (ctx->dpb_frames_nb == 0 || ctx->dpb_frames_nb > 17) { 467 dev_err(dev, "Bad DPB size %u\n", ctx->dpb_frames_nb); 468 return -EINVAL; 469 } 470 471 if (ctx->level_idc > 15) { 472 dev_err(dev, "Bad level value %u\n", ctx->level_idc); 473 return -EINVAL; 474 } 475 476 if (ctx->pic_init_qp > 52) { 477 dev_err(dev, "Bad pic_init_qp value %u\n", ctx->pic_init_qp); 478 return -EINVAL; 479 } 480 481 if (ctx->log2_max_pic_order_cnt_lsb > 16) { 482 dev_err(dev, "Bad log2_max_pic_order_cnt_lsb value %u\n", 483 ctx->log2_max_pic_order_cnt_lsb); 484 return -EINVAL; 485 } 486 487 if (ctx->log2_max_frame_num > 16) { 488 dev_err(dev, "Bad log2_max_frame_num value %u\n", 489 ctx->log2_max_frame_num); 490 return -EINVAL; 491 } 492 493 if (ctx->chroma_qp_index_offset > 31) { 494 dev_err(dev, "Bad chroma_qp_index_offset value %u\n", 495 ctx->chroma_qp_index_offset); 496 return -EINVAL; 497 } 498 499 if (ctx->pic_order_cnt_type > 2) { 500 dev_err(dev, "Bad pic_order_cnt_type value %u\n", 501 ctx->pic_order_cnt_type); 502 return -EINVAL; 503 } 504 505 if (ctx->num_ref_idx_l0_active_minus1 > 15) { 506 dev_err(dev, "Bad num_ref_idx_l0_active_minus1 value %u\n", 507 ctx->num_ref_idx_l0_active_minus1); 508 return -EINVAL; 509 } 510 511 if (ctx->num_ref_idx_l1_active_minus1 > 15) { 512 dev_err(dev, "Bad num_ref_idx_l1_active_minus1 value %u\n", 513 ctx->num_ref_idx_l1_active_minus1); 514 return -EINVAL; 515 } 516 517 if (!ctx->pic_width_in_mbs || ctx->pic_width_in_mbs > 127) { 518 dev_err(dev, "Bad pic_width_in_mbs value %u\n", 519 ctx->pic_width_in_mbs); 520 return -EINVAL; 521 } 522 523 if (!ctx->pic_height_in_mbs || ctx->pic_height_in_mbs > 127) { 524 dev_err(dev, "Bad pic_height_in_mbs value %u\n", 525 ctx->pic_height_in_mbs); 526 return -EINVAL; 527 } 528 529 return 0; 530} 531 532static int tegra_vde_decode_begin(struct tegra_vde *vde, 533 struct tegra_vde_h264_decoder_ctx *ctx, 534 struct tegra_video_frame *dpb_frames, 535 dma_addr_t bitstream_data_addr, 536 size_t bitstream_data_size) 537{ 538 struct device *dev = vde->dev; 539 unsigned int macroblocks_nb; 540 int err; 541 542 err = mutex_lock_interruptible(&vde->lock); 543 if (err) 544 return err; 545 546 err = pm_runtime_resume_and_get(dev); 547 if (err < 0) 548 goto unlock; 549 550 /* 551 * We rely on the VDE registers reset value, otherwise VDE 552 * causes bus lockup. 553 */ 554 err = reset_control_assert(vde->rst_mc); 555 if (err) { 556 dev_err(dev, "DEC start: Failed to assert MC reset: %d\n", 557 err); 558 goto put_runtime_pm; 559 } 560 561 err = reset_control_reset(vde->rst); 562 if (err) { 563 dev_err(dev, "DEC start: Failed to reset HW: %d\n", err); 564 goto put_runtime_pm; 565 } 566 567 err = reset_control_deassert(vde->rst_mc); 568 if (err) { 569 dev_err(dev, "DEC start: Failed to deassert MC reset: %d\n", 570 err); 571 goto put_runtime_pm; 572 } 573 574 macroblocks_nb = ctx->pic_width_in_mbs * ctx->pic_height_in_mbs; 575 576 err = tegra_vde_setup_hw_context(vde, ctx, dpb_frames, 577 bitstream_data_addr, 578 bitstream_data_size, 579 macroblocks_nb); 580 if (err) 581 goto put_runtime_pm; 582 583 tegra_vde_decode_frame(vde, macroblocks_nb); 584 585 return 0; 586 587put_runtime_pm: 588 pm_runtime_put_autosuspend(dev); 589 590unlock: 591 mutex_unlock(&vde->lock); 592 593 return err; 594} 595 596static void tegra_vde_decode_abort(struct tegra_vde *vde) 597{ 598 struct device *dev = vde->dev; 599 int err; 600 601 /* 602 * At first reset memory client to avoid resetting VDE HW in the 603 * middle of DMA which could result into memory corruption or hang 604 * the whole system. 605 */ 606 err = reset_control_assert(vde->rst_mc); 607 if (err) 608 dev_err(dev, "DEC end: Failed to assert MC reset: %d\n", err); 609 610 err = reset_control_assert(vde->rst); 611 if (err) 612 dev_err(dev, "DEC end: Failed to assert HW reset: %d\n", err); 613 614 pm_runtime_put_autosuspend(dev); 615 616 mutex_unlock(&vde->lock); 617} 618 619static int tegra_vde_decode_end(struct tegra_vde *vde) 620{ 621 unsigned int read_bytes, macroblocks_nb; 622 struct device *dev = vde->dev; 623 dma_addr_t bsev_ptr; 624 long time_left; 625 int ret; 626 627 time_left = wait_for_completion_interruptible_timeout( 628 &vde->decode_completion, msecs_to_jiffies(1000)); 629 if (time_left < 0) { 630 ret = time_left; 631 } else if (time_left == 0) { 632 bsev_ptr = tegra_vde_readl(vde, vde->bsev, 0x10); 633 macroblocks_nb = tegra_vde_readl(vde, vde->sxe, 0xC8) & 0x1FFF; 634 read_bytes = bsev_ptr ? bsev_ptr - vde->bitstream_data_addr : 0; 635 636 dev_err(dev, "Decoding failed: read 0x%X bytes, %u macroblocks parsed\n", 637 read_bytes, macroblocks_nb); 638 639 ret = -EIO; 640 } else { 641 ret = 0; 642 } 643 644 tegra_vde_decode_abort(vde); 645 646 return ret; 647} 648 649static struct vb2_buffer *get_ref_buf(struct tegra_ctx *ctx, 650 struct vb2_v4l2_buffer *dst, 651 unsigned int dpb_idx) 652{ 653 const struct v4l2_h264_dpb_entry *dpb = ctx->h264.decode_params->dpb; 654 struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q; 655 struct vb2_buffer *vb = NULL; 656 657 if (dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) 658 vb = vb2_find_buffer(cap_q, dpb[dpb_idx].reference_ts); 659 660 /* 661 * If a DPB entry is unused or invalid, address of current destination 662 * buffer is returned. 663 */ 664 if (!vb) 665 return &dst->vb2_buf; 666 667 return vb; 668} 669 670static int tegra_vde_validate_vb_size(struct tegra_ctx *ctx, 671 struct vb2_buffer *vb, 672 unsigned int plane_id, 673 size_t min_size) 674{ 675 u64 offset = vb->planes[plane_id].data_offset; 676 struct device *dev = ctx->vde->dev; 677 678 if (offset + min_size > vb2_plane_size(vb, plane_id)) { 679 dev_err(dev, "Too small plane[%u] size %lu @0x%llX, should be at least %zu\n", 680 plane_id, vb2_plane_size(vb, plane_id), offset, min_size); 681 return -EINVAL; 682 } 683 684 return 0; 685} 686 687static int tegra_vde_h264_setup_frame(struct tegra_ctx *ctx, 688 struct tegra_vde_h264_decoder_ctx *h264, 689 struct v4l2_h264_reflist_builder *b, 690 struct vb2_buffer *vb, 691 unsigned int ref_id, 692 unsigned int id) 693{ 694 struct v4l2_pix_format_mplane *pixfmt = &ctx->decoded_fmt.fmt.pix_mp; 695 struct tegra_m2m_buffer *tb = vb_to_tegra_buf(vb); 696 struct tegra_ctx_h264 *h = &ctx->h264; 697 struct tegra_vde *vde = ctx->vde; 698 struct device *dev = vde->dev; 699 unsigned int cstride, lstride; 700 unsigned int flags = 0; 701 size_t lsize, csize; 702 int err, frame_num; 703 704 lsize = h264->pic_width_in_mbs * 16 * h264->pic_height_in_mbs * 16; 705 csize = h264->pic_width_in_mbs * 8 * h264->pic_height_in_mbs * 8; 706 lstride = pixfmt->plane_fmt[0].bytesperline; 707 cstride = pixfmt->plane_fmt[1].bytesperline; 708 709 err = tegra_vde_validate_vb_size(ctx, vb, 0, lsize); 710 if (err) 711 return err; 712 713 err = tegra_vde_validate_vb_size(ctx, vb, 1, csize); 714 if (err) 715 return err; 716 717 err = tegra_vde_validate_vb_size(ctx, vb, 2, csize); 718 if (err) 719 return err; 720 721 if (!tb->aux || tb->aux->size < csize) { 722 dev_err(dev, "Too small aux size %zd, should be at least %zu\n", 723 tb->aux ? tb->aux->size : -1, csize); 724 return -EINVAL; 725 } 726 727 if (id == 0) { 728 frame_num = h->decode_params->frame_num; 729 730 if (h->decode_params->nal_ref_idc) 731 flags |= FLAG_REFERENCE; 732 } else { 733 frame_num = b->refs[ref_id].frame_num; 734 } 735 736 if (tb->b_frame) 737 flags |= FLAG_B_FRAME; 738 739 vde->frames[id].flags = flags; 740 vde->frames[id].y_addr = tb->dma_addr[0]; 741 vde->frames[id].cb_addr = tb->dma_addr[1]; 742 vde->frames[id].cr_addr = tb->dma_addr[2]; 743 vde->frames[id].aux_addr = tb->aux->dma_addr; 744 vde->frames[id].frame_num = frame_num & 0x7fffff; 745 vde->frames[id].luma_atoms_pitch = lstride / VDE_ATOM; 746 vde->frames[id].chroma_atoms_pitch = cstride / VDE_ATOM; 747 748 return 0; 749} 750 751static int tegra_vde_h264_setup_frames(struct tegra_ctx *ctx, 752 struct tegra_vde_h264_decoder_ctx *h264) 753{ 754 struct vb2_v4l2_buffer *src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); 755 struct vb2_v4l2_buffer *dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); 756 const struct v4l2_h264_dpb_entry *dpb = ctx->h264.decode_params->dpb; 757 struct tegra_m2m_buffer *tb = vb_to_tegra_buf(&dst->vb2_buf); 758 struct tegra_ctx_h264 *h = &ctx->h264; 759 struct v4l2_h264_reflist_builder b; 760 struct v4l2_h264_reference *dpb_id; 761 struct h264_reflists reflists; 762 struct vb2_buffer *ref; 763 unsigned int i; 764 int err; 765 766 /* 767 * Tegra hardware requires information about frame's type, assuming 768 * that frame consists of the same type slices. Userspace must tag 769 * frame's type appropriately. 770 * 771 * Decoding of a non-uniform frames isn't supported by hardware and 772 * require software preprocessing that we don't implement. Decoding 773 * is expected to fail in this case. Such video streams are rare in 774 * practice, so not a big deal. 775 * 776 * If userspace doesn't tell us frame's type, then we will try decode 777 * as-is. 778 */ 779 v4l2_m2m_buf_copy_metadata(src, dst); 780 781 if (h->decode_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BFRAME) 782 tb->b_frame = true; 783 else 784 tb->b_frame = false; 785 786 err = tegra_vde_h264_setup_frame(ctx, h264, NULL, &dst->vb2_buf, 0, 787 h264->dpb_frames_nb++); 788 if (err) 789 return err; 790 791 if (!(h->decode_params->flags & (V4L2_H264_DECODE_PARAM_FLAG_PFRAME | 792 V4L2_H264_DECODE_PARAM_FLAG_BFRAME))) 793 return 0; 794 795 v4l2_h264_init_reflist_builder(&b, h->decode_params, h->sps, dpb); 796 797 if (h->decode_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BFRAME) { 798 v4l2_h264_build_b_ref_lists(&b, reflists.b0, reflists.b1); 799 dpb_id = reflists.b0; 800 } else { 801 v4l2_h264_build_p_ref_list(&b, reflists.p); 802 dpb_id = reflists.p; 803 } 804 805 for (i = 0; i < b.num_valid; i++) { 806 int dpb_idx = dpb_id[i].index; 807 808 ref = get_ref_buf(ctx, dst, dpb_idx); 809 810 err = tegra_vde_h264_setup_frame(ctx, h264, &b, ref, dpb_idx, 811 h264->dpb_frames_nb++); 812 if (err) 813 return err; 814 815 if (b.refs[dpb_idx].top_field_order_cnt < b.cur_pic_order_count) 816 h264->dpb_ref_frames_with_earlier_poc_nb++; 817 } 818 819 return 0; 820} 821 822static unsigned int to_tegra_vde_h264_level_idc(unsigned int level_idc) 823{ 824 switch (level_idc) { 825 case 11: 826 return 2; 827 case 12: 828 return 3; 829 case 13: 830 return 4; 831 case 20: 832 return 5; 833 case 21: 834 return 6; 835 case 22: 836 return 7; 837 case 30: 838 return 8; 839 case 31: 840 return 9; 841 case 32: 842 return 10; 843 case 40: 844 return 11; 845 case 41: 846 return 12; 847 case 42: 848 return 13; 849 case 50: 850 return 14; 851 default: 852 break; 853 } 854 855 return 15; 856} 857 858static int tegra_vde_h264_setup_context(struct tegra_ctx *ctx, 859 struct tegra_vde_h264_decoder_ctx *h264) 860{ 861 struct tegra_ctx_h264 *h = &ctx->h264; 862 struct tegra_vde *vde = ctx->vde; 863 struct device *dev = vde->dev; 864 int err; 865 866 memset(h264, 0, sizeof(*h264)); 867 memset(vde->frames, 0, sizeof(vde->frames)); 868 869 tegra_vde_prepare_control_data(ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS); 870 tegra_vde_prepare_control_data(ctx, V4L2_CID_STATELESS_H264_SPS); 871 tegra_vde_prepare_control_data(ctx, V4L2_CID_STATELESS_H264_PPS); 872 873 /* CABAC unsupported by hardware, requires software preprocessing */ 874 if (h->pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) 875 return -EOPNOTSUPP; 876 877 if (h->decode_params->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) 878 return -EOPNOTSUPP; 879 880 if (h->sps->profile_idc == 66) 881 h264->baseline_profile = 1; 882 883 if (h->sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) 884 h264->direct_8x8_inference_flag = 1; 885 886 if (h->pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) 887 h264->constrained_intra_pred_flag = 1; 888 889 if (h->pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT) 890 h264->deblocking_filter_control_present_flag = 1; 891 892 if (h->pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT) 893 h264->pic_order_present_flag = 1; 894 895 h264->level_idc = to_tegra_vde_h264_level_idc(h->sps->level_idc); 896 h264->log2_max_pic_order_cnt_lsb = h->sps->log2_max_pic_order_cnt_lsb_minus4 + 4; 897 h264->log2_max_frame_num = h->sps->log2_max_frame_num_minus4 + 4; 898 h264->pic_order_cnt_type = h->sps->pic_order_cnt_type; 899 h264->pic_width_in_mbs = h->sps->pic_width_in_mbs_minus1 + 1; 900 h264->pic_height_in_mbs = h->sps->pic_height_in_map_units_minus1 + 1; 901 902 h264->num_ref_idx_l0_active_minus1 = h->pps->num_ref_idx_l0_default_active_minus1; 903 h264->num_ref_idx_l1_active_minus1 = h->pps->num_ref_idx_l1_default_active_minus1; 904 h264->chroma_qp_index_offset = h->pps->chroma_qp_index_offset & 0x1f; 905 h264->pic_init_qp = h->pps->pic_init_qp_minus26 + 26; 906 907 err = tegra_vde_h264_setup_frames(ctx, h264); 908 if (err) 909 return err; 910 911 err = tegra_vde_validate_h264_ctx(dev, h264); 912 if (err) 913 return err; 914 915 return 0; 916} 917 918int tegra_vde_h264_decode_run(struct tegra_ctx *ctx) 919{ 920 struct vb2_v4l2_buffer *src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); 921 struct tegra_m2m_buffer *bitstream = vb_to_tegra_buf(&src->vb2_buf); 922 size_t bitstream_size = vb2_get_plane_payload(&src->vb2_buf, 0); 923 struct tegra_vde_h264_decoder_ctx h264; 924 struct tegra_vde *vde = ctx->vde; 925 int err; 926 927 err = tegra_vde_h264_setup_context(ctx, &h264); 928 if (err) 929 return err; 930 931 err = tegra_vde_decode_begin(vde, &h264, vde->frames, 932 bitstream->dma_addr[0], 933 bitstream_size); 934 if (err) 935 return err; 936 937 return 0; 938} 939 940int tegra_vde_h264_decode_wait(struct tegra_ctx *ctx) 941{ 942 return tegra_vde_decode_end(ctx->vde); 943}
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