npcm-video.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Driver for Video Capture/Differentiation Engine (VCD) and Encoding
   4 * Compression Engine (ECE) present on Nuvoton NPCM SoCs.
   5 *
   6 * Copyright (C) 2022 Nuvoton Technologies
   7 */
   8
   9#include <linux/atomic.h>
  10#include <linux/bitfield.h>
  11#include <linux/bitmap.h>
  12#include <linux/clk.h>
  13#include <linux/delay.h>
  14#include <linux/device.h>
  15#include <linux/dma-mapping.h>
  16#include <linux/interrupt.h>
  17#include <linux/jiffies.h>
  18#include <linux/mfd/syscon.h>
  19#include <linux/module.h>
  20#include <linux/mutex.h>
  21#include <linux/of.h>
  22#include <linux/of_irq.h>
  23#include <linux/of_platform.h>
  24#include <linux/of_reserved_mem.h>
  25#include <linux/platform_device.h>
  26#include <linux/regmap.h>
  27#include <linux/reset.h>
  28#include <linux/sched.h>
  29#include <linux/string.h>
  30#include <linux/v4l2-controls.h>
  31#include <linux/videodev2.h>
  32#include <media/v4l2-ctrls.h>
  33#include <media/v4l2-dev.h>
  34#include <media/v4l2-device.h>
  35#include <media/v4l2-dv-timings.h>
  36#include <media/v4l2-event.h>
  37#include <media/v4l2-ioctl.h>
  38#include <media/videobuf2-dma-contig.h>
  39#include <uapi/linux/npcm-video.h>
  40#include "npcm-regs.h"
  41
  42#define DEVICE_NAME	"npcm-video"
  43#define MAX_WIDTH	1920
  44#define MAX_HEIGHT	1200
  45#define MIN_WIDTH	320
  46#define MIN_HEIGHT	240
  47#define MIN_LP		512
  48#define MAX_LP		4096
  49#define RECT_W		16
  50#define RECT_H		16
  51#define BITMAP_SIZE	32
  52
  53struct npcm_video_addr {
  54	size_t size;
  55	dma_addr_t dma;
  56	void *virt;
  57};
  58
  59struct npcm_video_buffer {
  60	struct vb2_v4l2_buffer vb;
  61	struct list_head link;
  62};
  63
  64#define to_npcm_video_buffer(x) \
  65	container_of((x), struct npcm_video_buffer, vb)
  66
  67/*
  68 * VIDEO_STREAMING:	a flag indicating if the video has started streaming
  69 * VIDEO_CAPTURING:	a flag indicating if the VCD is capturing a frame
  70 * VIDEO_RES_CHANGING:	a flag indicating if the resolution is changing
  71 * VIDEO_STOPPED:	a flag indicating if the video has stopped streaming
  72 */
  73enum {
  74	VIDEO_STREAMING,
  75	VIDEO_CAPTURING,
  76	VIDEO_RES_CHANGING,
  77	VIDEO_STOPPED,
  78};
  79
  80struct rect_list {
  81	struct v4l2_clip clip;
  82	struct list_head list;
  83};
  84
  85struct rect_list_info {
  86	struct rect_list *list;
  87	struct rect_list *first;
  88	struct list_head *head;
  89	unsigned int index;
  90	unsigned int tile_perline;
  91	unsigned int tile_perrow;
  92	unsigned int offset_perline;
  93	unsigned int tile_size;
  94	unsigned int tile_cnt;
  95};
  96
  97struct npcm_ece {
  98	struct regmap *regmap;
  99	atomic_t clients;
 100	struct reset_control *reset;
 101	bool enable;
 102};
 103
 104struct npcm_video {
 105	struct regmap *gcr_regmap;
 106	struct regmap *gfx_regmap;
 107	struct regmap *vcd_regmap;
 108
 109	struct device *dev;
 110	struct v4l2_ctrl_handler ctrl_handler;
 111	struct v4l2_ctrl *rect_cnt_ctrl;
 112	struct v4l2_device v4l2_dev;
 113	struct v4l2_pix_format pix_fmt;
 114	struct v4l2_bt_timings active_timings;
 115	struct v4l2_bt_timings detected_timings;
 116	unsigned int v4l2_input_status;
 117	struct vb2_queue queue;
 118	struct video_device vdev;
 119	struct mutex video_lock; /* v4l2 and videobuf2 lock */
 120
 121	struct list_head buffers;
 122	struct mutex buffer_lock; /* buffer list lock */
 123	unsigned long flags;
 124	unsigned int sequence;
 125
 126	struct npcm_video_addr src;
 127	struct reset_control *reset;
 128	struct npcm_ece ece;
 129
 130	unsigned int bytesperline;
 131	unsigned int bytesperpixel;
 132	unsigned int rect_cnt;
 133	struct list_head list[VIDEO_MAX_FRAME];
 134	unsigned int rect[VIDEO_MAX_FRAME];
 135	unsigned int ctrl_cmd;
 136	unsigned int op_cmd;
 137};
 138
 139#define to_npcm_video(x) container_of((x), struct npcm_video, v4l2_dev)
 140
 141struct npcm_fmt {
 142	unsigned int fourcc;
 143	unsigned int bpp; /* bytes per pixel */
 144};
 145
 146static const struct npcm_fmt npcm_fmt_list[] = {
 147	{
 148		.fourcc = V4L2_PIX_FMT_RGB565,
 149		.bpp	= 2,
 150	},
 151	{
 152		.fourcc = V4L2_PIX_FMT_HEXTILE,
 153		.bpp	= 2,
 154	},
 155};
 156
 157#define NUM_FORMATS ARRAY_SIZE(npcm_fmt_list)
 158
 159static const struct v4l2_dv_timings_cap npcm_video_timings_cap = {
 160	.type = V4L2_DV_BT_656_1120,
 161	.bt = {
 162		.min_width = MIN_WIDTH,
 163		.max_width = MAX_WIDTH,
 164		.min_height = MIN_HEIGHT,
 165		.max_height = MAX_HEIGHT,
 166		.min_pixelclock = 6574080, /* 640 x 480 x 24Hz */
 167		.max_pixelclock = 138240000, /* 1920 x 1200 x 60Hz */
 168		.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
 169			     V4L2_DV_BT_STD_CVT | V4L2_DV_BT_STD_GTF,
 170		.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
 171				V4L2_DV_BT_CAP_REDUCED_BLANKING |
 172				V4L2_DV_BT_CAP_CUSTOM,
 173	},
 174};
 175
 176static DECLARE_BITMAP(bitmap, BITMAP_SIZE);
 177
 178static const struct npcm_fmt *npcm_video_find_format(struct v4l2_format *f)
 179{
 180	const struct npcm_fmt *fmt;
 181	unsigned int k;
 182
 183	for (k = 0; k < NUM_FORMATS; k++) {
 184		fmt = &npcm_fmt_list[k];
 185		if (fmt->fourcc == f->fmt.pix.pixelformat)
 186			break;
 187	}
 188
 189	if (k == NUM_FORMATS)
 190		return NULL;
 191
 192	return &npcm_fmt_list[k];
 193}
 194
 195static void npcm_video_ece_prepend_rect_header(void *addr, u16 x, u16 y, u16 w, u16 h)
 196{
 197	__be16 x_pos = cpu_to_be16(x);
 198	__be16 y_pos = cpu_to_be16(y);
 199	__be16 width = cpu_to_be16(w);
 200	__be16 height = cpu_to_be16(h);
 201	__be32 encoding = cpu_to_be32(5); /* Hextile encoding */
 202
 203	memcpy(addr, &x_pos, 2);
 204	memcpy(addr + 2, &y_pos, 2);
 205	memcpy(addr + 4, &width, 2);
 206	memcpy(addr + 6, &height, 2);
 207	memcpy(addr + 8, &encoding, 4);
 208}
 209
 210static unsigned int npcm_video_ece_get_ed_size(struct npcm_video *video,
 211					       unsigned int offset, void *addr)
 212{
 213	struct regmap *ece = video->ece.regmap;
 214	unsigned int size, gap, val;
 215	int ret;
 216
 217	ret = regmap_read_poll_timeout(ece, ECE_DDA_STS, val,
 218				       (val & ECE_DDA_STS_CDREADY), 0,
 219				       ECE_POLL_TIMEOUT_US);
 220
 221	if (ret) {
 222		dev_warn(video->dev, "Wait for ECE_DDA_STS_CDREADY timeout\n");
 223		return 0;
 224	}
 225
 226	size = readl((void __iomem *)addr + offset);
 227	regmap_read(ece, ECE_HEX_CTRL, &val);
 228	gap = FIELD_GET(ECE_HEX_CTRL_ENC_GAP, val);
 229
 230	dev_dbg(video->dev, "offset = %u, ed_size = %u, gap = %u\n", offset,
 231		size, gap);
 232
 233	return size + gap;
 234}
 235
 236static void npcm_video_ece_enc_rect(struct npcm_video *video,
 237				    unsigned int r_off_x, unsigned int r_off_y,
 238				    unsigned int r_w, unsigned int r_h)
 239{
 240	struct regmap *ece = video->ece.regmap;
 241	unsigned int rect_offset = (r_off_y * video->bytesperline) + (r_off_x * 2);
 242	unsigned int w_size = ECE_TILE_W, h_size = ECE_TILE_H;
 243	unsigned int temp, w_tile, h_tile;
 244
 245	regmap_update_bits(ece, ECE_DDA_CTRL, ECE_DDA_CTRL_ECEEN, 0);
 246	regmap_update_bits(ece, ECE_DDA_CTRL, ECE_DDA_CTRL_ECEEN, ECE_DDA_CTRL_ECEEN);
 247	regmap_write(ece, ECE_DDA_STS, ECE_DDA_STS_CDREADY | ECE_DDA_STS_ACDRDY);
 248	regmap_write(ece, ECE_RECT_XY, rect_offset);
 249
 250	w_tile = r_w / ECE_TILE_W;
 251	h_tile = r_h / ECE_TILE_H;
 252
 253	if (r_w % ECE_TILE_W) {
 254		w_tile += 1;
 255		w_size = r_w % ECE_TILE_W;
 256	}
 257	if (r_h % ECE_TILE_H || !h_tile) {
 258		h_tile += 1;
 259		h_size = r_h % ECE_TILE_H;
 260	}
 261
 262	temp = FIELD_PREP(ECE_RECT_DIMEN_WLTR, w_size - 1) |
 263	       FIELD_PREP(ECE_RECT_DIMEN_HLTR, h_size - 1) |
 264	       FIELD_PREP(ECE_RECT_DIMEN_WR, w_tile - 1) |
 265	       FIELD_PREP(ECE_RECT_DIMEN_HR, h_tile - 1);
 266
 267	regmap_write(ece, ECE_RECT_DIMEN, temp);
 268}
 269
 270static unsigned int npcm_video_ece_read_rect_offset(struct npcm_video *video)
 271{
 272	struct regmap *ece = video->ece.regmap;
 273	unsigned int offset;
 274
 275	regmap_read(ece, ECE_HEX_RECT_OFFSET, &offset);
 276	return FIELD_GET(ECE_HEX_RECT_OFFSET_MASK, offset);
 277}
 278
 279/*
 280 * Set the line pitch (in bytes) for the frame buffers.
 281 * Can be on of those values: 512, 1024, 2048, 2560 or 4096 bytes.
 282 */
 283static void npcm_video_ece_set_lp(struct npcm_video *video, unsigned int pitch)
 284{
 285	struct regmap *ece = video->ece.regmap;
 286	unsigned int lp;
 287
 288	switch (pitch) {
 289	case 512:
 290		lp = ECE_RESOL_FB_LP_512;
 291		break;
 292	case 1024:
 293		lp = ECE_RESOL_FB_LP_1024;
 294		break;
 295	case 2048:
 296		lp = ECE_RESOL_FB_LP_2048;
 297		break;
 298	case 2560:
 299		lp = ECE_RESOL_FB_LP_2560;
 300		break;
 301	case 4096:
 302		lp = ECE_RESOL_FB_LP_4096;
 303		break;
 304	default:
 305		return;
 306	}
 307
 308	regmap_write(ece, ECE_RESOL, lp);
 309}
 310
 311static inline void npcm_video_ece_set_fb_addr(struct npcm_video *video,
 312					      unsigned int buffer)
 313{
 314	struct regmap *ece = video->ece.regmap;
 315
 316	regmap_write(ece, ECE_FBR_BA, buffer);
 317}
 318
 319static inline void npcm_video_ece_set_enc_dba(struct npcm_video *video,
 320					      unsigned int addr)
 321{
 322	struct regmap *ece = video->ece.regmap;
 323
 324	regmap_write(ece, ECE_ED_BA, addr);
 325}
 326
 327static inline void npcm_video_ece_clear_rect_offset(struct npcm_video *video)
 328{
 329	struct regmap *ece = video->ece.regmap;
 330
 331	regmap_write(ece, ECE_HEX_RECT_OFFSET, 0);
 332}
 333
 334static void npcm_video_ece_ctrl_reset(struct npcm_video *video)
 335{
 336	struct regmap *ece = video->ece.regmap;
 337
 338	regmap_update_bits(ece, ECE_DDA_CTRL, ECE_DDA_CTRL_ECEEN, 0);
 339	regmap_update_bits(ece, ECE_HEX_CTRL, ECE_HEX_CTRL_ENCDIS, ECE_HEX_CTRL_ENCDIS);
 340	regmap_update_bits(ece, ECE_DDA_CTRL, ECE_DDA_CTRL_ECEEN, ECE_DDA_CTRL_ECEEN);
 341	regmap_update_bits(ece, ECE_HEX_CTRL, ECE_HEX_CTRL_ENCDIS, 0);
 342
 343	npcm_video_ece_clear_rect_offset(video);
 344}
 345
 346static void npcm_video_ece_ip_reset(struct npcm_video *video)
 347{
 348	/*
 349	 * After resetting a module and clearing the reset bit, it should wait
 350	 * at least 10 us before accessing the module.
 351	 */
 352	reset_control_assert(video->ece.reset);
 353	usleep_range(10, 20);
 354	reset_control_deassert(video->ece.reset);
 355	usleep_range(10, 20);
 356}
 357
 358static void npcm_video_ece_stop(struct npcm_video *video)
 359{
 360	struct regmap *ece = video->ece.regmap;
 361
 362	regmap_update_bits(ece, ECE_DDA_CTRL, ECE_DDA_CTRL_ECEEN, 0);
 363	regmap_update_bits(ece, ECE_DDA_CTRL, ECE_DDA_CTRL_INTEN, 0);
 364	regmap_update_bits(ece, ECE_HEX_CTRL, ECE_HEX_CTRL_ENCDIS, ECE_HEX_CTRL_ENCDIS);
 365	npcm_video_ece_clear_rect_offset(video);
 366}
 367
 368static bool npcm_video_alloc_fb(struct npcm_video *video,
 369				struct npcm_video_addr *addr)
 370{
 371	addr->virt = dma_alloc_coherent(video->dev, VCD_FB_SIZE, &addr->dma,
 372					GFP_KERNEL);
 373	if (!addr->virt)
 374		return false;
 375
 376	addr->size = VCD_FB_SIZE;
 377	return true;
 378}
 379
 380static void npcm_video_free_fb(struct npcm_video *video,
 381			       struct npcm_video_addr *addr)
 382{
 383	dma_free_coherent(video->dev, addr->size, addr->virt, addr->dma);
 384	addr->size = 0;
 385	addr->dma = 0ULL;
 386	addr->virt = NULL;
 387}
 388
 389static void npcm_video_free_diff_table(struct npcm_video *video)
 390{
 391	struct list_head *head, *pos, *nx;
 392	struct rect_list *tmp;
 393	unsigned int i;
 394
 395	for (i = 0; i < vb2_get_num_buffers(&video->queue); i++) {
 396		head = &video->list[i];
 397		list_for_each_safe(pos, nx, head) {
 398			tmp = list_entry(pos, struct rect_list, list);
 399			list_del(&tmp->list);
 400			kfree(tmp);
 401		}
 402	}
 403}
 404
 405static unsigned int npcm_video_add_rect(struct npcm_video *video,
 406					unsigned int index,
 407					unsigned int x, unsigned int y,
 408					unsigned int w, unsigned int h)
 409{
 410	struct list_head *head = &video->list[index];
 411	struct rect_list *list = NULL;
 412	struct v4l2_rect *r;
 413
 414	list = kzalloc(sizeof(*list), GFP_KERNEL);
 415	if (!list)
 416		return 0;
 417
 418	r = &list->clip.c;
 419	r->left = x;
 420	r->top = y;
 421	r->width = w;
 422	r->height = h;
 423
 424	list_add_tail(&list->list, head);
 425	return 1;
 426}
 427
 428static void npcm_video_merge_rect(struct npcm_video *video,
 429				  struct rect_list_info *info)
 430{
 431	struct list_head *head = info->head;
 432	struct rect_list *list = info->list, *first = info->first;
 433	struct v4l2_rect *r = &list->clip.c, *f = &first->clip.c;
 434
 435	if (!first) {
 436		first = list;
 437		info->first = first;
 438		list_add_tail(&list->list, head);
 439		video->rect_cnt++;
 440	} else {
 441		if ((r->left == (f->left + f->width)) && r->top == f->top) {
 442			f->width += r->width;
 443			kfree(list);
 444		} else if ((r->top == (f->top + f->height)) &&
 445			   (r->left == f->left)) {
 446			f->height += r->height;
 447			kfree(list);
 448		} else if (((r->top > f->top) &&
 449			   (r->top < (f->top + f->height))) &&
 450			   ((r->left > f->left) &&
 451			   (r->left < (f->left + f->width)))) {
 452			kfree(list);
 453		} else {
 454			list_add_tail(&list->list, head);
 455			video->rect_cnt++;
 456			info->first = list;
 457		}
 458	}
 459}
 460
 461static struct rect_list *npcm_video_new_rect(struct npcm_video *video,
 462					     unsigned int offset,
 463					     unsigned int index)
 464{
 465	struct v4l2_bt_timings *act = &video->active_timings;
 466	struct rect_list *list = NULL;
 467	struct v4l2_rect *r;
 468
 469	list = kzalloc(sizeof(*list), GFP_KERNEL);
 470	if (!list)
 471		return NULL;
 472
 473	r = &list->clip.c;
 474
 475	r->left = (offset << 4);
 476	r->top = (index >> 2);
 477	r->width = RECT_W;
 478	r->height = RECT_H;
 479	if ((r->left + RECT_W) > act->width)
 480		r->width = act->width - r->left;
 481	if ((r->top + RECT_H) > act->height)
 482		r->height = act->height - r->top;
 483
 484	return list;
 485}
 486
 487static int npcm_video_find_rect(struct npcm_video *video,
 488				struct rect_list_info *info,
 489				unsigned int offset)
 490{
 491	if (offset < info->tile_perline) {
 492		info->list = npcm_video_new_rect(video, offset, info->index);
 493		if (!info->list) {
 494			dev_err(video->dev, "Failed to allocate rect_list\n");
 495			return -ENOMEM;
 496		}
 497
 498		npcm_video_merge_rect(video, info);
 499	}
 500	return 0;
 501}
 502
 503static int npcm_video_build_table(struct npcm_video *video,
 504				  struct rect_list_info *info)
 505{
 506	struct regmap *vcd = video->vcd_regmap;
 507	unsigned int j, bit, value;
 508	int ret;
 509
 510	for (j = 0; j < info->offset_perline; j += 4) {
 511		regmap_read(vcd, VCD_DIFF_TBL + (j + info->index), &value);
 512
 513		bitmap_from_arr32(bitmap, &value, BITMAP_SIZE);
 514
 515		for_each_set_bit(bit, bitmap, BITMAP_SIZE) {
 516			ret = npcm_video_find_rect(video, info, bit + (j << 3));
 517			if (ret)
 518				return ret;
 519		}
 520	}
 521	info->index += 64;
 522	return info->tile_perline;
 523}
 524
 525static void npcm_video_get_rect_list(struct npcm_video *video, unsigned int index)
 526{
 527	struct v4l2_bt_timings *act = &video->active_timings;
 528	struct rect_list_info info;
 529	unsigned int tile_cnt = 0, mod;
 530	int ret = 0;
 531
 532	memset(&info, 0, sizeof(struct rect_list_info));
 533	info.head = &video->list[index];
 534
 535	info.tile_perline = act->width >> 4;
 536	mod = act->width % RECT_W;
 537	if (mod != 0)
 538		info.tile_perline += 1;
 539
 540	info.tile_perrow = act->height >> 4;
 541	mod = act->height % RECT_H;
 542	if (mod != 0)
 543		info.tile_perrow += 1;
 544
 545	info.tile_size = info.tile_perrow * info.tile_perline;
 546
 547	info.offset_perline = info.tile_perline >> 5;
 548	mod = info.tile_perline % 32;
 549	if (mod != 0)
 550		info.offset_perline += 1;
 551
 552	info.offset_perline *= 4;
 553
 554	do {
 555		ret = npcm_video_build_table(video, &info);
 556		if (ret < 0)
 557			return;
 558
 559		tile_cnt += ret;
 560	} while (tile_cnt < info.tile_size);
 561}
 562
 563static unsigned int npcm_video_is_mga(struct npcm_video *video)
 564{
 565	struct regmap *gfxi = video->gfx_regmap;
 566	unsigned int dispst;
 567
 568	regmap_read(gfxi, DISPST, &dispst);
 569	return ((dispst & DISPST_MGAMODE) == DISPST_MGAMODE);
 570}
 571
 572static unsigned int npcm_video_hres(struct npcm_video *video)
 573{
 574	struct regmap *gfxi = video->gfx_regmap;
 575	unsigned int hvcnth, hvcntl, apb_hor_res;
 576
 577	regmap_read(gfxi, HVCNTH, &hvcnth);
 578	regmap_read(gfxi, HVCNTL, &hvcntl);
 579	apb_hor_res = (((hvcnth & HVCNTH_MASK) << 8) + (hvcntl & HVCNTL_MASK) + 1);
 580
 581	return (apb_hor_res > MAX_WIDTH) ? MAX_WIDTH : apb_hor_res;
 582}
 583
 584static unsigned int npcm_video_vres(struct npcm_video *video)
 585{
 586	struct regmap *gfxi = video->gfx_regmap;
 587	unsigned int vvcnth, vvcntl, apb_ver_res;
 588
 589	regmap_read(gfxi, VVCNTH, &vvcnth);
 590	regmap_read(gfxi, VVCNTL, &vvcntl);
 591
 592	apb_ver_res = (((vvcnth & VVCNTH_MASK) << 8) + (vvcntl & VVCNTL_MASK));
 593
 594	return (apb_ver_res > MAX_HEIGHT) ? MAX_HEIGHT : apb_ver_res;
 595}
 596
 597static int npcm_video_capres(struct npcm_video *video, unsigned int hor_res,
 598			     unsigned int vert_res)
 599{
 600	struct regmap *vcd = video->vcd_regmap;
 601	unsigned int res, cap_res;
 602
 603	if (hor_res > MAX_WIDTH || vert_res > MAX_HEIGHT)
 604		return -EINVAL;
 605
 606	res = FIELD_PREP(VCD_CAP_RES_VERT_RES, vert_res) |
 607	      FIELD_PREP(VCD_CAP_RES_HOR_RES, hor_res);
 608
 609	regmap_write(vcd, VCD_CAP_RES, res);
 610	regmap_read(vcd, VCD_CAP_RES, &cap_res);
 611
 612	if (cap_res != res)
 613		return -EINVAL;
 614
 615	return 0;
 616}
 617
 618static void npcm_video_vcd_ip_reset(struct npcm_video *video)
 619{
 620	/*
 621	 * After resetting a module and clearing the reset bit, it should wait
 622	 * at least 10 us before accessing the module.
 623	 */
 624	reset_control_assert(video->reset);
 625	usleep_range(10, 20);
 626	reset_control_deassert(video->reset);
 627	usleep_range(10, 20);
 628}
 629
 630static void npcm_video_vcd_state_machine_reset(struct npcm_video *video)
 631{
 632	struct regmap *vcd = video->vcd_regmap;
 633
 634	regmap_update_bits(vcd, VCD_MODE, VCD_MODE_VCDE, 0);
 635	regmap_update_bits(vcd, VCD_MODE, VCD_MODE_IDBC, 0);
 636	regmap_update_bits(vcd, VCD_CMD, VCD_CMD_RST, VCD_CMD_RST);
 637
 638	/*
 639	 * VCD_CMD_RST will reset VCD internal state machines and clear FIFOs,
 640	 * it should wait at least 800 us for the reset operations completed.
 641	 */
 642	usleep_range(800, 1000);
 643
 644	regmap_write(vcd, VCD_STAT, VCD_STAT_CLEAR);
 645	regmap_update_bits(vcd, VCD_MODE, VCD_MODE_VCDE, VCD_MODE_VCDE);
 646	regmap_update_bits(vcd, VCD_MODE, VCD_MODE_IDBC, VCD_MODE_IDBC);
 647}
 648
 649static void npcm_video_gfx_reset(struct npcm_video *video)
 650{
 651	struct regmap *gcr = video->gcr_regmap;
 652
 653	regmap_update_bits(gcr, INTCR2, INTCR2_GIRST2, INTCR2_GIRST2);
 654	npcm_video_vcd_state_machine_reset(video);
 655	regmap_update_bits(gcr, INTCR2, INTCR2_GIRST2, 0);
 656}
 657
 658static void npcm_video_kvm_bw(struct npcm_video *video, bool set_bw)
 659{
 660	struct regmap *vcd = video->vcd_regmap;
 661
 662	if (set_bw || !npcm_video_is_mga(video))
 663		regmap_update_bits(vcd, VCD_MODE, VCD_MODE_KVM_BW_SET,
 664				   VCD_MODE_KVM_BW_SET);
 665	else
 666		regmap_update_bits(vcd, VCD_MODE, VCD_MODE_KVM_BW_SET, 0);
 667}
 668
 669static unsigned int npcm_video_pclk(struct npcm_video *video)
 670{
 671	struct regmap *gfxi = video->gfx_regmap;
 672	unsigned int tmp, pllfbdiv, pllinotdiv, gpllfbdiv;
 673	unsigned int gpllfbdv109, gpllfbdv8, gpllindiv;
 674	unsigned int gpllst_pllotdiv1, gpllst_pllotdiv2;
 675
 676	regmap_read(gfxi, GPLLST, &tmp);
 677	gpllfbdv109 = FIELD_GET(GPLLST_GPLLFBDV109, tmp);
 678	gpllst_pllotdiv1 = FIELD_GET(GPLLST_PLLOTDIV1, tmp);
 679	gpllst_pllotdiv2 = FIELD_GET(GPLLST_PLLOTDIV2, tmp);
 680
 681	regmap_read(gfxi, GPLLINDIV, &tmp);
 682	gpllfbdv8 = FIELD_GET(GPLLINDIV_GPLLFBDV8, tmp);
 683	gpllindiv = FIELD_GET(GPLLINDIV_MASK, tmp);
 684
 685	regmap_read(gfxi, GPLLFBDIV, &tmp);
 686	gpllfbdiv = FIELD_GET(GPLLFBDIV_MASK, tmp);
 687
 688	pllfbdiv = (512 * gpllfbdv109 + 256 * gpllfbdv8 + gpllfbdiv);
 689	pllinotdiv = (gpllindiv * gpllst_pllotdiv1 * gpllst_pllotdiv2);
 690	if (pllfbdiv == 0 || pllinotdiv == 0)
 691		return 0;
 692
 693	return ((pllfbdiv * 25000) / pllinotdiv) * 1000;
 694}
 695
 696static unsigned int npcm_video_get_bpp(struct npcm_video *video)
 697{
 698	const struct npcm_fmt *fmt;
 699	unsigned int k;
 700
 701	for (k = 0; k < NUM_FORMATS; k++) {
 702		fmt = &npcm_fmt_list[k];
 703		if (fmt->fourcc == video->pix_fmt.pixelformat)
 704			break;
 705	}
 706
 707	return fmt->bpp;
 708}
 709
 710/*
 711 * Pitch must be a power of 2, >= linebytes,
 712 * at least 512, and no more than 4096.
 713 */
 714static void npcm_video_set_linepitch(struct npcm_video *video,
 715				     unsigned int linebytes)
 716{
 717	struct regmap *vcd = video->vcd_regmap;
 718	unsigned int pitch = MIN_LP;
 719
 720	while ((pitch < linebytes) && (pitch < MAX_LP))
 721		pitch *= 2;
 722
 723	regmap_write(vcd, VCD_FB_LP, FIELD_PREP(VCD_FBA_LP, pitch) |
 724		     FIELD_PREP(VCD_FBB_LP, pitch));
 725}
 726
 727static unsigned int npcm_video_get_linepitch(struct npcm_video *video)
 728{
 729	struct regmap *vcd = video->vcd_regmap;
 730	unsigned int linepitch;
 731
 732	regmap_read(vcd, VCD_FB_LP, &linepitch);
 733	return FIELD_GET(VCD_FBA_LP, linepitch);
 734}
 735
 736static void npcm_video_command(struct npcm_video *video, unsigned int value)
 737{
 738	struct regmap *vcd = video->vcd_regmap;
 739	unsigned int cmd;
 740
 741	regmap_write(vcd, VCD_STAT, VCD_STAT_CLEAR);
 742	regmap_read(vcd, VCD_CMD, &cmd);
 743	cmd |= FIELD_PREP(VCD_CMD_OPERATION, value);
 744
 745	regmap_write(vcd, VCD_CMD, cmd);
 746	regmap_update_bits(vcd, VCD_CMD, VCD_CMD_GO, VCD_CMD_GO);
 747	video->op_cmd = value;
 748}
 749
 750static void npcm_video_init_reg(struct npcm_video *video)
 751{
 752	struct regmap *gcr = video->gcr_regmap, *vcd = video->vcd_regmap;
 753
 754	/* Selects Data Enable */
 755	regmap_update_bits(gcr, INTCR, INTCR_DEHS, 0);
 756
 757	/* Enable display of KVM GFX and access to memory */
 758	regmap_update_bits(gcr, INTCR, INTCR_GFXIFDIS, 0);
 759
 760	/* Active Vertical/Horizontal Counters Reset */
 761	regmap_update_bits(gcr, INTCR2, INTCR2_GIHCRST | INTCR2_GIVCRST,
 762			   INTCR2_GIHCRST | INTCR2_GIVCRST);
 763
 764	/* Reset video modules */
 765	npcm_video_vcd_ip_reset(video);
 766	npcm_video_gfx_reset(video);
 767
 768	/* Set the FIFO thresholds */
 769	regmap_write(vcd, VCD_FIFO, VCD_FIFO_TH);
 770
 771	/* Set RCHG timer */
 772	regmap_write(vcd, VCD_RCHG, FIELD_PREP(VCD_RCHG_TIM_PRSCL, 0xf) |
 773		     FIELD_PREP(VCD_RCHG_IG_CHG0, 0x3));
 774
 775	/* Set video mode */
 776	regmap_write(vcd, VCD_MODE, VCD_MODE_VCDE | VCD_MODE_CM565 |
 777		     VCD_MODE_IDBC | VCD_MODE_KVM_BW_SET);
 778}
 779
 780static int npcm_video_start_frame(struct npcm_video *video)
 781{
 782	struct npcm_video_buffer *buf;
 783	struct regmap *vcd = video->vcd_regmap;
 784	unsigned int val;
 785	int ret;
 786
 787	if (video->v4l2_input_status) {
 788		dev_dbg(video->dev, "No video signal; skip capture frame\n");
 789		return 0;
 790	}
 791
 792	ret = regmap_read_poll_timeout(vcd, VCD_STAT, val, !(val & VCD_STAT_BUSY),
 793				       1000, VCD_TIMEOUT_US);
 794	if (ret) {
 795		dev_err(video->dev, "Wait for VCD_STAT_BUSY timeout\n");
 796		return -EBUSY;
 797	}
 798
 799	mutex_lock(&video->buffer_lock);
 800	buf = list_first_entry_or_null(&video->buffers,
 801				       struct npcm_video_buffer, link);
 802	if (!buf) {
 803		mutex_unlock(&video->buffer_lock);
 804		dev_dbg(video->dev, "No empty buffers; skip capture frame\n");
 805		return 0;
 806	}
 807
 808	set_bit(VIDEO_CAPTURING, &video->flags);
 809	mutex_unlock(&video->buffer_lock);
 810
 811	npcm_video_vcd_state_machine_reset(video);
 812
 813	regmap_read(vcd, VCD_HOR_AC_TIM, &val);
 814	regmap_update_bits(vcd, VCD_HOR_AC_LST, VCD_HOR_AC_LAST,
 815			   FIELD_GET(VCD_HOR_AC_TIME, val));
 816
 817	regmap_read(vcd, VCD_VER_HI_TIM, &val);
 818	regmap_update_bits(vcd, VCD_VER_HI_LST, VCD_VER_HI_LAST,
 819			   FIELD_GET(VCD_VER_HI_TIME, val));
 820
 821	regmap_update_bits(vcd, VCD_INTE, VCD_INTE_DONE_IE | VCD_INTE_IFOT_IE |
 822			   VCD_INTE_IFOR_IE | VCD_INTE_HAC_IE | VCD_INTE_VHT_IE,
 823			   VCD_INTE_DONE_IE | VCD_INTE_IFOT_IE | VCD_INTE_IFOR_IE |
 824			   VCD_INTE_HAC_IE | VCD_INTE_VHT_IE);
 825
 826	npcm_video_command(video, video->ctrl_cmd);
 827
 828	return 0;
 829}
 830
 831static void npcm_video_bufs_done(struct npcm_video *video,
 832				 enum vb2_buffer_state state)
 833{
 834	struct npcm_video_buffer *buf;
 835
 836	mutex_lock(&video->buffer_lock);
 837	list_for_each_entry(buf, &video->buffers, link)
 838		vb2_buffer_done(&buf->vb.vb2_buf, state);
 839
 840	INIT_LIST_HEAD(&video->buffers);
 841	mutex_unlock(&video->buffer_lock);
 842}
 843
 844static void npcm_video_get_diff_rect(struct npcm_video *video, unsigned int index)
 845{
 846	unsigned int width = video->active_timings.width;
 847	unsigned int height = video->active_timings.height;
 848
 849	if (video->op_cmd != VCD_CMD_OPERATION_CAPTURE) {
 850		video->rect_cnt = 0;
 851		npcm_video_get_rect_list(video, index);
 852		video->rect[index] = video->rect_cnt;
 853	} else {
 854		video->rect[index] = npcm_video_add_rect(video, index, 0, 0,
 855							 width, height);
 856	}
 857}
 858
 859static void npcm_video_detect_resolution(struct npcm_video *video)
 860{
 861	struct v4l2_bt_timings *act = &video->active_timings;
 862	struct v4l2_bt_timings *det = &video->detected_timings;
 863	struct regmap *gfxi = video->gfx_regmap;
 864	unsigned int dispst;
 865
 866	det->width = npcm_video_hres(video);
 867	det->height = npcm_video_vres(video);
 868
 869	if (act->width != det->width || act->height != det->height) {
 870		dev_dbg(video->dev, "Resolution changed\n");
 871
 872		if (npcm_video_hres(video) > 0 && npcm_video_vres(video) > 0) {
 873			if (test_bit(VIDEO_STREAMING, &video->flags)) {
 874				/*
 875				 * Wait for resolution is available,
 876				 * and it is also captured by host.
 877				 */
 878				do {
 879					mdelay(100);
 880					regmap_read(gfxi, DISPST, &dispst);
 881				} while (npcm_video_vres(video) < 100 ||
 882					 npcm_video_pclk(video) == 0 ||
 883					 (dispst & DISPST_HSCROFF));
 884			}
 885
 886			det->width = npcm_video_hres(video);
 887			det->height = npcm_video_vres(video);
 888			det->pixelclock = npcm_video_pclk(video);
 889		}
 890
 891		clear_bit(VIDEO_RES_CHANGING, &video->flags);
 892	}
 893
 894	if (det->width && det->height) {
 895		video->v4l2_input_status = 0;
 896		dev_dbg(video->dev, "Got resolution[%dx%d] -> [%dx%d], status %d\n",
 897			act->width, act->height, det->width, det->height,
 898			video->v4l2_input_status);
 899	} else {
 900		video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL;
 901		dev_err(video->dev, "Got invalid resolution[%dx%d]\n", det->width,
 902			det->height);
 903	}
 904}
 905
 906static int npcm_video_set_resolution(struct npcm_video *video,
 907				     struct v4l2_bt_timings *timing)
 908{
 909	struct regmap *vcd = video->vcd_regmap;
 910	unsigned int mode;
 911
 912	if (npcm_video_capres(video, timing->width, timing->height)) {
 913		dev_err(video->dev, "Failed to set VCD_CAP_RES\n");
 914		return -EINVAL;
 915	}
 916
 917	video->active_timings = *timing;
 918	video->bytesperpixel = npcm_video_get_bpp(video);
 919	npcm_video_set_linepitch(video, timing->width * video->bytesperpixel);
 920	video->bytesperline = npcm_video_get_linepitch(video);
 921	video->pix_fmt.width = timing->width ? timing->width : MIN_WIDTH;
 922	video->pix_fmt.height = timing->height ? timing->height : MIN_HEIGHT;
 923	video->pix_fmt.sizeimage = video->pix_fmt.width * video->pix_fmt.height *
 924				   video->bytesperpixel;
 925	video->pix_fmt.bytesperline = video->bytesperline;
 926
 927	npcm_video_kvm_bw(video, timing->pixelclock > VCD_KVM_BW_PCLK);
 928	npcm_video_gfx_reset(video);
 929	regmap_read(vcd, VCD_MODE, &mode);
 930
 931	dev_dbg(video->dev, "VCD mode = 0x%x, %s mode\n", mode,
 932		npcm_video_is_mga(video) ? "Hi Res" : "VGA");
 933
 934	dev_dbg(video->dev,
 935		"Digital mode: %d x %d x %d, pixelclock %lld, bytesperline %d\n",
 936		timing->width, timing->height, video->bytesperpixel,
 937		timing->pixelclock, video->bytesperline);
 938
 939	return 0;
 940}
 941
 942static void npcm_video_start(struct npcm_video *video)
 943{
 944	npcm_video_init_reg(video);
 945
 946	if (!npcm_video_alloc_fb(video, &video->src)) {
 947		dev_err(video->dev, "Failed to allocate VCD frame buffer\n");
 948		return;
 949	}
 950
 951	npcm_video_detect_resolution(video);
 952	if (npcm_video_set_resolution(video, &video->detected_timings)) {
 953		dev_err(video->dev, "Failed to set resolution\n");
 954		return;
 955	}
 956
 957	/* Set frame buffer physical address */
 958	regmap_write(video->vcd_regmap, VCD_FBA_ADR, video->src.dma);
 959	regmap_write(video->vcd_regmap, VCD_FBB_ADR, video->src.dma);
 960
 961	if (video->ece.enable && atomic_inc_return(&video->ece.clients) == 1) {
 962		npcm_video_ece_ip_reset(video);
 963		npcm_video_ece_ctrl_reset(video);
 964		npcm_video_ece_set_fb_addr(video, video->src.dma);
 965		npcm_video_ece_set_lp(video, video->bytesperline);
 966
 967		dev_dbg(video->dev, "ECE open: client %d\n",
 968			atomic_read(&video->ece.clients));
 969	}
 970}
 971
 972static void npcm_video_stop(struct npcm_video *video)
 973{
 974	struct regmap *vcd = video->vcd_regmap;
 975
 976	set_bit(VIDEO_STOPPED, &video->flags);
 977
 978	regmap_write(vcd, VCD_INTE, 0);
 979	regmap_write(vcd, VCD_MODE, 0);
 980	regmap_write(vcd, VCD_RCHG, 0);
 981	regmap_write(vcd, VCD_STAT, VCD_STAT_CLEAR);
 982
 983	if (video->src.size)
 984		npcm_video_free_fb(video, &video->src);
 985
 986	npcm_video_free_diff_table(video);
 987	video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL;
 988	video->flags = 0;
 989	video->ctrl_cmd = VCD_CMD_OPERATION_CAPTURE;
 990
 991	if (video->ece.enable && atomic_dec_return(&video->ece.clients) == 0) {
 992		npcm_video_ece_stop(video);
 993		dev_dbg(video->dev, "ECE close: client %d\n",
 994			atomic_read(&video->ece.clients));
 995	}
 996}
 997
 998static unsigned int npcm_video_raw(struct npcm_video *video, int index, void *addr)
 999{
1000	unsigned int width = video->active_timings.width;
1001	unsigned int height = video->active_timings.height;
1002	unsigned int i, len, offset, bytes = 0;
1003
1004	video->rect[index] = npcm_video_add_rect(video, index, 0, 0, width, height);
1005
1006	for (i = 0; i < height; i++) {
1007		len = width * video->bytesperpixel;
1008		offset = i * video->bytesperline;
1009
1010		memcpy(addr + bytes, video->src.virt + offset, len);
1011		bytes += len;
1012	}
1013
1014	return bytes;
1015}
1016
1017static unsigned int npcm_video_hextile(struct npcm_video *video, unsigned int index,
1018				       unsigned int dma_addr, void *vaddr)
1019{
1020	struct rect_list *rect_list;
1021	struct v4l2_rect *rect;
1022	unsigned int offset, len, bytes = 0;
1023
1024	npcm_video_ece_ctrl_reset(video);
1025	npcm_video_ece_clear_rect_offset(video);
1026	npcm_video_ece_set_fb_addr(video, video->src.dma);
1027
1028	/* Set base address of encoded data to video buffer */
1029	npcm_video_ece_set_enc_dba(video, dma_addr);
1030
1031	npcm_video_ece_set_lp(video, video->bytesperline);
1032	npcm_video_get_diff_rect(video, index);
1033
1034	list_for_each_entry(rect_list, &video->list[index], list) {
1035		rect = &rect_list->clip.c;
1036		offset = npcm_video_ece_read_rect_offset(video);
1037		npcm_video_ece_enc_rect(video, rect->left, rect->top,
1038					rect->width, rect->height);
1039
1040		len = npcm_video_ece_get_ed_size(video, offset, vaddr);
1041		npcm_video_ece_prepend_rect_header(vaddr + offset,
1042						   rect->left, rect->top,
1043						   rect->width, rect->height);
1044		bytes += len;
1045	}
1046
1047	return bytes;
1048}
1049
1050static irqreturn_t npcm_video_irq(int irq, void *arg)
1051{
1052	struct npcm_video *video = arg;
1053	struct regmap *vcd = video->vcd_regmap;
1054	struct npcm_video_buffer *buf;
1055	unsigned int index, size, status, fmt;
1056	dma_addr_t dma_addr;
1057	void *addr;
1058	static const struct v4l2_event ev = {
1059		.type = V4L2_EVENT_SOURCE_CHANGE,
1060		.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
1061	};
1062
1063	regmap_read(vcd, VCD_STAT, &status);
1064	dev_dbg(video->dev, "VCD irq status 0x%x\n", status);
1065
1066	regmap_write(vcd, VCD_STAT, VCD_STAT_CLEAR);
1067
1068	if (test_bit(VIDEO_STOPPED, &video->flags) ||
1069	    !test_bit(VIDEO_STREAMING, &video->flags))
1070		return IRQ_NONE;
1071
1072	if (status & VCD_STAT_DONE) {
1073		regmap_write(vcd, VCD_INTE, 0);
1074		mutex_lock(&video->buffer_lock);
1075		clear_bit(VIDEO_CAPTURING, &video->flags);
1076		buf = list_first_entry_or_null(&video->buffers,
1077					       struct npcm_video_buffer, link);
1078		if (!buf) {
1079			mutex_unlock(&video->buffer_lock);
1080			return IRQ_NONE;
1081		}
1082
1083		addr = vb2_plane_vaddr(&buf->vb.vb2_buf, 0);
1084		index = buf->vb.vb2_buf.index;
1085		fmt = video->pix_fmt.pixelformat;
1086
1087		switch (fmt) {
1088		case V4L2_PIX_FMT_RGB565:
1089			size = npcm_video_raw(video, index, addr);
1090			break;
1091		case V4L2_PIX_FMT_HEXTILE:
1092			dma_addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
1093			size = npcm_video_hextile(video, index, dma_addr, addr);
1094			break;
1095		default:
1096			mutex_unlock(&video->buffer_lock);
1097			return IRQ_NONE;
1098		}
1099
1100		vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);
1101		buf->vb.vb2_buf.timestamp = ktime_get_ns();
1102		buf->vb.sequence = video->sequence++;
1103		buf->vb.field = V4L2_FIELD_NONE;
1104
1105		vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
1106		list_del(&buf->link);
1107		mutex_unlock(&video->buffer_lock);
1108
1109		if (npcm_video_start_frame(video))
1110			dev_err(video->dev, "Failed to capture next frame\n");
1111	}
1112
1113	/* Resolution changed */
1114	if (status & VCD_STAT_VHT_CHG || status & VCD_STAT_HAC_CHG) {
1115		if (!test_bit(VIDEO_RES_CHANGING, &video->flags)) {
1116			set_bit(VIDEO_RES_CHANGING, &video->flags);
1117
1118			vb2_queue_error(&video->queue);
1119			v4l2_event_queue(&video->vdev, &ev);
1120		}
1121	}
1122
1123	if (status & VCD_STAT_IFOR || status & VCD_STAT_IFOT) {
1124		dev_warn(video->dev, "VCD FIFO overrun or over thresholds\n");
1125		if (npcm_video_start_frame(video))
1126			dev_err(video->dev, "Failed to recover from FIFO overrun\n");
1127	}
1128
1129	return IRQ_HANDLED;
1130}
1131
1132static int npcm_video_querycap(struct file *file, void *fh,
1133			       struct v4l2_capability *cap)
1134{
1135	strscpy(cap->driver, DEVICE_NAME, sizeof(cap->driver));
1136	strscpy(cap->card, "NPCM Video Engine", sizeof(cap->card));
1137
1138	return 0;
1139}
1140
1141static int npcm_video_enum_format(struct file *file, void *fh,
1142				  struct v4l2_fmtdesc *f)
1143{
1144	struct npcm_video *video = video_drvdata(file);
1145	const struct npcm_fmt *fmt;
1146
1147	if (f->index >= NUM_FORMATS)
1148		return -EINVAL;
1149
1150	fmt = &npcm_fmt_list[f->index];
1151	if (fmt->fourcc == V4L2_PIX_FMT_HEXTILE && !video->ece.enable)
1152		return -EINVAL;
1153
1154	f->pixelformat = fmt->fourcc;
1155	return 0;
1156}
1157
1158static int npcm_video_try_format(struct file *file, void *fh,
1159				 struct v4l2_format *f)
1160{
1161	struct npcm_video *video = video_drvdata(file);
1162	const struct npcm_fmt *fmt;
1163
1164	fmt = npcm_video_find_format(f);
1165
1166	/* If format not found or HEXTILE not supported, use RGB565 as default */
1167	if (!fmt || (fmt->fourcc == V4L2_PIX_FMT_HEXTILE && !video->ece.enable))
1168		f->fmt.pix.pixelformat = npcm_fmt_list[0].fourcc;
1169
1170	f->fmt.pix.field = V4L2_FIELD_NONE;
1171	f->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB;
1172	f->fmt.pix.quantization = V4L2_QUANTIZATION_FULL_RANGE;
1173	f->fmt.pix.width = video->pix_fmt.width;
1174	f->fmt.pix.height = video->pix_fmt.height;
1175	f->fmt.pix.bytesperline = video->bytesperline;
1176	f->fmt.pix.sizeimage = video->pix_fmt.sizeimage;
1177
1178	return 0;
1179}
1180
1181static int npcm_video_get_format(struct file *file, void *fh,
1182				 struct v4l2_format *f)
1183{
1184	struct npcm_video *video = video_drvdata(file);
1185
1186	f->fmt.pix = video->pix_fmt;
1187	return 0;
1188}
1189
1190static int npcm_video_set_format(struct file *file, void *fh,
1191				 struct v4l2_format *f)
1192{
1193	struct npcm_video *video = video_drvdata(file);
1194	int ret;
1195
1196	ret = npcm_video_try_format(file, fh, f);
1197	if (ret)
1198		return ret;
1199
1200	if (vb2_is_busy(&video->queue)) {
1201		dev_err(video->dev, "%s device busy\n", __func__);
1202		return -EBUSY;
1203	}
1204
1205	video->pix_fmt.pixelformat = f->fmt.pix.pixelformat;
1206	return 0;
1207}
1208
1209static int npcm_video_enum_input(struct file *file, void *fh,
1210				 struct v4l2_input *inp)
1211{
1212	struct npcm_video *video = video_drvdata(file);
1213
1214	if (inp->index)
1215		return -EINVAL;
1216
1217	strscpy(inp->name, "Host VGA capture", sizeof(inp->name));
1218	inp->type = V4L2_INPUT_TYPE_CAMERA;
1219	inp->capabilities = V4L2_IN_CAP_DV_TIMINGS;
1220	inp->status = video->v4l2_input_status;
1221
1222	return 0;
1223}
1224
1225static int npcm_video_get_input(struct file *file, void *fh, unsigned int *i)
1226{
1227	*i = 0;
1228
1229	return 0;
1230}
1231
1232static int npcm_video_set_input(struct file *file, void *fh, unsigned int i)
1233{
1234	if (i)
1235		return -EINVAL;
1236
1237	return 0;
1238}
1239
1240static int npcm_video_set_dv_timings(struct file *file, void *fh,
1241				     struct v4l2_dv_timings *timings)
1242{
1243	struct npcm_video *video = video_drvdata(file);
1244	int rc;
1245
1246	if (timings->bt.width == video->active_timings.width &&
1247	    timings->bt.height == video->active_timings.height)
1248		return 0;
1249
1250	if (vb2_is_busy(&video->queue)) {
1251		dev_err(video->dev, "%s device busy\n", __func__);
1252		return -EBUSY;
1253	}
1254
1255	rc = npcm_video_set_resolution(video, &timings->bt);
1256	if (rc)
1257		return rc;
1258
1259	timings->type = V4L2_DV_BT_656_1120;
1260
1261	return 0;
1262}
1263
1264static int npcm_video_get_dv_timings(struct file *file, void *fh,
1265				     struct v4l2_dv_timings *timings)
1266{
1267	struct npcm_video *video = video_drvdata(file);
1268
1269	timings->type = V4L2_DV_BT_656_1120;
1270	timings->bt = video->active_timings;
1271
1272	return 0;
1273}
1274
1275static int npcm_video_query_dv_timings(struct file *file, void *fh,
1276				       struct v4l2_dv_timings *timings)
1277{
1278	struct npcm_video *video = video_drvdata(file);
1279
1280	npcm_video_detect_resolution(video);
1281	timings->type = V4L2_DV_BT_656_1120;
1282	timings->bt = video->detected_timings;
1283
1284	return video->v4l2_input_status ? -ENOLINK : 0;
1285}
1286
1287static int npcm_video_enum_dv_timings(struct file *file, void *fh,
1288				      struct v4l2_enum_dv_timings *timings)
1289{
1290	return v4l2_enum_dv_timings_cap(timings, &npcm_video_timings_cap,
1291					NULL, NULL);
1292}
1293
1294static int npcm_video_dv_timings_cap(struct file *file, void *fh,
1295				     struct v4l2_dv_timings_cap *cap)
1296{
1297	*cap = npcm_video_timings_cap;
1298
1299	return 0;
1300}
1301
1302static int npcm_video_sub_event(struct v4l2_fh *fh,
1303				const struct v4l2_event_subscription *sub)
1304{
1305	switch (sub->type) {
1306	case V4L2_EVENT_SOURCE_CHANGE:
1307		return v4l2_src_change_event_subscribe(fh, sub);
1308	}
1309
1310	return v4l2_ctrl_subscribe_event(fh, sub);
1311}
1312
1313static const struct v4l2_ioctl_ops npcm_video_ioctls = {
1314	.vidioc_querycap = npcm_video_querycap,
1315
1316	.vidioc_enum_fmt_vid_cap = npcm_video_enum_format,
1317	.vidioc_g_fmt_vid_cap = npcm_video_get_format,
1318	.vidioc_s_fmt_vid_cap = npcm_video_set_format,
1319	.vidioc_try_fmt_vid_cap = npcm_video_try_format,
1320
1321	.vidioc_reqbufs = vb2_ioctl_reqbufs,
1322	.vidioc_querybuf = vb2_ioctl_querybuf,
1323	.vidioc_qbuf = vb2_ioctl_qbuf,
1324	.vidioc_expbuf = vb2_ioctl_expbuf,
1325	.vidioc_dqbuf = vb2_ioctl_dqbuf,
1326	.vidioc_create_bufs = vb2_ioctl_create_bufs,
1327	.vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1328	.vidioc_streamon = vb2_ioctl_streamon,
1329	.vidioc_streamoff = vb2_ioctl_streamoff,
1330
1331	.vidioc_enum_input = npcm_video_enum_input,
1332	.vidioc_g_input = npcm_video_get_input,
1333	.vidioc_s_input = npcm_video_set_input,
1334
1335	.vidioc_s_dv_timings = npcm_video_set_dv_timings,
1336	.vidioc_g_dv_timings = npcm_video_get_dv_timings,
1337	.vidioc_query_dv_timings = npcm_video_query_dv_timings,
1338	.vidioc_enum_dv_timings = npcm_video_enum_dv_timings,
1339	.vidioc_dv_timings_cap = npcm_video_dv_timings_cap,
1340
1341	.vidioc_subscribe_event = npcm_video_sub_event,
1342	.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1343};
1344
1345static int npcm_video_set_ctrl(struct v4l2_ctrl *ctrl)
1346{
1347	struct npcm_video *video = container_of(ctrl->handler, struct npcm_video,
1348						ctrl_handler);
1349
1350	switch (ctrl->id) {
1351	case V4L2_CID_NPCM_CAPTURE_MODE:
1352		if (ctrl->val == V4L2_NPCM_CAPTURE_MODE_COMPLETE)
1353			video->ctrl_cmd = VCD_CMD_OPERATION_CAPTURE;
1354		else if (ctrl->val == V4L2_NPCM_CAPTURE_MODE_DIFF)
1355			video->ctrl_cmd = VCD_CMD_OPERATION_COMPARE;
1356		break;
1357	default:
1358		return -EINVAL;
1359	}
1360
1361	return 0;
1362}
1363
1364static const struct v4l2_ctrl_ops npcm_video_ctrl_ops = {
1365	.s_ctrl = npcm_video_set_ctrl,
1366};
1367
1368static const char * const npcm_ctrl_capture_mode_menu[] = {
1369	"COMPLETE",
1370	"DIFF",
1371	NULL,
1372};
1373
1374static const struct v4l2_ctrl_config npcm_ctrl_capture_mode = {
1375	.ops = &npcm_video_ctrl_ops,
1376	.id = V4L2_CID_NPCM_CAPTURE_MODE,
1377	.name = "NPCM Video Capture Mode",
1378	.type = V4L2_CTRL_TYPE_MENU,
1379	.min = 0,
1380	.max = V4L2_NPCM_CAPTURE_MODE_DIFF,
1381	.def = 0,
1382	.qmenu = npcm_ctrl_capture_mode_menu,
1383};
1384
1385/*
1386 * This control value is set when a buffer is dequeued by userspace, i.e. in
1387 * npcm_video_buf_finish function.
1388 */
1389static const struct v4l2_ctrl_config npcm_ctrl_rect_count = {
1390	.id = V4L2_CID_NPCM_RECT_COUNT,
1391	.name = "NPCM Hextile Rectangle Count",
1392	.type = V4L2_CTRL_TYPE_INTEGER,
1393	.min = 0,
1394	.max = (MAX_WIDTH / RECT_W) * (MAX_HEIGHT / RECT_H),
1395	.step = 1,
1396	.def = 0,
1397};
1398
1399static int npcm_video_open(struct file *file)
1400{
1401	struct npcm_video *video = video_drvdata(file);
1402	int rc;
1403
1404	mutex_lock(&video->video_lock);
1405	rc = v4l2_fh_open(file);
1406	if (rc) {
1407		mutex_unlock(&video->video_lock);
1408		return rc;
1409	}
1410
1411	if (v4l2_fh_is_singular_file(file))
1412		npcm_video_start(video);
1413
1414	mutex_unlock(&video->video_lock);
1415	return 0;
1416}
1417
1418static int npcm_video_release(struct file *file)
1419{
1420	struct npcm_video *video = video_drvdata(file);
1421	int rc;
1422
1423	mutex_lock(&video->video_lock);
1424	if (v4l2_fh_is_singular_file(file))
1425		npcm_video_stop(video);
1426
1427	rc = _vb2_fop_release(file, NULL);
1428
1429	mutex_unlock(&video->video_lock);
1430	return rc;
1431}
1432
1433static const struct v4l2_file_operations npcm_video_v4l2_fops = {
1434	.owner = THIS_MODULE,
1435	.read = vb2_fop_read,
1436	.poll = vb2_fop_poll,
1437	.unlocked_ioctl = video_ioctl2,
1438	.mmap = vb2_fop_mmap,
1439	.open = npcm_video_open,
1440	.release = npcm_video_release,
1441};
1442
1443static int npcm_video_queue_setup(struct vb2_queue *q, unsigned int *num_buffers,
1444				  unsigned int *num_planes, unsigned int sizes[],
1445				  struct device *alloc_devs[])
1446{
1447	struct npcm_video *video = vb2_get_drv_priv(q);
1448	unsigned int i;
1449
1450	if (*num_planes) {
1451		if (sizes[0] < video->pix_fmt.sizeimage)
1452			return -EINVAL;
1453
1454		return 0;
1455	}
1456
1457	*num_planes = 1;
1458	sizes[0] = video->pix_fmt.sizeimage;
1459
1460	for (i = 0; i < VIDEO_MAX_FRAME; i++)
1461		INIT_LIST_HEAD(&video->list[i]);
1462
1463	return 0;
1464}
1465
1466static int npcm_video_buf_prepare(struct vb2_buffer *vb)
1467{
1468	struct npcm_video *video = vb2_get_drv_priv(vb->vb2_queue);
1469
1470	if (vb2_plane_size(vb, 0) < video->pix_fmt.sizeimage)
1471		return -EINVAL;
1472
1473	return 0;
1474}
1475
1476static int npcm_video_start_streaming(struct vb2_queue *q, unsigned int count)
1477{
1478	struct npcm_video *video = vb2_get_drv_priv(q);
1479	int rc;
1480
1481	video->sequence = 0;
1482	rc = npcm_video_start_frame(video);
1483	if (rc) {
1484		npcm_video_bufs_done(video, VB2_BUF_STATE_QUEUED);
1485		return rc;
1486	}
1487
1488	set_bit(VIDEO_STREAMING, &video->flags);
1489	return 0;
1490}
1491
1492static void npcm_video_stop_streaming(struct vb2_queue *q)
1493{
1494	struct npcm_video *video = vb2_get_drv_priv(q);
1495	struct regmap *vcd = video->vcd_regmap;
1496
1497	clear_bit(VIDEO_STREAMING, &video->flags);
1498	regmap_write(vcd, VCD_INTE, 0);
1499	regmap_write(vcd, VCD_STAT, VCD_STAT_CLEAR);
1500	npcm_video_gfx_reset(video);
1501	npcm_video_bufs_done(video, VB2_BUF_STATE_ERROR);
1502	video->ctrl_cmd = VCD_CMD_OPERATION_CAPTURE;
1503	v4l2_ctrl_s_ctrl(video->rect_cnt_ctrl, 0);
1504}
1505
1506static void npcm_video_buf_queue(struct vb2_buffer *vb)
1507{
1508	struct npcm_video *video = vb2_get_drv_priv(vb->vb2_queue);
1509	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1510	struct npcm_video_buffer *nvb = to_npcm_video_buffer(vbuf);
1511	bool empty;
1512
1513	mutex_lock(&video->buffer_lock);
1514	empty = list_empty(&video->buffers);
1515	list_add_tail(&nvb->link, &video->buffers);
1516	mutex_unlock(&video->buffer_lock);
1517
1518	if (test_bit(VIDEO_STREAMING, &video->flags) &&
1519	    !test_bit(VIDEO_CAPTURING, &video->flags) && empty) {
1520		if (npcm_video_start_frame(video))
1521			dev_err(video->dev, "Failed to capture next frame\n");
1522	}
1523}
1524
1525static void npcm_video_buf_finish(struct vb2_buffer *vb)
1526{
1527	struct npcm_video *video = vb2_get_drv_priv(vb->vb2_queue);
1528	struct list_head *head, *pos, *nx;
1529	struct rect_list *tmp;
1530
1531	/*
1532	 * This callback is called when the buffer is dequeued, so update
1533	 * V4L2_CID_NPCM_RECT_COUNT control value with the number of rectangles
1534	 * in this buffer and free associated rect_list.
1535	 */
1536	if (test_bit(VIDEO_STREAMING, &video->flags)) {
1537		v4l2_ctrl_s_ctrl(video->rect_cnt_ctrl, video->rect[vb->index]);
1538
1539		head = &video->list[vb->index];
1540		list_for_each_safe(pos, nx, head) {
1541			tmp = list_entry(pos, struct rect_list, list);
1542			list_del(&tmp->list);
1543			kfree(tmp);
1544		}
1545	}
1546}
1547
1548static const struct regmap_config npcm_video_regmap_cfg = {
1549	.reg_bits	= 32,
1550	.reg_stride	= 4,
1551	.val_bits	= 32,
1552	.max_register	= VCD_FIFO,
1553};
1554
1555static const struct regmap_config npcm_video_ece_regmap_cfg = {
1556	.reg_bits	= 32,
1557	.reg_stride	= 4,
1558	.val_bits	= 32,
1559	.max_register	= ECE_HEX_RECT_OFFSET,
1560};
1561
1562static const struct vb2_ops npcm_video_vb2_ops = {
1563	.queue_setup = npcm_video_queue_setup,
1564	.buf_prepare = npcm_video_buf_prepare,
1565	.buf_finish = npcm_video_buf_finish,
1566	.start_streaming = npcm_video_start_streaming,
1567	.stop_streaming = npcm_video_stop_streaming,
1568	.buf_queue =  npcm_video_buf_queue,
1569};
1570
1571static int npcm_video_setup_video(struct npcm_video *video)
1572{
1573	struct v4l2_device *v4l2_dev = &video->v4l2_dev;
1574	struct video_device *vdev = &video->vdev;
1575	struct vb2_queue *vbq = &video->queue;
1576	int rc;
1577
1578	if (video->ece.enable)
1579		video->pix_fmt.pixelformat = V4L2_PIX_FMT_HEXTILE;
1580	else
1581		video->pix_fmt.pixelformat = V4L2_PIX_FMT_RGB565;
1582
1583	video->pix_fmt.field = V4L2_FIELD_NONE;
1584	video->pix_fmt.colorspace = V4L2_COLORSPACE_SRGB;
1585	video->pix_fmt.quantization = V4L2_QUANTIZATION_FULL_RANGE;
1586	video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL;
1587
1588	rc = v4l2_device_register(video->dev, v4l2_dev);
1589	if (rc) {
1590		dev_err(video->dev, "Failed to register v4l2 device\n");
1591		return rc;
1592	}
1593
1594	v4l2_ctrl_handler_init(&video->ctrl_handler, 2);
1595	v4l2_ctrl_new_custom(&video->ctrl_handler, &npcm_ctrl_capture_mode, NULL);
1596	video->rect_cnt_ctrl = v4l2_ctrl_new_custom(&video->ctrl_handler,
1597						    &npcm_ctrl_rect_count, NULL);
1598	if (video->ctrl_handler.error) {
1599		dev_err(video->dev, "Failed to init controls: %d\n",
1600			video->ctrl_handler.error);
1601
1602		rc = video->ctrl_handler.error;
1603		goto rel_ctrl_handler;
1604	}
1605	v4l2_dev->ctrl_handler = &video->ctrl_handler;
1606
1607	vbq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1608	vbq->io_modes = VB2_MMAP | VB2_DMABUF;
1609	vbq->dev = v4l2_dev->dev;
1610	vbq->lock = &video->video_lock;
1611	vbq->ops = &npcm_video_vb2_ops;
1612	vbq->mem_ops = &vb2_dma_contig_memops;
1613	vbq->drv_priv = video;
1614	vbq->buf_struct_size = sizeof(struct npcm_video_buffer);
1615	vbq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1616	vbq->min_queued_buffers = 3;
1617
1618	rc = vb2_queue_init(vbq);
1619	if (rc) {
1620		dev_err(video->dev, "Failed to init vb2 queue\n");
1621		goto rel_ctrl_handler;
1622	}
1623	vdev->queue = vbq;
1624	vdev->fops = &npcm_video_v4l2_fops;
1625	vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1626	vdev->v4l2_dev = v4l2_dev;
1627	strscpy(vdev->name, DEVICE_NAME, sizeof(vdev->name));
1628	vdev->vfl_type = VFL_TYPE_VIDEO;
1629	vdev->vfl_dir = VFL_DIR_RX;
1630	vdev->release = video_device_release_empty;
1631	vdev->ioctl_ops = &npcm_video_ioctls;
1632	vdev->lock = &video->video_lock;
1633
1634	video_set_drvdata(vdev, video);
1635	rc = video_register_device(vdev, VFL_TYPE_VIDEO, 0);
1636	if (rc) {
1637		dev_err(video->dev, "Failed to register video device\n");
1638		goto rel_vb_queue;
1639	}
1640
1641	return 0;
1642
1643rel_vb_queue:
1644	vb2_queue_release(vbq);
1645rel_ctrl_handler:
1646	v4l2_ctrl_handler_free(&video->ctrl_handler);
1647	v4l2_device_unregister(v4l2_dev);
1648
1649	return rc;
1650}
1651
1652static int npcm_video_ece_init(struct npcm_video *video)
1653{
1654	struct device_node *ece_node __free(device_node) = NULL;
1655	struct device *dev = video->dev;
1656	struct platform_device *ece_pdev;
1657	void __iomem *regs;
1658
1659	ece_node = of_parse_phandle(video->dev->of_node, "nuvoton,ece", 0);
1660	if (!ece_node) {
1661		dev_err(dev, "Failed to get ECE phandle in DTS\n");
1662		return -ENODEV;
1663	}
1664
1665	video->ece.enable = of_device_is_available(ece_node);
1666
1667	if (video->ece.enable) {
1668		dev_info(dev, "Support HEXTILE pixel format\n");
1669
1670		ece_pdev = of_find_device_by_node(ece_node);
1671		if (!ece_pdev) {
1672			dev_err(dev, "Failed to find ECE device\n");
1673			return -ENODEV;
1674		}
1675		struct device *ece_dev __free(put_device) = &ece_pdev->dev;
1676
1677		regs = devm_platform_ioremap_resource(ece_pdev, 0);
1678		if (IS_ERR(regs)) {
1679			dev_err(dev, "Failed to parse ECE reg in DTS\n");
1680			return PTR_ERR(regs);
1681		}
1682
1683		video->ece.regmap = devm_regmap_init_mmio(dev, regs,
1684							  &npcm_video_ece_regmap_cfg);
1685		if (IS_ERR(video->ece.regmap)) {
1686			dev_err(dev, "Failed to initialize ECE regmap\n");
1687			return PTR_ERR(video->ece.regmap);
1688		}
1689
1690		video->ece.reset = devm_reset_control_get(ece_dev, NULL);
1691		if (IS_ERR(video->ece.reset)) {
1692			dev_err(dev, "Failed to get ECE reset control in DTS\n");
1693			return PTR_ERR(video->ece.reset);
1694		}
1695	}
1696
1697	return 0;
1698}
1699
1700static int npcm_video_init(struct npcm_video *video)
1701{
1702	struct device *dev = video->dev;
1703	int irq, rc;
1704
1705	irq = irq_of_parse_and_map(dev->of_node, 0);
1706	if (!irq) {
1707		dev_err(dev, "Failed to find VCD IRQ\n");
1708		return -ENODEV;
1709	}
1710
1711	rc = devm_request_threaded_irq(dev, irq, NULL, npcm_video_irq,
1712				       IRQF_ONESHOT, DEVICE_NAME, video);
1713	if (rc < 0) {
1714		dev_err(dev, "Failed to request IRQ %d\n", irq);
1715		return rc;
1716	}
1717
1718	of_reserved_mem_device_init(dev);
1719	rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
1720	if (rc) {
1721		dev_err(dev, "Failed to set DMA mask\n");
1722		of_reserved_mem_device_release(dev);
1723	}
1724
1725	rc = npcm_video_ece_init(video);
1726	if (rc) {
1727		dev_err(dev, "Failed to initialize ECE\n");
1728		return rc;
1729	}
1730
1731	return 0;
1732}
1733
1734static int npcm_video_probe(struct platform_device *pdev)
1735{
1736	struct npcm_video *video = kzalloc(sizeof(*video), GFP_KERNEL);
1737	int rc;
1738	void __iomem *regs;
1739
1740	if (!video)
1741		return -ENOMEM;
1742
1743	video->dev = &pdev->dev;
1744	mutex_init(&video->video_lock);
1745	mutex_init(&video->buffer_lock);
1746	INIT_LIST_HEAD(&video->buffers);
1747
1748	regs = devm_platform_ioremap_resource(pdev, 0);
1749	if (IS_ERR(regs)) {
1750		dev_err(&pdev->dev, "Failed to parse VCD reg in DTS\n");
1751		return PTR_ERR(regs);
1752	}
1753
1754	video->vcd_regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1755						  &npcm_video_regmap_cfg);
1756	if (IS_ERR(video->vcd_regmap)) {
1757		dev_err(&pdev->dev, "Failed to initialize VCD regmap\n");
1758		return PTR_ERR(video->vcd_regmap);
1759	}
1760
1761	video->reset = devm_reset_control_get(&pdev->dev, NULL);
1762	if (IS_ERR(video->reset)) {
1763		dev_err(&pdev->dev, "Failed to get VCD reset control in DTS\n");
1764		return PTR_ERR(video->reset);
1765	}
1766
1767	video->gcr_regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1768							    "nuvoton,sysgcr");
1769	if (IS_ERR(video->gcr_regmap))
1770		return PTR_ERR(video->gcr_regmap);
1771
1772	video->gfx_regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1773							    "nuvoton,sysgfxi");
1774	if (IS_ERR(video->gfx_regmap))
1775		return PTR_ERR(video->gfx_regmap);
1776
1777	rc = npcm_video_init(video);
1778	if (rc)
1779		return rc;
1780
1781	rc = npcm_video_setup_video(video);
1782	if (rc)
1783		return rc;
1784
1785	dev_info(video->dev, "NPCM video driver probed\n");
1786	return 0;
1787}
1788
1789static void npcm_video_remove(struct platform_device *pdev)
1790{
1791	struct device *dev = &pdev->dev;
1792	struct v4l2_device *v4l2_dev = dev_get_drvdata(dev);
1793	struct npcm_video *video = to_npcm_video(v4l2_dev);
1794
1795	video_unregister_device(&video->vdev);
1796	vb2_queue_release(&video->queue);
1797	v4l2_ctrl_handler_free(&video->ctrl_handler);
1798	v4l2_device_unregister(v4l2_dev);
1799	if (video->ece.enable)
1800		npcm_video_ece_stop(video);
1801	of_reserved_mem_device_release(dev);
1802}
1803
1804static const struct of_device_id npcm_video_match[] = {
1805	{ .compatible = "nuvoton,npcm750-vcd" },
1806	{ .compatible = "nuvoton,npcm845-vcd" },
1807	{},
1808};
1809
1810MODULE_DEVICE_TABLE(of, npcm_video_match);
1811
1812static struct platform_driver npcm_video_driver = {
1813	.driver = {
1814		.name = DEVICE_NAME,
1815		.of_match_table = npcm_video_match,
1816	},
1817	.probe = npcm_video_probe,
1818	.remove = npcm_video_remove,
1819};
1820
1821module_platform_driver(npcm_video_driver);
1822
1823MODULE_AUTHOR("Joseph Liu <kwliu@nuvoton.com>");
1824MODULE_AUTHOR("Marvin Lin <kflin@nuvoton.com>");
1825MODULE_DESCRIPTION("Driver for Nuvoton NPCM Video Capture/Encode Engine");
1826MODULE_LICENSE("GPL v2");