mtk_vcodec_dec_stateless.c

  1// SPDX-License-Identifier: GPL-2.0
  2
  3#include <media/videobuf2-v4l2.h>
  4#include <media/videobuf2-dma-contig.h>
  5#include <media/v4l2-event.h>
  6#include <media/v4l2-mem2mem.h>
  7#include <linux/module.h>
  8
  9#include "mtk_vcodec_dec.h"
 10#include "mtk_vcodec_dec_pm.h"
 11#include "vdec_drv_if.h"
 12
 13/**
 14 * struct mtk_stateless_control  - CID control type
 15 * @cfg: control configuration
 16 * @codec_type: codec type (V4L2 pixel format) for CID control type
 17 */
 18struct mtk_stateless_control {
 19	struct v4l2_ctrl_config cfg;
 20	int codec_type;
 21};
 22
 23static const struct mtk_stateless_control mtk_stateless_controls[] = {
 24	{
 25		.cfg = {
 26			.id = V4L2_CID_STATELESS_H264_SPS,
 27		},
 28		.codec_type = V4L2_PIX_FMT_H264_SLICE,
 29	},
 30	{
 31		.cfg = {
 32			.id = V4L2_CID_STATELESS_H264_PPS,
 33		},
 34		.codec_type = V4L2_PIX_FMT_H264_SLICE,
 35	},
 36	{
 37		.cfg = {
 38			.id = V4L2_CID_STATELESS_H264_SCALING_MATRIX,
 39		},
 40		.codec_type = V4L2_PIX_FMT_H264_SLICE,
 41	},
 42	{
 43		.cfg = {
 44			.id = V4L2_CID_STATELESS_H264_DECODE_PARAMS,
 45		},
 46		.codec_type = V4L2_PIX_FMT_H264_SLICE,
 47	},
 48	{
 49		.cfg = {
 50			.id = V4L2_CID_MPEG_VIDEO_H264_PROFILE,
 51			.def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN,
 52			.max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
 53			.menu_skip_mask =
 54				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
 55				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED),
 56		},
 57		.codec_type = V4L2_PIX_FMT_H264_SLICE,
 58	},
 59	{
 60		.cfg = {
 61			.id = V4L2_CID_MPEG_VIDEO_H264_LEVEL,
 62			.min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
 63			.def = V4L2_MPEG_VIDEO_H264_LEVEL_4_1,
 64			.max = V4L2_MPEG_VIDEO_H264_LEVEL_4_2,
 65		},
 66		.codec_type = V4L2_PIX_FMT_H264_SLICE,
 67	},
 68	{
 69		.cfg = {
 70			.id = V4L2_CID_STATELESS_H264_DECODE_MODE,
 71			.min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
 72			.def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
 73			.max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
 74		},
 75		.codec_type = V4L2_PIX_FMT_H264_SLICE,
 76	},
 77	{
 78		.cfg = {
 79			.id = V4L2_CID_STATELESS_H264_START_CODE,
 80			.min = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
 81			.def = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
 82			.max = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
 83		},
 84		.codec_type = V4L2_PIX_FMT_H264_SLICE,
 85	},
 86	{
 87		.cfg = {
 88			.id = V4L2_CID_STATELESS_VP8_FRAME,
 89		},
 90		.codec_type = V4L2_PIX_FMT_VP8_FRAME,
 91	},
 92	{
 93		.cfg = {
 94			.id = V4L2_CID_MPEG_VIDEO_VP8_PROFILE,
 95			.min = V4L2_MPEG_VIDEO_VP8_PROFILE_0,
 96			.def = V4L2_MPEG_VIDEO_VP8_PROFILE_0,
 97			.max = V4L2_MPEG_VIDEO_VP8_PROFILE_3,
 98		},
 99		.codec_type = V4L2_PIX_FMT_VP8_FRAME,
100	},
101	{
102		.cfg = {
103			.id = V4L2_CID_STATELESS_VP9_FRAME,
104		},
105		.codec_type = V4L2_PIX_FMT_VP9_FRAME,
106	},
107	{
108		.cfg = {
109			.id = V4L2_CID_MPEG_VIDEO_VP9_PROFILE,
110			.min = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
111			.def = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
112			.max = V4L2_MPEG_VIDEO_VP9_PROFILE_2,
113			.menu_skip_mask = BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_1),
114		},
115		.codec_type = V4L2_PIX_FMT_VP9_FRAME,
116	},
117	{
118		.cfg = {
119			.id = V4L2_CID_MPEG_VIDEO_VP9_LEVEL,
120			.min = V4L2_MPEG_VIDEO_VP9_LEVEL_1_0,
121			.def = V4L2_MPEG_VIDEO_VP9_LEVEL_4_0,
122			.max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_1,
123		},
124		.codec_type = V4L2_PIX_FMT_VP9_FRAME,
125	},
126	{
127		.cfg = {
128			.id = V4L2_CID_STATELESS_HEVC_SPS,
129		},
130		.codec_type = V4L2_PIX_FMT_HEVC_SLICE,
131	},
132	{
133		.cfg = {
134			.id = V4L2_CID_STATELESS_HEVC_PPS,
135		},
136		.codec_type = V4L2_PIX_FMT_HEVC_SLICE,
137	},
138	{
139		.cfg = {
140			.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
141		},
142		.codec_type = V4L2_PIX_FMT_HEVC_SLICE,
143	},
144	{
145		.cfg = {
146			.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
147		},
148		.codec_type = V4L2_PIX_FMT_HEVC_SLICE,
149	},
150	{
151		.cfg = {
152			.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
153			.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
154			.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
155		},
156		.codec_type = V4L2_PIX_FMT_HEVC_SLICE,
157	},
158	{
159		.cfg = {
160			.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
161			.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
162			.def = V4L2_MPEG_VIDEO_HEVC_LEVEL_4,
163			.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1,
164		},
165		.codec_type = V4L2_PIX_FMT_HEVC_SLICE,
166	},
167
168	{
169		.cfg = {
170			.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,
171			.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
172			.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
173			.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
174		},
175		.codec_type = V4L2_PIX_FMT_HEVC_SLICE,
176	},
177	{
178		.cfg = {
179			.id = V4L2_CID_STATELESS_HEVC_START_CODE,
180			.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
181			.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
182			.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
183		},
184		.codec_type = V4L2_PIX_FMT_HEVC_SLICE,
185	},
186	{
187		.cfg = {
188			.id = V4L2_CID_STATELESS_AV1_SEQUENCE,
189
190		},
191		.codec_type = V4L2_PIX_FMT_AV1_FRAME,
192	},
193	{
194		.cfg = {
195			.id = V4L2_CID_STATELESS_AV1_FRAME,
196
197		},
198		.codec_type = V4L2_PIX_FMT_AV1_FRAME,
199	},
200	{
201		.cfg = {
202			.id = V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY,
203			.dims = { V4L2_AV1_MAX_TILE_COUNT },
204
205		},
206		.codec_type = V4L2_PIX_FMT_AV1_FRAME,
207	},
208	{
209		.cfg = {
210			.id = V4L2_CID_MPEG_VIDEO_AV1_PROFILE,
211			.min = V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN,
212			.def = V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN,
213			.max = V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN,
214		},
215		.codec_type = V4L2_PIX_FMT_AV1_FRAME,
216	},
217	{
218		.cfg = {
219			.id = V4L2_CID_MPEG_VIDEO_AV1_LEVEL,
220			.min = V4L2_MPEG_VIDEO_AV1_LEVEL_2_0,
221			.def = V4L2_MPEG_VIDEO_AV1_LEVEL_4_0,
222			.max = V4L2_MPEG_VIDEO_AV1_LEVEL_5_1,
223		},
224		.codec_type = V4L2_PIX_FMT_AV1_FRAME,
225	},
226};
227
228#define NUM_CTRLS ARRAY_SIZE(mtk_stateless_controls)
229
230static struct mtk_video_fmt mtk_video_formats[9];
231
232static struct mtk_video_fmt default_out_format;
233static struct mtk_video_fmt default_cap_format;
234static unsigned int num_formats;
235
236static const struct v4l2_frmsize_stepwise stepwise_fhd = {
237	.min_width = MTK_VDEC_MIN_W,
238	.max_width = MTK_VDEC_MAX_W,
239	.step_width = 16,
240	.min_height = MTK_VDEC_MIN_H,
241	.max_height = MTK_VDEC_MAX_H,
242	.step_height = 16
243};
244
245static void mtk_vdec_stateless_cap_to_disp(struct mtk_vcodec_dec_ctx *ctx, int error,
246					   struct media_request *src_buf_req)
247{
248	struct vb2_v4l2_buffer *vb2_dst;
249	enum vb2_buffer_state state;
250
251	if (error)
252		state = VB2_BUF_STATE_ERROR;
253	else
254		state = VB2_BUF_STATE_DONE;
255
256	vb2_dst = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
257	if (vb2_dst) {
258		v4l2_m2m_buf_done(vb2_dst, state);
259		mtk_v4l2_vdec_dbg(2, ctx, "free frame buffer id:%d to done list",
260				  vb2_dst->vb2_buf.index);
261	} else {
262		mtk_v4l2_vdec_err(ctx, "dst buffer is NULL");
263	}
264
265	if (src_buf_req)
266		v4l2_ctrl_request_complete(src_buf_req, &ctx->ctrl_hdl);
267}
268
269static struct vdec_fb *vdec_get_cap_buffer(struct mtk_vcodec_dec_ctx *ctx)
270{
271	struct mtk_video_dec_buf *framebuf;
272	struct vb2_v4l2_buffer *vb2_v4l2;
273	struct vb2_buffer *dst_buf;
274	struct vdec_fb *pfb;
275
276	vb2_v4l2 = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
277	if (!vb2_v4l2) {
278		mtk_v4l2_vdec_dbg(1, ctx, "[%d] dst_buf empty!!", ctx->id);
279		return NULL;
280	}
281
282	dst_buf = &vb2_v4l2->vb2_buf;
283	framebuf = container_of(vb2_v4l2, struct mtk_video_dec_buf, m2m_buf.vb);
284
285	pfb = &framebuf->frame_buffer;
286	pfb->base_y.va = vb2_plane_vaddr(dst_buf, 0);
287	pfb->base_y.dma_addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
288	pfb->base_y.size = ctx->q_data[MTK_Q_DATA_DST].sizeimage[0];
289
290	if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 2) {
291		pfb->base_c.va = vb2_plane_vaddr(dst_buf, 1);
292		pfb->base_c.dma_addr =
293			vb2_dma_contig_plane_dma_addr(dst_buf, 1);
294		pfb->base_c.size = ctx->q_data[MTK_Q_DATA_DST].sizeimage[1];
295	}
296	mtk_v4l2_vdec_dbg(1, ctx,
297			  "id=%d Framebuf pfb=%p VA=%p Y/C_DMA=%pad_%pad Sz=%zx frame_count = %d",
298			  dst_buf->index, pfb, pfb->base_y.va, &pfb->base_y.dma_addr,
299			  &pfb->base_c.dma_addr, pfb->base_y.size, ctx->decoded_frame_cnt);
300
301	return pfb;
302}
303
304static void vb2ops_vdec_buf_request_complete(struct vb2_buffer *vb)
305{
306	struct mtk_vcodec_dec_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
307
308	v4l2_ctrl_request_complete(vb->req_obj.req, &ctx->ctrl_hdl);
309}
310
311static void mtk_vdec_worker(struct work_struct *work)
312{
313	struct mtk_vcodec_dec_ctx *ctx =
314		container_of(work, struct mtk_vcodec_dec_ctx, decode_work);
315	struct mtk_vcodec_dec_dev *dev = ctx->dev;
316	struct vb2_v4l2_buffer *vb2_v4l2_src;
317	struct vb2_buffer *vb2_src;
318	struct mtk_vcodec_mem *bs_src;
319	struct mtk_video_dec_buf *dec_buf_src;
320	struct media_request *src_buf_req;
321	enum vb2_buffer_state state;
322	bool res_chg = false;
323	int ret;
324
325	vb2_v4l2_src = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
326	if (!vb2_v4l2_src) {
327		v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx);
328		mtk_v4l2_vdec_dbg(1, ctx, "[%d] no available source buffer", ctx->id);
329		return;
330	}
331
332	vb2_src = &vb2_v4l2_src->vb2_buf;
333	dec_buf_src = container_of(vb2_v4l2_src, struct mtk_video_dec_buf,
334				   m2m_buf.vb);
335	bs_src = &dec_buf_src->bs_buffer;
336
337	mtk_v4l2_vdec_dbg(3, ctx, "[%d] (%d) id=%d, vb=%p", ctx->id,
338			  vb2_src->vb2_queue->type, vb2_src->index, vb2_src);
339
340	bs_src->va = vb2_plane_vaddr(vb2_src, 0);
341	bs_src->dma_addr = vb2_dma_contig_plane_dma_addr(vb2_src, 0);
342	bs_src->size = (size_t)vb2_src->planes[0].bytesused;
343	if (!bs_src->va) {
344		v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx);
345		mtk_v4l2_vdec_err(ctx, "[%d] id=%d source buffer is NULL", ctx->id,
346				  vb2_src->index);
347		return;
348	}
349
350	mtk_v4l2_vdec_dbg(3, ctx, "[%d] Bitstream VA=%p DMA=%pad Size=%zx vb=%p",
351			  ctx->id, bs_src->va, &bs_src->dma_addr, bs_src->size, vb2_src);
352	/* Apply request controls. */
353	src_buf_req = vb2_src->req_obj.req;
354	if (src_buf_req)
355		v4l2_ctrl_request_setup(src_buf_req, &ctx->ctrl_hdl);
356	else
357		mtk_v4l2_vdec_err(ctx, "vb2 buffer media request is NULL");
358
359	ret = vdec_if_decode(ctx, bs_src, NULL, &res_chg);
360	if (ret && ret != -EAGAIN) {
361		mtk_v4l2_vdec_err(ctx,
362				  "[%d] decode src_buf[%d] sz=0x%zx pts=%llu ret=%d res_chg=%d",
363				  ctx->id, vb2_src->index, bs_src->size,
364				  vb2_src->timestamp, ret, res_chg);
365		if (ret == -EIO) {
366			mutex_lock(&ctx->lock);
367			dec_buf_src->error = true;
368			mutex_unlock(&ctx->lock);
369		}
370	}
371
372	state = ret ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE;
373	if (!IS_VDEC_LAT_ARCH(dev->vdec_pdata->hw_arch) ||
374	    ctx->current_codec == V4L2_PIX_FMT_VP8_FRAME) {
375		v4l2_m2m_buf_done_and_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx, state);
376		if (src_buf_req)
377			v4l2_ctrl_request_complete(src_buf_req, &ctx->ctrl_hdl);
378	} else {
379		if (ret != -EAGAIN) {
380			v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
381			v4l2_m2m_buf_done(vb2_v4l2_src, state);
382		}
383		v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx);
384	}
385}
386
387static void vb2ops_vdec_stateless_buf_queue(struct vb2_buffer *vb)
388{
389	struct mtk_vcodec_dec_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
390	struct vb2_v4l2_buffer *vb2_v4l2 = to_vb2_v4l2_buffer(vb);
391
392	mtk_v4l2_vdec_dbg(3, ctx, "[%d] (%d) id=%d, vb=%p", ctx->id, vb->vb2_queue->type,
393			  vb->index, vb);
394
395	mutex_lock(&ctx->lock);
396	v4l2_m2m_buf_queue(ctx->m2m_ctx, vb2_v4l2);
397	mutex_unlock(&ctx->lock);
398	if (vb->vb2_queue->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
399		return;
400
401	/* If an OUTPUT buffer, we may need to update the state */
402	if (ctx->state == MTK_STATE_INIT) {
403		ctx->state = MTK_STATE_HEADER;
404		mtk_v4l2_vdec_dbg(1, ctx, "Init driver from init to header.");
405	} else {
406		mtk_v4l2_vdec_dbg(3, ctx, "[%d] already init driver %d", ctx->id, ctx->state);
407	}
408}
409
410static int mtk_vdec_flush_decoder(struct mtk_vcodec_dec_ctx *ctx)
411{
412	bool res_chg;
413
414	return vdec_if_decode(ctx, NULL, NULL, &res_chg);
415}
416
417static int mtk_vcodec_get_pic_info(struct mtk_vcodec_dec_ctx *ctx)
418{
419	struct mtk_q_data *q_data;
420	int ret = 0;
421
422	q_data = &ctx->q_data[MTK_Q_DATA_DST];
423	if (q_data->fmt->num_planes == 1) {
424		mtk_v4l2_vdec_err(ctx, "[%d]Error!! 10bit mode not support one plane", ctx->id);
425		return -EINVAL;
426	}
427
428	ctx->capture_fourcc = q_data->fmt->fourcc;
429	ret = vdec_if_get_param(ctx, GET_PARAM_PIC_INFO, &ctx->picinfo);
430	if (ret) {
431		mtk_v4l2_vdec_err(ctx, "[%d]Error!! Get GET_PARAM_PICTURE_INFO Fail", ctx->id);
432		return ret;
433	}
434
435	ctx->last_decoded_picinfo = ctx->picinfo;
436
437	q_data->sizeimage[0] = ctx->picinfo.fb_sz[0];
438	q_data->bytesperline[0] = ctx->picinfo.buf_w * 5 / 4;
439
440	q_data->sizeimage[1] = ctx->picinfo.fb_sz[1];
441	q_data->bytesperline[1] = ctx->picinfo.buf_w * 5 / 4;
442
443	q_data->coded_width = ctx->picinfo.buf_w;
444	q_data->coded_height = ctx->picinfo.buf_h;
445	mtk_v4l2_vdec_dbg(1, ctx, "[%d] wxh=%dx%d pic wxh=%dx%d sz[0]=0x%x sz[1]=0x%x",
446			  ctx->id, ctx->picinfo.buf_w, ctx->picinfo.buf_h,
447			  ctx->picinfo.pic_w, ctx->picinfo.pic_h,
448			  q_data->sizeimage[0], q_data->sizeimage[1]);
449
450	return ret;
451}
452
453static int mtk_vdec_s_ctrl(struct v4l2_ctrl *ctrl)
454{
455	struct mtk_vcodec_dec_ctx *ctx = ctrl_to_dec_ctx(ctrl);
456	struct v4l2_ctrl_h264_sps *h264;
457	struct v4l2_ctrl_hevc_sps *h265;
458	struct v4l2_ctrl_vp9_frame *frame;
459	struct v4l2_ctrl_av1_sequence *seq;
460	struct v4l2_ctrl *hdr_ctrl;
461	const struct mtk_vcodec_dec_pdata *dec_pdata = ctx->dev->vdec_pdata;
462	const struct mtk_video_fmt *fmt;
463	int i = 0, ret = 0;
464
465	hdr_ctrl = ctrl;
466	if (!hdr_ctrl || !hdr_ctrl->p_new.p)
467		return -EINVAL;
468
469	switch (hdr_ctrl->id) {
470	case V4L2_CID_STATELESS_H264_SPS:
471		h264 = (struct v4l2_ctrl_h264_sps *)hdr_ctrl->p_new.p;
472
473		if (h264->bit_depth_chroma_minus8 == 2 && h264->bit_depth_luma_minus8 == 2) {
474			ctx->is_10bit_bitstream = true;
475		} else if (h264->bit_depth_chroma_minus8 != 0 &&
476			   h264->bit_depth_luma_minus8 != 0) {
477			mtk_v4l2_vdec_err(ctx, "H264: chroma_minus8:%d, luma_minus8:%d",
478					  h264->bit_depth_chroma_minus8,
479					  h264->bit_depth_luma_minus8);
480			return -EINVAL;
481		}
482		break;
483	case V4L2_CID_STATELESS_HEVC_SPS:
484		h265 = (struct v4l2_ctrl_hevc_sps *)hdr_ctrl->p_new.p;
485
486		if (h265->bit_depth_chroma_minus8 == 2 && h265->bit_depth_luma_minus8 == 2) {
487			ctx->is_10bit_bitstream = true;
488		} else if (h265->bit_depth_chroma_minus8 != 0 &&
489			   h265->bit_depth_luma_minus8 != 0) {
490			mtk_v4l2_vdec_err(ctx, "HEVC: chroma_minus8:%d, luma_minus8:%d",
491					  h265->bit_depth_chroma_minus8,
492					  h265->bit_depth_luma_minus8);
493			return -EINVAL;
494		}
495		break;
496	case V4L2_CID_STATELESS_VP9_FRAME:
497		frame = (struct v4l2_ctrl_vp9_frame *)hdr_ctrl->p_new.p;
498
499		if (frame->bit_depth == 10) {
500			ctx->is_10bit_bitstream = true;
501		} else if (frame->bit_depth != 8) {
502			mtk_v4l2_vdec_err(ctx, "VP9: bit_depth:%d", frame->bit_depth);
503			return -EINVAL;
504		}
505
506		if (!(frame->flags & V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING) ||
507		    !(frame->flags & V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING)) {
508			mtk_v4l2_vdec_err(ctx, "VP9: only 420 subsampling is supported");
509			return -EINVAL;
510		}
511		break;
512	case V4L2_CID_STATELESS_AV1_SEQUENCE:
513		seq = (struct v4l2_ctrl_av1_sequence *)hdr_ctrl->p_new.p;
514
515		if (seq->bit_depth == 10) {
516			ctx->is_10bit_bitstream = true;
517		} else if (seq->bit_depth != 8) {
518			mtk_v4l2_vdec_err(ctx, "AV1: bit_depth:%d", seq->bit_depth);
519			return -EINVAL;
520		}
521		break;
522	default:
523		mtk_v4l2_vdec_dbg(3, ctx, "Not supported to set ctrl id: 0x%x\n", hdr_ctrl->id);
524		return ret;
525	}
526
527	if (!ctx->is_10bit_bitstream)
528		return ret;
529
530	for (i = 0; i < *dec_pdata->num_formats; i++) {
531		fmt = &dec_pdata->vdec_formats[i];
532		if (fmt->fourcc == V4L2_PIX_FMT_MT2110R &&
533		    hdr_ctrl->id == V4L2_CID_STATELESS_H264_SPS) {
534			ctx->q_data[MTK_Q_DATA_DST].fmt = fmt;
535			break;
536		}
537
538		if (fmt->fourcc == V4L2_PIX_FMT_MT2110T &&
539		    (hdr_ctrl->id == V4L2_CID_STATELESS_HEVC_SPS ||
540		    hdr_ctrl->id == V4L2_CID_STATELESS_VP9_FRAME ||
541		    hdr_ctrl->id == V4L2_CID_STATELESS_AV1_SEQUENCE)) {
542			ctx->q_data[MTK_Q_DATA_DST].fmt = fmt;
543			break;
544		}
545	}
546	ret = mtk_vcodec_get_pic_info(ctx);
547
548	return ret;
549}
550
551static const struct v4l2_ctrl_ops mtk_vcodec_dec_ctrl_ops = {
552	.s_ctrl = mtk_vdec_s_ctrl,
553};
554
555static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg,
556					   struct mtk_vcodec_dec_ctx *ctx)
557{
558	switch (ctx->dev->chip_name) {
559	case MTK_VDEC_MT8192:
560	case MTK_VDEC_MT8188:
561		cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_5_2;
562		break;
563	case MTK_VDEC_MT8195:
564		cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_6_0;
565		break;
566	case MTK_VDEC_MT8183:
567	case MTK_VDEC_MT8186:
568		cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_4_2;
569		break;
570	default:
571		cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_4_1;
572		break;
573	}
574}
575
576static void mtk_vcodec_dec_fill_h264_profile(struct v4l2_ctrl_config *cfg,
577					     struct mtk_vcodec_dec_ctx *ctx)
578{
579	switch (ctx->dev->chip_name) {
580	case MTK_VDEC_MT8188:
581	case MTK_VDEC_MT8195:
582		cfg->max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10;
583		break;
584	default:
585		cfg->max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH;
586		break;
587	}
588}
589
590static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg,
591					   struct mtk_vcodec_dec_ctx *ctx)
592{
593	switch (ctx->dev->chip_name) {
594	case MTK_VDEC_MT8188:
595		cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1;
596		break;
597	case MTK_VDEC_MT8195:
598		cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2;
599		break;
600	default:
601		cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4;
602		break;
603	}
604}
605
606static void mtk_vcodec_dec_fill_h265_profile(struct v4l2_ctrl_config *cfg,
607					     struct mtk_vcodec_dec_ctx *ctx)
608{
609	switch (ctx->dev->chip_name) {
610	case MTK_VDEC_MT8188:
611	case MTK_VDEC_MT8195:
612		cfg->max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10;
613		break;
614	default:
615		cfg->max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE;
616		break;
617	}
618}
619
620static void mtk_vcodec_dec_fill_vp9_level(struct v4l2_ctrl_config *cfg,
621					  struct mtk_vcodec_dec_ctx *ctx)
622{
623	switch (ctx->dev->chip_name) {
624	case MTK_VDEC_MT8192:
625	case MTK_VDEC_MT8188:
626		cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_1;
627		break;
628	case MTK_VDEC_MT8195:
629		cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_2;
630		break;
631	case MTK_VDEC_MT8186:
632		cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_1;
633		break;
634	default:
635		cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_0;
636		break;
637	}
638}
639
640static void mtk_vcodec_dec_fill_vp9_profile(struct v4l2_ctrl_config *cfg,
641					    struct mtk_vcodec_dec_ctx *ctx)
642{
643	switch (ctx->dev->chip_name) {
644	case MTK_VDEC_MT8188:
645	case MTK_VDEC_MT8195:
646		cfg->max = V4L2_MPEG_VIDEO_VP9_PROFILE_2;
647		break;
648	default:
649		cfg->max = V4L2_MPEG_VIDEO_VP9_PROFILE_1;
650		break;
651	}
652}
653
654static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg,
655					  struct mtk_vcodec_dec_ctx *ctx)
656{
657	switch (cfg->id) {
658	case V4L2_CID_MPEG_VIDEO_H264_LEVEL:
659		mtk_vcodec_dec_fill_h264_level(cfg, ctx);
660		mtk_v4l2_vdec_dbg(3, ctx, "h264 supported level: %lld %lld", cfg->max, cfg->def);
661		break;
662	case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL:
663		mtk_vcodec_dec_fill_h265_level(cfg, ctx);
664		mtk_v4l2_vdec_dbg(3, ctx, "h265 supported level: %lld %lld", cfg->max, cfg->def);
665		break;
666	case V4L2_CID_MPEG_VIDEO_VP9_LEVEL:
667		mtk_vcodec_dec_fill_vp9_level(cfg, ctx);
668		mtk_v4l2_vdec_dbg(3, ctx, "vp9 supported level: %lld %lld", cfg->max, cfg->def);
669		break;
670	case V4L2_CID_MPEG_VIDEO_H264_PROFILE:
671		mtk_vcodec_dec_fill_h264_profile(cfg, ctx);
672		mtk_v4l2_vdec_dbg(3, ctx, "h264 supported profile: %lld %lld", cfg->max,
673				  cfg->menu_skip_mask);
674		break;
675	case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE:
676		mtk_vcodec_dec_fill_h265_profile(cfg, ctx);
677		mtk_v4l2_vdec_dbg(3, ctx, "h265 supported profile: %lld %lld", cfg->max,
678				  cfg->menu_skip_mask);
679		break;
680	case V4L2_CID_MPEG_VIDEO_VP9_PROFILE:
681		mtk_vcodec_dec_fill_vp9_profile(cfg, ctx);
682		mtk_v4l2_vdec_dbg(3, ctx, "vp9 supported profile: %lld %lld", cfg->max,
683				  cfg->menu_skip_mask);
684		break;
685	default:
686		break;
687	}
688}
689
690static int mtk_vcodec_dec_ctrls_setup(struct mtk_vcodec_dec_ctx *ctx)
691{
692	unsigned int i;
693
694	v4l2_ctrl_handler_init(&ctx->ctrl_hdl, NUM_CTRLS);
695	if (ctx->ctrl_hdl.error) {
696		mtk_v4l2_vdec_err(ctx, "v4l2_ctrl_handler_init failed\n");
697		return ctx->ctrl_hdl.error;
698	}
699
700	for (i = 0; i < NUM_CTRLS; i++) {
701		struct v4l2_ctrl_config cfg = mtk_stateless_controls[i].cfg;
702		cfg.ops = &mtk_vcodec_dec_ctrl_ops;
703
704		mtk_vcodec_dec_reset_controls(&cfg, ctx);
705		v4l2_ctrl_new_custom(&ctx->ctrl_hdl, &cfg, NULL);
706		if (ctx->ctrl_hdl.error) {
707			mtk_v4l2_vdec_err(ctx, "Adding control %d failed %d", i,
708					  ctx->ctrl_hdl.error);
709			return ctx->ctrl_hdl.error;
710		}
711	}
712
713	v4l2_ctrl_handler_setup(&ctx->ctrl_hdl);
714
715	return 0;
716}
717
718static int fops_media_request_validate(struct media_request *mreq)
719{
720	const unsigned int buffer_cnt = vb2_request_buffer_cnt(mreq);
721
722	switch (buffer_cnt) {
723	case 1:
724		/* We expect exactly one buffer with the request */
725		break;
726	case 0:
727		pr_debug(MTK_DBG_VCODEC_STR "No buffer provided with the request.");
728		return -ENOENT;
729	default:
730		pr_debug(MTK_DBG_VCODEC_STR "Too many buffers (%d) provided with the request.",
731			 buffer_cnt);
732		return -EINVAL;
733	}
734
735	return vb2_request_validate(mreq);
736}
737
738const struct media_device_ops mtk_vcodec_media_ops = {
739	.req_validate	= fops_media_request_validate,
740	.req_queue	= v4l2_m2m_request_queue,
741};
742
743static void mtk_vcodec_add_formats(unsigned int fourcc,
744				   struct mtk_vcodec_dec_ctx *ctx)
745{
746	struct mtk_vcodec_dec_dev *dev = ctx->dev;
747	const struct mtk_vcodec_dec_pdata *pdata = dev->vdec_pdata;
748	int count_formats = *pdata->num_formats;
749
750	switch (fourcc) {
751	case V4L2_PIX_FMT_H264_SLICE:
752	case V4L2_PIX_FMT_VP8_FRAME:
753	case V4L2_PIX_FMT_VP9_FRAME:
754	case V4L2_PIX_FMT_HEVC_SLICE:
755	case V4L2_PIX_FMT_AV1_FRAME:
756		mtk_video_formats[count_formats].fourcc = fourcc;
757		mtk_video_formats[count_formats].type = MTK_FMT_DEC;
758		mtk_video_formats[count_formats].num_planes = 1;
759		mtk_video_formats[count_formats].frmsize = stepwise_fhd;
760
761		if (!(ctx->dev->dec_capability & VCODEC_CAPABILITY_4K_DISABLED) &&
762		    fourcc != V4L2_PIX_FMT_VP8_FRAME) {
763			mtk_video_formats[count_formats].frmsize.max_width =
764				VCODEC_DEC_4K_CODED_WIDTH;
765			mtk_video_formats[count_formats].frmsize.max_height =
766				VCODEC_DEC_4K_CODED_HEIGHT;
767		}
768		break;
769	case V4L2_PIX_FMT_MM21:
770	case V4L2_PIX_FMT_MT21C:
771	case V4L2_PIX_FMT_MT2110T:
772	case V4L2_PIX_FMT_MT2110R:
773		mtk_video_formats[count_formats].fourcc = fourcc;
774		mtk_video_formats[count_formats].type = MTK_FMT_FRAME;
775		mtk_video_formats[count_formats].num_planes = 2;
776		break;
777	default:
778		mtk_v4l2_vdec_err(ctx, "Can not add unsupported format type");
779		return;
780	}
781
782	num_formats++;
783	mtk_v4l2_vdec_dbg(3, ctx, "num_formats: %d dec_capability: 0x%x",
784			  count_formats, ctx->dev->dec_capability);
785}
786
787static void mtk_vcodec_get_supported_formats(struct mtk_vcodec_dec_ctx *ctx)
788{
789	int cap_format_count = 0, out_format_count = 0;
790
791	if (num_formats)
792		return;
793
794	if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_MT21C) {
795		mtk_vcodec_add_formats(V4L2_PIX_FMT_MT21C, ctx);
796		cap_format_count++;
797	}
798	if (ctx->dev->dec_capability & MTK_VDEC_IS_SUPPORT_10BIT) {
799		mtk_vcodec_add_formats(V4L2_PIX_FMT_MT2110T, ctx);
800		cap_format_count++;
801		mtk_vcodec_add_formats(V4L2_PIX_FMT_MT2110R, ctx);
802		cap_format_count++;
803	}
804	if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_MM21) {
805		mtk_vcodec_add_formats(V4L2_PIX_FMT_MM21, ctx);
806		cap_format_count++;
807	}
808	if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_H264_SLICE) {
809		mtk_vcodec_add_formats(V4L2_PIX_FMT_H264_SLICE, ctx);
810		out_format_count++;
811	}
812	if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_VP8_FRAME) {
813		mtk_vcodec_add_formats(V4L2_PIX_FMT_VP8_FRAME, ctx);
814		out_format_count++;
815	}
816	if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_VP9_FRAME) {
817		mtk_vcodec_add_formats(V4L2_PIX_FMT_VP9_FRAME, ctx);
818		out_format_count++;
819	}
820	if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_HEVC_FRAME) {
821		mtk_vcodec_add_formats(V4L2_PIX_FMT_HEVC_SLICE, ctx);
822		out_format_count++;
823	}
824	if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_AV1_FRAME) {
825		mtk_vcodec_add_formats(V4L2_PIX_FMT_AV1_FRAME, ctx);
826		out_format_count++;
827	}
828
829	if (cap_format_count)
830		default_cap_format = mtk_video_formats[cap_format_count - 1];
831	if (out_format_count)
832		default_out_format =
833			mtk_video_formats[cap_format_count + out_format_count - 1];
834}
835
836static void mtk_init_vdec_params(struct mtk_vcodec_dec_ctx *ctx)
837{
838	struct vb2_queue *src_vq;
839
840	src_vq = v4l2_m2m_get_vq(ctx->m2m_ctx,
841				 V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
842
843	if (!ctx->dev->vdec_pdata->is_subdev_supported)
844		ctx->dev->dec_capability |=
845			MTK_VDEC_FORMAT_H264_SLICE | MTK_VDEC_FORMAT_MM21;
846	mtk_vcodec_get_supported_formats(ctx);
847
848	/* Support request api for output plane */
849	src_vq->supports_requests = true;
850	src_vq->requires_requests = true;
851}
852
853static int vb2ops_vdec_out_buf_validate(struct vb2_buffer *vb)
854{
855	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
856
857	vbuf->field = V4L2_FIELD_NONE;
858	return 0;
859}
860
861static const struct vb2_ops mtk_vdec_request_vb2_ops = {
862	.queue_setup	= vb2ops_vdec_queue_setup,
863	.start_streaming	= vb2ops_vdec_start_streaming,
864	.stop_streaming	= vb2ops_vdec_stop_streaming,
865
866	.buf_queue	= vb2ops_vdec_stateless_buf_queue,
867	.buf_out_validate = vb2ops_vdec_out_buf_validate,
868	.buf_init	= vb2ops_vdec_buf_init,
869	.buf_prepare	= vb2ops_vdec_buf_prepare,
870	.buf_finish	= vb2ops_vdec_buf_finish,
871	.buf_request_complete = vb2ops_vdec_buf_request_complete,
872};
873
874const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = {
875	.init_vdec_params = mtk_init_vdec_params,
876	.ctrls_setup = mtk_vcodec_dec_ctrls_setup,
877	.vdec_vb2_ops = &mtk_vdec_request_vb2_ops,
878	.vdec_formats = mtk_video_formats,
879	.num_formats = &num_formats,
880	.default_out_fmt = &default_out_format,
881	.default_cap_fmt = &default_cap_format,
882	.uses_stateless_api = true,
883	.worker = mtk_vdec_worker,
884	.flush_decoder = mtk_vdec_flush_decoder,
885	.cap_to_disp = mtk_vdec_stateless_cap_to_disp,
886	.get_cap_buffer = vdec_get_cap_buffer,
887	.is_subdev_supported = false,
888	.hw_arch = MTK_VDEC_PURE_SINGLE_CORE,
889};
890
891/* This platform data is used for one lat and one core architecture. */
892const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pdata = {
893	.init_vdec_params = mtk_init_vdec_params,
894	.ctrls_setup = mtk_vcodec_dec_ctrls_setup,
895	.vdec_vb2_ops = &mtk_vdec_request_vb2_ops,
896	.vdec_formats = mtk_video_formats,
897	.num_formats = &num_formats,
898	.default_out_fmt = &default_out_format,
899	.default_cap_fmt = &default_cap_format,
900	.uses_stateless_api = true,
901	.worker = mtk_vdec_worker,
902	.flush_decoder = mtk_vdec_flush_decoder,
903	.cap_to_disp = mtk_vdec_stateless_cap_to_disp,
904	.get_cap_buffer = vdec_get_cap_buffer,
905	.is_subdev_supported = true,
906	.hw_arch = MTK_VDEC_LAT_SINGLE_CORE,
907};
908
909const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata = {
910	.init_vdec_params = mtk_init_vdec_params,
911	.ctrls_setup = mtk_vcodec_dec_ctrls_setup,
912	.vdec_vb2_ops = &mtk_vdec_request_vb2_ops,
913	.vdec_formats = mtk_video_formats,
914	.num_formats = &num_formats,
915	.default_out_fmt = &default_out_format,
916	.default_cap_fmt = &default_cap_format,
917	.uses_stateless_api = true,
918	.worker = mtk_vdec_worker,
919	.flush_decoder = mtk_vdec_flush_decoder,
920	.cap_to_disp = mtk_vdec_stateless_cap_to_disp,
921	.get_cap_buffer = vdec_get_cap_buffer,
922	.is_subdev_supported = true,
923	.hw_arch = MTK_VDEC_PURE_SINGLE_CORE,
924};