mtk-mdp3-comp.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2022 MediaTek Inc.
  4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
  5 */
  6
  7#ifndef __MTK_MDP3_COMP_H__
  8#define __MTK_MDP3_COMP_H__
  9
 10#include "mtk-mdp3-cmdq.h"
 11
 12#define MM_REG_WRITE_MASK(cmd, id, base, ofst, val, mask)	\
 13do {								\
 14	typeof(mask) (m) = (mask);				\
 15	cmdq_pkt_write_mask(&((cmd)->pkt), id, (base) + (ofst),	\
 16			    (val),				\
 17		(((m) & (ofst##_MASK)) == (ofst##_MASK)) ?	\
 18			(0xffffffff) : (m));			\
 19} while (0)
 20
 21#define MM_REG_WRITE(cmd, id, base, ofst, val)			\
 22	cmdq_pkt_write(&((cmd)->pkt), id, (base) + (ofst), (val))
 23
 24#define MM_REG_WAIT(cmd, evt)					\
 25do {								\
 26	typeof(cmd) (c) = (cmd);				\
 27	typeof(evt) (e) = (evt);				\
 28	cmdq_pkt_wfe(&((c)->pkt), (e), true);			\
 29} while (0)
 30
 31#define MM_REG_WAIT_NO_CLEAR(cmd, evt)				\
 32do {								\
 33	typeof(cmd) (c) = (cmd);				\
 34	typeof(evt) (e) = (evt);				\
 35	cmdq_pkt_wfe(&((c)->pkt), (e), false);			\
 36} while (0)
 37
 38#define MM_REG_CLEAR(cmd, evt)					\
 39do {								\
 40	typeof(cmd) (c) = (cmd);				\
 41	typeof(evt) (e) = (evt);				\
 42	cmdq_pkt_clear_event(&((c)->pkt), (e));			\
 43} while (0)
 44
 45#define MM_REG_SET_EVENT(cmd, evt)				\
 46do {								\
 47	typeof(cmd) (c) = (cmd);				\
 48	typeof(evt) (e) = (evt);				\
 49	cmdq_pkt_set_event(&((c)->pkt), (e));			\
 50} while (0)
 51
 52#define MM_REG_POLL_MASK(cmd, id, base, ofst, val, _mask)	\
 53do {								\
 54	typeof(_mask) (_m) = (_mask);				\
 55	cmdq_pkt_poll_mask(&((cmd)->pkt), id,			\
 56		(base) + (ofst), (val),				\
 57		(((_m) & (ofst##_MASK)) == (ofst##_MASK)) ?	\
 58			(0xffffffff) : (_m));			\
 59} while (0)
 60
 61#define MM_REG_POLL(cmd, id, base, ofst, val)			\
 62	cmdq_pkt_poll(&((cmd)->pkt), id, (base) + (ofst), (val))
 63
 64enum mtk_mdp_comp_id {
 65	MDP_COMP_NONE = -1,	/* Invalid engine */
 66
 67	/* ISP */
 68	MDP_COMP_WPEI = 0,
 69	MDP_COMP_WPEO,		/* 1 */
 70	MDP_COMP_WPEI2,		/* 2 */
 71	MDP_COMP_WPEO2,		/* 3 */
 72	MDP_COMP_ISP_IMGI,	/* 4 */
 73	MDP_COMP_ISP_IMGO,	/* 5 */
 74	MDP_COMP_ISP_IMG2O,	/* 6 */
 75
 76	/* IPU */
 77	MDP_COMP_IPUI,		/* 7 */
 78	MDP_COMP_IPUO,		/* 8 */
 79
 80	/* MDP */
 81	MDP_COMP_CAMIN,		/* 9 */
 82	MDP_COMP_CAMIN2,	/* 10 */
 83	MDP_COMP_RDMA0,		/* 11 */
 84	MDP_COMP_RDMA1,		/* 12 */
 85	MDP_COMP_RDMA2,		/* 13 */
 86	MDP_COMP_RDMA3,		/* 14 */
 87	MDP_COMP_AAL0,		/* 15 */
 88	MDP_COMP_AAL1,		/* 16 */
 89	MDP_COMP_AAL2,		/* 17 */
 90	MDP_COMP_AAL3,		/* 18 */
 91	MDP_COMP_CCORR0,	/* 19 */
 92	MDP_COMP_RSZ0,		/* 20 */
 93	MDP_COMP_RSZ1,		/* 21 */
 94	MDP_COMP_RSZ2,		/* 22 */
 95	MDP_COMP_RSZ3,		/* 23 */
 96	MDP_COMP_TDSHP0,	/* 24 */
 97	MDP_COMP_TDSHP1,	/* 25 */
 98	MDP_COMP_TDSHP2,	/* 26 */
 99	MDP_COMP_TDSHP3,	/* 27 */
100	MDP_COMP_COLOR0,	/* 28 */
101	MDP_COMP_COLOR1,	/* 29 */
102	MDP_COMP_COLOR2,	/* 30 */
103	MDP_COMP_COLOR3,	/* 31 */
104	MDP_COMP_PATH0_SOUT,	/* 32 */
105	MDP_COMP_PATH1_SOUT,	/* 33 */
106	MDP_COMP_WROT0,		/* 34 */
107	MDP_COMP_WROT1,		/* 35 */
108	MDP_COMP_WROT2,		/* 36 */
109	MDP_COMP_WROT3,		/* 37 */
110	MDP_COMP_WDMA,		/* 38 */
111	MDP_COMP_SPLIT,		/* 39 */
112	MDP_COMP_SPLIT2,	/* 40 */
113	MDP_COMP_STITCH,	/* 41 */
114	MDP_COMP_FG0,		/* 42 */
115	MDP_COMP_FG1,		/* 43 */
116	MDP_COMP_FG2,		/* 44 */
117	MDP_COMP_FG3,		/* 45 */
118	MDP_COMP_TO_SVPP2MOUT,	/* 46 */
119	MDP_COMP_TO_SVPP3MOUT,	/* 47 */
120	MDP_COMP_TO_WARP0MOUT,	/* 48 */
121	MDP_COMP_TO_WARP1MOUT,	/* 49 */
122	MDP_COMP_VPP0_SOUT,	/* 50 */
123	MDP_COMP_VPP1_SOUT,	/* 51 */
124	MDP_COMP_PQ0_SOUT,	/* 52 */
125	MDP_COMP_PQ1_SOUT,	/* 53 */
126	MDP_COMP_HDR0,		/* 54 */
127	MDP_COMP_HDR1,		/* 55 */
128	MDP_COMP_HDR2,		/* 56 */
129	MDP_COMP_HDR3,		/* 57 */
130	MDP_COMP_OVL0,		/* 58 */
131	MDP_COMP_OVL1,		/* 59 */
132	MDP_COMP_PAD0,		/* 60 */
133	MDP_COMP_PAD1,		/* 61 */
134	MDP_COMP_PAD2,		/* 62 */
135	MDP_COMP_PAD3,		/* 63 */
136	MDP_COMP_TCC0,		/* 64 */
137	MDP_COMP_TCC1,		/* 65 */
138	MDP_COMP_MERGE2,	/* 66 */
139	MDP_COMP_MERGE3,	/* 67 */
140	MDP_COMP_VDO0DL0,	/* 68 */
141	MDP_COMP_VDO1DL0,	/* 69 */
142	MDP_COMP_VDO0DL1,	/* 70 */
143	MDP_COMP_VDO1DL1,	/* 71 */
144
145	MDP_MAX_COMP_COUNT	/* ALWAYS keep at the end */
146};
147
148enum mdp_comp_type {
149	MDP_COMP_TYPE_INVALID = 0,
150
151	MDP_COMP_TYPE_RDMA,
152	MDP_COMP_TYPE_RSZ,
153	MDP_COMP_TYPE_WROT,
154	MDP_COMP_TYPE_WDMA,
155	MDP_COMP_TYPE_PATH,
156
157	MDP_COMP_TYPE_TDSHP,
158	MDP_COMP_TYPE_COLOR,
159	MDP_COMP_TYPE_DRE,
160	MDP_COMP_TYPE_CCORR,
161	MDP_COMP_TYPE_AAL,
162	MDP_COMP_TYPE_TCC,
163	MDP_COMP_TYPE_HDR,
164	MDP_COMP_TYPE_SPLIT,
165	MDP_COMP_TYPE_STITCH,
166	MDP_COMP_TYPE_FG,
167	MDP_COMP_TYPE_OVL,
168	MDP_COMP_TYPE_PAD,
169	MDP_COMP_TYPE_MERGE,
170
171	MDP_COMP_TYPE_IMGI,
172	MDP_COMP_TYPE_WPEI,
173	MDP_COMP_TYPE_EXTO,	/* External path */
174	MDP_COMP_TYPE_DL_PATH,	/* Direct-link path */
175	MDP_COMP_TYPE_DUMMY,
176
177	MDP_COMP_TYPE_COUNT	/* ALWAYS keep at the end */
178};
179
180#define MDP_GCE_NO_EVENT (-1)
181enum {
182	MDP_GCE_EVENT_SOF = 0,
183	MDP_GCE_EVENT_EOF = 1,
184	MDP_GCE_EVENT_MAX,
185};
186
187struct mdp_comp_match {
188	enum mdp_comp_type type;
189	u32 alias_id;
190	s32 inner_id;
191	s32 subsys_id;
192};
193
194/* Used to describe the item order in MDP property */
195struct mdp_comp_info {
196	u32 clk_num;
197	u32 clk_ofst;
198	u32 dts_reg_ofst;
199};
200
201struct mdp_comp_blend {
202	enum mtk_mdp_comp_id b_id;
203	bool aid_mod;
204	bool aid_clk;
205};
206
207struct mdp_comp_data {
208	struct mdp_comp_match match;
209	struct mdp_comp_info info;
210	struct mdp_comp_blend blend;
211};
212
213struct mdp_comp_ops;
214
215struct mdp_comp {
216	struct mdp_dev			*mdp_dev;
217	void __iomem			*regs;
218	phys_addr_t			reg_base;
219	u8				subsys_id;
220	u8				clk_num;
221	struct clk			**clks;
222	struct device			*comp_dev;
223	enum mdp_comp_type		type;
224	enum mtk_mdp_comp_id		public_id;
225	s32				inner_id;
226	u32				alias_id;
227	s32				gce_event[MDP_GCE_EVENT_MAX];
228	const struct mdp_comp_ops	*ops;
229};
230
231struct mdp_comp_ctx {
232	struct mdp_comp			*comp;
233	const struct img_compparam	*param;
234	const struct img_input		*input;
235	const struct img_output		*outputs[IMG_MAX_HW_OUTPUTS];
236};
237
238struct mdp_comp_ops {
239	s64 (*get_comp_flag)(const struct mdp_comp_ctx *ctx);
240	int (*init_comp)(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd);
241	int (*config_frame)(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd,
242			    const struct v4l2_rect *compose);
243	int (*config_subfrm)(struct mdp_comp_ctx *ctx,
244			     struct mdp_cmdq_cmd *cmd, u32 index);
245	int (*wait_comp_event)(struct mdp_comp_ctx *ctx,
246			       struct mdp_cmdq_cmd *cmd);
247	int (*advance_subfrm)(struct mdp_comp_ctx *ctx,
248			      struct mdp_cmdq_cmd *cmd, u32 index);
249	int (*post_process)(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd);
250};
251
252struct mdp_dev;
253
254int mdp_comp_config(struct mdp_dev *mdp);
255void mdp_comp_destroy(struct mdp_dev *mdp);
256int mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp);
257void mdp_comp_clock_off(struct device *dev, struct mdp_comp *comp);
258int mdp_comp_clocks_on(struct device *dev, struct mdp_comp *comps, int num);
259void mdp_comp_clocks_off(struct device *dev, struct mdp_comp *comps, int num);
260int mdp_comp_ctx_config(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx,
261			const struct img_compparam *param,
262			const struct img_ipi_frameparam *frame);
263
264#endif  /* __MTK_MDP3_COMP_H__ */