pxa_camera.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * V4L2 Driver for PXA camera host
   4 *
   5 * Copyright (C) 2006, Sascha Hauer, Pengutronix
   6 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
   7 * Copyright (C) 2016, Robert Jarzmik <robert.jarzmik@free.fr>
   8 */
   9
  10#include <linux/init.h>
  11#include <linux/module.h>
  12#include <linux/io.h>
  13#include <linux/delay.h>
  14#include <linux/device.h>
  15#include <linux/dma-mapping.h>
  16#include <linux/err.h>
  17#include <linux/errno.h>
  18#include <linux/fs.h>
  19#include <linux/interrupt.h>
  20#include <linux/kernel.h>
  21#include <linux/mm.h>
  22#include <linux/moduleparam.h>
  23#include <linux/of.h>
  24#include <linux/of_graph.h>
  25#include <linux/time.h>
  26#include <linux/platform_device.h>
  27#include <linux/clk.h>
  28#include <linux/sched.h>
  29#include <linux/slab.h>
  30#include <linux/dmaengine.h>
  31#include <linux/dma/pxa-dma.h>
  32
  33#include <media/v4l2-async.h>
  34#include <media/v4l2-common.h>
  35#include <media/v4l2-ctrls.h>
  36#include <media/v4l2-device.h>
  37#include <media/v4l2-event.h>
  38#include <media/v4l2-ioctl.h>
  39#include <media/v4l2-fwnode.h>
  40
  41#include <media/videobuf2-dma-sg.h>
  42
  43#include <linux/videodev2.h>
  44
  45#include <linux/platform_data/media/camera-pxa.h>
  46#include <linux/workqueue.h>
  47
  48#define PXA_CAM_VERSION "0.0.6"
  49#define PXA_CAM_DRV_NAME "pxa27x-camera"
  50
  51#define DEFAULT_WIDTH	640
  52#define DEFAULT_HEIGHT	480
  53
  54/* Camera Interface */
  55#define CICR0		0x0000
  56#define CICR1		0x0004
  57#define CICR2		0x0008
  58#define CICR3		0x000C
  59#define CICR4		0x0010
  60#define CISR		0x0014
  61#define CIFR		0x0018
  62#define CITOR		0x001C
  63#define CIBR0		0x0028
  64#define CIBR1		0x0030
  65#define CIBR2		0x0038
  66
  67#define CICR0_DMAEN	(1UL << 31)	/* DMA request enable */
  68#define CICR0_PAR_EN	(1 << 30)	/* Parity enable */
  69#define CICR0_SL_CAP_EN	(1 << 29)	/* Capture enable for slave mode */
  70#define CICR0_ENB	(1 << 28)	/* Camera interface enable */
  71#define CICR0_DIS	(1 << 27)	/* Camera interface disable */
  72#define CICR0_SIM	(0x7 << 24)	/* Sensor interface mode mask */
  73#define CICR0_TOM	(1 << 9)	/* Time-out mask */
  74#define CICR0_RDAVM	(1 << 8)	/* Receive-data-available mask */
  75#define CICR0_FEM	(1 << 7)	/* FIFO-empty mask */
  76#define CICR0_EOLM	(1 << 6)	/* End-of-line mask */
  77#define CICR0_PERRM	(1 << 5)	/* Parity-error mask */
  78#define CICR0_QDM	(1 << 4)	/* Quick-disable mask */
  79#define CICR0_CDM	(1 << 3)	/* Disable-done mask */
  80#define CICR0_SOFM	(1 << 2)	/* Start-of-frame mask */
  81#define CICR0_EOFM	(1 << 1)	/* End-of-frame mask */
  82#define CICR0_FOM	(1 << 0)	/* FIFO-overrun mask */
  83
  84#define CICR1_TBIT	(1UL << 31)	/* Transparency bit */
  85#define CICR1_RGBT_CONV	(0x3 << 29)	/* RGBT conversion mask */
  86#define CICR1_PPL	(0x7ff << 15)	/* Pixels per line mask */
  87#define CICR1_RGB_CONV	(0x7 << 12)	/* RGB conversion mask */
  88#define CICR1_RGB_F	(1 << 11)	/* RGB format */
  89#define CICR1_YCBCR_F	(1 << 10)	/* YCbCr format */
  90#define CICR1_RGB_BPP	(0x7 << 7)	/* RGB bis per pixel mask */
  91#define CICR1_RAW_BPP	(0x3 << 5)	/* Raw bis per pixel mask */
  92#define CICR1_COLOR_SP	(0x3 << 3)	/* Color space mask */
  93#define CICR1_DW	(0x7 << 0)	/* Data width mask */
  94
  95#define CICR2_BLW	(0xff << 24)	/* Beginning-of-line pixel clock
  96					   wait count mask */
  97#define CICR2_ELW	(0xff << 16)	/* End-of-line pixel clock
  98					   wait count mask */
  99#define CICR2_HSW	(0x3f << 10)	/* Horizontal sync pulse width mask */
 100#define CICR2_BFPW	(0x3f << 3)	/* Beginning-of-frame pixel clock
 101					   wait count mask */
 102#define CICR2_FSW	(0x7 << 0)	/* Frame stabilization
 103					   wait count mask */
 104
 105#define CICR3_BFW	(0xff << 24)	/* Beginning-of-frame line clock
 106					   wait count mask */
 107#define CICR3_EFW	(0xff << 16)	/* End-of-frame line clock
 108					   wait count mask */
 109#define CICR3_VSW	(0x3f << 10)	/* Vertical sync pulse width mask */
 110#define CICR3_BFPW	(0x3f << 3)	/* Beginning-of-frame pixel clock
 111					   wait count mask */
 112#define CICR3_LPF	(0x7ff << 0)	/* Lines per frame mask */
 113
 114#define CICR4_MCLK_DLY	(0x3 << 24)	/* MCLK Data Capture Delay mask */
 115#define CICR4_PCLK_EN	(1 << 23)	/* Pixel clock enable */
 116#define CICR4_PCP	(1 << 22)	/* Pixel clock polarity */
 117#define CICR4_HSP	(1 << 21)	/* Horizontal sync polarity */
 118#define CICR4_VSP	(1 << 20)	/* Vertical sync polarity */
 119#define CICR4_MCLK_EN	(1 << 19)	/* MCLK enable */
 120#define CICR4_FR_RATE	(0x7 << 8)	/* Frame rate mask */
 121#define CICR4_DIV	(0xff << 0)	/* Clock divisor mask */
 122
 123#define CISR_FTO	(1 << 15)	/* FIFO time-out */
 124#define CISR_RDAV_2	(1 << 14)	/* Channel 2 receive data available */
 125#define CISR_RDAV_1	(1 << 13)	/* Channel 1 receive data available */
 126#define CISR_RDAV_0	(1 << 12)	/* Channel 0 receive data available */
 127#define CISR_FEMPTY_2	(1 << 11)	/* Channel 2 FIFO empty */
 128#define CISR_FEMPTY_1	(1 << 10)	/* Channel 1 FIFO empty */
 129#define CISR_FEMPTY_0	(1 << 9)	/* Channel 0 FIFO empty */
 130#define CISR_EOL	(1 << 8)	/* End of line */
 131#define CISR_PAR_ERR	(1 << 7)	/* Parity error */
 132#define CISR_CQD	(1 << 6)	/* Camera interface quick disable */
 133#define CISR_CDD	(1 << 5)	/* Camera interface disable done */
 134#define CISR_SOF	(1 << 4)	/* Start of frame */
 135#define CISR_EOF	(1 << 3)	/* End of frame */
 136#define CISR_IFO_2	(1 << 2)	/* FIFO overrun for Channel 2 */
 137#define CISR_IFO_1	(1 << 1)	/* FIFO overrun for Channel 1 */
 138#define CISR_IFO_0	(1 << 0)	/* FIFO overrun for Channel 0 */
 139
 140#define CIFR_FLVL2	(0x7f << 23)	/* FIFO 2 level mask */
 141#define CIFR_FLVL1	(0x7f << 16)	/* FIFO 1 level mask */
 142#define CIFR_FLVL0	(0xff << 8)	/* FIFO 0 level mask */
 143#define CIFR_THL_0	(0x3 << 4)	/* Threshold Level for Channel 0 FIFO */
 144#define CIFR_RESET_F	(1 << 3)	/* Reset input FIFOs */
 145#define CIFR_FEN2	(1 << 2)	/* FIFO enable for channel 2 */
 146#define CIFR_FEN1	(1 << 1)	/* FIFO enable for channel 1 */
 147#define CIFR_FEN0	(1 << 0)	/* FIFO enable for channel 0 */
 148
 149#define CICR0_SIM_MP	(0 << 24)
 150#define CICR0_SIM_SP	(1 << 24)
 151#define CICR0_SIM_MS	(2 << 24)
 152#define CICR0_SIM_EP	(3 << 24)
 153#define CICR0_SIM_ES	(4 << 24)
 154
 155#define CICR1_DW_VAL(x)   ((x) & CICR1_DW)	    /* Data bus width */
 156#define CICR1_PPL_VAL(x)  (((x) << 15) & CICR1_PPL) /* Pixels per line */
 157#define CICR1_COLOR_SP_VAL(x)	(((x) << 3) & CICR1_COLOR_SP)	/* color space */
 158#define CICR1_RGB_BPP_VAL(x)	(((x) << 7) & CICR1_RGB_BPP)	/* bpp for rgb */
 159#define CICR1_RGBT_CONV_VAL(x)	(((x) << 29) & CICR1_RGBT_CONV)	/* rgbt conv */
 160
 161#define CICR2_BLW_VAL(x)  (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
 162#define CICR2_ELW_VAL(x)  (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
 163#define CICR2_HSW_VAL(x)  (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
 164#define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
 165#define CICR2_FSW_VAL(x)  (((x) << 0) & CICR2_FSW)  /* Frame stabilization wait count */
 166
 167#define CICR3_BFW_VAL(x)  (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count  */
 168#define CICR3_EFW_VAL(x)  (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
 169#define CICR3_VSW_VAL(x)  (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
 170#define CICR3_LPF_VAL(x)  (((x) << 0) & CICR3_LPF)  /* Lines per frame */
 171
 172#define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
 173			CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
 174			CICR0_EOFM | CICR0_FOM)
 175
 176#define sensor_call(cam, o, f, args...) \
 177	v4l2_subdev_call(cam->sensor, o, f, ##args)
 178
 179/*
 180 * Format handling
 181 */
 182
 183/**
 184 * enum pxa_mbus_packing - data packing types on the media-bus
 185 * @PXA_MBUS_PACKING_NONE:	no packing, bit-for-bit transfer to RAM, one
 186 *				sample represents one pixel
 187 * @PXA_MBUS_PACKING_2X8_PADHI:	16 bits transferred in 2 8-bit samples, in the
 188 *				possibly incomplete byte high bits are padding
 189 * @PXA_MBUS_PACKING_EXTEND16:	sample width (e.g., 10 bits) has to be extended
 190 *				to 16 bits
 191 */
 192enum pxa_mbus_packing {
 193	PXA_MBUS_PACKING_NONE,
 194	PXA_MBUS_PACKING_2X8_PADHI,
 195	PXA_MBUS_PACKING_EXTEND16,
 196};
 197
 198/**
 199 * enum pxa_mbus_order - sample order on the media bus
 200 * @PXA_MBUS_ORDER_LE:		least significant sample first
 201 * @PXA_MBUS_ORDER_BE:		most significant sample first
 202 */
 203enum pxa_mbus_order {
 204	PXA_MBUS_ORDER_LE,
 205	PXA_MBUS_ORDER_BE,
 206};
 207
 208/**
 209 * enum pxa_mbus_layout - planes layout in memory
 210 * @PXA_MBUS_LAYOUT_PACKED:		color components packed
 211 * @PXA_MBUS_LAYOUT_PLANAR_2Y_U_V:	YUV components stored in 3 planes (4:2:2)
 212 * @PXA_MBUS_LAYOUT_PLANAR_2Y_C:	YUV components stored in a luma and a
 213 *					chroma plane (C plane is half the size
 214 *					of Y plane)
 215 * @PXA_MBUS_LAYOUT_PLANAR_Y_C:		YUV components stored in a luma and a
 216 *					chroma plane (C plane is the same size
 217 *					as Y plane)
 218 */
 219enum pxa_mbus_layout {
 220	PXA_MBUS_LAYOUT_PACKED = 0,
 221	PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
 222	PXA_MBUS_LAYOUT_PLANAR_2Y_C,
 223	PXA_MBUS_LAYOUT_PLANAR_Y_C,
 224};
 225
 226/**
 227 * struct pxa_mbus_pixelfmt - Data format on the media bus
 228 * @name:		Name of the format
 229 * @fourcc:		Fourcc code, that will be obtained if the data is
 230 *			stored in memory in the following way:
 231 * @packing:		Type of sample-packing, that has to be used
 232 * @order:		Sample order when storing in memory
 233 * @layout:		Planes layout in memory
 234 * @bits_per_sample:	How many bits the bridge has to sample
 235 */
 236struct pxa_mbus_pixelfmt {
 237	const char		*name;
 238	u32			fourcc;
 239	enum pxa_mbus_packing	packing;
 240	enum pxa_mbus_order	order;
 241	enum pxa_mbus_layout	layout;
 242	u8			bits_per_sample;
 243};
 244
 245/**
 246 * struct pxa_mbus_lookup - Lookup FOURCC IDs by mediabus codes for pass-through
 247 * @code:	mediabus pixel-code
 248 * @fmt:	pixel format description
 249 */
 250struct pxa_mbus_lookup {
 251	u32	code;
 252	struct pxa_mbus_pixelfmt	fmt;
 253};
 254
 255static const struct pxa_mbus_lookup mbus_fmt[] = {
 256{
 257	.code = MEDIA_BUS_FMT_YUYV8_2X8,
 258	.fmt = {
 259		.fourcc			= V4L2_PIX_FMT_YUYV,
 260		.name			= "YUYV",
 261		.bits_per_sample	= 8,
 262		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
 263		.order			= PXA_MBUS_ORDER_LE,
 264		.layout			= PXA_MBUS_LAYOUT_PACKED,
 265	},
 266}, {
 267	.code = MEDIA_BUS_FMT_YVYU8_2X8,
 268	.fmt = {
 269		.fourcc			= V4L2_PIX_FMT_YVYU,
 270		.name			= "YVYU",
 271		.bits_per_sample	= 8,
 272		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
 273		.order			= PXA_MBUS_ORDER_LE,
 274		.layout			= PXA_MBUS_LAYOUT_PACKED,
 275	},
 276}, {
 277	.code = MEDIA_BUS_FMT_UYVY8_2X8,
 278	.fmt = {
 279		.fourcc			= V4L2_PIX_FMT_UYVY,
 280		.name			= "UYVY",
 281		.bits_per_sample	= 8,
 282		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
 283		.order			= PXA_MBUS_ORDER_LE,
 284		.layout			= PXA_MBUS_LAYOUT_PACKED,
 285	},
 286}, {
 287	.code = MEDIA_BUS_FMT_VYUY8_2X8,
 288	.fmt = {
 289		.fourcc			= V4L2_PIX_FMT_VYUY,
 290		.name			= "VYUY",
 291		.bits_per_sample	= 8,
 292		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
 293		.order			= PXA_MBUS_ORDER_LE,
 294		.layout			= PXA_MBUS_LAYOUT_PACKED,
 295	},
 296}, {
 297	.code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
 298	.fmt = {
 299		.fourcc			= V4L2_PIX_FMT_RGB555,
 300		.name			= "RGB555",
 301		.bits_per_sample	= 8,
 302		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
 303		.order			= PXA_MBUS_ORDER_LE,
 304		.layout			= PXA_MBUS_LAYOUT_PACKED,
 305	},
 306}, {
 307	.code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
 308	.fmt = {
 309		.fourcc			= V4L2_PIX_FMT_RGB555X,
 310		.name			= "RGB555X",
 311		.bits_per_sample	= 8,
 312		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
 313		.order			= PXA_MBUS_ORDER_BE,
 314		.layout			= PXA_MBUS_LAYOUT_PACKED,
 315	},
 316}, {
 317	.code = MEDIA_BUS_FMT_RGB565_2X8_LE,
 318	.fmt = {
 319		.fourcc			= V4L2_PIX_FMT_RGB565,
 320		.name			= "RGB565",
 321		.bits_per_sample	= 8,
 322		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
 323		.order			= PXA_MBUS_ORDER_LE,
 324		.layout			= PXA_MBUS_LAYOUT_PACKED,
 325	},
 326}, {
 327	.code = MEDIA_BUS_FMT_RGB565_2X8_BE,
 328	.fmt = {
 329		.fourcc			= V4L2_PIX_FMT_RGB565X,
 330		.name			= "RGB565X",
 331		.bits_per_sample	= 8,
 332		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
 333		.order			= PXA_MBUS_ORDER_BE,
 334		.layout			= PXA_MBUS_LAYOUT_PACKED,
 335	},
 336}, {
 337	.code = MEDIA_BUS_FMT_SBGGR8_1X8,
 338	.fmt = {
 339		.fourcc			= V4L2_PIX_FMT_SBGGR8,
 340		.name			= "Bayer 8 BGGR",
 341		.bits_per_sample	= 8,
 342		.packing		= PXA_MBUS_PACKING_NONE,
 343		.order			= PXA_MBUS_ORDER_LE,
 344		.layout			= PXA_MBUS_LAYOUT_PACKED,
 345	},
 346}, {
 347	.code = MEDIA_BUS_FMT_SGBRG8_1X8,
 348	.fmt = {
 349		.fourcc			= V4L2_PIX_FMT_SGBRG8,
 350		.name			= "Bayer 8 GBRG",
 351		.bits_per_sample	= 8,
 352		.packing		= PXA_MBUS_PACKING_NONE,
 353		.order			= PXA_MBUS_ORDER_LE,
 354		.layout			= PXA_MBUS_LAYOUT_PACKED,
 355	},
 356}, {
 357	.code = MEDIA_BUS_FMT_SGRBG8_1X8,
 358	.fmt = {
 359		.fourcc			= V4L2_PIX_FMT_SGRBG8,
 360		.name			= "Bayer 8 GRBG",
 361		.bits_per_sample	= 8,
 362		.packing		= PXA_MBUS_PACKING_NONE,
 363		.order			= PXA_MBUS_ORDER_LE,
 364		.layout			= PXA_MBUS_LAYOUT_PACKED,
 365	},
 366}, {
 367	.code = MEDIA_BUS_FMT_SRGGB8_1X8,
 368	.fmt = {
 369		.fourcc			= V4L2_PIX_FMT_SRGGB8,
 370		.name			= "Bayer 8 RGGB",
 371		.bits_per_sample	= 8,
 372		.packing		= PXA_MBUS_PACKING_NONE,
 373		.order			= PXA_MBUS_ORDER_LE,
 374		.layout			= PXA_MBUS_LAYOUT_PACKED,
 375	},
 376}, {
 377	.code = MEDIA_BUS_FMT_SBGGR10_1X10,
 378	.fmt = {
 379		.fourcc			= V4L2_PIX_FMT_SBGGR10,
 380		.name			= "Bayer 10 BGGR",
 381		.bits_per_sample	= 10,
 382		.packing		= PXA_MBUS_PACKING_EXTEND16,
 383		.order			= PXA_MBUS_ORDER_LE,
 384		.layout			= PXA_MBUS_LAYOUT_PACKED,
 385	},
 386}, {
 387	.code = MEDIA_BUS_FMT_Y8_1X8,
 388	.fmt = {
 389		.fourcc			= V4L2_PIX_FMT_GREY,
 390		.name			= "Grey",
 391		.bits_per_sample	= 8,
 392		.packing		= PXA_MBUS_PACKING_NONE,
 393		.order			= PXA_MBUS_ORDER_LE,
 394		.layout			= PXA_MBUS_LAYOUT_PACKED,
 395	},
 396}, {
 397	.code = MEDIA_BUS_FMT_Y10_1X10,
 398	.fmt = {
 399		.fourcc			= V4L2_PIX_FMT_Y10,
 400		.name			= "Grey 10bit",
 401		.bits_per_sample	= 10,
 402		.packing		= PXA_MBUS_PACKING_EXTEND16,
 403		.order			= PXA_MBUS_ORDER_LE,
 404		.layout			= PXA_MBUS_LAYOUT_PACKED,
 405	},
 406}, {
 407	.code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
 408	.fmt = {
 409		.fourcc			= V4L2_PIX_FMT_SBGGR10,
 410		.name			= "Bayer 10 BGGR",
 411		.bits_per_sample	= 8,
 412		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
 413		.order			= PXA_MBUS_ORDER_LE,
 414		.layout			= PXA_MBUS_LAYOUT_PACKED,
 415	},
 416}, {
 417	.code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE,
 418	.fmt = {
 419		.fourcc			= V4L2_PIX_FMT_SBGGR10,
 420		.name			= "Bayer 10 BGGR",
 421		.bits_per_sample	= 8,
 422		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
 423		.order			= PXA_MBUS_ORDER_BE,
 424		.layout			= PXA_MBUS_LAYOUT_PACKED,
 425	},
 426}, {
 427	.code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE,
 428	.fmt = {
 429		.fourcc			= V4L2_PIX_FMT_RGB444,
 430		.name			= "RGB444",
 431		.bits_per_sample	= 8,
 432		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
 433		.order			= PXA_MBUS_ORDER_BE,
 434		.layout			= PXA_MBUS_LAYOUT_PACKED,
 435	},
 436}, {
 437	.code = MEDIA_BUS_FMT_UYVY8_1X16,
 438	.fmt = {
 439		.fourcc			= V4L2_PIX_FMT_UYVY,
 440		.name			= "UYVY 16bit",
 441		.bits_per_sample	= 16,
 442		.packing		= PXA_MBUS_PACKING_EXTEND16,
 443		.order			= PXA_MBUS_ORDER_LE,
 444		.layout			= PXA_MBUS_LAYOUT_PACKED,
 445	},
 446}, {
 447	.code = MEDIA_BUS_FMT_VYUY8_1X16,
 448	.fmt = {
 449		.fourcc			= V4L2_PIX_FMT_VYUY,
 450		.name			= "VYUY 16bit",
 451		.bits_per_sample	= 16,
 452		.packing		= PXA_MBUS_PACKING_EXTEND16,
 453		.order			= PXA_MBUS_ORDER_LE,
 454		.layout			= PXA_MBUS_LAYOUT_PACKED,
 455	},
 456}, {
 457	.code = MEDIA_BUS_FMT_YUYV8_1X16,
 458	.fmt = {
 459		.fourcc			= V4L2_PIX_FMT_YUYV,
 460		.name			= "YUYV 16bit",
 461		.bits_per_sample	= 16,
 462		.packing		= PXA_MBUS_PACKING_EXTEND16,
 463		.order			= PXA_MBUS_ORDER_LE,
 464		.layout			= PXA_MBUS_LAYOUT_PACKED,
 465	},
 466}, {
 467	.code = MEDIA_BUS_FMT_YVYU8_1X16,
 468	.fmt = {
 469		.fourcc			= V4L2_PIX_FMT_YVYU,
 470		.name			= "YVYU 16bit",
 471		.bits_per_sample	= 16,
 472		.packing		= PXA_MBUS_PACKING_EXTEND16,
 473		.order			= PXA_MBUS_ORDER_LE,
 474		.layout			= PXA_MBUS_LAYOUT_PACKED,
 475	},
 476}, {
 477	.code = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
 478	.fmt = {
 479		.fourcc			= V4L2_PIX_FMT_SGRBG10DPCM8,
 480		.name			= "Bayer 10 BGGR DPCM 8",
 481		.bits_per_sample	= 8,
 482		.packing		= PXA_MBUS_PACKING_NONE,
 483		.order			= PXA_MBUS_ORDER_LE,
 484		.layout			= PXA_MBUS_LAYOUT_PACKED,
 485	},
 486}, {
 487	.code = MEDIA_BUS_FMT_SGBRG10_1X10,
 488	.fmt = {
 489		.fourcc			= V4L2_PIX_FMT_SGBRG10,
 490		.name			= "Bayer 10 GBRG",
 491		.bits_per_sample	= 10,
 492		.packing		= PXA_MBUS_PACKING_EXTEND16,
 493		.order			= PXA_MBUS_ORDER_LE,
 494		.layout			= PXA_MBUS_LAYOUT_PACKED,
 495	},
 496}, {
 497	.code = MEDIA_BUS_FMT_SGRBG10_1X10,
 498	.fmt = {
 499		.fourcc			= V4L2_PIX_FMT_SGRBG10,
 500		.name			= "Bayer 10 GRBG",
 501		.bits_per_sample	= 10,
 502		.packing		= PXA_MBUS_PACKING_EXTEND16,
 503		.order			= PXA_MBUS_ORDER_LE,
 504		.layout			= PXA_MBUS_LAYOUT_PACKED,
 505	},
 506}, {
 507	.code = MEDIA_BUS_FMT_SRGGB10_1X10,
 508	.fmt = {
 509		.fourcc			= V4L2_PIX_FMT_SRGGB10,
 510		.name			= "Bayer 10 RGGB",
 511		.bits_per_sample	= 10,
 512		.packing		= PXA_MBUS_PACKING_EXTEND16,
 513		.order			= PXA_MBUS_ORDER_LE,
 514		.layout			= PXA_MBUS_LAYOUT_PACKED,
 515	},
 516}, {
 517	.code = MEDIA_BUS_FMT_SBGGR12_1X12,
 518	.fmt = {
 519		.fourcc			= V4L2_PIX_FMT_SBGGR12,
 520		.name			= "Bayer 12 BGGR",
 521		.bits_per_sample	= 12,
 522		.packing		= PXA_MBUS_PACKING_EXTEND16,
 523		.order			= PXA_MBUS_ORDER_LE,
 524		.layout			= PXA_MBUS_LAYOUT_PACKED,
 525	},
 526}, {
 527	.code = MEDIA_BUS_FMT_SGBRG12_1X12,
 528	.fmt = {
 529		.fourcc			= V4L2_PIX_FMT_SGBRG12,
 530		.name			= "Bayer 12 GBRG",
 531		.bits_per_sample	= 12,
 532		.packing		= PXA_MBUS_PACKING_EXTEND16,
 533		.order			= PXA_MBUS_ORDER_LE,
 534		.layout			= PXA_MBUS_LAYOUT_PACKED,
 535	},
 536}, {
 537	.code = MEDIA_BUS_FMT_SGRBG12_1X12,
 538	.fmt = {
 539		.fourcc			= V4L2_PIX_FMT_SGRBG12,
 540		.name			= "Bayer 12 GRBG",
 541		.bits_per_sample	= 12,
 542		.packing		= PXA_MBUS_PACKING_EXTEND16,
 543		.order			= PXA_MBUS_ORDER_LE,
 544		.layout			= PXA_MBUS_LAYOUT_PACKED,
 545	},
 546}, {
 547	.code = MEDIA_BUS_FMT_SRGGB12_1X12,
 548	.fmt = {
 549		.fourcc			= V4L2_PIX_FMT_SRGGB12,
 550		.name			= "Bayer 12 RGGB",
 551		.bits_per_sample	= 12,
 552		.packing		= PXA_MBUS_PACKING_EXTEND16,
 553		.order			= PXA_MBUS_ORDER_LE,
 554		.layout			= PXA_MBUS_LAYOUT_PACKED,
 555	},
 556},
 557};
 558
 559static s32 pxa_mbus_bytes_per_line(u32 width, const struct pxa_mbus_pixelfmt *mf)
 560{
 561	if (mf->layout != PXA_MBUS_LAYOUT_PACKED)
 562		return width * mf->bits_per_sample / 8;
 563
 564	switch (mf->packing) {
 565	case PXA_MBUS_PACKING_NONE:
 566		return width * mf->bits_per_sample / 8;
 567	case PXA_MBUS_PACKING_2X8_PADHI:
 568	case PXA_MBUS_PACKING_EXTEND16:
 569		return width * 2;
 570	}
 571	return -EINVAL;
 572}
 573
 574static s32 pxa_mbus_image_size(const struct pxa_mbus_pixelfmt *mf,
 575			u32 bytes_per_line, u32 height)
 576{
 577	if (mf->layout == PXA_MBUS_LAYOUT_PACKED)
 578		return bytes_per_line * height;
 579
 580	switch (mf->packing) {
 581	case PXA_MBUS_PACKING_2X8_PADHI:
 582		return bytes_per_line * height * 2;
 583	default:
 584		return -EINVAL;
 585	}
 586}
 587
 588static const struct pxa_mbus_pixelfmt *pxa_mbus_find_fmtdesc(
 589	u32 code,
 590	const struct pxa_mbus_lookup *lookup,
 591	int n)
 592{
 593	int i;
 594
 595	for (i = 0; i < n; i++)
 596		if (lookup[i].code == code)
 597			return &lookup[i].fmt;
 598
 599	return NULL;
 600}
 601
 602static const struct pxa_mbus_pixelfmt *pxa_mbus_get_fmtdesc(
 603	u32 code)
 604{
 605	return pxa_mbus_find_fmtdesc(code, mbus_fmt, ARRAY_SIZE(mbus_fmt));
 606}
 607
 608/**
 609 * struct pxa_camera_format_xlate - match between host and sensor formats
 610 * @code: code of a sensor provided format
 611 * @host_fmt: host format after host translation from code
 612 *
 613 * Host and sensor translation structure. Used in table of host and sensor
 614 * formats matchings in pxa_camera_device. A host can override the generic list
 615 * generation by implementing get_formats(), and use it for format checks and
 616 * format setup.
 617 */
 618struct pxa_camera_format_xlate {
 619	u32 code;
 620	const struct pxa_mbus_pixelfmt *host_fmt;
 621};
 622
 623/*
 624 * Structures
 625 */
 626enum pxa_camera_active_dma {
 627	DMA_Y = 0x1,
 628	DMA_U = 0x2,
 629	DMA_V = 0x4,
 630};
 631
 632/* buffer for one video frame */
 633struct pxa_buffer {
 634	/* common v4l buffer stuff -- must be first */
 635	struct vb2_v4l2_buffer		vbuf;
 636	struct list_head		queue;
 637	u32	code;
 638	int				nb_planes;
 639	/* our descriptor lists for Y, U and V channels */
 640	struct dma_async_tx_descriptor	*descs[3];
 641	dma_cookie_t			cookie[3];
 642	struct scatterlist		*sg[3];
 643	int				sg_len[3];
 644	size_t				plane_sizes[3];
 645	int				inwork;
 646	enum pxa_camera_active_dma	active_dma;
 647};
 648
 649struct pxa_camera_dev {
 650	struct v4l2_device	v4l2_dev;
 651	struct video_device	vdev;
 652	struct v4l2_async_notifier notifier;
 653	struct vb2_queue	vb2_vq;
 654	struct v4l2_subdev	*sensor;
 655	struct pxa_camera_format_xlate *user_formats;
 656	const struct pxa_camera_format_xlate *current_fmt;
 657	struct v4l2_pix_format	current_pix;
 658
 659	/*
 660	 * PXA27x is only supposed to handle one camera on its Quick Capture
 661	 * interface. If anyone ever builds hardware to enable more than
 662	 * one camera, they will have to modify this driver too
 663	 */
 664	struct clk		*clk;
 665
 666	unsigned int		irq;
 667	void __iomem		*base;
 668
 669	int			channels;
 670	struct dma_chan		*dma_chans[3];
 671
 672	struct pxacamera_platform_data *pdata;
 673	struct resource		*res;
 674	unsigned long		platform_flags;
 675	unsigned long		ciclk;
 676	unsigned long		mclk;
 677	u32			mclk_divisor;
 678	u16			width_flags;	/* max 10 bits */
 679
 680	struct list_head	capture;
 681
 682	spinlock_t		lock;
 683	struct mutex		mlock;
 684	unsigned int		buf_sequence;
 685
 686	struct pxa_buffer	*active;
 687	struct work_struct	eof_bh_work;
 688
 689	u32			save_cicr[5];
 690};
 691
 692struct pxa_cam {
 693	unsigned long flags;
 694};
 695
 696static const char *pxa_cam_driver_description = "PXA_Camera";
 697
 698/*
 699 * Format translation functions
 700 */
 701static const struct pxa_camera_format_xlate
 702*pxa_mbus_xlate_by_fourcc(struct pxa_camera_format_xlate *user_formats,
 703			  unsigned int fourcc)
 704{
 705	unsigned int i;
 706
 707	for (i = 0; user_formats[i].code; i++)
 708		if (user_formats[i].host_fmt->fourcc == fourcc)
 709			return user_formats + i;
 710	return NULL;
 711}
 712
 713static struct pxa_camera_format_xlate *pxa_mbus_build_fmts_xlate(
 714	struct v4l2_device *v4l2_dev, struct v4l2_subdev *subdev,
 715	int (*get_formats)(struct v4l2_device *, unsigned int,
 716			   struct pxa_camera_format_xlate *xlate))
 717{
 718	unsigned int i, fmts = 0, raw_fmts = 0;
 719	int ret;
 720	struct v4l2_subdev_mbus_code_enum code = {
 721		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
 722	};
 723	struct pxa_camera_format_xlate *user_formats;
 724
 725	while (!v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL, &code)) {
 726		raw_fmts++;
 727		code.index++;
 728	}
 729
 730	/*
 731	 * First pass - only count formats this host-sensor
 732	 * configuration can provide
 733	 */
 734	for (i = 0; i < raw_fmts; i++) {
 735		ret = get_formats(v4l2_dev, i, NULL);
 736		if (ret < 0)
 737			return ERR_PTR(ret);
 738		fmts += ret;
 739	}
 740
 741	if (!fmts)
 742		return ERR_PTR(-ENXIO);
 743
 744	user_formats = kcalloc(fmts + 1, sizeof(*user_formats), GFP_KERNEL);
 745	if (!user_formats)
 746		return ERR_PTR(-ENOMEM);
 747
 748	/* Second pass - actually fill data formats */
 749	fmts = 0;
 750	for (i = 0; i < raw_fmts; i++) {
 751		ret = get_formats(v4l2_dev, i, user_formats + fmts);
 752		if (ret < 0)
 753			goto egfmt;
 754		fmts += ret;
 755	}
 756	user_formats[fmts].code = 0;
 757
 758	return user_formats;
 759egfmt:
 760	kfree(user_formats);
 761	return ERR_PTR(ret);
 762}
 763
 764/*
 765 *  Videobuf operations
 766 */
 767static struct pxa_buffer *vb2_to_pxa_buffer(struct vb2_buffer *vb)
 768{
 769	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 770
 771	return container_of(vbuf, struct pxa_buffer, vbuf);
 772}
 773
 774static struct device *pcdev_to_dev(struct pxa_camera_dev *pcdev)
 775{
 776	return pcdev->v4l2_dev.dev;
 777}
 778
 779static struct pxa_camera_dev *v4l2_dev_to_pcdev(struct v4l2_device *v4l2_dev)
 780{
 781	return container_of(v4l2_dev, struct pxa_camera_dev, v4l2_dev);
 782}
 783
 784static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
 785			       enum pxa_camera_active_dma act_dma);
 786
 787static void pxa_camera_dma_irq_y(void *data)
 788{
 789	struct pxa_camera_dev *pcdev = data;
 790
 791	pxa_camera_dma_irq(pcdev, DMA_Y);
 792}
 793
 794static void pxa_camera_dma_irq_u(void *data)
 795{
 796	struct pxa_camera_dev *pcdev = data;
 797
 798	pxa_camera_dma_irq(pcdev, DMA_U);
 799}
 800
 801static void pxa_camera_dma_irq_v(void *data)
 802{
 803	struct pxa_camera_dev *pcdev = data;
 804
 805	pxa_camera_dma_irq(pcdev, DMA_V);
 806}
 807
 808/**
 809 * pxa_init_dma_channel - init dma descriptors
 810 * @pcdev: pxa camera device
 811 * @buf: pxa camera buffer
 812 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
 813 * @sg: dma scatter list
 814 * @sglen: dma scatter list length
 815 *
 816 * Prepares the pxa dma descriptors to transfer one camera channel.
 817 *
 818 * Returns 0 if success or -ENOMEM if no memory is available
 819 */
 820static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
 821				struct pxa_buffer *buf, int channel,
 822				struct scatterlist *sg, int sglen)
 823{
 824	struct dma_chan *dma_chan = pcdev->dma_chans[channel];
 825	struct dma_async_tx_descriptor *tx;
 826
 827	tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM,
 828				     DMA_PREP_INTERRUPT | DMA_CTRL_REUSE);
 829	if (!tx) {
 830		dev_err(pcdev_to_dev(pcdev),
 831			"dmaengine_prep_slave_sg failed\n");
 832		goto fail;
 833	}
 834
 835	tx->callback_param = pcdev;
 836	switch (channel) {
 837	case 0:
 838		tx->callback = pxa_camera_dma_irq_y;
 839		break;
 840	case 1:
 841		tx->callback = pxa_camera_dma_irq_u;
 842		break;
 843	case 2:
 844		tx->callback = pxa_camera_dma_irq_v;
 845		break;
 846	}
 847
 848	buf->descs[channel] = tx;
 849	return 0;
 850fail:
 851	dev_dbg(pcdev_to_dev(pcdev),
 852		"%s (vb=%p) dma_tx=%p\n",
 853		__func__, buf, tx);
 854
 855	return -ENOMEM;
 856}
 857
 858static void pxa_video_buf_set_actdma(struct pxa_camera_dev *pcdev,
 859				    struct pxa_buffer *buf)
 860{
 861	buf->active_dma = DMA_Y;
 862	if (buf->nb_planes == 3)
 863		buf->active_dma |= DMA_U | DMA_V;
 864}
 865
 866/**
 867 * pxa_dma_start_channels - start DMA channel for active buffer
 868 * @pcdev: pxa camera device
 869 *
 870 * Initialize DMA channels to the beginning of the active video buffer, and
 871 * start these channels.
 872 */
 873static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
 874{
 875	int i;
 876
 877	for (i = 0; i < pcdev->channels; i++) {
 878		dev_dbg(pcdev_to_dev(pcdev),
 879			"%s (channel=%d)\n", __func__, i);
 880		dma_async_issue_pending(pcdev->dma_chans[i]);
 881	}
 882}
 883
 884static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
 885{
 886	int i;
 887
 888	for (i = 0; i < pcdev->channels; i++) {
 889		dev_dbg(pcdev_to_dev(pcdev),
 890			"%s (channel=%d)\n", __func__, i);
 891		dmaengine_terminate_all(pcdev->dma_chans[i]);
 892	}
 893}
 894
 895static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
 896				 struct pxa_buffer *buf)
 897{
 898	int i;
 899
 900	for (i = 0; i < pcdev->channels; i++) {
 901		buf->cookie[i] = dmaengine_submit(buf->descs[i]);
 902		dev_dbg(pcdev_to_dev(pcdev),
 903			"%s (channel=%d) : submit vb=%p cookie=%d\n",
 904			__func__, i, buf, buf->descs[i]->cookie);
 905	}
 906}
 907
 908/**
 909 * pxa_camera_start_capture - start video capturing
 910 * @pcdev: camera device
 911 *
 912 * Launch capturing. DMA channels should not be active yet. They should get
 913 * activated at the end of frame interrupt, to capture only whole frames, and
 914 * never begin the capture of a partial frame.
 915 */
 916static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
 917{
 918	unsigned long cicr0;
 919
 920	dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
 921	__raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR);
 922	/* Enable End-Of-Frame Interrupt */
 923	cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
 924	cicr0 &= ~CICR0_EOFM;
 925	__raw_writel(cicr0, pcdev->base + CICR0);
 926}
 927
 928static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
 929{
 930	unsigned long cicr0;
 931
 932	pxa_dma_stop_channels(pcdev);
 933
 934	cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
 935	__raw_writel(cicr0, pcdev->base + CICR0);
 936
 937	pcdev->active = NULL;
 938	dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
 939}
 940
 941static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
 942			      struct pxa_buffer *buf,
 943			      enum vb2_buffer_state state)
 944{
 945	struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
 946	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 947
 948	/* _init is used to debug races, see comment in pxa_camera_reqbufs() */
 949	list_del_init(&buf->queue);
 950	vb->timestamp = ktime_get_ns();
 951	vbuf->sequence = pcdev->buf_sequence++;
 952	vbuf->field = V4L2_FIELD_NONE;
 953	vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
 954	dev_dbg(pcdev_to_dev(pcdev), "%s dequeued buffer (buf=0x%p)\n",
 955		__func__, buf);
 956
 957	if (list_empty(&pcdev->capture)) {
 958		pxa_camera_stop_capture(pcdev);
 959		return;
 960	}
 961
 962	pcdev->active = list_entry(pcdev->capture.next,
 963				   struct pxa_buffer, queue);
 964}
 965
 966/**
 967 * pxa_camera_check_link_miss - check missed DMA linking
 968 * @pcdev: camera device
 969 * @last_submitted: an opaque DMA cookie for last submitted
 970 * @last_issued: an opaque DMA cookie for last issued
 971 *
 972 * The DMA chaining is done with DMA running. This means a tiny temporal window
 973 * remains, where a buffer is queued on the chain, while the chain is already
 974 * stopped. This means the tailed buffer would never be transferred by DMA.
 975 * This function restarts the capture for this corner case, where :
 976 *  - DADR() == DADDR_STOP
 977 *  - a video buffer is queued on the pcdev->capture list
 978 *
 979 * Please check the "DMA hot chaining timeslice issue" in
 980 *   Documentation/driver-api/media/drivers/pxa_camera.rst
 981 *
 982 * Context: should only be called within the dma irq handler
 983 */
 984static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev,
 985				       dma_cookie_t last_submitted,
 986				       dma_cookie_t last_issued)
 987{
 988	bool is_dma_stopped = last_submitted != last_issued;
 989
 990	dev_dbg(pcdev_to_dev(pcdev),
 991		"%s : top queued buffer=%p, is_dma_stopped=%d\n",
 992		__func__, pcdev->active, is_dma_stopped);
 993
 994	if (pcdev->active && is_dma_stopped)
 995		pxa_camera_start_capture(pcdev);
 996}
 997
 998static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
 999			       enum pxa_camera_active_dma act_dma)
1000{
1001	struct pxa_buffer *buf, *last_buf;
1002	unsigned long flags;
1003	u32 camera_status, overrun;
1004	int chan;
1005	enum dma_status last_status;
1006	dma_cookie_t last_issued;
1007
1008	spin_lock_irqsave(&pcdev->lock, flags);
1009
1010	camera_status = __raw_readl(pcdev->base + CISR);
1011	dev_dbg(pcdev_to_dev(pcdev), "camera dma irq, cisr=0x%x dma=%d\n",
1012		camera_status, act_dma);
1013	overrun = CISR_IFO_0;
1014	if (pcdev->channels == 3)
1015		overrun |= CISR_IFO_1 | CISR_IFO_2;
1016
1017	/*
1018	 * pcdev->active should not be NULL in DMA irq handler.
1019	 *
1020	 * But there is one corner case : if capture was stopped due to an
1021	 * overrun of channel 1, and at that same channel 2 was completed.
1022	 *
1023	 * When handling the overrun in DMA irq for channel 1, we'll stop the
1024	 * capture and restart it (and thus set pcdev->active to NULL). But the
1025	 * DMA irq handler will already be pending for channel 2. So on entering
1026	 * the DMA irq handler for channel 2 there will be no active buffer, yet
1027	 * that is normal.
1028	 */
1029	if (!pcdev->active)
1030		goto out;
1031
1032	buf = pcdev->active;
1033	WARN_ON(buf->inwork || list_empty(&buf->queue));
1034
1035	/*
1036	 * It's normal if the last frame creates an overrun, as there
1037	 * are no more DMA descriptors to fetch from QCI fifos
1038	 */
1039	switch (act_dma) {
1040	case DMA_U:
1041		chan = 1;
1042		break;
1043	case DMA_V:
1044		chan = 2;
1045		break;
1046	default:
1047		chan = 0;
1048		break;
1049	}
1050	last_buf = list_entry(pcdev->capture.prev,
1051			      struct pxa_buffer, queue);
1052	last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan],
1053					       last_buf->cookie[chan],
1054					       NULL, &last_issued);
1055	if (camera_status & overrun &&
1056	    last_status != DMA_COMPLETE) {
1057		dev_dbg(pcdev_to_dev(pcdev), "FIFO overrun! CISR: %x\n",
1058			camera_status);
1059		pxa_camera_stop_capture(pcdev);
1060		list_for_each_entry(buf, &pcdev->capture, queue)
1061			pxa_dma_add_tail_buf(pcdev, buf);
1062		pxa_camera_start_capture(pcdev);
1063		goto out;
1064	}
1065	buf->active_dma &= ~act_dma;
1066	if (!buf->active_dma) {
1067		pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_DONE);
1068		pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan],
1069					   last_issued);
1070	}
1071
1072out:
1073	spin_unlock_irqrestore(&pcdev->lock, flags);
1074}
1075
1076static u32 mclk_get_divisor(struct platform_device *pdev,
1077			    struct pxa_camera_dev *pcdev)
1078{
1079	unsigned long mclk = pcdev->mclk;
1080	u32 div;
1081	unsigned long lcdclk;
1082
1083	lcdclk = clk_get_rate(pcdev->clk);
1084	pcdev->ciclk = lcdclk;
1085
1086	/* mclk <= ciclk / 4 (27.4.2) */
1087	if (mclk > lcdclk / 4) {
1088		mclk = lcdclk / 4;
1089		dev_warn(&pdev->dev,
1090			 "Limiting master clock to %lu\n", mclk);
1091	}
1092
1093	/* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
1094	div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
1095
1096	/* If we're not supplying MCLK, leave it at 0 */
1097	if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1098		pcdev->mclk = lcdclk / (2 * (div + 1));
1099
1100	dev_dbg(&pdev->dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
1101		lcdclk, mclk, div);
1102
1103	return div;
1104}
1105
1106static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
1107				     unsigned long pclk)
1108{
1109	/* We want a timeout > 1 pixel time, not ">=" */
1110	u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
1111
1112	__raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
1113}
1114
1115static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
1116{
1117	u32 cicr4 = 0;
1118
1119	/* disable all interrupts */
1120	__raw_writel(0x3ff, pcdev->base + CICR0);
1121
1122	if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1123		cicr4 |= CICR4_PCLK_EN;
1124	if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1125		cicr4 |= CICR4_MCLK_EN;
1126	if (pcdev->platform_flags & PXA_CAMERA_PCP)
1127		cicr4 |= CICR4_PCP;
1128	if (pcdev->platform_flags & PXA_CAMERA_HSP)
1129		cicr4 |= CICR4_HSP;
1130	if (pcdev->platform_flags & PXA_CAMERA_VSP)
1131		cicr4 |= CICR4_VSP;
1132
1133	__raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
1134
1135	if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1136		/* Initialise the timeout under the assumption pclk = mclk */
1137		recalculate_fifo_timeout(pcdev, pcdev->mclk);
1138	else
1139		/* "Safe default" - 13MHz */
1140		recalculate_fifo_timeout(pcdev, 13000000);
1141
1142	clk_prepare_enable(pcdev->clk);
1143}
1144
1145static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
1146{
1147	clk_disable_unprepare(pcdev->clk);
1148}
1149
1150static void pxa_camera_eof_bh_work(struct work_struct *t)
1151{
1152	struct pxa_camera_dev *pcdev = from_work(pcdev, t, eof_bh_work);
1153	unsigned long cifr;
1154	struct pxa_buffer *buf;
1155
1156	dev_dbg(pcdev_to_dev(pcdev),
1157		"Camera interrupt status 0x%x\n",
1158		__raw_readl(pcdev->base + CISR));
1159
1160	/* Reset the FIFOs */
1161	cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
1162	__raw_writel(cifr, pcdev->base + CIFR);
1163
1164	pcdev->active = list_first_entry(&pcdev->capture,
1165					 struct pxa_buffer, queue);
1166	buf = pcdev->active;
1167	pxa_video_buf_set_actdma(pcdev, buf);
1168
1169	pxa_dma_start_channels(pcdev);
1170}
1171
1172static irqreturn_t pxa_camera_irq(int irq, void *data)
1173{
1174	struct pxa_camera_dev *pcdev = data;
1175	unsigned long status, cicr0;
1176
1177	status = __raw_readl(pcdev->base + CISR);
1178	dev_dbg(pcdev_to_dev(pcdev),
1179		"Camera interrupt status 0x%lx\n", status);
1180
1181	if (!status)
1182		return IRQ_NONE;
1183
1184	__raw_writel(status, pcdev->base + CISR);
1185
1186	if (status & CISR_EOF) {
1187		cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
1188		__raw_writel(cicr0, pcdev->base + CICR0);
1189		queue_work(system_bh_wq, &pcdev->eof_bh_work);
1190	}
1191
1192	return IRQ_HANDLED;
1193}
1194
1195static void pxa_camera_setup_cicr(struct pxa_camera_dev *pcdev,
1196				  unsigned long flags, __u32 pixfmt)
1197{
1198	unsigned long dw, bpp;
1199	u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
1200	int ret = sensor_call(pcdev, sensor, g_skip_top_lines, &y_skip_top);
1201
1202	if (ret < 0)
1203		y_skip_top = 0;
1204
1205	/*
1206	 * Datawidth is now guaranteed to be equal to one of the three values.
1207	 * We fix bit-per-pixel equal to data-width...
1208	 */
1209	switch (pcdev->current_fmt->host_fmt->bits_per_sample) {
1210	case 10:
1211		dw = 4;
1212		bpp = 0x40;
1213		break;
1214	case 9:
1215		dw = 3;
1216		bpp = 0x20;
1217		break;
1218	default:
1219		/*
1220		 * Actually it can only be 8 now,
1221		 * default is just to silence compiler warnings
1222		 */
1223	case 8:
1224		dw = 2;
1225		bpp = 0;
1226	}
1227
1228	if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1229		cicr4 |= CICR4_PCLK_EN;
1230	if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1231		cicr4 |= CICR4_MCLK_EN;
1232	if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1233		cicr4 |= CICR4_PCP;
1234	if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1235		cicr4 |= CICR4_HSP;
1236	if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1237		cicr4 |= CICR4_VSP;
1238
1239	cicr0 = __raw_readl(pcdev->base + CICR0);
1240	if (cicr0 & CICR0_ENB)
1241		__raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1242
1243	cicr1 = CICR1_PPL_VAL(pcdev->current_pix.width - 1) | bpp | dw;
1244
1245	switch (pixfmt) {
1246	case V4L2_PIX_FMT_YUV422P:
1247		pcdev->channels = 3;
1248		cicr1 |= CICR1_YCBCR_F;
1249		/*
1250		 * Normally, pxa bus wants as input UYVY format. We allow all
1251		 * reorderings of the YUV422 format, as no processing is done,
1252		 * and the YUV stream is just passed through without any
1253		 * transformation. Note that UYVY is the only format that
1254		 * should be used if pxa framebuffer Overlay2 is used.
1255		 */
1256		fallthrough;
1257	case V4L2_PIX_FMT_UYVY:
1258	case V4L2_PIX_FMT_VYUY:
1259	case V4L2_PIX_FMT_YUYV:
1260	case V4L2_PIX_FMT_YVYU:
1261		cicr1 |= CICR1_COLOR_SP_VAL(2);
1262		break;
1263	case V4L2_PIX_FMT_RGB555:
1264		cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1265			CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1266		break;
1267	case V4L2_PIX_FMT_RGB565:
1268		cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1269		break;
1270	}
1271
1272	cicr2 = 0;
1273	cicr3 = CICR3_LPF_VAL(pcdev->current_pix.height - 1) |
1274		CICR3_BFW_VAL(min((u32)255, y_skip_top));
1275	cicr4 |= pcdev->mclk_divisor;
1276
1277	__raw_writel(cicr1, pcdev->base + CICR1);
1278	__raw_writel(cicr2, pcdev->base + CICR2);
1279	__raw_writel(cicr3, pcdev->base + CICR3);
1280	__raw_writel(cicr4, pcdev->base + CICR4);
1281
1282	/* CIF interrupts are not used, only DMA */
1283	cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1284		CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1285	cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1286	__raw_writel(cicr0, pcdev->base + CICR0);
1287}
1288
1289/*
1290 * Videobuf2 section
1291 */
1292static void pxa_buffer_cleanup(struct pxa_buffer *buf)
1293{
1294	int i;
1295
1296	for (i = 0; i < 3 && buf->descs[i]; i++) {
1297		dmaengine_desc_free(buf->descs[i]);
1298		kfree(buf->sg[i]);
1299		buf->descs[i] = NULL;
1300		buf->sg[i] = NULL;
1301		buf->sg_len[i] = 0;
1302		buf->plane_sizes[i] = 0;
1303	}
1304	buf->nb_planes = 0;
1305}
1306
1307static int pxa_buffer_init(struct pxa_camera_dev *pcdev,
1308			   struct pxa_buffer *buf)
1309{
1310	struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
1311	struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
1312	int nb_channels = pcdev->channels;
1313	int i, ret = 0;
1314	unsigned long size = vb2_plane_size(vb, 0);
1315
1316	switch (nb_channels) {
1317	case 1:
1318		buf->plane_sizes[0] = size;
1319		break;
1320	case 3:
1321		buf->plane_sizes[0] = size / 2;
1322		buf->plane_sizes[1] = size / 4;
1323		buf->plane_sizes[2] = size / 4;
1324		break;
1325	default:
1326		return -EINVAL;
1327	}
1328	buf->nb_planes = nb_channels;
1329
1330	ret = sg_split(sgt->sgl, sgt->nents, 0, nb_channels,
1331		       buf->plane_sizes, buf->sg, buf->sg_len, GFP_KERNEL);
1332	if (ret < 0) {
1333		dev_err(pcdev_to_dev(pcdev),
1334			"sg_split failed: %d\n", ret);
1335		return ret;
1336	}
1337	for (i = 0; i < nb_channels; i++) {
1338		ret = pxa_init_dma_channel(pcdev, buf, i,
1339					   buf->sg[i], buf->sg_len[i]);
1340		if (ret) {
1341			pxa_buffer_cleanup(buf);
1342			return ret;
1343		}
1344	}
1345	INIT_LIST_HEAD(&buf->queue);
1346
1347	return ret;
1348}
1349
1350static void pxac_vb2_cleanup(struct vb2_buffer *vb)
1351{
1352	struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1353	struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1354
1355	dev_dbg(pcdev_to_dev(pcdev),
1356		 "%s(vb=%p)\n", __func__, vb);
1357	pxa_buffer_cleanup(buf);
1358}
1359
1360static void pxac_vb2_queue(struct vb2_buffer *vb)
1361{
1362	struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1363	struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1364
1365	dev_dbg(pcdev_to_dev(pcdev),
1366		 "%s(vb=%p) nb_channels=%d size=%lu active=%p\n",
1367		__func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0),
1368		pcdev->active);
1369
1370	list_add_tail(&buf->queue, &pcdev->capture);
1371
1372	pxa_dma_add_tail_buf(pcdev, buf);
1373}
1374
1375/*
1376 * Please check the DMA prepared buffer structure in :
1377 *   Documentation/driver-api/media/drivers/pxa_camera.rst
1378 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
1379 * modification while DMA chain is running will work anyway.
1380 */
1381static int pxac_vb2_prepare(struct vb2_buffer *vb)
1382{
1383	struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1384	struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1385	int ret = 0;
1386#ifdef DEBUG
1387	int i;
1388#endif
1389
1390	switch (pcdev->channels) {
1391	case 1:
1392	case 3:
1393		vb2_set_plane_payload(vb, 0, pcdev->current_pix.sizeimage);
1394		break;
1395	default:
1396		return -EINVAL;
1397	}
1398
1399	dev_dbg(pcdev_to_dev(pcdev),
1400		 "%s (vb=%p) nb_channels=%d size=%lu\n",
1401		__func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0));
1402
1403	WARN_ON(!pcdev->current_fmt);
1404
1405#ifdef DEBUG
1406	/*
1407	 * This can be useful if you want to see if we actually fill
1408	 * the buffer with something
1409	 */
1410	for (i = 0; i < vb->num_planes; i++)
1411		memset((void *)vb2_plane_vaddr(vb, i),
1412		       0xaa, vb2_get_plane_payload(vb, i));
1413#endif
1414
1415	/*
1416	 * I think, in buf_prepare you only have to protect global data,
1417	 * the actual buffer is yours
1418	 */
1419	buf->inwork = 0;
1420	pxa_video_buf_set_actdma(pcdev, buf);
1421
1422	return ret;
1423}
1424
1425static int pxac_vb2_init(struct vb2_buffer *vb)
1426{
1427	struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1428	struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1429
1430	dev_dbg(pcdev_to_dev(pcdev),
1431		 "%s(nb_channels=%d)\n",
1432		__func__, pcdev->channels);
1433
1434	return pxa_buffer_init(pcdev, buf);
1435}
1436
1437static int pxac_vb2_queue_setup(struct vb2_queue *vq,
1438				unsigned int *nbufs,
1439				unsigned int *num_planes, unsigned int sizes[],
1440				struct device *alloc_devs[])
1441{
1442	struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1443	int size = pcdev->current_pix.sizeimage;
1444
1445	dev_dbg(pcdev_to_dev(pcdev),
1446		 "%s(vq=%p nbufs=%d num_planes=%d size=%d)\n",
1447		__func__, vq, *nbufs, *num_planes, size);
1448	/*
1449	 * Called from VIDIOC_REQBUFS or in compatibility mode For YUV422P
1450	 * format, even if there are 3 planes Y, U and V, we reply there is only
1451	 * one plane, containing Y, U and V data, one after the other.
1452	 */
1453	if (*num_planes)
1454		return sizes[0] < size ? -EINVAL : 0;
1455
1456	*num_planes = 1;
1457	switch (pcdev->channels) {
1458	case 1:
1459	case 3:
1460		sizes[0] = size;
1461		break;
1462	default:
1463		return -EINVAL;
1464	}
1465
1466	if (!*nbufs)
1467		*nbufs = 1;
1468
1469	return 0;
1470}
1471
1472static int pxac_vb2_start_streaming(struct vb2_queue *vq, unsigned int count)
1473{
1474	struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1475
1476	dev_dbg(pcdev_to_dev(pcdev), "%s(count=%d) active=%p\n",
1477		__func__, count, pcdev->active);
1478
1479	pcdev->buf_sequence = 0;
1480	if (!pcdev->active)
1481		pxa_camera_start_capture(pcdev);
1482
1483	return 0;
1484}
1485
1486static void pxac_vb2_stop_streaming(struct vb2_queue *vq)
1487{
1488	struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1489	struct pxa_buffer *buf, *tmp;
1490
1491	dev_dbg(pcdev_to_dev(pcdev), "%s active=%p\n",
1492		__func__, pcdev->active);
1493	pxa_camera_stop_capture(pcdev);
1494
1495	list_for_each_entry_safe(buf, tmp, &pcdev->capture, queue)
1496		pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_ERROR);
1497}
1498
1499static const struct vb2_ops pxac_vb2_ops = {
1500	.queue_setup		= pxac_vb2_queue_setup,
1501	.buf_init		= pxac_vb2_init,
1502	.buf_prepare		= pxac_vb2_prepare,
1503	.buf_queue		= pxac_vb2_queue,
1504	.buf_cleanup		= pxac_vb2_cleanup,
1505	.start_streaming	= pxac_vb2_start_streaming,
1506	.stop_streaming		= pxac_vb2_stop_streaming,
1507};
1508
1509static int pxa_camera_init_videobuf2(struct pxa_camera_dev *pcdev)
1510{
1511	int ret;
1512	struct vb2_queue *vq = &pcdev->vb2_vq;
1513
1514	memset(vq, 0, sizeof(*vq));
1515	vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1516	vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
1517	vq->drv_priv = pcdev;
1518	vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1519	vq->buf_struct_size = sizeof(struct pxa_buffer);
1520	vq->dev = pcdev->v4l2_dev.dev;
1521
1522	vq->ops = &pxac_vb2_ops;
1523	vq->mem_ops = &vb2_dma_sg_memops;
1524	vq->lock = &pcdev->mlock;
1525
1526	ret = vb2_queue_init(vq);
1527	dev_dbg(pcdev_to_dev(pcdev),
1528		 "vb2_queue_init(vq=%p): %d\n", vq, ret);
1529
1530	return ret;
1531}
1532
1533/*
1534 * Video ioctls section
1535 */
1536static int pxa_camera_set_bus_param(struct pxa_camera_dev *pcdev)
1537{
1538	unsigned int bus_width = pcdev->current_fmt->host_fmt->bits_per_sample;
1539	struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1540	u32 pixfmt = pcdev->current_fmt->host_fmt->fourcc;
1541	int mbus_config;
1542	int ret;
1543
1544	if (!((1 << (bus_width - 1)) & pcdev->width_flags)) {
1545		dev_err(pcdev_to_dev(pcdev), "Unsupported bus width %u",
1546			bus_width);
1547		return -EINVAL;
1548	}
1549
1550	pcdev->channels = 1;
1551
1552	/* Make choices, based on platform preferences */
1553	mbus_config = 0;
1554	if (pcdev->platform_flags & PXA_CAMERA_MASTER)
1555		mbus_config |= V4L2_MBUS_MASTER;
1556	else
1557		mbus_config |= V4L2_MBUS_SLAVE;
1558
1559	if (pcdev->platform_flags & PXA_CAMERA_HSP)
1560		mbus_config |= V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1561	else
1562		mbus_config |= V4L2_MBUS_HSYNC_ACTIVE_LOW;
1563
1564	if (pcdev->platform_flags & PXA_CAMERA_VSP)
1565		mbus_config |= V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1566	else
1567		mbus_config |= V4L2_MBUS_VSYNC_ACTIVE_LOW;
1568
1569	if (pcdev->platform_flags & PXA_CAMERA_PCP)
1570		mbus_config |= V4L2_MBUS_PCLK_SAMPLE_RISING;
1571	else
1572		mbus_config |= V4L2_MBUS_PCLK_SAMPLE_FALLING;
1573	mbus_config |= V4L2_MBUS_DATA_ACTIVE_HIGH;
1574
1575	ret = sensor_call(pcdev, pad, get_mbus_config, 0, &cfg);
1576	if (ret < 0 && ret != -ENOIOCTLCMD) {
1577		dev_err(pcdev_to_dev(pcdev),
1578			"Failed to call get_mbus_config: %d\n", ret);
1579		return ret;
1580	}
1581
1582	/*
1583	 * If the media bus configuration of the sensor differs, make sure it
1584	 * is supported by the platform.
1585	 *
1586	 * PXA does not support V4L2_MBUS_DATA_ACTIVE_LOW and the bus mastering
1587	 * roles should match.
1588	 */
1589	if (cfg.bus.parallel.flags != mbus_config) {
1590		unsigned int pxa_mbus_role = mbus_config & (V4L2_MBUS_MASTER |
1591							    V4L2_MBUS_SLAVE);
1592		unsigned int flags = cfg.bus.parallel.flags;
1593
1594		if (pxa_mbus_role != (flags & (V4L2_MBUS_MASTER |
1595					       V4L2_MBUS_SLAVE))) {
1596			dev_err(pcdev_to_dev(pcdev),
1597				"Unsupported mbus configuration: bus mastering\n");
1598			return -EINVAL;
1599		}
1600
1601		if (flags & V4L2_MBUS_DATA_ACTIVE_LOW) {
1602			dev_err(pcdev_to_dev(pcdev),
1603				"Unsupported mbus configuration: DATA_ACTIVE_LOW\n");
1604			return -EINVAL;
1605		}
1606	}
1607
1608	pxa_camera_setup_cicr(pcdev, cfg.bus.parallel.flags, pixfmt);
1609
1610	return 0;
1611}
1612
1613static const struct pxa_mbus_pixelfmt pxa_camera_formats[] = {
1614	{
1615		.fourcc			= V4L2_PIX_FMT_YUV422P,
1616		.name			= "Planar YUV422 16 bit",
1617		.bits_per_sample	= 8,
1618		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
1619		.order			= PXA_MBUS_ORDER_LE,
1620		.layout			= PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
1621	},
1622};
1623
1624/* This will be corrected as we get more formats */
1625static bool pxa_camera_packing_supported(const struct pxa_mbus_pixelfmt *fmt)
1626{
1627	return	fmt->packing == PXA_MBUS_PACKING_NONE ||
1628		(fmt->bits_per_sample == 8 &&
1629		 fmt->packing == PXA_MBUS_PACKING_2X8_PADHI) ||
1630		(fmt->bits_per_sample > 8 &&
1631		 fmt->packing == PXA_MBUS_PACKING_EXTEND16);
1632}
1633
1634static int pxa_camera_get_formats(struct v4l2_device *v4l2_dev,
1635				  unsigned int idx,
1636				  struct pxa_camera_format_xlate *xlate)
1637{
1638	struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
1639	int formats = 0, ret;
1640	struct v4l2_subdev_mbus_code_enum code = {
1641		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
1642		.index = idx,
1643	};
1644	const struct pxa_mbus_pixelfmt *fmt;
1645
1646	ret = sensor_call(pcdev, pad, enum_mbus_code, NULL, &code);
1647	if (ret < 0)
1648		/* No more formats */
1649		return 0;
1650
1651	fmt = pxa_mbus_get_fmtdesc(code.code);
1652	if (!fmt) {
1653		dev_err(pcdev_to_dev(pcdev),
1654			"Invalid format code #%u: %d\n", idx, code.code);
1655		return 0;
1656	}
1657
1658	switch (code.code) {
1659	case MEDIA_BUS_FMT_UYVY8_2X8:
1660		formats++;
1661		if (xlate) {
1662			xlate->host_fmt	= &pxa_camera_formats[0];
1663			xlate->code	= code.code;
1664			xlate++;
1665			dev_dbg(pcdev_to_dev(pcdev),
1666				"Providing format %s using code %d\n",
1667				pxa_camera_formats[0].name, code.code);
1668		}
1669		fallthrough;
1670	case MEDIA_BUS_FMT_VYUY8_2X8:
1671	case MEDIA_BUS_FMT_YUYV8_2X8:
1672	case MEDIA_BUS_FMT_YVYU8_2X8:
1673	case MEDIA_BUS_FMT_RGB565_2X8_LE:
1674	case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
1675		if (xlate)
1676			dev_dbg(pcdev_to_dev(pcdev),
1677				"Providing format %s packed\n",
1678				fmt->name);
1679		break;
1680	default:
1681		if (!pxa_camera_packing_supported(fmt))
1682			return 0;
1683		if (xlate)
1684			dev_dbg(pcdev_to_dev(pcdev),
1685				"Providing format %s in pass-through mode\n",
1686				fmt->name);
1687		break;
1688	}
1689
1690	/* Generic pass-through */
1691	formats++;
1692	if (xlate) {
1693		xlate->host_fmt	= fmt;
1694		xlate->code	= code.code;
1695		xlate++;
1696	}
1697
1698	return formats;
1699}
1700
1701static int pxa_camera_build_formats(struct pxa_camera_dev *pcdev)
1702{
1703	struct pxa_camera_format_xlate *xlate;
1704
1705	xlate = pxa_mbus_build_fmts_xlate(&pcdev->v4l2_dev, pcdev->sensor,
1706					  pxa_camera_get_formats);
1707	if (IS_ERR(xlate))
1708		return PTR_ERR(xlate);
1709
1710	pcdev->user_formats = xlate;
1711	return 0;
1712}
1713
1714static void pxa_camera_destroy_formats(struct pxa_camera_dev *pcdev)
1715{
1716	kfree(pcdev->user_formats);
1717}
1718
1719static int pxa_camera_check_frame(u32 width, u32 height)
1720{
1721	/* limit to pxa hardware capabilities */
1722	return height < 32 || height > 2048 || width < 48 || width > 2048 ||
1723		(width & 0x01);
1724}
1725
1726#ifdef CONFIG_VIDEO_ADV_DEBUG
1727static int pxac_vidioc_g_register(struct file *file, void *priv,
1728				  struct v4l2_dbg_register *reg)
1729{
1730	struct pxa_camera_dev *pcdev = video_drvdata(file);
1731
1732	if (reg->reg > CIBR2)
1733		return -ERANGE;
1734
1735	reg->val = __raw_readl(pcdev->base + reg->reg);
1736	reg->size = sizeof(__u32);
1737	return 0;
1738}
1739
1740static int pxac_vidioc_s_register(struct file *file, void *priv,
1741				  const struct v4l2_dbg_register *reg)
1742{
1743	struct pxa_camera_dev *pcdev = video_drvdata(file);
1744
1745	if (reg->reg > CIBR2)
1746		return -ERANGE;
1747	if (reg->size != sizeof(__u32))
1748		return -EINVAL;
1749	__raw_writel(reg->val, pcdev->base + reg->reg);
1750	return 0;
1751}
1752#endif
1753
1754static int pxac_vidioc_enum_fmt_vid_cap(struct file *filp, void  *priv,
1755					struct v4l2_fmtdesc *f)
1756{
1757	struct pxa_camera_dev *pcdev = video_drvdata(filp);
1758	const struct pxa_mbus_pixelfmt *format;
1759	unsigned int idx;
1760
1761	for (idx = 0; pcdev->user_formats[idx].code; idx++);
1762	if (f->index >= idx)
1763		return -EINVAL;
1764
1765	format = pcdev->user_formats[f->index].host_fmt;
1766	f->pixelformat = format->fourcc;
1767	return 0;
1768}
1769
1770static int pxac_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
1771				    struct v4l2_format *f)
1772{
1773	struct pxa_camera_dev *pcdev = video_drvdata(filp);
1774	struct v4l2_pix_format *pix = &f->fmt.pix;
1775
1776	pix->width		= pcdev->current_pix.width;
1777	pix->height		= pcdev->current_pix.height;
1778	pix->bytesperline	= pcdev->current_pix.bytesperline;
1779	pix->sizeimage		= pcdev->current_pix.sizeimage;
1780	pix->field		= pcdev->current_pix.field;
1781	pix->pixelformat	= pcdev->current_fmt->host_fmt->fourcc;
1782	pix->colorspace		= pcdev->current_pix.colorspace;
1783	dev_dbg(pcdev_to_dev(pcdev), "current_fmt->fourcc: 0x%08x\n",
1784		pcdev->current_fmt->host_fmt->fourcc);
1785	return 0;
1786}
1787
1788static int pxac_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
1789				      struct v4l2_format *f)
1790{
1791	struct pxa_camera_dev *pcdev = video_drvdata(filp);
1792	const struct pxa_camera_format_xlate *xlate;
1793	struct v4l2_pix_format *pix = &f->fmt.pix;
1794	struct v4l2_subdev_pad_config pad_cfg;
1795	struct v4l2_subdev_state pad_state = {
1796		.pads = &pad_cfg,
1797	};
1798	struct v4l2_subdev_format format = {
1799		.which = V4L2_SUBDEV_FORMAT_TRY,
1800	};
1801	struct v4l2_mbus_framefmt *mf = &format.format;
1802	__u32 pixfmt = pix->pixelformat;
1803	int ret;
1804
1805	xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats, pixfmt);
1806	if (!xlate) {
1807		dev_warn(pcdev_to_dev(pcdev), "Format %x not found\n", pixfmt);
1808		return -EINVAL;
1809	}
1810
1811	/*
1812	 * Limit to pxa hardware capabilities.  YUV422P planar format requires
1813	 * images size to be a multiple of 16 bytes.  If not, zeros will be
1814	 * inserted between Y and U planes, and U and V planes, which violates
1815	 * the YUV422P standard.
1816	 */
1817	v4l_bound_align_image(&pix->width, 48, 2048, 1,
1818			      &pix->height, 32, 2048, 0,
1819			      pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1820
1821	v4l2_fill_mbus_format(mf, pix, xlate->code);
1822	ret = sensor_call(pcdev, pad, set_fmt, &pad_state, &format);
1823	if (ret < 0)
1824		return ret;
1825
1826	v4l2_fill_pix_format(pix, mf);
1827
1828	/* Only progressive video supported so far */
1829	switch (mf->field) {
1830	case V4L2_FIELD_ANY:
1831	case V4L2_FIELD_NONE:
1832		pix->field = V4L2_FIELD_NONE;
1833		break;
1834	default:
1835		/* TODO: support interlaced at least in pass-through mode */
1836		dev_err(pcdev_to_dev(pcdev), "Field type %d unsupported.\n",
1837			mf->field);
1838		return -EINVAL;
1839	}
1840
1841	ret = pxa_mbus_bytes_per_line(pix->width, xlate->host_fmt);
1842	if (ret < 0)
1843		return ret;
1844
1845	pix->bytesperline = ret;
1846	ret = pxa_mbus_image_size(xlate->host_fmt, pix->bytesperline,
1847				  pix->height);
1848	if (ret < 0)
1849		return ret;
1850
1851	pix->sizeimage = ret;
1852	return 0;
1853}
1854
1855static int pxac_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
1856				    struct v4l2_format *f)
1857{
1858	struct pxa_camera_dev *pcdev = video_drvdata(filp);
1859	const struct pxa_camera_format_xlate *xlate;
1860	struct v4l2_pix_format *pix = &f->fmt.pix;
1861	struct v4l2_subdev_format format = {
1862		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
1863	};
1864	unsigned long flags;
1865	int ret, is_busy;
1866
1867	dev_dbg(pcdev_to_dev(pcdev),
1868		"s_fmt_vid_cap(pix=%dx%d:%x)\n",
1869		pix->width, pix->height, pix->pixelformat);
1870
1871	spin_lock_irqsave(&pcdev->lock, flags);
1872	is_busy = pcdev->active || vb2_is_busy(&pcdev->vb2_vq);
1873	spin_unlock_irqrestore(&pcdev->lock, flags);
1874
1875	if (is_busy)
1876		return -EBUSY;
1877
1878	ret = pxac_vidioc_try_fmt_vid_cap(filp, priv, f);
1879	if (ret)
1880		return ret;
1881
1882	xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats,
1883					 pix->pixelformat);
1884	v4l2_fill_mbus_format(&format.format, pix, xlate->code);
1885	ret = sensor_call(pcdev, pad, set_fmt, NULL, &format);
1886	if (ret < 0) {
1887		dev_warn(pcdev_to_dev(pcdev),
1888			 "Failed to configure for format %x\n",
1889			 pix->pixelformat);
1890	} else if (pxa_camera_check_frame(pix->width, pix->height)) {
1891		dev_warn(pcdev_to_dev(pcdev),
1892			 "Camera driver produced an unsupported frame %dx%d\n",
1893			 pix->width, pix->height);
1894		return -EINVAL;
1895	}
1896
1897	pcdev->current_fmt = xlate;
1898	pcdev->current_pix = *pix;
1899
1900	ret = pxa_camera_set_bus_param(pcdev);
1901	return ret;
1902}
1903
1904static int pxac_vidioc_querycap(struct file *file, void *priv,
1905				struct v4l2_capability *cap)
1906{
1907	strscpy(cap->bus_info, "platform:pxa-camera", sizeof(cap->bus_info));
1908	strscpy(cap->driver, PXA_CAM_DRV_NAME, sizeof(cap->driver));
1909	strscpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1910	return 0;
1911}
1912
1913static int pxac_vidioc_enum_input(struct file *file, void *priv,
1914				  struct v4l2_input *i)
1915{
1916	if (i->index > 0)
1917		return -EINVAL;
1918
1919	i->type = V4L2_INPUT_TYPE_CAMERA;
1920	strscpy(i->name, "Camera", sizeof(i->name));
1921
1922	return 0;
1923}
1924
1925static int pxac_vidioc_g_input(struct file *file, void *priv, unsigned int *i)
1926{
1927	*i = 0;
1928
1929	return 0;
1930}
1931
1932static int pxac_vidioc_s_input(struct file *file, void *priv, unsigned int i)
1933{
1934	if (i > 0)
1935		return -EINVAL;
1936
1937	return 0;
1938}
1939
1940static int pxac_sensor_set_power(struct pxa_camera_dev *pcdev, int on)
1941{
1942	int ret;
1943
1944	ret = sensor_call(pcdev, core, s_power, on);
1945	if (ret == -ENOIOCTLCMD)
1946		ret = 0;
1947	if (ret) {
1948		dev_warn(pcdev_to_dev(pcdev),
1949			 "Failed to put subdevice in %s mode: %d\n",
1950			 on ? "normal operation" : "power saving", ret);
1951	}
1952
1953	return ret;
1954}
1955
1956static int pxac_fops_camera_open(struct file *filp)
1957{
1958	struct pxa_camera_dev *pcdev = video_drvdata(filp);
1959	int ret;
1960
1961	mutex_lock(&pcdev->mlock);
1962	ret = v4l2_fh_open(filp);
1963	if (ret < 0)
1964		goto out;
1965
1966	if (!v4l2_fh_is_singular_file(filp))
1967		goto out;
1968
1969	ret = pxac_sensor_set_power(pcdev, 1);
1970	if (ret)
1971		v4l2_fh_release(filp);
1972out:
1973	mutex_unlock(&pcdev->mlock);
1974	return ret;
1975}
1976
1977static int pxac_fops_camera_release(struct file *filp)
1978{
1979	struct pxa_camera_dev *pcdev = video_drvdata(filp);
1980	int ret;
1981	bool fh_singular;
1982
1983	mutex_lock(&pcdev->mlock);
1984
1985	fh_singular = v4l2_fh_is_singular_file(filp);
1986
1987	ret = _vb2_fop_release(filp, NULL);
1988
1989	if (fh_singular)
1990		ret = pxac_sensor_set_power(pcdev, 0);
1991
1992	mutex_unlock(&pcdev->mlock);
1993
1994	return ret;
1995}
1996
1997static const struct v4l2_file_operations pxa_camera_fops = {
1998	.owner		= THIS_MODULE,
1999	.open		= pxac_fops_camera_open,
2000	.release	= pxac_fops_camera_release,
2001	.read		= vb2_fop_read,
2002	.poll		= vb2_fop_poll,
2003	.mmap		= vb2_fop_mmap,
2004	.unlocked_ioctl = video_ioctl2,
2005};
2006
2007static const struct v4l2_ioctl_ops pxa_camera_ioctl_ops = {
2008	.vidioc_querycap		= pxac_vidioc_querycap,
2009
2010	.vidioc_enum_input		= pxac_vidioc_enum_input,
2011	.vidioc_g_input			= pxac_vidioc_g_input,
2012	.vidioc_s_input			= pxac_vidioc_s_input,
2013
2014	.vidioc_enum_fmt_vid_cap	= pxac_vidioc_enum_fmt_vid_cap,
2015	.vidioc_g_fmt_vid_cap		= pxac_vidioc_g_fmt_vid_cap,
2016	.vidioc_s_fmt_vid_cap		= pxac_vidioc_s_fmt_vid_cap,
2017	.vidioc_try_fmt_vid_cap		= pxac_vidioc_try_fmt_vid_cap,
2018
2019	.vidioc_reqbufs			= vb2_ioctl_reqbufs,
2020	.vidioc_create_bufs		= vb2_ioctl_create_bufs,
2021	.vidioc_querybuf		= vb2_ioctl_querybuf,
2022	.vidioc_qbuf			= vb2_ioctl_qbuf,
2023	.vidioc_dqbuf			= vb2_ioctl_dqbuf,
2024	.vidioc_expbuf			= vb2_ioctl_expbuf,
2025	.vidioc_streamon		= vb2_ioctl_streamon,
2026	.vidioc_streamoff		= vb2_ioctl_streamoff,
2027#ifdef CONFIG_VIDEO_ADV_DEBUG
2028	.vidioc_g_register		= pxac_vidioc_g_register,
2029	.vidioc_s_register		= pxac_vidioc_s_register,
2030#endif
2031	.vidioc_subscribe_event		= v4l2_ctrl_subscribe_event,
2032	.vidioc_unsubscribe_event	= v4l2_event_unsubscribe,
2033};
2034
2035static const struct video_device pxa_camera_videodev_template = {
2036	.name = "pxa-camera",
2037	.minor = -1,
2038	.fops = &pxa_camera_fops,
2039	.ioctl_ops = &pxa_camera_ioctl_ops,
2040	.release = video_device_release_empty,
2041	.device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING,
2042};
2043
2044static int pxa_camera_sensor_bound(struct v4l2_async_notifier *notifier,
2045		     struct v4l2_subdev *subdev,
2046		     struct v4l2_async_connection *asd)
2047{
2048	int err;
2049	struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
2050	struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
2051	struct video_device *vdev = &pcdev->vdev;
2052	struct v4l2_pix_format *pix = &pcdev->current_pix;
2053	struct v4l2_subdev_format format = {
2054		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
2055	};
2056	struct v4l2_mbus_framefmt *mf = &format.format;
2057
2058	dev_info(pcdev_to_dev(pcdev), "%s(): trying to bind a device\n",
2059		 __func__);
2060	mutex_lock(&pcdev->mlock);
2061	*vdev = pxa_camera_videodev_template;
2062	vdev->v4l2_dev = v4l2_dev;
2063	vdev->lock = &pcdev->mlock;
2064	pcdev->sensor = subdev;
2065	pcdev->vdev.queue = &pcdev->vb2_vq;
2066	pcdev->vdev.v4l2_dev = &pcdev->v4l2_dev;
2067	pcdev->vdev.ctrl_handler = subdev->ctrl_handler;
2068	video_set_drvdata(&pcdev->vdev, pcdev);
2069
2070	err = pxa_camera_build_formats(pcdev);
2071	if (err) {
2072		dev_err(pcdev_to_dev(pcdev), "building formats failed: %d\n",
2073			err);
2074		goto out;
2075	}
2076
2077	pcdev->current_fmt = pcdev->user_formats;
2078	pix->field = V4L2_FIELD_NONE;
2079	pix->width = DEFAULT_WIDTH;
2080	pix->height = DEFAULT_HEIGHT;
2081	pix->bytesperline =
2082		pxa_mbus_bytes_per_line(pix->width,
2083					pcdev->current_fmt->host_fmt);
2084	pix->sizeimage =
2085		pxa_mbus_image_size(pcdev->current_fmt->host_fmt,
2086				    pix->bytesperline, pix->height);
2087	pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
2088	v4l2_fill_mbus_format(mf, pix, pcdev->current_fmt->code);
2089
2090	err = pxac_sensor_set_power(pcdev, 1);
2091	if (err)
2092		goto out;
2093
2094	err = sensor_call(pcdev, pad, set_fmt, NULL, &format);
2095	if (err)
2096		goto out_sensor_poweroff;
2097
2098	v4l2_fill_pix_format(pix, mf);
2099	pr_info("%s(): colorspace=0x%x pixfmt=0x%x\n",
2100		__func__, pix->colorspace, pix->pixelformat);
2101
2102	err = pxa_camera_init_videobuf2(pcdev);
2103	if (err)
2104		goto out_sensor_poweroff;
2105
2106	err = video_register_device(&pcdev->vdev, VFL_TYPE_VIDEO, -1);
2107	if (err) {
2108		v4l2_err(v4l2_dev, "register video device failed: %d\n", err);
2109		pcdev->sensor = NULL;
2110	} else {
2111		dev_info(pcdev_to_dev(pcdev),
2112			 "PXA Camera driver attached to camera %s\n",
2113			 subdev->name);
2114	}
2115
2116out_sensor_poweroff:
2117	err = pxac_sensor_set_power(pcdev, 0);
2118out:
2119	mutex_unlock(&pcdev->mlock);
2120	return err;
2121}
2122
2123static void pxa_camera_sensor_unbind(struct v4l2_async_notifier *notifier,
2124		     struct v4l2_subdev *subdev,
2125		     struct v4l2_async_connection *asd)
2126{
2127	struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(notifier->v4l2_dev);
2128
2129	mutex_lock(&pcdev->mlock);
2130	dev_info(pcdev_to_dev(pcdev),
2131		 "PXA Camera driver detached from camera %s\n",
2132		 subdev->name);
2133
2134	/* disable capture, disable interrupts */
2135	__raw_writel(0x3ff, pcdev->base + CICR0);
2136
2137	/* Stop DMA engine */
2138	pxa_dma_stop_channels(pcdev);
2139
2140	pxa_camera_destroy_formats(pcdev);
2141
2142	video_unregister_device(&pcdev->vdev);
2143	pcdev->sensor = NULL;
2144
2145	mutex_unlock(&pcdev->mlock);
2146}
2147
2148static const struct v4l2_async_notifier_operations pxa_camera_sensor_ops = {
2149	.bound = pxa_camera_sensor_bound,
2150	.unbind = pxa_camera_sensor_unbind,
2151};
2152
2153/*
2154 * Driver probe, remove, suspend and resume operations
2155 */
2156static int pxa_camera_suspend(struct device *dev)
2157{
2158	struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2159	int i = 0, ret = 0;
2160
2161	pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
2162	pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
2163	pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
2164	pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
2165	pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
2166
2167	if (pcdev->sensor)
2168		ret = pxac_sensor_set_power(pcdev, 0);
2169
2170	return ret;
2171}
2172
2173static int pxa_camera_resume(struct device *dev)
2174{
2175	struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2176	int i = 0, ret = 0;
2177
2178	__raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
2179	__raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
2180	__raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
2181	__raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
2182	__raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
2183
2184	if (pcdev->sensor) {
2185		ret = pxac_sensor_set_power(pcdev, 1);
2186	}
2187
2188	/* Restart frame capture if active buffer exists */
2189	if (!ret && pcdev->active)
2190		pxa_camera_start_capture(pcdev);
2191
2192	return ret;
2193}
2194
2195static int pxa_camera_pdata_from_dt(struct device *dev,
2196				    struct pxa_camera_dev *pcdev)
2197{
2198	u32 mclk_rate;
2199	struct v4l2_async_connection *asd;
2200	struct device_node *np = dev->of_node;
2201	struct v4l2_fwnode_endpoint ep = { .bus_type = 0 };
2202	int err = of_property_read_u32(np, "clock-frequency",
2203				       &mclk_rate);
2204	if (!err) {
2205		pcdev->platform_flags |= PXA_CAMERA_MCLK_EN;
2206		pcdev->mclk = mclk_rate;
2207	}
2208
2209	np = of_graph_get_endpoint_by_regs(np, 0, -1);
2210	if (!np) {
2211		dev_err(dev, "could not find endpoint\n");
2212		return -EINVAL;
2213	}
2214
2215	err = v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &ep);
2216	if (err) {
2217		dev_err(dev, "could not parse endpoint\n");
2218		goto out;
2219	}
2220
2221	switch (ep.bus.parallel.bus_width) {
2222	case 4:
2223		pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4;
2224		break;
2225	case 5:
2226		pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5;
2227		break;
2228	case 8:
2229		pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8;
2230		break;
2231	case 9:
2232		pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9;
2233		break;
2234	case 10:
2235		pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2236		break;
2237	default:
2238		break;
2239	}
2240
2241	if (ep.bus.parallel.flags & V4L2_MBUS_MASTER)
2242		pcdev->platform_flags |= PXA_CAMERA_MASTER;
2243	if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2244		pcdev->platform_flags |= PXA_CAMERA_HSP;
2245	if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2246		pcdev->platform_flags |= PXA_CAMERA_VSP;
2247	if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2248		pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP;
2249	if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
2250		pcdev->platform_flags |= PXA_CAMERA_PCLK_EN;
2251
2252	asd = v4l2_async_nf_add_fwnode_remote(&pcdev->notifier,
2253					      of_fwnode_handle(np),
2254					      struct v4l2_async_connection);
2255	if (IS_ERR(asd))
2256		err = PTR_ERR(asd);
2257out:
2258	of_node_put(np);
2259
2260	return err;
2261}
2262
2263static int pxa_camera_probe(struct platform_device *pdev)
2264{
2265	struct pxa_camera_dev *pcdev;
2266	struct resource *res;
2267	void __iomem *base;
2268	struct dma_slave_config config = {
2269		.src_addr_width = 0,
2270		.src_maxburst = 8,
2271		.direction = DMA_DEV_TO_MEM,
2272	};
2273	int irq;
2274	int err = 0, i;
2275
2276	irq = platform_get_irq(pdev, 0);
2277	if (irq < 0)
2278		return -ENODEV;
2279
2280	pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
2281	if (!pcdev) {
2282		dev_err(&pdev->dev, "Could not allocate pcdev\n");
2283		return -ENOMEM;
2284	}
2285
2286	pcdev->clk = devm_clk_get(&pdev->dev, NULL);
2287	if (IS_ERR(pcdev->clk))
2288		return PTR_ERR(pcdev->clk);
2289
2290	/*
2291	 * Request the regions.
2292	 */
2293	base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2294	if (IS_ERR(base))
2295		return PTR_ERR(base);
2296
2297	pcdev->irq = irq;
2298	pcdev->base = base;
2299
2300	err = v4l2_device_register(&pdev->dev, &pcdev->v4l2_dev);
2301	if (err)
2302		return err;
2303
2304	v4l2_async_nf_init(&pcdev->notifier, &pcdev->v4l2_dev);
2305	pcdev->res = res;
2306	pcdev->pdata = pdev->dev.platform_data;
2307	if (pcdev->pdata) {
2308		struct v4l2_async_connection *asd;
2309
2310		pcdev->platform_flags = pcdev->pdata->flags;
2311		pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
2312		asd = v4l2_async_nf_add_i2c(&pcdev->notifier,
2313					    pcdev->pdata->sensor_i2c_adapter_id,
2314					    pcdev->pdata->sensor_i2c_address,
2315					    struct v4l2_async_connection);
2316		if (IS_ERR(asd))
2317			err = PTR_ERR(asd);
2318	} else if (pdev->dev.of_node) {
2319		err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev);
2320	} else {
2321		err = -ENODEV;
2322	}
2323	if (err < 0)
2324		goto exit_v4l2_device_unregister;
2325
2326	if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
2327			PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
2328		/*
2329		 * Platform hasn't set available data widths. This is bad.
2330		 * Warn and use a default.
2331		 */
2332		dev_warn(&pdev->dev, "WARNING! Platform hasn't set available data widths, using default 10 bit\n");
2333		pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2334	}
2335	if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)
2336		pcdev->width_flags = 1 << 7;
2337	if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)
2338		pcdev->width_flags |= 1 << 8;
2339	if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)
2340		pcdev->width_flags |= 1 << 9;
2341	if (!pcdev->mclk) {
2342		dev_warn(&pdev->dev,
2343			 "mclk == 0! Please, fix your platform data. Using default 20MHz\n");
2344		pcdev->mclk = 20000000;
2345	}
2346
2347	pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
2348
2349	INIT_LIST_HEAD(&pcdev->capture);
2350	spin_lock_init(&pcdev->lock);
2351	mutex_init(&pcdev->mlock);
2352
2353	/* request dma */
2354	pcdev->dma_chans[0] = dma_request_chan(&pdev->dev, "CI_Y");
2355	if (IS_ERR(pcdev->dma_chans[0])) {
2356		dev_err(&pdev->dev, "Can't request DMA for Y\n");
2357		err = PTR_ERR(pcdev->dma_chans[0]);
2358		goto exit_notifier_cleanup;
2359	}
2360
2361	pcdev->dma_chans[1] = dma_request_chan(&pdev->dev, "CI_U");
2362	if (IS_ERR(pcdev->dma_chans[1])) {
2363		dev_err(&pdev->dev, "Can't request DMA for U\n");
2364		err = PTR_ERR(pcdev->dma_chans[1]);
2365		goto exit_free_dma_y;
2366	}
2367
2368	pcdev->dma_chans[2] = dma_request_chan(&pdev->dev, "CI_V");
2369	if (IS_ERR(pcdev->dma_chans[2])) {
2370		dev_err(&pdev->dev, "Can't request DMA for V\n");
2371		err = PTR_ERR(pcdev->dma_chans[2]);
2372		goto exit_free_dma_u;
2373	}
2374
2375	for (i = 0; i < 3; i++) {
2376		config.src_addr = pcdev->res->start + CIBR0 + i * 8;
2377		err = dmaengine_slave_config(pcdev->dma_chans[i], &config);
2378		if (err < 0) {
2379			dev_err(&pdev->dev, "dma slave config failed: %d\n",
2380				err);
2381			goto exit_free_dma;
2382		}
2383	}
2384
2385	INIT_WORK(&pcdev->eof_bh_work, pxa_camera_eof_bh_work);
2386
2387	pxa_camera_activate(pcdev);
2388
2389	platform_set_drvdata(pdev, pcdev);
2390
2391	err = pxa_camera_init_videobuf2(pcdev);
2392	if (err)
2393		goto exit_deactivate;
2394
2395	/* request irq */
2396	err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0,
2397			       PXA_CAM_DRV_NAME, pcdev);
2398	if (err) {
2399		dev_err(&pdev->dev, "Camera interrupt register failed\n");
2400		goto exit_deactivate;
2401	}
2402
2403	pcdev->notifier.ops = &pxa_camera_sensor_ops;
2404	err = v4l2_async_nf_register(&pcdev->notifier);
2405	if (err)
2406		goto exit_deactivate;
2407
2408	return 0;
2409exit_deactivate:
2410	pxa_camera_deactivate(pcdev);
2411	cancel_work_sync(&pcdev->eof_bh_work);
2412exit_free_dma:
2413	dma_release_channel(pcdev->dma_chans[2]);
2414exit_free_dma_u:
2415	dma_release_channel(pcdev->dma_chans[1]);
2416exit_free_dma_y:
2417	dma_release_channel(pcdev->dma_chans[0]);
2418exit_notifier_cleanup:
2419	v4l2_async_nf_cleanup(&pcdev->notifier);
2420exit_v4l2_device_unregister:
2421	v4l2_device_unregister(&pcdev->v4l2_dev);
2422	return err;
2423}
2424
2425static void pxa_camera_remove(struct platform_device *pdev)
2426{
2427	struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev);
2428
2429	pxa_camera_deactivate(pcdev);
2430	cancel_work_sync(&pcdev->eof_bh_work);
2431	dma_release_channel(pcdev->dma_chans[0]);
2432	dma_release_channel(pcdev->dma_chans[1]);
2433	dma_release_channel(pcdev->dma_chans[2]);
2434
2435	v4l2_async_nf_unregister(&pcdev->notifier);
2436	v4l2_async_nf_cleanup(&pcdev->notifier);
2437
2438	v4l2_device_unregister(&pcdev->v4l2_dev);
2439
2440	dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
2441}
2442
2443static const struct dev_pm_ops pxa_camera_pm = {
2444	.suspend	= pxa_camera_suspend,
2445	.resume		= pxa_camera_resume,
2446};
2447
2448static const struct of_device_id pxa_camera_of_match[] = {
2449	{ .compatible = "marvell,pxa270-qci", },
2450	{},
2451};
2452MODULE_DEVICE_TABLE(of, pxa_camera_of_match);
2453
2454static struct platform_driver pxa_camera_driver = {
2455	.driver		= {
2456		.name	= PXA_CAM_DRV_NAME,
2457		.pm	= &pxa_camera_pm,
2458		.of_match_table = pxa_camera_of_match,
2459	},
2460	.probe		= pxa_camera_probe,
2461	.remove		= pxa_camera_remove,
2462};
2463
2464module_platform_driver(pxa_camera_driver);
2465
2466MODULE_DESCRIPTION("PXA27x Camera Driver");
2467MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
2468MODULE_LICENSE("GPL");
2469MODULE_VERSION(PXA_CAM_VERSION);
2470MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);