e5010-jpeg-enc-hw.h

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * Imagination E5010 JPEG Encoder driver.
 4 *
 5 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
 6 *
 7 * Author: David Huang <d-huang@ti.com>
 8 * Author: Devarsh Thakkar <devarsht@ti.com>
 9 */
10
11#ifndef _E5010_JPEG_ENC_HW_H
12#define _E5010_JPEG_ENC_HW_H
13
14#include "e5010-core-regs.h"
15#include "e5010-mmu-regs.h"
16
17int e5010_hw_enable_output_address_error_irq(void __iomem *core_offset, u32 enable);
18int e5010_hw_enable_picture_done_irq(void __iomem *core_offset, u32 enable);
19int e5010_hw_enable_auto_clock_gating(void __iomem *core_offset, u32 enable);
20int e5010_hw_enable_manual_clock_gating(void __iomem *core_offset, u32 enable);
21int e5010_hw_enable_crc_check(void __iomem *core_offset, u32 enable);
22int e5010_hw_set_input_source_to_memory(void __iomem *core_offset, u32 set);
23int e5010_hw_set_input_luma_addr(void __iomem *core_offset, u32 val);
24int e5010_hw_set_input_chroma_addr(void __iomem *core_offset, u32 val);
25int e5010_hw_set_output_base_addr(void __iomem *core_offset, u32 val);
26int e5010_hw_get_output_size(void __iomem *core_offset);
27int e5010_hw_set_horizontal_size(void __iomem *core_offset, u32 val);
28int e5010_hw_set_vertical_size(void __iomem *core_offset, u32 val);
29int e5010_hw_set_luma_stride(void __iomem *core_offset, u32 bytesperline);
30int e5010_hw_set_chroma_stride(void __iomem *core_offset, u32 bytesperline);
31int e5010_hw_set_input_subsampling(void __iomem *core_offset, u32 val);
32int e5010_hw_set_chroma_order(void __iomem *core_offset, u32 val);
33int e5010_hw_set_qpvalue(void __iomem *core_offset, u32 offset, u32 value);
34void e5010_reset(struct device *dev, void __iomem *core_offset, void __iomem *mmu_offset);
35void e5010_hw_set_output_max_size(void __iomem *core_offset, u32 val);
36void e5010_hw_clear_picture_done(void __iomem *core_offset, u32 clear);
37void e5010_hw_encode_start(void __iomem *core_offset, u32 start);
38void e5010_hw_clear_output_error(void __iomem *core_offset, u32 clear);
39void e5010_hw_bypass_mmu(void __iomem *mmu_base, u32 enable);
40bool e5010_hw_pic_done_irq(void __iomem *core_base);
41bool e5010_hw_output_address_irq(void __iomem *core_base);
42#endif