wave5.h

  1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
  2/*
  3 * Wave5 series multi-standard codec IP - wave5 backend definitions
  4 *
  5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC
  6 */
  7
  8#ifndef __WAVE5_FUNCTION_H__
  9#define __WAVE5_FUNCTION_H__
 10
 11#define WAVE5_SUBSAMPLED_ONE_SIZE(_w, _h)	(ALIGN((_w) / 4, 16) * ALIGN((_h) / 4, 8))
 12#define WAVE5_SUBSAMPLED_ONE_SIZE_AVC(_w, _h)	(ALIGN((_w) / 4, 32) * ALIGN((_h) / 4, 4))
 13
 14/*
 15 * Bitstream buffer option: Explicit End
 16 * When set to 1 the VPU assumes that the bitstream has at least one frame and
 17 * will read until the end of the bitstream buffer.
 18 * When set to 0 the VPU will not read the last few bytes.
 19 * This option can be set anytime but cannot be cleared during processing.
 20 * It can be set to force finish decoding even though there is not enough
 21 * bitstream data for a full frame.
 22 */
 23#define BSOPTION_ENABLE_EXPLICIT_END		BIT(0)
 24#define BSOPTION_HIGHLIGHT_STREAM_END		BIT(1)
 25/*
 26 * When RD_PTR_VALID_FLAG is 0 Wave515 ignores RD_PTR value and starts to
 27 * decode from the access unit end position of the last decoded picture in
 28 * bitstream buffer.
 29 */
 30#define BSOPTION_RD_PTR_VALID_FLAG		BIT(31)
 31
 32/*
 33 * Currently the driver only supports hardware with little endian but for source
 34 * picture format, the bitstream and the report parameter the hardware works
 35 * with the opposite endianness, thus hard-code big endian for the register
 36 * writes
 37 */
 38#define PIC_SRC_ENDIANNESS_BIG_ENDIAN		0xf
 39#define BITSTREAM_ENDIANNESS_BIG_ENDIAN		0xf
 40#define REPORT_PARAM_ENDIANNESS_BIG_ENDIAN	0xf
 41
 42#define WTL_RIGHT_JUSTIFIED          0
 43#define WTL_LEFT_JUSTIFIED           1
 44#define WTL_PIXEL_8BIT               0
 45#define WTL_PIXEL_16BIT              1
 46#define WTL_PIXEL_32BIT              2
 47
 48/* Mirror & rotation modes of the PRP (pre-processing) module */
 49#define NONE_ROTATE		0x0
 50#define ROT_CLOCKWISE_90	0x3
 51#define ROT_CLOCKWISE_180	0x5
 52#define ROT_CLOCKWISE_270	0x7
 53#define MIR_HOR_FLIP		0x11
 54#define MIR_VER_FLIP		0x9
 55#define MIR_HOR_VER_FLIP	(MIR_HOR_FLIP | MIR_VER_FLIP)
 56
 57bool wave5_vpu_is_init(struct vpu_device *vpu_dev);
 58
 59unsigned int wave5_vpu_get_product_id(struct vpu_device *vpu_dev);
 60
 61int wave5_vpu_get_version(struct vpu_device *vpu_dev, u32 *revision);
 62
 63int wave5_vpu_init(struct device *dev, u8 *fw, size_t size);
 64
 65int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uint16_t *code,
 66			 size_t size);
 67
 68int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode);
 69
 70int wave5_vpu_build_up_dec_param(struct vpu_instance *inst, struct dec_open_param *param);
 71
 72int wave5_vpu_dec_set_bitstream_flag(struct vpu_instance *inst, bool eos);
 73
 74int wave5_vpu_hw_flush_instance(struct vpu_instance *inst);
 75
 76int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst,
 77				       struct frame_buffer *fb_arr, enum tiled_map_type map_type,
 78				       unsigned int count);
 79
 80int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size);
 81
 82int wave5_vpu_dec_init_seq(struct vpu_instance *inst);
 83
 84int wave5_vpu_dec_get_seq_info(struct vpu_instance *inst, struct dec_initial_info *info);
 85
 86int wave5_vpu_decode(struct vpu_instance *inst, u32 *fail_res);
 87
 88int wave5_vpu_dec_get_result(struct vpu_instance *inst, struct dec_output_info *result);
 89
 90int wave5_vpu_dec_finish_seq(struct vpu_instance *inst, u32 *fail_res);
 91
 92int wave5_dec_clr_disp_flag(struct vpu_instance *inst, unsigned int index);
 93
 94int wave5_dec_set_disp_flag(struct vpu_instance *inst, unsigned int index);
 95
 96int wave5_vpu_clear_interrupt(struct vpu_instance *inst, u32 flags);
 97
 98dma_addr_t wave5_dec_get_rd_ptr(struct vpu_instance *inst);
 99
100int wave5_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr);
101
102/***< WAVE5 encoder >******/
103
104int wave5_vpu_build_up_enc_param(struct device *dev, struct vpu_instance *inst,
105				 struct enc_open_param *open_param);
106
107int wave5_vpu_enc_init_seq(struct vpu_instance *inst);
108
109int wave5_vpu_enc_get_seq_info(struct vpu_instance *inst, struct enc_initial_info *info);
110
111int wave5_vpu_enc_register_framebuffer(struct device *dev, struct vpu_instance *inst,
112				       struct frame_buffer *fb_arr, enum tiled_map_type map_type,
113				       unsigned int count);
114
115int wave5_vpu_encode(struct vpu_instance *inst, struct enc_param *option, u32 *fail_res);
116
117int wave5_vpu_enc_get_result(struct vpu_instance *inst, struct enc_output_info *result);
118
119int wave5_vpu_enc_finish_seq(struct vpu_instance *inst, u32 *fail_res);
120
121int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_param *open_param);
122
123#endif /* __WAVE5_FUNCTION_H__ */