wave5-vpuconfig.h

  1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
  2/*
  3 * Wave5 series multi-standard codec IP - product config definitions
  4 *
  5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC
  6 */
  7
  8#ifndef _VPU_CONFIG_H_
  9#define _VPU_CONFIG_H_
 10
 11#define WAVE515_CODE			0x5150
 12#define WAVE517_CODE                    0x5170
 13#define WAVE537_CODE                    0x5370
 14#define WAVE511_CODE                    0x5110
 15#define WAVE521_CODE                    0x5210
 16#define WAVE521C_CODE                   0x521c
 17#define WAVE521C_DUAL_CODE              0x521d  // wave521 dual core
 18#define WAVE521E1_CODE                  0x5211
 19
 20#define PRODUCT_CODE_W_SERIES(x) ({					\
 21		int c = x;						\
 22		((c) == WAVE517_CODE ||	(c) == WAVE537_CODE ||		\
 23		 (c) == WAVE511_CODE || (c) == WAVE521_CODE ||		\
 24		 (c) == WAVE521E1_CODE || (c) == WAVE521C_CODE ||	\
 25		 (c) == WAVE521C_DUAL_CODE) || (c) == WAVE515_CODE;	\
 26})
 27
 28#define WAVE517_WORKBUF_SIZE            (2 * 1024 * 1024)
 29#define WAVE521ENC_WORKBUF_SIZE         (128 * 1024)      //HEVC 128K, AVC 40K
 30#define WAVE521DEC_WORKBUF_SIZE         (1784 * 1024)
 31#define WAVE515DEC_WORKBUF_SIZE		(2 * 1024 * 1024)
 32
 33#define MAX_NUM_INSTANCE                32
 34
 35#define W5_DEF_DEC_PIC_WIDTH            720U
 36#define W5_DEF_DEC_PIC_HEIGHT           480U
 37#define W5_MIN_DEC_PIC_8_WIDTH          8U
 38#define W5_MIN_DEC_PIC_8_HEIGHT         8U
 39#define W5_MIN_DEC_PIC_32_WIDTH         32U
 40#define W5_MIN_DEC_PIC_32_HEIGHT        32U
 41#define W5_MAX_DEC_PIC_WIDTH            8192U
 42#define W5_MAX_DEC_PIC_HEIGHT           4320U
 43#define W5_DEC_CODEC_STEP_WIDTH         1U
 44#define W5_DEC_CODEC_STEP_HEIGHT        1U
 45#define W5_DEC_RAW_STEP_WIDTH           32U
 46#define W5_DEC_RAW_STEP_HEIGHT          16U
 47
 48#define W5_DEF_ENC_PIC_WIDTH            416U
 49#define W5_DEF_ENC_PIC_HEIGHT           240U
 50#define W5_MIN_ENC_PIC_WIDTH            256U
 51#define W5_MIN_ENC_PIC_HEIGHT           128U
 52#define W5_MAX_ENC_PIC_WIDTH            8192U
 53#define W5_MAX_ENC_PIC_HEIGHT           8192U
 54#define W5_ENC_CODEC_STEP_WIDTH         8U
 55#define W5_ENC_CODEC_STEP_HEIGHT        8U
 56#define W5_ENC_RAW_STEP_WIDTH           32U
 57#define W5_ENC_RAW_STEP_HEIGHT          16U
 58
 59//  application specific configuration
 60#define VPU_ENC_TIMEOUT                 60000
 61#define VPU_DEC_TIMEOUT                 60000
 62
 63// for WAVE encoder
 64#define USE_SRC_PRP_AXI         0
 65#define USE_SRC_PRI_AXI         1
 66#define DEFAULT_SRC_AXI         USE_SRC_PRP_AXI
 67
 68/************************************************************************/
 69/* VPU COMMON MEMORY                                                    */
 70/************************************************************************/
 71#define VLC_BUF_NUM                     (2)
 72
 73#define WAVE521_COMMAND_QUEUE_DEPTH	(2)
 74#define WAVE515_COMMAND_QUEUE_DEPTH	(4)
 75
 76#define W5_REMAP_INDEX0                 0
 77#define W5_REMAP_INDEX1                 1
 78#define W5_REMAP_MAX_SIZE               (1024 * 1024)
 79
 80#define WAVE521_MAX_CODE_BUF_SIZE	(2 * 1024 * 1024)
 81#define WAVE515_MAX_CODE_BUF_SIZE	(1024 * 1024)
 82#define WAVE5_TEMPBUF_SIZE              (1024 * 1024)
 83
 84#define WAVE521_SIZE_COMMON		(WAVE521_MAX_CODE_BUF_SIZE + WAVE5_TEMPBUF_SIZE)
 85#define WAVE515_ONE_TASKBUF_SIZE	(8 * 1024 * 1024)
 86#define WAVE515_SIZE_COMMON		(WAVE515_MAX_CODE_BUF_SIZE + WAVE5_TEMPBUF_SIZE + \
 87					 WAVE515_COMMAND_QUEUE_DEPTH * WAVE515_ONE_TASKBUF_SIZE)
 88
 89//=====4. VPU REPORT MEMORY  ======================//
 90
 91#define WAVE5_UPPER_PROC_AXI_ID     0x0
 92
 93#define WAVE5_PROC_AXI_ID           0x0
 94#define WAVE5_PRP_AXI_ID            0x0
 95#define WAVE5_FBD_Y_AXI_ID          0x0
 96#define WAVE5_FBC_Y_AXI_ID          0x0
 97#define WAVE5_FBD_C_AXI_ID          0x0
 98#define WAVE5_FBC_C_AXI_ID          0x0
 99#define WAVE5_SEC_AXI_ID            0x0
100#define WAVE5_PRI_AXI_ID            0x0
101
102#endif  /* _VPU_CONFIG_H_ */