wave5-vpuapi.h

  1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
  2/*
  3 * Wave5 series multi-standard codec IP - helper definitions
  4 *
  5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC
  6 */
  7
  8#ifndef VPUAPI_H_INCLUDED
  9#define VPUAPI_H_INCLUDED
 10
 11#include <linux/kfifo.h>
 12#include <linux/idr.h>
 13#include <linux/genalloc.h>
 14#include <media/v4l2-device.h>
 15#include <media/v4l2-mem2mem.h>
 16#include <media/v4l2-ctrls.h>
 17#include "wave5-vpuerror.h"
 18#include "wave5-vpuconfig.h"
 19#include "wave5-vdi.h"
 20
 21enum product_id {
 22	PRODUCT_ID_515,
 23	PRODUCT_ID_521,
 24	PRODUCT_ID_511,
 25	PRODUCT_ID_517,
 26	PRODUCT_ID_NONE,
 27};
 28
 29struct vpu_attr;
 30
 31enum vpu_instance_type {
 32	VPU_INST_TYPE_DEC = 0,
 33	VPU_INST_TYPE_ENC = 1
 34};
 35
 36enum vpu_instance_state {
 37	VPU_INST_STATE_NONE = 0,
 38	VPU_INST_STATE_OPEN = 1,
 39	VPU_INST_STATE_INIT_SEQ = 2,
 40	VPU_INST_STATE_PIC_RUN = 3,
 41	VPU_INST_STATE_STOP = 4
 42};
 43
 44/* Maximum available on hardware. */
 45#define WAVE5_MAX_FBS 32
 46
 47#define MAX_REG_FRAME (WAVE5_MAX_FBS * 2)
 48
 49#define WAVE5_DEC_HEVC_BUF_SIZE(_w, _h) (DIV_ROUND_UP(_w, 64) * DIV_ROUND_UP(_h, 64) * 256 + 64)
 50#define WAVE5_DEC_AVC_BUF_SIZE(_w, _h) ((((ALIGN(_w, 256) / 16) * (ALIGN(_h, 16) / 16)) + 16) * 80)
 51
 52#define WAVE5_FBC_LUMA_TABLE_SIZE(_w, _h) (ALIGN(_h, 64) * ALIGN(_w, 256) / 32)
 53#define WAVE5_FBC_CHROMA_TABLE_SIZE(_w, _h) (ALIGN((_h), 64) * ALIGN((_w) / 2, 256) / 32)
 54#define WAVE5_ENC_AVC_BUF_SIZE(_w, _h) (ALIGN(_w, 64) * ALIGN(_h, 64) / 32)
 55#define WAVE5_ENC_HEVC_BUF_SIZE(_w, _h) (ALIGN(_w, 64) / 64 * ALIGN(_h, 64) / 64 * 128)
 56
 57/*
 58 * common struct and definition
 59 */
 60enum cod_std {
 61	STD_AVC = 0,
 62	STD_HEVC = 12,
 63	STD_MAX
 64};
 65
 66enum wave_std {
 67	W_HEVC_DEC = 0x00,
 68	W_HEVC_ENC = 0x01,
 69	W_AVC_DEC = 0x02,
 70	W_AVC_ENC = 0x03,
 71	STD_UNKNOWN = 0xFF
 72};
 73
 74enum set_param_option {
 75	OPT_COMMON = 0, /* SET_PARAM command option for encoding sequence */
 76	OPT_CUSTOM_GOP = 1, /* SET_PARAM command option for setting custom GOP */
 77	OPT_CUSTOM_HEADER = 2, /* SET_PARAM command option for setting custom VPS/SPS/PPS */
 78	OPT_VUI = 3, /* SET_PARAM command option for encoding VUI */
 79	OPT_CHANGE_PARAM = 0x10,
 80};
 81
 82/************************************************************************/
 83/* PROFILE & LEVEL */
 84/************************************************************************/
 85/* HEVC */
 86#define HEVC_PROFILE_MAIN 1
 87#define HEVC_PROFILE_MAIN10 2
 88#define HEVC_PROFILE_STILLPICTURE 3
 89#define HEVC_PROFILE_MAIN10_STILLPICTURE 2
 90
 91/* H.264 profile for encoder*/
 92#define H264_PROFILE_BP 1
 93#define H264_PROFILE_MP 2
 94#define H264_PROFILE_EXTENDED 3
 95#define H264_PROFILE_HP 4
 96#define H264_PROFILE_HIGH10 5
 97#define H264_PROFILE_HIGH422 6
 98#define H264_PROFILE_HIGH444 7
 99
100/************************************************************************/
101/* error codes */
102/************************************************************************/
103
104/************************************************************************/
105/* utility macros */
106/************************************************************************/
107
108/* Initialize sequence firmware command mode */
109#define INIT_SEQ_NORMAL				1
110
111/* Decode firmware command mode */
112#define DEC_PIC_NORMAL				0
113
114/* bit_alloc_mode */
115#define BIT_ALLOC_MODE_FIXED_RATIO		2
116
117/* bit_rate */
118#define MAX_BIT_RATE				700000000
119
120/* decoding_refresh_type */
121#define DEC_REFRESH_TYPE_NON_IRAP		0
122#define DEC_REFRESH_TYPE_CRA			1
123#define DEC_REFRESH_TYPE_IDR			2
124
125/* depend_slice_mode */
126#define DEPEND_SLICE_MODE_RECOMMENDED		1
127#define DEPEND_SLICE_MODE_BOOST			2
128#define DEPEND_SLICE_MODE_FAST			3
129
130/* hvs_max_delta_qp */
131#define MAX_HVS_MAX_DELTA_QP			51
132
133/* intra_refresh_mode */
134#define REFRESH_MODE_CTU_ROWS			1
135#define REFRESH_MODE_CTU_COLUMNS		2
136#define REFRESH_MODE_CTU_STEP_SIZE		3
137#define REFRESH_MODE_CTUS			4
138
139/* intra_mb_refresh_mode */
140#define REFRESH_MB_MODE_NONE			0
141#define REFRESH_MB_MODE_CTU_ROWS		1
142#define REFRESH_MB_MODE_CTU_COLUMNS		2
143#define REFRESH_MB_MODE_CTU_STEP_SIZE		3
144
145/* intra_qp */
146#define MAX_INTRA_QP				63
147
148/* nr_inter_weight_* */
149#define MAX_INTER_WEIGHT			31
150
151/* nr_intra_weight_* */
152#define MAX_INTRA_WEIGHT			31
153
154/* nr_noise_sigma_* */
155#define MAX_NOISE_SIGMA				255
156
157/* bitstream_buffer_size */
158#define MIN_BITSTREAM_BUFFER_SIZE		1024
159#define MIN_BITSTREAM_BUFFER_SIZE_WAVE521	(1024 * 64)
160
161/* vbv_buffer_size */
162#define MIN_VBV_BUFFER_SIZE			10
163#define MAX_VBV_BUFFER_SIZE			3000
164
165#define BUFFER_MARGIN				4096
166
167#define MAX_FIRMWARE_CALL_RETRY			10
168
169#define VDI_LITTLE_ENDIAN	0x0
170
171/*
172 * Parameters of DEC_SET_SEQ_CHANGE_MASK
173 */
174#define SEQ_CHANGE_ENABLE_PROFILE BIT(5)
175#define SEQ_CHANGE_ENABLE_SIZE BIT(16)
176#define SEQ_CHANGE_ENABLE_BITDEPTH BIT(18)
177#define SEQ_CHANGE_ENABLE_DPB_COUNT BIT(19)
178#define SEQ_CHANGE_ENABLE_ASPECT_RATIO BIT(21)
179#define SEQ_CHANGE_ENABLE_VIDEO_SIGNAL BIT(23)
180#define SEQ_CHANGE_ENABLE_VUI_TIMING_INFO BIT(29)
181
182#define SEQ_CHANGE_ENABLE_ALL_HEVC (SEQ_CHANGE_ENABLE_PROFILE | \
183		SEQ_CHANGE_ENABLE_SIZE | \
184		SEQ_CHANGE_ENABLE_BITDEPTH | \
185		SEQ_CHANGE_ENABLE_DPB_COUNT)
186
187#define SEQ_CHANGE_ENABLE_ALL_AVC (SEQ_CHANGE_ENABLE_SIZE | \
188		SEQ_CHANGE_ENABLE_BITDEPTH | \
189		SEQ_CHANGE_ENABLE_DPB_COUNT | \
190		SEQ_CHANGE_ENABLE_ASPECT_RATIO | \
191		SEQ_CHANGE_ENABLE_VIDEO_SIGNAL | \
192		SEQ_CHANGE_ENABLE_VUI_TIMING_INFO)
193
194#define DISPLAY_IDX_FLAG_SEQ_END -1
195#define DISPLAY_IDX_FLAG_NO_FB -3
196#define DECODED_IDX_FLAG_NO_FB -1
197#define DECODED_IDX_FLAG_SKIP -2
198
199#define RECON_IDX_FLAG_ENC_END -1
200#define RECON_IDX_FLAG_ENC_DELAY -2
201#define RECON_IDX_FLAG_HEADER_ONLY -3
202#define RECON_IDX_FLAG_CHANGE_PARAM -4
203
204enum codec_command {
205	ENABLE_ROTATION,
206	ENABLE_MIRRORING,
207	SET_MIRROR_DIRECTION,
208	SET_ROTATION_ANGLE,
209	DEC_GET_QUEUE_STATUS,
210	ENC_GET_QUEUE_STATUS,
211	DEC_RESET_FRAMEBUF_INFO,
212	DEC_GET_SEQ_INFO,
213};
214
215enum mirror_direction {
216	MIRDIR_NONE, /* no mirroring */
217	MIRDIR_VER, /* vertical mirroring */
218	MIRDIR_HOR, /* horizontal mirroring */
219	MIRDIR_HOR_VER /* horizontal and vertical mirroring */
220};
221
222enum frame_buffer_format {
223	FORMAT_ERR = -1,
224	FORMAT_420 = 0, /* 8bit */
225	FORMAT_422, /* 8bit */
226	FORMAT_224, /* 8bit */
227	FORMAT_444, /* 8bit */
228	FORMAT_400, /* 8bit */
229
230	/* little endian perspective */
231	/* | addr 0 | addr 1 | */
232	FORMAT_420_P10_16BIT_MSB = 5, /* lsb |000000xx|xxxxxxxx | msb */
233	FORMAT_420_P10_16BIT_LSB, /* lsb |xxxxxxx |xx000000 | msb */
234	FORMAT_420_P10_32BIT_MSB, /* lsb |00xxxxxxxxxxxxxxxxxxxxxxxxxxx| msb */
235	FORMAT_420_P10_32BIT_LSB, /* lsb |xxxxxxxxxxxxxxxxxxxxxxxxxxx00| msb */
236
237	/* 4:2:2 packed format */
238	/* little endian perspective */
239	/* | addr 0 | addr 1 | */
240	FORMAT_422_P10_16BIT_MSB, /* lsb |000000xx |xxxxxxxx | msb */
241	FORMAT_422_P10_16BIT_LSB, /* lsb |xxxxxxxx |xx000000 | msb */
242	FORMAT_422_P10_32BIT_MSB, /* lsb |00xxxxxxxxxxxxxxxxxxxxxxxxxxx| msb */
243	FORMAT_422_P10_32BIT_LSB, /* lsb |xxxxxxxxxxxxxxxxxxxxxxxxxxx00| msb */
244
245	FORMAT_YUYV, /* 8bit packed format : Y0U0Y1V0 Y2U1Y3V1 ... */
246	FORMAT_YUYV_P10_16BIT_MSB,
247	FORMAT_YUYV_P10_16BIT_LSB,
248	FORMAT_YUYV_P10_32BIT_MSB,
249	FORMAT_YUYV_P10_32BIT_LSB,
250
251	FORMAT_YVYU, /* 8bit packed format : Y0V0Y1U0 Y2V1Y3U1 ... */
252	FORMAT_YVYU_P10_16BIT_MSB,
253	FORMAT_YVYU_P10_16BIT_LSB,
254	FORMAT_YVYU_P10_32BIT_MSB,
255	FORMAT_YVYU_P10_32BIT_LSB,
256
257	FORMAT_UYVY, /* 8bit packed format : U0Y0V0Y1 U1Y2V1Y3 ... */
258	FORMAT_UYVY_P10_16BIT_MSB,
259	FORMAT_UYVY_P10_16BIT_LSB,
260	FORMAT_UYVY_P10_32BIT_MSB,
261	FORMAT_UYVY_P10_32BIT_LSB,
262
263	FORMAT_VYUY, /* 8bit packed format : V0Y0U0Y1 V1Y2U1Y3 ... */
264	FORMAT_VYUY_P10_16BIT_MSB,
265	FORMAT_VYUY_P10_16BIT_LSB,
266	FORMAT_VYUY_P10_32BIT_MSB,
267	FORMAT_VYUY_P10_32BIT_LSB,
268
269	FORMAT_MAX,
270};
271
272enum packed_format_num {
273	NOT_PACKED = 0,
274	PACKED_YUYV,
275	PACKED_YVYU,
276	PACKED_UYVY,
277	PACKED_VYUY,
278};
279
280enum wave5_interrupt_bit {
281	INT_WAVE5_INIT_VPU = 0,
282	INT_WAVE5_WAKEUP_VPU = 1,
283	INT_WAVE5_SLEEP_VPU = 2,
284	INT_WAVE5_CREATE_INSTANCE = 3,
285	INT_WAVE5_FLUSH_INSTANCE = 4,
286	INT_WAVE5_DESTROY_INSTANCE = 5,
287	INT_WAVE5_INIT_SEQ = 6,
288	INT_WAVE5_SET_FRAMEBUF = 7,
289	INT_WAVE5_DEC_PIC = 8,
290	INT_WAVE5_ENC_PIC = 8,
291	INT_WAVE5_ENC_SET_PARAM = 9,
292	INT_WAVE5_DEC_QUERY = 14,
293	INT_WAVE5_BSBUF_EMPTY = 15,
294	INT_WAVE5_BSBUF_FULL = 15,
295};
296
297enum pic_type {
298	PIC_TYPE_I = 0,
299	PIC_TYPE_P = 1,
300	PIC_TYPE_B = 2,
301	PIC_TYPE_IDR = 5, /* H.264/H.265 IDR (Instantaneous Decoder Refresh) picture */
302	PIC_TYPE_MAX /* no meaning */
303};
304
305enum sw_reset_mode {
306	SW_RESET_SAFETY,
307	SW_RESET_FORCE,
308	SW_RESET_ON_BOOT
309};
310
311enum tiled_map_type {
312	LINEAR_FRAME_MAP = 0, /* linear frame map type */
313	COMPRESSED_FRAME_MAP = 17, /* compressed frame map type*/
314};
315
316enum temporal_id_mode {
317	TEMPORAL_ID_MODE_ABSOLUTE,
318	TEMPORAL_ID_MODE_RELATIVE,
319};
320
321struct vpu_attr {
322	u32 product_id;
323	char product_name[8]; /* product name in ascii code */
324	u32 product_version;
325	u32 fw_version;
326	u32 customer_id;
327	u32 support_decoders; /* bitmask */
328	u32 support_encoders; /* bitmask */
329	u32 support_backbone: 1;
330	u32 support_avc10bit_enc: 1;
331	u32 support_hevc10bit_enc: 1;
332	u32 support_hevc10bit_dec: 1;
333	u32 support_vcore_backbone: 1;
334	u32 support_vcpu_backbone: 1;
335};
336
337struct frame_buffer {
338	dma_addr_t buf_y;
339	dma_addr_t buf_cb;
340	dma_addr_t buf_cr;
341	unsigned int buf_y_size;
342	unsigned int buf_cb_size;
343	unsigned int buf_cr_size;
344	enum tiled_map_type map_type;
345	unsigned int stride; /* horizontal stride for the given frame buffer */
346	unsigned int width; /* width of the given frame buffer */
347	unsigned int height; /* height of the given frame buffer */
348	size_t size; /* size of the given frame buffer */
349	unsigned int sequence_no;
350	bool update_fb_info;
351};
352
353struct vpu_rect {
354	unsigned int left; /* horizontal pixel offset from left edge */
355	unsigned int top; /* vertical pixel offset from top edge */
356	unsigned int right; /* horizontal pixel offset from right edge */
357	unsigned int bottom; /* vertical pixel offset from bottom edge */
358};
359
360/*
361 * decode struct and definition
362 */
363
364struct dec_open_param {
365	dma_addr_t bitstream_buffer;
366	size_t bitstream_buffer_size;
367};
368
369struct dec_initial_info {
370	u32 pic_width;
371	u32 pic_height;
372	struct vpu_rect pic_crop_rect;
373	u32 min_frame_buffer_count; /* between 1 to 16 */
374
375	u32 profile;
376	u32 luma_bitdepth; /* bit-depth of the luma sample */
377	u32 chroma_bitdepth; /* bit-depth of the chroma sample */
378	u32 seq_init_err_reason;
379	dma_addr_t rd_ptr; /* read pointer of bitstream buffer */
380	dma_addr_t wr_ptr; /* write pointer of bitstream buffer */
381	u32 sequence_no;
382	u32 vlc_buf_size;
383	u32 param_buf_size;
384};
385
386struct dec_output_info {
387	/**
388	 * This is a frame buffer index for the picture to be displayed at the moment
389	 * among frame buffers which are registered using vpu_dec_register_frame_buffer().
390	 * Frame data that will be displayed is stored in the frame buffer with this index
391	 * When there is no display delay, this index is always the equal to
392	 * index_frame_decoded, however, if displaying is delayed (for display
393	 * reordering in AVC or B-frames in VC1), this index might be different to
394	 * index_frame_decoded. By checking this index, HOST applications can easily figure
395	 * out whether sequence decoding has been finished or not.
396	 *
397	 * -3(0xFFFD) or -2(0xFFFE) : when a display output cannot be given due to picture
398	 * reordering or skip option
399	 * -1(0xFFFF) : when there is no more output for display at the end of sequence
400	 * decoding
401	 */
402	s32 index_frame_display;
403	/**
404	 * This is the frame buffer index of the decoded picture among the frame buffers which were
405	 * registered using vpu_dec_register_frame_buffer(). The currently decoded frame is stored
406	 * into the frame buffer specified by this index.
407	 *
408	 * -2 : indicates that no decoded output is generated because decoder meets EOS
409	 * (end of sequence) or skip
410	 * -1 : indicates that the decoder fails to decode a picture because there is no available
411	 * frame buffer
412	 */
413	s32 index_frame_decoded;
414	s32 index_frame_decoded_for_tiled;
415	u32 nal_type;
416	unsigned int pic_type;
417	struct vpu_rect rc_display;
418	unsigned int disp_pic_width;
419	unsigned int disp_pic_height;
420	struct vpu_rect rc_decoded;
421	u32 dec_pic_width;
422	u32 dec_pic_height;
423	s32 decoded_poc;
424	int temporal_id; /* temporal ID of the picture */
425	dma_addr_t rd_ptr; /* stream buffer read pointer for the current decoder instance */
426	dma_addr_t wr_ptr; /* stream buffer write pointer for the current decoder instance */
427	struct frame_buffer disp_frame;
428	u32 frame_display_flag; /* it reports a frame buffer flag to be displayed */
429	/**
430	 * this variable reports that sequence has been changed while H.264/AVC stream decoding.
431	 * if it is 1, HOST application can get the new sequence information by calling
432	 * vpu_dec_get_initial_info() or wave5_vpu_dec_issue_seq_init().
433	 *
434	 * for H.265/HEVC decoder, each bit has a different meaning as follows.
435	 *
436	 * sequence_changed[5] : it indicates that the profile_idc has been changed
437	 * sequence_changed[16] : it indicates that the resolution has been changed
438	 * sequence_changed[19] : it indicates that the required number of frame buffer has
439	 * been changed.
440	 */
441	unsigned int frame_cycle; /* reports the number of cycles for processing a frame */
442	u32 sequence_no;
443
444	u32 dec_host_cmd_tick; /* tick of DEC_PIC command for the picture */
445	u32 dec_decode_end_tick; /* end tick of decoding slices of the picture */
446
447	u32 sequence_changed;
448};
449
450struct queue_status_info {
451	u32 instance_queue_count;
452	u32 report_queue_count;
453};
454
455/*
456 * encode struct and definition
457 */
458
459#define MAX_NUM_TEMPORAL_LAYER 7
460#define MAX_NUM_SPATIAL_LAYER 3
461#define MAX_GOP_NUM 8
462
463struct custom_gop_pic_param {
464	u32 pic_type; /* picture type of nth picture in the custom GOP */
465	u32 poc_offset; /* POC of nth picture in the custom GOP */
466	u32 pic_qp; /* quantization parameter of nth picture in the custom GOP */
467	u32 use_multi_ref_p; /* use multiref pic for P picture. valid only if PIC_TYPE is P */
468	u32 ref_poc_l0; /* POC of reference L0 of nth picture in the custom GOP */
469	u32 ref_poc_l1; /* POC of reference L1 of nth picture in the custom GOP */
470	s32 temporal_id; /* temporal ID of nth picture in the custom GOP */
471};
472
473struct enc_wave_param {
474	/*
475	 * profile indicator (HEVC only)
476	 *
477	 * 0 : the firmware determines a profile according to the internal_bit_depth
478	 * 1 : main profile
479	 * 2 : main10 profile
480	 * 3 : main still picture profile
481	 * In the AVC encoder, a profile cannot be set by the host application.
482	 * The firmware decides it based on internal_bit_depth.
483	 * profile = HIGH (bitdepth 8) profile = HIGH10 (bitdepth 10)
484	 */
485	u32 profile;
486	u32 level; /* level indicator (level * 10) */
487	u32 internal_bit_depth: 4; /* 8/10 */
488	u32 gop_preset_idx: 4; /* 0 - 9 */
489	u32 decoding_refresh_type: 2; /* 0=non-IRAP, 1=CRA, 2=IDR */
490	u32 intra_qp; /* quantization parameter of intra picture */
491	u32 intra_period; /* period of intra picture in GOP size */
492	u32 conf_win_top; /* top offset of conformance window */
493	u32 conf_win_bot; /* bottom offset of conformance window */
494	u32 conf_win_left; /* left offset of conformance window */
495	u32 conf_win_right; /* right offset of conformance window */
496	u32 intra_refresh_mode: 3;
497	/*
498	 * Argument for intra_ctu_refresh_mode.
499	 *
500	 * Depending on intra_refresh_mode, it can mean one of the following:
501	 * - intra_ctu_refresh_mode (1) -> number of consecutive CTU rows
502	 * - intra_ctu_refresh_mode (2) -> the number of consecutive CTU columns
503	 * - intra_ctu_refresh_mode (3) -> step size in CTU
504	 * - intra_ctu_refresh_mode (4) -> number of intra ct_us to be encoded in a picture
505	 */
506	u32 intra_refresh_arg;
507	/*
508	 * 0 : custom setting
509	 * 1 : recommended encoder parameters (slow encoding speed, highest picture quality)
510	 * 2 : boost mode (normal encoding speed, moderate picture quality)
511	 * 3 : fast mode (fast encoding speed, low picture quality)
512	 */
513	u32 depend_slice_mode : 2;
514	u32 depend_slice_mode_arg;
515	u32 independ_slice_mode : 1; /* 0=no-multi-slice, 1=slice-in-ctu-number*/
516	u32 independ_slice_mode_arg;
517	u32 max_num_merge: 2;
518	s32 beta_offset_div2: 4; /* sets beta_offset_div2 for deblocking filter */
519	s32 tc_offset_div2: 4; /* sets tc_offset_div3 for deblocking filter */
520	u32 hvs_qp_scale: 4; /* QP scaling factor for CU QP adjust if hvs_qp_scale_enable is 1 */
521	u32 hvs_max_delta_qp; /* maximum delta QP for HVS */
522	s32 chroma_cb_qp_offset; /* the value of chroma(cb) QP offset */
523	s32 chroma_cr_qp_offset; /* the value of chroma(cr) QP offset */
524	s32 initial_rc_qp;
525	u32 nr_intra_weight_y;
526	u32 nr_intra_weight_cb; /* weight to cb noise level for intra picture (0 ~ 31) */
527	u32 nr_intra_weight_cr; /* weight to cr noise level for intra picture (0 ~ 31) */
528	u32 nr_inter_weight_y;
529	u32 nr_inter_weight_cb; /* weight to cb noise level for inter picture (0 ~ 31) */
530	u32 nr_inter_weight_cr; /* weight to cr noise level for inter picture (0 ~ 31) */
531	u32 min_qp_i; /* minimum QP of I picture for rate control */
532	u32 max_qp_i; /* maximum QP of I picture for rate control */
533	u32 min_qp_p; /* minimum QP of P picture for rate control */
534	u32 max_qp_p; /* maximum QP of P picture for rate control */
535	u32 min_qp_b; /* minimum QP of B picture for rate control */
536	u32 max_qp_b; /* maximum QP of B picture for rate control */
537	u32 avc_idr_period; /* period of IDR picture (0 ~ 1024). 0 - implies an infinite period */
538	u32 avc_slice_arg; /* the number of MB for a slice when avc_slice_mode is set with 1 */
539	u32 intra_mb_refresh_mode: 2; /* 0=none, 1=row, 2=column, 3=step-size-in-mb */
540	/**
541	 * Argument for intra_mb_refresh_mode.
542	 *
543	 * intra_mb_refresh_mode (1) -> number of consecutive MB rows
544	 * intra_mb_refresh_mode (2) ->the number of consecutive MB columns
545	 * intra_mb_refresh_mode (3) -> step size in MB
546	 */
547	u32 intra_mb_refresh_arg;
548	u32 rc_weight_param;
549	u32 rc_weight_buf;
550
551	/* flags */
552	u32 en_still_picture: 1; /* still picture profile */
553	u32 tier: 1; /* 0=main, 1=high */
554	u32 avc_slice_mode: 1; /* 0=none, 1=slice-in-mb-number */
555	u32 entropy_coding_mode: 1; /* 0=CAVLC, 1=CABAC */
556	u32 lossless_enable: 1; /* enable lossless encoding */
557	u32 const_intra_pred_flag: 1; /* enable constrained intra prediction */
558	u32 tmvp_enable: 1; /* enable temporal motion vector prediction */
559	u32 wpp_enable: 1;
560	u32 disable_deblk: 1; /* disable in-loop deblocking filtering */
561	u32 lf_cross_slice_boundary_enable: 1;
562	u32 skip_intra_trans: 1;
563	u32 sao_enable: 1; /* enable SAO (sample adaptive offset) */
564	u32 intra_nx_n_enable: 1; /* enables intra nx_n p_us */
565	u32 cu_level_rc_enable: 1; /* enable CU level rate control */
566	u32 hvs_qp_enable: 1; /* enable CU QP adjustment for subjective quality enhancement */
567	u32 strong_intra_smooth_enable: 1; /* enable strong intra smoothing */
568	u32 rdo_skip: 1; /* skip RDO (rate distortion optimization) */
569	u32 lambda_scaling_enable: 1; /* enable lambda scaling using custom GOP */
570	u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8 transform */
571	u32 mb_level_rc_enable: 1; /* enable MB-level rate control */
572	u32 forced_idr_header_enable: 1; /* enable header encoding before IDR frame */
573};
574
575struct enc_open_param {
576	dma_addr_t bitstream_buffer;
577	unsigned int bitstream_buffer_size;
578	u32 pic_width; /* width of a picture to be encoded in unit of sample */
579	u32 pic_height; /* height of a picture to be encoded in unit of sample */
580	u32 frame_rate_info;/* desired fps */
581	u32 vbv_buffer_size;
582	u32 bit_rate; /* target bitrate in bps */
583	struct enc_wave_param wave_param;
584	enum packed_format_num packed_format; /* <<vpuapi_h_packed_format_num>> */
585	enum frame_buffer_format src_format;
586	bool line_buf_int_en;
587	u32 rc_enable : 1; /* rate control */
588};
589
590struct enc_initial_info {
591	u32 min_frame_buffer_count; /* minimum number of frame buffers */
592	u32 min_src_frame_count; /* minimum number of source buffers */
593	u32 seq_init_err_reason;
594	u32 warn_info;
595	u32 vlc_buf_size; /* size of task buffer */
596	u32 param_buf_size; /* size of task buffer */
597};
598
599/*
600 * Flags to encode NAL units explicitly
601 */
602struct enc_code_opt {
603	u32 implicit_header_encode: 1;
604	u32 encode_vcl: 1;
605	u32 encode_vps: 1;
606	u32 encode_sps: 1;
607	u32 encode_pps: 1;
608	u32 encode_aud: 1;
609	u32 encode_eos: 1;
610	u32 encode_eob: 1;
611	u32 encode_vui: 1;
612};
613
614struct enc_param {
615	struct frame_buffer *source_frame;
616	u32 pic_stream_buffer_addr;
617	u64 pic_stream_buffer_size;
618	u32 src_idx; /* source frame buffer index */
619	struct enc_code_opt code_option;
620	u64 pts; /* presentation timestamp (PTS) of the input source */
621	bool src_end_flag;
622};
623
624struct enc_output_info {
625	u32 bitstream_buffer;
626	u32 bitstream_size; /* byte size of encoded bitstream */
627	u32 pic_type: 2; /* <<vpuapi_h_pic_type>> */
628	s32 recon_frame_index;
629	dma_addr_t rd_ptr;
630	dma_addr_t wr_ptr;
631	u32 enc_pic_byte; /* number of encoded picture bytes */
632	s32 enc_src_idx; /* source buffer index of the currently encoded picture */
633	u32 enc_vcl_nut;
634	u32 error_reason; /* error reason of the currently encoded picture */
635	u32 warn_info; /* warning information on the currently encoded picture */
636	unsigned int frame_cycle; /* param for reporting the cycle number of encoding one frame*/
637	u64 pts;
638	u32 enc_host_cmd_tick; /* tick of ENC_PIC command for the picture */
639	u32 enc_encode_end_tick; /* end tick of encoding slices of the picture */
640};
641
642enum enc_pic_code_option {
643	CODEOPT_ENC_HEADER_IMPLICIT = BIT(0),
644	CODEOPT_ENC_VCL = BIT(1), /* flag to encode VCL nal unit explicitly */
645};
646
647enum gop_preset_idx {
648	PRESET_IDX_CUSTOM_GOP = 0, /* user defined GOP structure */
649	PRESET_IDX_ALL_I = 1, /* all intra, gopsize = 1 */
650	PRESET_IDX_IPP = 2, /* consecutive P, cyclic gopsize = 1 */
651	PRESET_IDX_IBBB = 3, /* consecutive B, cyclic gopsize = 1 */
652	PRESET_IDX_IBPBP = 4, /* gopsize = 2 */
653	PRESET_IDX_IBBBP = 5, /* gopsize = 4 */
654	PRESET_IDX_IPPPP = 6, /* consecutive P, cyclic gopsize = 4 */
655	PRESET_IDX_IBBBB = 7, /* consecutive B, cyclic gopsize = 4 */
656	PRESET_IDX_RA_IB = 8, /* random access, cyclic gopsize = 8 */
657	PRESET_IDX_IPP_SINGLE = 9, /* consecutive P, cyclic gopsize = 1, with single ref */
658};
659
660struct sec_axi_info {
661	u32 use_ip_enable;
662	u32 use_bit_enable;
663	u32 use_lf_row_enable: 1;
664	u32 use_enc_rdo_enable: 1;
665	u32 use_enc_lf_enable: 1;
666};
667
668struct dec_info {
669	struct dec_open_param open_param;
670	struct dec_initial_info initial_info;
671	struct dec_initial_info new_seq_info; /* temporal new sequence information */
672	u32 stream_wr_ptr;
673	u32 stream_rd_ptr;
674	u32 frame_display_flag;
675	dma_addr_t stream_buf_start_addr;
676	dma_addr_t stream_buf_end_addr;
677	u32 stream_buf_size;
678	struct vpu_buf vb_mv[MAX_REG_FRAME];
679	struct vpu_buf vb_fbc_y_tbl[MAX_REG_FRAME];
680	struct vpu_buf vb_fbc_c_tbl[MAX_REG_FRAME];
681	unsigned int num_of_decoding_fbs: 7;
682	unsigned int num_of_display_fbs: 7;
683	unsigned int stride;
684	struct sec_axi_info sec_axi_info;
685	dma_addr_t user_data_buf_addr;
686	u32 user_data_enable;
687	u32 user_data_buf_size;
688	struct vpu_buf vb_work;
689	struct vpu_buf vb_task;
690	struct dec_output_info dec_out_info[WAVE5_MAX_FBS];
691	u32 seq_change_mask;
692	enum temporal_id_mode temp_id_select_mode;
693	u32 target_temp_id;
694	u32 target_spatial_id;
695	u32 instance_queue_count;
696	u32 report_queue_count;
697	u32 cycle_per_tick;
698	u32 product_code;
699	u32 vlc_buf_size;
700	u32 param_buf_size;
701	bool initial_info_obtained;
702	bool reorder_enable;
703	bool first_cycle_check;
704	u32 stream_endflag: 1;
705};
706
707struct enc_info {
708	struct enc_open_param open_param;
709	struct enc_initial_info initial_info;
710	u32 stream_rd_ptr;
711	u32 stream_wr_ptr;
712	dma_addr_t stream_buf_start_addr;
713	dma_addr_t stream_buf_end_addr;
714	u32 stream_buf_size;
715	unsigned int num_frame_buffers;
716	unsigned int stride;
717	bool rotation_enable;
718	bool mirror_enable;
719	enum mirror_direction mirror_direction;
720	unsigned int rotation_angle;
721	bool initial_info_obtained;
722	struct sec_axi_info sec_axi_info;
723	bool line_buf_int_en;
724	struct vpu_buf vb_work;
725	struct vpu_buf vb_mv; /* col_mv buffer */
726	struct vpu_buf vb_fbc_y_tbl; /* FBC luma table buffer */
727	struct vpu_buf vb_fbc_c_tbl; /* FBC chroma table buffer */
728	struct vpu_buf vb_sub_sam_buf; /* sub-sampled buffer for ME */
729	struct vpu_buf vb_task;
730	u64 cur_pts; /* current timestamp in 90_k_hz */
731	u64 pts_map[32]; /* PTS mapped with source frame index */
732	u32 instance_queue_count;
733	u32 report_queue_count;
734	bool first_cycle_check;
735	u32 cycle_per_tick;
736	u32 product_code;
737	u32 vlc_buf_size;
738	u32 param_buf_size;
739};
740
741struct vpu_device {
742	struct device *dev;
743	struct v4l2_device v4l2_dev;
744	struct v4l2_m2m_dev *v4l2_m2m_dec_dev;
745	struct v4l2_m2m_dev *v4l2_m2m_enc_dev;
746	struct list_head instances;
747	struct video_device *video_dev_dec;
748	struct video_device *video_dev_enc;
749	struct mutex dev_lock; /* lock for the src, dst v4l2 queues */
750	struct mutex hw_lock; /* lock hw configurations */
751	struct mutex irq_lock;
752	int irq;
753	enum product_id product;
754	struct vpu_attr attr;
755	struct vpu_buf common_mem;
756	u32 last_performance_cycles;
757	u32 sram_size;
758	struct gen_pool *sram_pool;
759	struct vpu_buf sram_buf;
760	void __iomem *vdb_register;
761	u32 product_code;
762	struct ida inst_ida;
763	struct clk_bulk_data *clks;
764	struct hrtimer hrtimer;
765	struct kthread_work work;
766	struct kthread_worker *worker;
767	int vpu_poll_interval;
768	int num_clks;
769	struct task_struct *irq_thread;
770	struct semaphore irq_sem; /* signal to irq_thread when interrupt happens*/
771	struct reset_control *resets;
772	spinlock_t irq_spinlock; /* protect instances list */
773};
774
775struct vpu_instance;
776
777struct vpu_instance_ops {
778	void (*finish_process)(struct vpu_instance *inst);
779};
780
781struct vpu_instance {
782	struct list_head list;
783	struct v4l2_fh v4l2_fh;
784	struct v4l2_m2m_dev *v4l2_m2m_dev;
785	struct v4l2_ctrl_handler v4l2_ctrl_hdl;
786	struct vpu_device *dev;
787	struct completion irq_done;
788
789	struct v4l2_pix_format_mplane src_fmt;
790	struct v4l2_pix_format_mplane dst_fmt;
791	enum v4l2_colorspace colorspace;
792	enum v4l2_xfer_func xfer_func;
793	enum v4l2_ycbcr_encoding ycbcr_enc;
794	enum v4l2_quantization quantization;
795
796	struct kfifo irq_status;
797	enum vpu_instance_state state;
798	enum vpu_instance_type type;
799	const struct vpu_instance_ops *ops;
800	spinlock_t state_spinlock; /* This protects the instance state */
801
802	enum wave_std std;
803	s32 id;
804	union {
805		struct enc_info enc_info;
806		struct dec_info dec_info;
807	} *codec_info;
808	struct frame_buffer frame_buf[MAX_REG_FRAME];
809	struct vpu_buf frame_vbuf[MAX_REG_FRAME];
810	u32 fbc_buf_count;
811	u32 queued_src_buf_num;
812	u32 queued_dst_buf_num;
813	struct list_head avail_src_bufs;
814	struct list_head avail_dst_bufs;
815	struct v4l2_rect conf_win;
816	u64 timestamp;
817	enum frame_buffer_format output_format;
818	bool cbcr_interleave;
819	bool nv21;
820	bool eos;
821	struct vpu_buf bitstream_vbuf;
822	dma_addr_t last_rd_ptr;
823	size_t remaining_consumed_bytes;
824	bool needs_reallocation;
825
826	unsigned int min_src_buf_count;
827	unsigned int rot_angle;
828	unsigned int mirror_direction;
829	unsigned int bit_depth;
830	unsigned int frame_rate;
831	unsigned int vbv_buf_size;
832	unsigned int rc_mode;
833	unsigned int rc_enable;
834	unsigned int bit_rate;
835	unsigned int encode_aud;
836	struct enc_wave_param enc_param;
837};
838
839void wave5_vdi_write_register(struct vpu_device *vpu_dev, u32 addr, u32 data);
840u32 wave5_vdi_read_register(struct vpu_device *vpu_dev, u32 addr);
841int wave5_vdi_clear_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb);
842int wave5_vdi_allocate_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb);
843int wave5_vdi_allocate_array(struct vpu_device *vpu_dev, struct vpu_buf *array, unsigned int count,
844			     size_t size);
845int wave5_vdi_write_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb, size_t offset,
846			   u8 *data, size_t len);
847int wave5_vdi_free_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb);
848void wave5_vdi_allocate_sram(struct vpu_device *vpu_dev);
849void wave5_vdi_free_sram(struct vpu_device *vpu_dev);
850
851int wave5_vpu_init_with_bitcode(struct device *dev, u8 *bitcode, size_t size);
852int wave5_vpu_flush_instance(struct vpu_instance *inst);
853int wave5_vpu_get_version_info(struct device *dev, u32 *revision, unsigned int *product_id);
854int wave5_vpu_dec_open(struct vpu_instance *inst, struct dec_open_param *open_param);
855int wave5_vpu_dec_close(struct vpu_instance *inst, u32 *fail_res);
856int wave5_vpu_dec_issue_seq_init(struct vpu_instance *inst);
857int wave5_vpu_dec_complete_seq_init(struct vpu_instance *inst, struct dec_initial_info *info);
858int wave5_vpu_dec_register_frame_buffer_ex(struct vpu_instance *inst, int num_of_decoding_fbs,
859					   int num_of_display_fbs, int stride, int height);
860int wave5_vpu_dec_start_one_frame(struct vpu_instance *inst, u32 *res_fail);
861int wave5_vpu_dec_get_output_info(struct vpu_instance *inst, struct dec_output_info *info);
862int wave5_vpu_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr, int update_wr_ptr);
863dma_addr_t wave5_vpu_dec_get_rd_ptr(struct vpu_instance *inst);
864int wave5_vpu_dec_reset_framebuffer(struct vpu_instance *inst, unsigned int index);
865int wave5_vpu_dec_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter);
866int wave5_vpu_dec_get_bitstream_buffer(struct vpu_instance *inst, dma_addr_t *prd_ptr,
867				       dma_addr_t *pwr_ptr, size_t *size);
868int wave5_vpu_dec_update_bitstream_buffer(struct vpu_instance *inst, size_t size);
869int wave5_vpu_dec_clr_disp_flag(struct vpu_instance *inst, int index);
870int wave5_vpu_dec_set_disp_flag(struct vpu_instance *inst, int index);
871
872int wave5_vpu_enc_open(struct vpu_instance *inst, struct enc_open_param *open_param);
873int wave5_vpu_enc_close(struct vpu_instance *inst, u32 *fail_res);
874int wave5_vpu_enc_issue_seq_init(struct vpu_instance *inst);
875int wave5_vpu_enc_complete_seq_init(struct vpu_instance *inst, struct enc_initial_info *info);
876int wave5_vpu_enc_register_frame_buffer(struct vpu_instance *inst, unsigned int num,
877					unsigned int stride, int height,
878					enum tiled_map_type map_type);
879int wave5_vpu_enc_start_one_frame(struct vpu_instance *inst, struct enc_param *param,
880				  u32 *fail_res);
881int wave5_vpu_enc_get_output_info(struct vpu_instance *inst, struct enc_output_info *info);
882int wave5_vpu_enc_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter);
883
884#endif