wave5-vpu.c

  1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
  2/*
  3 * Wave5 series multi-standard codec IP - platform driver
  4 *
  5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC
  6 */
  7#include <linux/kernel.h>
  8#include <linux/module.h>
  9#include <linux/platform_device.h>
 10#include <linux/clk.h>
 11#include <linux/firmware.h>
 12#include <linux/interrupt.h>
 13#include <linux/pm_runtime.h>
 14#include <linux/reset.h>
 15#include "wave5-vpu.h"
 16#include "wave5-regdefine.h"
 17#include "wave5-vpuconfig.h"
 18#include "wave5.h"
 19
 20#define VPU_PLATFORM_DEVICE_NAME "vdec"
 21#define VPU_CLK_NAME "vcodec"
 22
 23#define WAVE5_IS_ENC BIT(0)
 24#define WAVE5_IS_DEC BIT(1)
 25
 26struct wave5_match_data {
 27	int flags;
 28	const char *fw_name;
 29	u32 sram_size;
 30};
 31
 32static int vpu_poll_interval = 5;
 33module_param(vpu_poll_interval, int, 0644);
 34
 35int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout)
 36{
 37	int ret;
 38
 39	ret = wait_for_completion_timeout(&inst->irq_done,
 40					  msecs_to_jiffies(timeout));
 41	if (!ret)
 42		return -ETIMEDOUT;
 43
 44	reinit_completion(&inst->irq_done);
 45
 46	return 0;
 47}
 48
 49static void wave5_vpu_handle_irq(void *dev_id)
 50{
 51	u32 seq_done;
 52	u32 cmd_done;
 53	u32 irq_reason;
 54	u32 irq_subreason;
 55	struct vpu_instance *inst, *tmp;
 56	struct vpu_device *dev = dev_id;
 57	int val;
 58	unsigned long flags;
 59
 60	irq_reason = wave5_vdi_read_register(dev, W5_VPU_VINT_REASON);
 61	seq_done = wave5_vdi_read_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO);
 62	cmd_done = wave5_vdi_read_register(dev, W5_RET_QUEUE_CMD_DONE_INST);
 63	wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_CLR, irq_reason);
 64	wave5_vdi_write_register(dev, W5_VPU_VINT_CLEAR, 0x1);
 65
 66	spin_lock_irqsave(&dev->irq_spinlock, flags);
 67	list_for_each_entry_safe(inst, tmp, &dev->instances, list) {
 68
 69		if (irq_reason & BIT(INT_WAVE5_INIT_SEQ) ||
 70		    irq_reason & BIT(INT_WAVE5_ENC_SET_PARAM)) {
 71			if (dev->product_code == WAVE515_CODE &&
 72			    (cmd_done & BIT(inst->id))) {
 73				cmd_done &= ~BIT(inst->id);
 74				wave5_vdi_write_register(dev, W5_RET_QUEUE_CMD_DONE_INST,
 75							 cmd_done);
 76				complete(&inst->irq_done);
 77			} else if (seq_done & BIT(inst->id)) {
 78				seq_done &= ~BIT(inst->id);
 79				wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO,
 80							 seq_done);
 81				complete(&inst->irq_done);
 82			}
 83		}
 84
 85		if (irq_reason & BIT(INT_WAVE5_DEC_PIC) ||
 86		    irq_reason & BIT(INT_WAVE5_ENC_PIC)) {
 87			if (cmd_done & BIT(inst->id)) {
 88				cmd_done &= ~BIT(inst->id);
 89				if (dev->irq >= 0) {
 90					irq_subreason =
 91						wave5_vdi_read_register(dev, W5_VPU_VINT_REASON);
 92					if (!(irq_subreason & BIT(INT_WAVE5_DEC_PIC)))
 93						wave5_vdi_write_register(dev,
 94									 W5_RET_QUEUE_CMD_DONE_INST,
 95									 cmd_done);
 96				}
 97				val = BIT(INT_WAVE5_DEC_PIC);
 98				kfifo_in(&inst->irq_status, &val, sizeof(int));
 99			}
100		}
101	}
102	spin_unlock_irqrestore(&dev->irq_spinlock, flags);
103
104	if (dev->irq < 0)
105		up(&dev->irq_sem);
106}
107
108static irqreturn_t wave5_vpu_irq(int irq, void *dev_id)
109{
110	struct vpu_device *dev = dev_id;
111
112	if (wave5_vdi_read_register(dev, W5_VPU_VPU_INT_STS)) {
113		wave5_vpu_handle_irq(dev);
114		return IRQ_WAKE_THREAD;
115	}
116
117	return IRQ_HANDLED;
118}
119
120static irqreturn_t wave5_vpu_irq_thread(int irq, void *dev_id)
121{
122	struct vpu_device *dev = dev_id;
123	struct vpu_instance *inst, *tmp;
124	int irq_status, ret;
125
126	mutex_lock(&dev->irq_lock);
127	list_for_each_entry_safe(inst, tmp, &dev->instances, list) {
128		while (kfifo_len(&inst->irq_status)) {
129			ret = kfifo_out(&inst->irq_status, &irq_status, sizeof(int));
130			if (!ret)
131				break;
132
133			inst->ops->finish_process(inst);
134		}
135	}
136	mutex_unlock(&dev->irq_lock);
137
138	return IRQ_HANDLED;
139}
140
141static void wave5_vpu_irq_work_fn(struct kthread_work *work)
142{
143	struct vpu_device *dev = container_of(work, struct vpu_device, work);
144
145	if (wave5_vdi_read_register(dev, W5_VPU_VPU_INT_STS))
146		wave5_vpu_handle_irq(dev);
147}
148
149static enum hrtimer_restart wave5_vpu_timer_callback(struct hrtimer *timer)
150{
151	struct vpu_device *dev =
152			container_of(timer, struct vpu_device, hrtimer);
153
154	kthread_queue_work(dev->worker, &dev->work);
155	hrtimer_forward_now(timer, ns_to_ktime(vpu_poll_interval * NSEC_PER_MSEC));
156
157	return HRTIMER_RESTART;
158}
159
160static int irq_thread(void *data)
161{
162	struct vpu_device *dev = (struct vpu_device *)data;
163	struct vpu_instance *inst, *tmp;
164	int irq_status, ret;
165
166	while (!kthread_should_stop()) {
167		if (down_interruptible(&dev->irq_sem))
168			continue;
169
170		if (kthread_should_stop())
171			break;
172
173		mutex_lock(&dev->irq_lock);
174		list_for_each_entry_safe(inst, tmp, &dev->instances, list) {
175			while (kfifo_len(&inst->irq_status)) {
176				ret = kfifo_out(&inst->irq_status, &irq_status, sizeof(int));
177				if (!ret)
178					break;
179
180				inst->ops->finish_process(inst);
181			}
182		}
183		mutex_unlock(&dev->irq_lock);
184	}
185
186	return 0;
187}
188
189static int wave5_vpu_load_firmware(struct device *dev, const char *fw_name,
190				   u32 *revision)
191{
192	const struct firmware *fw;
193	int ret;
194	unsigned int product_id;
195
196	ret = request_firmware(&fw, fw_name, dev);
197	if (ret) {
198		dev_err(dev, "request_firmware, fail: %d\n", ret);
199		return ret;
200	}
201
202	ret = wave5_vpu_init_with_bitcode(dev, (u8 *)fw->data, fw->size);
203	if (ret) {
204		dev_err(dev, "vpu_init_with_bitcode, fail: %d\n", ret);
205		release_firmware(fw);
206		return ret;
207	}
208	release_firmware(fw);
209
210	ret = wave5_vpu_get_version_info(dev, revision, &product_id);
211	if (ret) {
212		dev_err(dev, "vpu_get_version_info fail: %d\n", ret);
213		return ret;
214	}
215
216	dev_dbg(dev, "%s: enum product_id: %08x, fw revision: %u\n",
217		__func__, product_id, *revision);
218
219	return 0;
220}
221
222static __maybe_unused int wave5_pm_suspend(struct device *dev)
223{
224	struct vpu_device *vpu = dev_get_drvdata(dev);
225
226	if (pm_runtime_suspended(dev))
227		return 0;
228
229	if (vpu->irq < 0)
230		hrtimer_cancel(&vpu->hrtimer);
231
232	wave5_vpu_sleep_wake(dev, true, NULL, 0);
233	clk_bulk_disable_unprepare(vpu->num_clks, vpu->clks);
234
235	return 0;
236}
237
238static __maybe_unused int wave5_pm_resume(struct device *dev)
239{
240	struct vpu_device *vpu = dev_get_drvdata(dev);
241	int ret = 0;
242
243	wave5_vpu_sleep_wake(dev, false, NULL, 0);
244	ret = clk_bulk_prepare_enable(vpu->num_clks, vpu->clks);
245	if (ret) {
246		dev_err(dev, "Enabling clocks, fail: %d\n", ret);
247		return ret;
248	}
249
250	if (vpu->irq < 0 && !hrtimer_active(&vpu->hrtimer))
251		hrtimer_start(&vpu->hrtimer, ns_to_ktime(vpu->vpu_poll_interval * NSEC_PER_MSEC),
252			      HRTIMER_MODE_REL_PINNED);
253
254	return ret;
255}
256
257static const struct dev_pm_ops wave5_pm_ops = {
258	SET_RUNTIME_PM_OPS(wave5_pm_suspend, wave5_pm_resume, NULL)
259};
260
261static int wave5_vpu_probe(struct platform_device *pdev)
262{
263	int ret;
264	struct vpu_device *dev;
265	const struct wave5_match_data *match_data;
266	u32 fw_revision;
267
268	match_data = device_get_match_data(&pdev->dev);
269	if (!match_data) {
270		dev_err(&pdev->dev, "missing device match data\n");
271		return -EINVAL;
272	}
273
274	/* physical addresses limited to 32 bits */
275	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
276	if (ret) {
277		dev_err(&pdev->dev, "Failed to set DMA mask: %d\n", ret);
278		return ret;
279	}
280
281	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
282	if (!dev)
283		return -ENOMEM;
284
285	dev->vdb_register = devm_platform_ioremap_resource(pdev, 0);
286	if (IS_ERR(dev->vdb_register))
287		return PTR_ERR(dev->vdb_register);
288	ida_init(&dev->inst_ida);
289
290	mutex_init(&dev->dev_lock);
291	mutex_init(&dev->hw_lock);
292	mutex_init(&dev->irq_lock);
293	spin_lock_init(&dev->irq_spinlock);
294	dev_set_drvdata(&pdev->dev, dev);
295	dev->dev = &pdev->dev;
296
297	dev->resets = devm_reset_control_array_get_optional_exclusive(&pdev->dev);
298	if (IS_ERR(dev->resets)) {
299		return dev_err_probe(&pdev->dev, PTR_ERR(dev->resets),
300				     "Failed to get reset control\n");
301	}
302
303	ret = reset_control_deassert(dev->resets);
304	if (ret)
305		return dev_err_probe(&pdev->dev, ret, "Failed to deassert resets\n");
306
307	ret = devm_clk_bulk_get_all(&pdev->dev, &dev->clks);
308
309	/* continue without clock, assume externally managed */
310	if (ret < 0) {
311		dev_warn(&pdev->dev, "Getting clocks, fail: %d\n", ret);
312		ret = 0;
313	}
314	dev->num_clks = ret;
315
316	ret = clk_bulk_prepare_enable(dev->num_clks, dev->clks);
317	if (ret) {
318		dev_err(&pdev->dev, "Enabling clocks, fail: %d\n", ret);
319		goto err_reset_assert;
320	}
321
322	dev->sram_pool = of_gen_pool_get(pdev->dev.of_node, "sram", 0);
323	if (!dev->sram_pool)
324		dev_warn(&pdev->dev, "sram node not found\n");
325
326	dev->sram_size = match_data->sram_size;
327
328	dev->product_code = wave5_vdi_read_register(dev, VPU_PRODUCT_CODE_REGISTER);
329	ret = wave5_vdi_init(&pdev->dev);
330	if (ret < 0) {
331		dev_err(&pdev->dev, "wave5_vdi_init, fail: %d\n", ret);
332		goto err_clk_dis;
333	}
334	dev->product = wave5_vpu_get_product_id(dev);
335
336	INIT_LIST_HEAD(&dev->instances);
337
338	dev->irq = platform_get_irq(pdev, 0);
339	if (dev->irq < 0) {
340		dev_err(&pdev->dev, "failed to get irq resource, falling back to polling\n");
341		sema_init(&dev->irq_sem, 1);
342		dev->irq_thread = kthread_run(irq_thread, dev, "irq thread");
343		hrtimer_setup(&dev->hrtimer, &wave5_vpu_timer_callback, CLOCK_MONOTONIC,
344			      HRTIMER_MODE_REL_PINNED);
345		dev->worker = kthread_run_worker(0, "vpu_irq_thread");
346		if (IS_ERR(dev->worker)) {
347			dev_err(&pdev->dev, "failed to create vpu irq worker\n");
348			ret = PTR_ERR(dev->worker);
349			goto err_vdi_release;
350		}
351		dev->vpu_poll_interval = vpu_poll_interval;
352		kthread_init_work(&dev->work, wave5_vpu_irq_work_fn);
353	} else {
354		ret = devm_request_threaded_irq(&pdev->dev, dev->irq, wave5_vpu_irq,
355						wave5_vpu_irq_thread, IRQF_ONESHOT, "vpu_irq", dev);
356		if (ret) {
357			dev_err(&pdev->dev, "Register interrupt handler, fail: %d\n", ret);
358			goto err_enc_unreg;
359		}
360	}
361
362	ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
363	if (ret) {
364		dev_err(&pdev->dev, "v4l2_device_register, fail: %d\n", ret);
365		goto err_vdi_release;
366	}
367
368	if (match_data->flags & WAVE5_IS_DEC) {
369		ret = wave5_vpu_dec_register_device(dev);
370		if (ret) {
371			dev_err(&pdev->dev, "wave5_vpu_dec_register_device, fail: %d\n", ret);
372			goto err_v4l2_unregister;
373		}
374	}
375	if (match_data->flags & WAVE5_IS_ENC) {
376		ret = wave5_vpu_enc_register_device(dev);
377		if (ret) {
378			dev_err(&pdev->dev, "wave5_vpu_enc_register_device, fail: %d\n", ret);
379			goto err_dec_unreg;
380		}
381	}
382
383	ret = wave5_vpu_load_firmware(&pdev->dev, match_data->fw_name, &fw_revision);
384	if (ret) {
385		dev_err(&pdev->dev, "wave5_vpu_load_firmware, fail: %d\n", ret);
386		goto err_enc_unreg;
387	}
388
389	dev_info(&pdev->dev, "Added wave5 driver with caps: %s %s\n",
390		 (match_data->flags & WAVE5_IS_ENC) ? "'ENCODE'" : "",
391		 (match_data->flags & WAVE5_IS_DEC) ? "'DECODE'" : "");
392	dev_info(&pdev->dev, "Product Code:      0x%x\n", dev->product_code);
393	dev_info(&pdev->dev, "Firmware Revision: %u\n", fw_revision);
394
395	pm_runtime_set_autosuspend_delay(&pdev->dev, 500);
396	pm_runtime_use_autosuspend(&pdev->dev);
397	pm_runtime_enable(&pdev->dev);
398	wave5_vpu_sleep_wake(&pdev->dev, true, NULL, 0);
399
400	return 0;
401
402err_enc_unreg:
403	if (match_data->flags & WAVE5_IS_ENC)
404		wave5_vpu_enc_unregister_device(dev);
405err_dec_unreg:
406	if (match_data->flags & WAVE5_IS_DEC)
407		wave5_vpu_dec_unregister_device(dev);
408err_v4l2_unregister:
409	v4l2_device_unregister(&dev->v4l2_dev);
410err_vdi_release:
411	wave5_vdi_release(&pdev->dev);
412err_clk_dis:
413	clk_bulk_disable_unprepare(dev->num_clks, dev->clks);
414err_reset_assert:
415	reset_control_assert(dev->resets);
416
417	return ret;
418}
419
420static void wave5_vpu_remove(struct platform_device *pdev)
421{
422	struct vpu_device *dev = dev_get_drvdata(&pdev->dev);
423
424	wave5_vpu_enc_unregister_device(dev);
425	wave5_vpu_dec_unregister_device(dev);
426	v4l2_device_unregister(&dev->v4l2_dev);
427
428	if (dev->irq < 0) {
429		if (dev->irq_thread) {
430			kthread_stop(dev->irq_thread);
431			up(&dev->irq_sem);
432			dev->irq_thread = NULL;
433		}
434
435		hrtimer_cancel(&dev->hrtimer);
436		kthread_cancel_work_sync(&dev->work);
437		kthread_destroy_worker(dev->worker);
438	}
439
440	pm_runtime_dont_use_autosuspend(&pdev->dev);
441	pm_runtime_disable(&pdev->dev);
442
443	mutex_destroy(&dev->dev_lock);
444	mutex_destroy(&dev->hw_lock);
445	mutex_destroy(&dev->irq_lock);
446	reset_control_assert(dev->resets);
447	clk_bulk_disable_unprepare(dev->num_clks, dev->clks);
448	wave5_vdi_release(&pdev->dev);
449	ida_destroy(&dev->inst_ida);
450}
451
452static const struct wave5_match_data ti_wave521c_data = {
453	.flags = WAVE5_IS_ENC | WAVE5_IS_DEC,
454	.fw_name = "cnm/wave521c_k3_codec_fw.bin",
455	.sram_size = (64 * 1024),
456};
457
458static const struct of_device_id wave5_dt_ids[] = {
459	{ .compatible = "ti,j721s2-wave521c", .data = &ti_wave521c_data },
460	{ /* sentinel */ }
461};
462MODULE_DEVICE_TABLE(of, wave5_dt_ids);
463
464static struct platform_driver wave5_vpu_driver = {
465	.driver = {
466		.name = VPU_PLATFORM_DEVICE_NAME,
467		.of_match_table = of_match_ptr(wave5_dt_ids),
468		.pm = &wave5_pm_ops,
469		},
470	.probe = wave5_vpu_probe,
471	.remove = wave5_vpu_remove,
472};
473
474module_platform_driver(wave5_vpu_driver);
475MODULE_DESCRIPTION("chips&media VPU V4L2 driver");
476MODULE_LICENSE("Dual BSD/GPL");