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wave5-hw.c
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linux-6.19.14/drivers/media/platform/chips-media/wave5/wave5-hw.c
1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2/* 3 * Wave5 series multi-standard codec IP - wave5 backend logic 4 * 5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC 6 */ 7 8#include <linux/iopoll.h> 9#include <linux/bitfield.h> 10#include "wave5-vpu.h" 11#include "wave5.h" 12#include "wave5-regdefine.h" 13 14#define FIO_TIMEOUT 10000000 15#define FIO_CTRL_READY BIT(31) 16#define FIO_CTRL_WRITE BIT(16) 17#define VPU_BUSY_CHECK_TIMEOUT 10000000 18#define QUEUE_REPORT_MASK 0xffff 19 20/* Encoder support fields */ 21#define W521_FEATURE_HEVC10BIT_ENC BIT(3) 22#define W521_FEATURE_AVC10BIT_ENC BIT(11) 23#define W521_FEATURE_AVC_ENCODER BIT(1) 24#define W521_FEATURE_HEVC_ENCODER BIT(0) 25 26#define ENC_AVC_INTRA_IDR_PARAM_MASK 0x7ff 27#define ENC_AVC_INTRA_PERIOD_SHIFT 6 28#define ENC_AVC_IDR_PERIOD_SHIFT 17 29#define ENC_AVC_FORCED_IDR_HEADER_SHIFT 28 30 31#define ENC_HEVC_INTRA_QP_SHIFT 3 32#define ENC_HEVC_FORCED_IDR_HEADER_SHIFT 9 33#define ENC_HEVC_INTRA_PERIOD_SHIFT 16 34 35/* Decoder support fields */ 36#define W521_FEATURE_AVC_DECODER BIT(3) 37#define W521_FEATURE_HEVC_DECODER BIT(2) 38#define W515_FEATURE_HEVC10BIT_DEC BIT(1) 39#define W515_FEATURE_HEVC_DECODER BIT(0) 40 41#define W521_FEATURE_BACKBONE BIT(16) 42#define W521_FEATURE_VCORE_BACKBONE BIT(22) 43#define W521_FEATURE_VCPU_BACKBONE BIT(28) 44 45#define REMAP_CTRL_MAX_SIZE_BITS ((W5_REMAP_MAX_SIZE >> 12) & 0x1ff) 46#define REMAP_CTRL_REGISTER_VALUE(index) ( \ 47 (BIT(31) | ((index) << 12) | BIT(11) | REMAP_CTRL_MAX_SIZE_BITS)\ 48) 49 50#define FASTIO_ADDRESS_MASK GENMASK(15, 0) 51#define SEQ_PARAM_PROFILE_MASK GENMASK(30, 24) 52 53static void _wave5_print_reg_err(struct vpu_device *vpu_dev, u32 reg_fail_reason, 54 const char *func); 55#define PRINT_REG_ERR(dev, reason) _wave5_print_reg_err((dev), (reason), __func__) 56 57static inline const char *cmd_to_str(int cmd, bool is_dec) 58{ 59 switch (cmd) { 60 case W5_INIT_VPU: 61 return "W5_INIT_VPU"; 62 case W5_WAKEUP_VPU: 63 return "W5_WAKEUP_VPU"; 64 case W5_SLEEP_VPU: 65 return "W5_SLEEP_VPU"; 66 case W5_CREATE_INSTANCE: 67 return "W5_CREATE_INSTANCE"; 68 case W5_FLUSH_INSTANCE: 69 return "W5_FLUSH_INSTANCE"; 70 case W5_DESTROY_INSTANCE: 71 return "W5_DESTROY_INSTANCE"; 72 case W5_INIT_SEQ: 73 return "W5_INIT_SEQ"; 74 case W5_SET_FB: 75 return "W5_SET_FB"; 76 case W5_DEC_ENC_PIC: 77 if (is_dec) 78 return "W5_DEC_PIC"; 79 return "W5_ENC_PIC"; 80 case W5_ENC_SET_PARAM: 81 return "W5_ENC_SET_PARAM"; 82 case W5_QUERY: 83 return "W5_QUERY"; 84 case W5_UPDATE_BS: 85 return "W5_UPDATE_BS"; 86 case W5_MAX_VPU_COMD: 87 return "W5_MAX_VPU_COMD"; 88 default: 89 return "UNKNOWN"; 90 } 91} 92 93static void _wave5_print_reg_err(struct vpu_device *vpu_dev, u32 reg_fail_reason, 94 const char *func) 95{ 96 struct device *dev = vpu_dev->dev; 97 u32 reg_val; 98 99 switch (reg_fail_reason) { 100 case WAVE5_SYSERR_QUEUEING_FAIL: 101 reg_val = vpu_read_reg(vpu_dev, W5_RET_QUEUE_FAIL_REASON); 102 dev_dbg(dev, "%s: queueing failure: 0x%x\n", func, reg_val); 103 break; 104 case WAVE5_SYSERR_RESULT_NOT_READY: 105 dev_err(dev, "%s: result not ready: 0x%x\n", func, reg_fail_reason); 106 break; 107 case WAVE5_SYSERR_ACCESS_VIOLATION_HW: 108 dev_err(dev, "%s: access violation: 0x%x\n", func, reg_fail_reason); 109 break; 110 case WAVE5_SYSERR_WATCHDOG_TIMEOUT: 111 dev_err(dev, "%s: watchdog timeout: 0x%x\n", func, reg_fail_reason); 112 break; 113 case WAVE5_SYSERR_BUS_ERROR: 114 dev_err(dev, "%s: bus error: 0x%x\n", func, reg_fail_reason); 115 break; 116 case WAVE5_SYSERR_DOUBLE_FAULT: 117 dev_err(dev, "%s: double fault: 0x%x\n", func, reg_fail_reason); 118 break; 119 case WAVE5_SYSERR_VPU_STILL_RUNNING: 120 dev_err(dev, "%s: still running: 0x%x\n", func, reg_fail_reason); 121 break; 122 case WAVE5_SYSERR_VLC_BUF_FULL: 123 dev_err(dev, "%s: vlc buf full: 0x%x\n", func, reg_fail_reason); 124 break; 125 default: 126 dev_err(dev, "%s: failure:: 0x%x\n", func, reg_fail_reason); 127 break; 128 } 129} 130 131static int wave5_wait_fio_readl(struct vpu_device *vpu_dev, u32 addr, u32 val) 132{ 133 u32 ctrl; 134 int ret; 135 136 ctrl = addr & 0xffff; 137 wave5_vdi_write_register(vpu_dev, W5_VPU_FIO_CTRL_ADDR, ctrl); 138 ret = read_poll_timeout(wave5_vdi_read_register, ctrl, ctrl & FIO_CTRL_READY, 139 0, FIO_TIMEOUT, false, vpu_dev, W5_VPU_FIO_CTRL_ADDR); 140 if (ret) 141 return ret; 142 143 if (wave5_vdi_read_register(vpu_dev, W5_VPU_FIO_DATA) != val) 144 return -ETIMEDOUT; 145 146 return 0; 147} 148 149static void wave5_fio_writel(struct vpu_device *vpu_dev, unsigned int addr, unsigned int data) 150{ 151 int ret; 152 unsigned int ctrl; 153 154 wave5_vdi_write_register(vpu_dev, W5_VPU_FIO_DATA, data); 155 ctrl = FIELD_GET(FASTIO_ADDRESS_MASK, addr); 156 ctrl |= FIO_CTRL_WRITE; 157 wave5_vdi_write_register(vpu_dev, W5_VPU_FIO_CTRL_ADDR, ctrl); 158 ret = read_poll_timeout(wave5_vdi_read_register, ctrl, ctrl & FIO_CTRL_READY, 0, 159 FIO_TIMEOUT, false, vpu_dev, W5_VPU_FIO_CTRL_ADDR); 160 if (ret) 161 dev_dbg_ratelimited(vpu_dev->dev, "FIO write timeout: addr=0x%x data=%x\n", 162 ctrl, data); 163} 164 165static int wave5_wait_bus_busy(struct vpu_device *vpu_dev, unsigned int addr) 166{ 167 u32 gdi_status_check_value = 0x3f; 168 169 if (vpu_dev->product_code == WAVE515_CODE) 170 gdi_status_check_value = 0x0738; 171 if (vpu_dev->product_code == WAVE521C_CODE || 172 vpu_dev->product_code == WAVE521_CODE || 173 vpu_dev->product_code == WAVE521E1_CODE) 174 gdi_status_check_value = 0x00ff1f3f; 175 176 return wave5_wait_fio_readl(vpu_dev, addr, gdi_status_check_value); 177} 178 179static int wave5_wait_vpu_busy(struct vpu_device *vpu_dev, unsigned int addr) 180{ 181 u32 data; 182 183 return read_poll_timeout(wave5_vdi_read_register, data, data == 0, 184 0, VPU_BUSY_CHECK_TIMEOUT, false, vpu_dev, addr); 185} 186 187static int wave5_wait_vcpu_bus_busy(struct vpu_device *vpu_dev, unsigned int addr) 188{ 189 return wave5_wait_fio_readl(vpu_dev, addr, 0); 190} 191 192bool wave5_vpu_is_init(struct vpu_device *vpu_dev) 193{ 194 return vpu_read_reg(vpu_dev, W5_VCPU_CUR_PC) != 0; 195} 196 197unsigned int wave5_vpu_get_product_id(struct vpu_device *vpu_dev) 198{ 199 u32 val = vpu_read_reg(vpu_dev, W5_PRODUCT_NUMBER); 200 201 switch (val) { 202 case WAVE515_CODE: 203 return PRODUCT_ID_515; 204 case WAVE521C_CODE: 205 return PRODUCT_ID_521; 206 case WAVE521_CODE: 207 case WAVE521C_DUAL_CODE: 208 case WAVE521E1_CODE: 209 case WAVE511_CODE: 210 case WAVE517_CODE: 211 case WAVE537_CODE: 212 dev_err(vpu_dev->dev, "Unsupported product id (%x)\n", val); 213 break; 214 default: 215 dev_err(vpu_dev->dev, "Invalid product id (%x)\n", val); 216 break; 217 } 218 219 return PRODUCT_ID_NONE; 220} 221 222static void wave5_bit_issue_command(struct vpu_device *vpu_dev, struct vpu_instance *inst, u32 cmd) 223{ 224 u32 instance_index; 225 u32 codec_mode; 226 227 if (inst) { 228 instance_index = inst->id; 229 codec_mode = inst->std; 230 231 vpu_write_reg(vpu_dev, W5_CMD_INSTANCE_INFO, (codec_mode << 16) | 232 (instance_index & 0xffff)); 233 vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); 234 } 235 236 vpu_write_reg(vpu_dev, W5_COMMAND, cmd); 237 238 if (inst) { 239 dev_dbg(vpu_dev->dev, "%s: cmd=0x%x (%s)\n", __func__, cmd, 240 cmd_to_str(cmd, inst->type == VPU_INST_TYPE_DEC)); 241 } else { 242 dev_dbg(vpu_dev->dev, "%s: cmd=0x%x\n", __func__, cmd); 243 } 244 245 vpu_write_reg(vpu_dev, W5_VPU_HOST_INT_REQ, 1); 246} 247 248static int wave5_vpu_firmware_command_queue_error_check(struct vpu_device *dev, u32 *fail_res) 249{ 250 u32 reason = 0; 251 252 /* Check if we were able to add a command into the VCPU QUEUE */ 253 if (!vpu_read_reg(dev, W5_RET_SUCCESS)) { 254 reason = vpu_read_reg(dev, W5_RET_FAIL_REASON); 255 PRINT_REG_ERR(dev, reason); 256 257 /* 258 * The fail_res argument will be either NULL or 0. 259 * If the fail_res argument is NULL, then just return -EIO. 260 * Otherwise, assign the reason to fail_res, so that the 261 * calling function can use it. 262 */ 263 if (fail_res) 264 *fail_res = reason; 265 else 266 return -EIO; 267 268 if (reason == WAVE5_SYSERR_VPU_STILL_RUNNING) 269 return -EBUSY; 270 } 271 return 0; 272} 273 274static int send_firmware_command(struct vpu_instance *inst, u32 cmd, bool check_success, 275 u32 *queue_status, u32 *fail_result) 276{ 277 int ret; 278 279 wave5_bit_issue_command(inst->dev, inst, cmd); 280 ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); 281 if (ret) { 282 dev_warn(inst->dev->dev, "%s: command: '%s', timed out\n", __func__, 283 cmd_to_str(cmd, inst->type == VPU_INST_TYPE_DEC)); 284 return -ETIMEDOUT; 285 } 286 287 if (queue_status) 288 *queue_status = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); 289 290 /* In some cases we want to send multiple commands before checking 291 * whether they are queued properly 292 */ 293 if (!check_success) 294 return 0; 295 296 return wave5_vpu_firmware_command_queue_error_check(inst->dev, fail_result); 297} 298 299static int wave5_send_query(struct vpu_device *vpu_dev, struct vpu_instance *inst, 300 enum query_opt query_opt) 301{ 302 int ret; 303 304 vpu_write_reg(vpu_dev, W5_QUERY_OPTION, query_opt); 305 vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); 306 wave5_bit_issue_command(vpu_dev, inst, W5_QUERY); 307 308 ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); 309 if (ret) { 310 dev_warn(vpu_dev->dev, "command: 'W5_QUERY', timed out opt=0x%x\n", query_opt); 311 return ret; 312 } 313 314 return wave5_vpu_firmware_command_queue_error_check(vpu_dev, NULL); 315} 316 317static void setup_wave5_interrupts(struct vpu_device *vpu_dev) 318{ 319 u32 reg_val = 0; 320 321 if (vpu_dev->attr.support_encoders) { 322 /* Encoder interrupt */ 323 reg_val |= BIT(INT_WAVE5_ENC_SET_PARAM); 324 reg_val |= BIT(INT_WAVE5_ENC_PIC); 325 reg_val |= BIT(INT_WAVE5_BSBUF_FULL); 326 } 327 328 if (vpu_dev->attr.support_decoders) { 329 /* Decoder interrupt */ 330 reg_val |= BIT(INT_WAVE5_INIT_SEQ); 331 reg_val |= BIT(INT_WAVE5_DEC_PIC); 332 reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY); 333 } 334 335 return vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val); 336} 337 338static int setup_wave5_properties(struct device *dev) 339{ 340 struct vpu_device *vpu_dev = dev_get_drvdata(dev); 341 struct vpu_attr *p_attr = &vpu_dev->attr; 342 u32 reg_val; 343 u8 *str; 344 int ret; 345 u32 hw_config_def0, hw_config_def1, hw_config_feature; 346 347 ret = wave5_send_query(vpu_dev, NULL, GET_VPU_INFO); 348 if (ret) 349 return ret; 350 351 reg_val = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_NAME); 352 str = (u8 *)®_val; 353 p_attr->product_name[0] = str[3]; 354 p_attr->product_name[1] = str[2]; 355 p_attr->product_name[2] = str[1]; 356 p_attr->product_name[3] = str[0]; 357 p_attr->product_name[4] = 0; 358 359 p_attr->product_id = wave5_vpu_get_product_id(vpu_dev); 360 p_attr->product_version = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_VERSION); 361 p_attr->fw_version = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION); 362 p_attr->customer_id = vpu_read_reg(vpu_dev, W5_RET_CUSTOMER_ID); 363 hw_config_def0 = vpu_read_reg(vpu_dev, W5_RET_STD_DEF0); 364 hw_config_def1 = vpu_read_reg(vpu_dev, W5_RET_STD_DEF1); 365 hw_config_feature = vpu_read_reg(vpu_dev, W5_RET_CONF_FEATURE); 366 367 if (vpu_dev->product_code == WAVE515_CODE) { 368 p_attr->support_hevc10bit_dec = FIELD_GET(W515_FEATURE_HEVC10BIT_DEC, 369 hw_config_feature); 370 p_attr->support_decoders = FIELD_GET(W515_FEATURE_HEVC_DECODER, 371 hw_config_def1) << STD_HEVC; 372 } else { 373 p_attr->support_hevc10bit_enc = FIELD_GET(W521_FEATURE_HEVC10BIT_ENC, 374 hw_config_feature); 375 p_attr->support_avc10bit_enc = FIELD_GET(W521_FEATURE_AVC10BIT_ENC, 376 hw_config_feature); 377 378 p_attr->support_decoders = FIELD_GET(W521_FEATURE_AVC_DECODER, 379 hw_config_def1) << STD_AVC; 380 p_attr->support_decoders |= FIELD_GET(W521_FEATURE_HEVC_DECODER, 381 hw_config_def1) << STD_HEVC; 382 p_attr->support_encoders = FIELD_GET(W521_FEATURE_AVC_ENCODER, 383 hw_config_def1) << STD_AVC; 384 p_attr->support_encoders |= FIELD_GET(W521_FEATURE_HEVC_ENCODER, 385 hw_config_def1) << STD_HEVC; 386 387 p_attr->support_backbone = FIELD_GET(W521_FEATURE_BACKBONE, 388 hw_config_def0); 389 p_attr->support_vcpu_backbone = FIELD_GET(W521_FEATURE_VCPU_BACKBONE, 390 hw_config_def0); 391 p_attr->support_vcore_backbone = FIELD_GET(W521_FEATURE_VCORE_BACKBONE, 392 hw_config_def0); 393 } 394 395 setup_wave5_interrupts(vpu_dev); 396 397 return 0; 398} 399 400int wave5_vpu_get_version(struct vpu_device *vpu_dev, u32 *revision) 401{ 402 u32 reg_val; 403 int ret; 404 405 ret = wave5_send_query(vpu_dev, NULL, GET_VPU_INFO); 406 if (ret) 407 return ret; 408 409 reg_val = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION); 410 if (revision) { 411 *revision = reg_val; 412 return 0; 413 } 414 415 return -EINVAL; 416} 417 418static void remap_page(struct vpu_device *vpu_dev, dma_addr_t code_base, u32 index) 419{ 420 vpu_write_reg(vpu_dev, W5_VPU_REMAP_CTRL, REMAP_CTRL_REGISTER_VALUE(index)); 421 vpu_write_reg(vpu_dev, W5_VPU_REMAP_VADDR, index * W5_REMAP_MAX_SIZE); 422 vpu_write_reg(vpu_dev, W5_VPU_REMAP_PADDR, code_base + index * W5_REMAP_MAX_SIZE); 423} 424 425int wave5_vpu_init(struct device *dev, u8 *fw, size_t size) 426{ 427 struct vpu_buf *common_vb; 428 dma_addr_t code_base, temp_base; 429 u32 code_size, temp_size; 430 u32 i, reg_val, reason_code; 431 int ret; 432 struct vpu_device *vpu_dev = dev_get_drvdata(dev); 433 434 common_vb = &vpu_dev->common_mem; 435 436 code_base = common_vb->daddr; 437 438 if (vpu_dev->product_code == WAVE515_CODE) 439 code_size = WAVE515_MAX_CODE_BUF_SIZE; 440 else 441 code_size = WAVE521_MAX_CODE_BUF_SIZE; 442 443 /* ALIGN TO 4KB */ 444 code_size &= ~0xfff; 445 if (code_size < size * 2) 446 return -EINVAL; 447 448 temp_base = code_base + code_size; 449 temp_size = WAVE5_TEMPBUF_SIZE; 450 451 ret = wave5_vdi_write_memory(vpu_dev, common_vb, 0, fw, size); 452 if (ret < 0) { 453 dev_err(vpu_dev->dev, "VPU init, Writing firmware to common buffer, fail: %d\n", 454 ret); 455 return ret; 456 } 457 458 vpu_write_reg(vpu_dev, W5_PO_CONF, 0); 459 460 /* clear registers */ 461 462 for (i = W5_CMD_REG_BASE; i < W5_CMD_REG_END; i += 4) 463 vpu_write_reg(vpu_dev, i, 0x00); 464 465 remap_page(vpu_dev, code_base, W5_REMAP_INDEX0); 466 remap_page(vpu_dev, code_base, W5_REMAP_INDEX1); 467 468 vpu_write_reg(vpu_dev, W5_ADDR_CODE_BASE, code_base); 469 vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size); 470 vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID << 4) | 0); 471 vpu_write_reg(vpu_dev, W5_ADDR_TEMP_BASE, temp_base); 472 vpu_write_reg(vpu_dev, W5_TEMP_SIZE, temp_size); 473 474 /* These register must be reset explicitly */ 475 vpu_write_reg(vpu_dev, W5_HW_OPTION, 0); 476 477 if (vpu_dev->product_code != WAVE515_CODE) { 478 wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0); 479 wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0); 480 vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0); 481 } 482 483 reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); 484 if (FIELD_GET(W521_FEATURE_BACKBONE, reg_val)) { 485 reg_val = ((WAVE5_PROC_AXI_ID << 28) | 486 (WAVE5_PRP_AXI_ID << 24) | 487 (WAVE5_FBD_Y_AXI_ID << 20) | 488 (WAVE5_FBC_Y_AXI_ID << 16) | 489 (WAVE5_FBD_C_AXI_ID << 12) | 490 (WAVE5_FBC_C_AXI_ID << 8) | 491 (WAVE5_PRI_AXI_ID << 4) | 492 WAVE5_SEC_AXI_ID); 493 wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val); 494 } 495 496 if (vpu_dev->product_code == WAVE515_CODE) { 497 dma_addr_t task_buf_base; 498 499 vpu_write_reg(vpu_dev, W5_CMD_INIT_NUM_TASK_BUF, WAVE515_COMMAND_QUEUE_DEPTH); 500 vpu_write_reg(vpu_dev, W5_CMD_INIT_TASK_BUF_SIZE, WAVE515_ONE_TASKBUF_SIZE); 501 502 for (i = 0; i < WAVE515_COMMAND_QUEUE_DEPTH; i++) { 503 task_buf_base = temp_base + temp_size + 504 (i * WAVE515_ONE_TASKBUF_SIZE); 505 vpu_write_reg(vpu_dev, 506 W5_CMD_INIT_ADDR_TASK_BUF0 + (i * 4), 507 task_buf_base); 508 } 509 510 vpu_write_reg(vpu_dev, W515_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr); 511 vpu_write_reg(vpu_dev, W515_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size); 512 } 513 514 vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); 515 vpu_write_reg(vpu_dev, W5_COMMAND, W5_INIT_VPU); 516 vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1); 517 ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); 518 if (ret) { 519 dev_err(vpu_dev->dev, "VPU init(W5_VPU_REMAP_CORE_START) timeout\n"); 520 return ret; 521 } 522 523 ret = wave5_vpu_firmware_command_queue_error_check(vpu_dev, &reason_code); 524 if (ret) 525 return ret; 526 527 return setup_wave5_properties(dev); 528} 529 530int wave5_vpu_build_up_dec_param(struct vpu_instance *inst, 531 struct dec_open_param *param) 532{ 533 int ret; 534 struct dec_info *p_dec_info = &inst->codec_info->dec_info; 535 struct vpu_device *vpu_dev = inst->dev; 536 537 p_dec_info->cycle_per_tick = 256; 538 if (vpu_dev->sram_buf.size) { 539 p_dec_info->sec_axi_info.use_bit_enable = 1; 540 p_dec_info->sec_axi_info.use_ip_enable = 1; 541 p_dec_info->sec_axi_info.use_lf_row_enable = 1; 542 } 543 switch (inst->std) { 544 case W_HEVC_DEC: 545 p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_HEVC; 546 break; 547 case W_AVC_DEC: 548 p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_AVC; 549 break; 550 default: 551 return -EINVAL; 552 } 553 554 if (vpu_dev->product == PRODUCT_ID_515) 555 p_dec_info->vb_work.size = WAVE515DEC_WORKBUF_SIZE; 556 else 557 p_dec_info->vb_work.size = WAVE521DEC_WORKBUF_SIZE; 558 559 ret = wave5_vdi_allocate_dma_memory(inst->dev, &p_dec_info->vb_work); 560 if (ret) 561 return ret; 562 563 if (inst->dev->product_code != WAVE515_CODE) 564 vpu_write_reg(inst->dev, W5_CMD_DEC_VCORE_INFO, 1); 565 566 wave5_vdi_clear_memory(inst->dev, &p_dec_info->vb_work); 567 568 vpu_write_reg(inst->dev, W5_ADDR_WORK_BASE, p_dec_info->vb_work.daddr); 569 vpu_write_reg(inst->dev, W5_WORK_SIZE, p_dec_info->vb_work.size); 570 571 if (inst->dev->product_code != WAVE515_CODE) { 572 vpu_write_reg(inst->dev, W5_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr); 573 vpu_write_reg(inst->dev, W5_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size); 574 } 575 576 vpu_write_reg(inst->dev, W5_CMD_DEC_BS_START_ADDR, p_dec_info->stream_buf_start_addr); 577 vpu_write_reg(inst->dev, W5_CMD_DEC_BS_SIZE, p_dec_info->stream_buf_size); 578 579 /* NOTE: SDMA reads MSB first */ 580 vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, BITSTREAM_ENDIANNESS_BIG_ENDIAN); 581 582 if (inst->dev->product_code != WAVE515_CODE) { 583 /* This register must be reset explicitly */ 584 vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, 0); 585 vpu_write_reg(inst->dev, W5_CMD_NUM_CQ_DEPTH_M1, 586 WAVE521_COMMAND_QUEUE_DEPTH - 1); 587 } 588 vpu_write_reg(inst->dev, W5_CMD_ERR_CONCEAL, 0); 589 ret = send_firmware_command(inst, W5_CREATE_INSTANCE, true, NULL, NULL); 590 if (ret) { 591 wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_work); 592 return ret; 593 } 594 595 p_dec_info->product_code = vpu_read_reg(inst->dev, W5_PRODUCT_NUMBER); 596 597 return 0; 598} 599 600int wave5_vpu_hw_flush_instance(struct vpu_instance *inst) 601{ 602 struct dec_info *p_dec_info = &inst->codec_info->dec_info; 603 u32 instance_queue_count, report_queue_count; 604 u32 reg_val = 0; 605 u32 fail_res = 0; 606 int ret; 607 608 ret = send_firmware_command(inst, W5_FLUSH_INSTANCE, true, ®_val, &fail_res); 609 if (ret) 610 return ret; 611 612 instance_queue_count = (reg_val >> 16) & 0xff; 613 report_queue_count = (reg_val & QUEUE_REPORT_MASK); 614 if (instance_queue_count != 0 || report_queue_count != 0) { 615 dev_warn(inst->dev->dev, 616 "FLUSH_INSTANCE cmd didn't reset the amount of queued commands & reports"); 617 } 618 619 /* reset our local copy of the counts */ 620 p_dec_info->instance_queue_count = 0; 621 p_dec_info->report_queue_count = 0; 622 623 return 0; 624} 625 626static u32 get_bitstream_options(struct dec_info *info) 627{ 628 u32 bs_option = BSOPTION_ENABLE_EXPLICIT_END; 629 630 if (info->stream_endflag) 631 bs_option |= BSOPTION_HIGHLIGHT_STREAM_END; 632 return bs_option; 633} 634 635int wave5_vpu_dec_init_seq(struct vpu_instance *inst) 636{ 637 struct dec_info *p_dec_info = &inst->codec_info->dec_info; 638 u32 bs_option, cmd_option = INIT_SEQ_NORMAL; 639 u32 reg_val, fail_res; 640 int ret; 641 642 if (!inst->codec_info) 643 return -EINVAL; 644 645 vpu_write_reg(inst->dev, W5_BS_RD_PTR, p_dec_info->stream_rd_ptr); 646 vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); 647 648 bs_option = get_bitstream_options(p_dec_info); 649 650 /* Without RD_PTR_VALID_FLAG Wave515 ignores RD_PTR value */ 651 if (inst->dev->product_code == WAVE515_CODE) 652 bs_option |= BSOPTION_RD_PTR_VALID_FLAG; 653 654 vpu_write_reg(inst->dev, W5_BS_OPTION, bs_option); 655 656 vpu_write_reg(inst->dev, W5_COMMAND_OPTION, cmd_option); 657 vpu_write_reg(inst->dev, W5_CMD_DEC_USER_MASK, p_dec_info->user_data_enable); 658 659 ret = send_firmware_command(inst, W5_INIT_SEQ, true, ®_val, &fail_res); 660 if (ret) 661 return ret; 662 663 p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; 664 p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); 665 666 dev_dbg(inst->dev->dev, "%s: init seq sent (queue %u : %u)\n", __func__, 667 p_dec_info->instance_queue_count, p_dec_info->report_queue_count); 668 669 return 0; 670} 671 672static void wave5_get_dec_seq_result(struct vpu_instance *inst, struct dec_initial_info *info) 673{ 674 u32 reg_val; 675 u32 profile_compatibility_flag; 676 struct dec_info *p_dec_info = &inst->codec_info->dec_info; 677 678 p_dec_info->stream_rd_ptr = wave5_dec_get_rd_ptr(inst); 679 info->rd_ptr = p_dec_info->stream_rd_ptr; 680 681 p_dec_info->frame_display_flag = vpu_read_reg(inst->dev, W5_RET_DEC_DISP_IDC); 682 683 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_SIZE); 684 info->pic_width = ((reg_val >> 16) & 0xffff); 685 info->pic_height = (reg_val & 0xffff); 686 info->min_frame_buffer_count = vpu_read_reg(inst->dev, W5_RET_DEC_NUM_REQUIRED_FB); 687 688 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_LEFT_RIGHT); 689 info->pic_crop_rect.left = (reg_val >> 16) & 0xffff; 690 info->pic_crop_rect.right = reg_val & 0xffff; 691 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_TOP_BOTTOM); 692 info->pic_crop_rect.top = (reg_val >> 16) & 0xffff; 693 info->pic_crop_rect.bottom = reg_val & 0xffff; 694 695 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_COLOR_SAMPLE_INFO); 696 info->luma_bitdepth = reg_val & 0xf; 697 info->chroma_bitdepth = (reg_val >> 4) & 0xf; 698 699 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_SEQ_PARAM); 700 profile_compatibility_flag = (reg_val >> 12) & 0xff; 701 info->profile = (reg_val >> 24) & 0x1f; 702 703 if (inst->std == W_HEVC_DEC) { 704 /* guessing profile */ 705 if (!info->profile) { 706 if ((profile_compatibility_flag & 0x06) == 0x06) 707 info->profile = HEVC_PROFILE_MAIN; /* main profile */ 708 else if (profile_compatibility_flag & 0x04) 709 info->profile = HEVC_PROFILE_MAIN10; /* main10 profile */ 710 else if (profile_compatibility_flag & 0x08) 711 /* main still picture profile */ 712 info->profile = HEVC_PROFILE_STILLPICTURE; 713 else 714 info->profile = HEVC_PROFILE_MAIN; /* for old version HM */ 715 } 716 } else if (inst->std == W_AVC_DEC) { 717 info->profile = FIELD_GET(SEQ_PARAM_PROFILE_MASK, reg_val); 718 } 719 720 if (inst->dev->product_code != WAVE515_CODE) { 721 info->vlc_buf_size = vpu_read_reg(inst->dev, W5_RET_VLC_BUF_SIZE); 722 info->param_buf_size = vpu_read_reg(inst->dev, W5_RET_PARAM_BUF_SIZE); 723 p_dec_info->vlc_buf_size = info->vlc_buf_size; 724 p_dec_info->param_buf_size = info->param_buf_size; 725 } 726} 727 728int wave5_vpu_dec_get_seq_info(struct vpu_instance *inst, struct dec_initial_info *info) 729{ 730 int ret; 731 u32 reg_val; 732 struct dec_info *p_dec_info = &inst->codec_info->dec_info; 733 734 vpu_write_reg(inst->dev, W5_CMD_DEC_ADDR_REPORT_BASE, p_dec_info->user_data_buf_addr); 735 vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_SIZE, p_dec_info->user_data_buf_size); 736 vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_PARAM, REPORT_PARAM_ENDIANNESS_BIG_ENDIAN); 737 738 /* send QUERY cmd */ 739 ret = wave5_send_query(inst->dev, inst, GET_RESULT); 740 if (ret) 741 return ret; 742 743 reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); 744 745 p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; 746 p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); 747 748 dev_dbg(inst->dev->dev, "%s: init seq complete (queue %u : %u)\n", __func__, 749 p_dec_info->instance_queue_count, p_dec_info->report_queue_count); 750 751 /* this is not a fatal error, set ret to -EIO but don't return immediately */ 752 if (vpu_read_reg(inst->dev, W5_RET_DEC_DECODING_SUCCESS) != 1) { 753 info->seq_init_err_reason = vpu_read_reg(inst->dev, W5_RET_DEC_ERR_INFO); 754 ret = -EIO; 755 } 756 757 wave5_get_dec_seq_result(inst, info); 758 759 return ret; 760} 761 762int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst, struct frame_buffer *fb_arr, 763 enum tiled_map_type map_type, unsigned int count) 764{ 765 int ret; 766 struct dec_info *p_dec_info = &inst->codec_info->dec_info; 767 struct dec_initial_info *init_info = &p_dec_info->initial_info; 768 size_t remain, idx, j, i, cnt_8_chunk, size; 769 u32 start_no, end_no; 770 u32 reg_val, cbcr_interleave, nv21, pic_size; 771 u32 addr_y, addr_cb, addr_cr; 772 u32 mv_col_size, frame_width, frame_height, fbc_y_tbl_size, fbc_c_tbl_size; 773 struct vpu_buf vb_buf; 774 bool justified = WTL_RIGHT_JUSTIFIED; 775 u32 format_no = WTL_PIXEL_8BIT; 776 u32 color_format = 0; 777 u32 pixel_order = 1; 778 u32 bwb_flag = (map_type == LINEAR_FRAME_MAP) ? 1 : 0; 779 780 cbcr_interleave = inst->cbcr_interleave; 781 nv21 = inst->nv21; 782 mv_col_size = 0; 783 fbc_y_tbl_size = 0; 784 fbc_c_tbl_size = 0; 785 786 if (map_type >= COMPRESSED_FRAME_MAP) { 787 cbcr_interleave = 0; 788 nv21 = 0; 789 790 switch (inst->std) { 791 case W_HEVC_DEC: 792 mv_col_size = WAVE5_DEC_HEVC_BUF_SIZE(init_info->pic_width, 793 init_info->pic_height); 794 break; 795 case W_AVC_DEC: 796 mv_col_size = WAVE5_DEC_AVC_BUF_SIZE(init_info->pic_width, 797 init_info->pic_height); 798 break; 799 default: 800 return -EINVAL; 801 } 802 803 if (inst->std == W_HEVC_DEC || inst->std == W_AVC_DEC) { 804 size = ALIGN(ALIGN(mv_col_size, 16), BUFFER_MARGIN) + BUFFER_MARGIN; 805 ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_mv, count, size); 806 if (ret) 807 goto free_mv_buffers; 808 } 809 810 frame_width = init_info->pic_width; 811 frame_height = init_info->pic_height; 812 fbc_y_tbl_size = ALIGN(WAVE5_FBC_LUMA_TABLE_SIZE(frame_width, frame_height), 16); 813 fbc_c_tbl_size = ALIGN(WAVE5_FBC_CHROMA_TABLE_SIZE(frame_width, frame_height), 16); 814 815 size = ALIGN(fbc_y_tbl_size, BUFFER_MARGIN) + BUFFER_MARGIN; 816 ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_fbc_y_tbl, count, size); 817 if (ret) 818 goto free_fbc_y_tbl_buffers; 819 820 size = ALIGN(fbc_c_tbl_size, BUFFER_MARGIN) + BUFFER_MARGIN; 821 ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_fbc_c_tbl, count, size); 822 if (ret) 823 goto free_fbc_c_tbl_buffers; 824 825 pic_size = (init_info->pic_width << 16) | (init_info->pic_height); 826 827 if (inst->dev->product_code != WAVE515_CODE) { 828 vb_buf.size = (p_dec_info->vlc_buf_size * VLC_BUF_NUM) + 829 (p_dec_info->param_buf_size * WAVE521_COMMAND_QUEUE_DEPTH); 830 vb_buf.daddr = 0; 831 832 if (vb_buf.size != p_dec_info->vb_task.size) { 833 wave5_vdi_free_dma_memory(inst->dev, 834 &p_dec_info->vb_task); 835 ret = wave5_vdi_allocate_dma_memory(inst->dev, 836 &vb_buf); 837 if (ret) 838 goto free_fbc_c_tbl_buffers; 839 840 p_dec_info->vb_task = vb_buf; 841 } 842 843 vpu_write_reg(inst->dev, W5_CMD_SET_FB_ADDR_TASK_BUF, 844 p_dec_info->vb_task.daddr); 845 vpu_write_reg(inst->dev, W5_CMD_SET_FB_TASK_BUF_SIZE, 846 vb_buf.size); 847 } 848 } else { 849 pic_size = (init_info->pic_width << 16) | (init_info->pic_height); 850 851 if (inst->output_format == FORMAT_422) 852 color_format = 1; 853 } 854 vpu_write_reg(inst->dev, W5_PIC_SIZE, pic_size); 855 856 reg_val = (bwb_flag << 28) | 857 (pixel_order << 23) | 858 (justified << 22) | 859 (format_no << 20) | 860 (color_format << 19) | 861 (nv21 << 17) | 862 (cbcr_interleave << 16) | 863 (fb_arr[0].stride); 864 vpu_write_reg(inst->dev, W5_COMMON_PIC_INFO, reg_val); 865 866 remain = count; 867 cnt_8_chunk = DIV_ROUND_UP(count, 8); 868 idx = 0; 869 for (j = 0; j < cnt_8_chunk; j++) { 870 reg_val = (j == cnt_8_chunk - 1) << 4 | ((j == 0) << 3); 871 vpu_write_reg(inst->dev, W5_SFB_OPTION, reg_val); 872 start_no = j * 8; 873 end_no = start_no + ((remain >= 8) ? 8 : remain) - 1; 874 875 vpu_write_reg(inst->dev, W5_SET_FB_NUM, (start_no << 8) | end_no); 876 877 for (i = 0; i < 8 && i < remain; i++) { 878 addr_y = fb_arr[i + start_no].buf_y; 879 addr_cb = fb_arr[i + start_no].buf_cb; 880 addr_cr = fb_arr[i + start_no].buf_cr; 881 vpu_write_reg(inst->dev, W5_ADDR_LUMA_BASE0 + (i << 4), addr_y); 882 vpu_write_reg(inst->dev, W5_ADDR_CB_BASE0 + (i << 4), addr_cb); 883 if (map_type >= COMPRESSED_FRAME_MAP) { 884 /* luma FBC offset table */ 885 vpu_write_reg(inst->dev, W5_ADDR_FBC_Y_OFFSET0 + (i << 4), 886 p_dec_info->vb_fbc_y_tbl[idx].daddr); 887 /* chroma FBC offset table */ 888 vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4), 889 p_dec_info->vb_fbc_c_tbl[idx].daddr); 890 vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2), 891 p_dec_info->vb_mv[idx].daddr); 892 } else { 893 vpu_write_reg(inst->dev, W5_ADDR_CR_BASE0 + (i << 4), addr_cr); 894 vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4), 0); 895 vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2), 0); 896 } 897 idx++; 898 } 899 remain -= i; 900 901 ret = send_firmware_command(inst, W5_SET_FB, false, NULL, NULL); 902 if (ret) 903 goto free_buffers; 904 } 905 906 reg_val = vpu_read_reg(inst->dev, W5_RET_SUCCESS); 907 if (!reg_val) { 908 ret = -EIO; 909 goto free_buffers; 910 } 911 912 return 0; 913 914free_buffers: 915 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_task); 916free_fbc_c_tbl_buffers: 917 for (i = 0; i < count; i++) 918 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_c_tbl[i]); 919free_fbc_y_tbl_buffers: 920 for (i = 0; i < count; i++) 921 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_y_tbl[i]); 922free_mv_buffers: 923 for (i = 0; i < count; i++) 924 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_mv[i]); 925 return ret; 926} 927 928static u32 wave5_vpu_dec_validate_sec_axi(struct vpu_instance *inst) 929{ 930 u32 bitdepth = inst->codec_info->dec_info.initial_info.luma_bitdepth; 931 struct dec_info *p_dec_info = &inst->codec_info->dec_info; 932 u32 bit_size = 0, ip_size = 0, lf_size = 0, ret = 0; 933 u32 sram_size = inst->dev->sram_size; 934 u32 width = inst->src_fmt.width; 935 936 if (!sram_size) 937 return 0; 938 939 /* 940 * TODO: calculate bit_size, ip_size, lf_size from width and bitdepth 941 * for Wave521. 942 */ 943 if (inst->dev->product_code == WAVE515_CODE) { 944 bit_size = DIV_ROUND_UP(width, 16) * 5 * 8; 945 ip_size = ALIGN(width, 16) * 2 * bitdepth / 8; 946 lf_size = ALIGN(width, 16) * 10 * bitdepth / 8; 947 } 948 949 if (p_dec_info->sec_axi_info.use_bit_enable && sram_size >= bit_size) { 950 ret |= BIT(0); 951 sram_size -= bit_size; 952 } 953 954 if (p_dec_info->sec_axi_info.use_ip_enable && sram_size >= ip_size) { 955 ret |= BIT(9); 956 sram_size -= ip_size; 957 } 958 959 if (p_dec_info->sec_axi_info.use_lf_row_enable && sram_size >= lf_size) 960 ret |= BIT(15); 961 962 return ret; 963} 964 965int wave5_vpu_decode(struct vpu_instance *inst, u32 *fail_res) 966{ 967 u32 reg_val; 968 struct dec_info *p_dec_info = &inst->codec_info->dec_info; 969 int ret; 970 971 vpu_write_reg(inst->dev, W5_BS_RD_PTR, p_dec_info->stream_rd_ptr); 972 vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); 973 974 vpu_write_reg(inst->dev, W5_BS_OPTION, get_bitstream_options(p_dec_info)); 975 976 /* secondary AXI */ 977 reg_val = wave5_vpu_dec_validate_sec_axi(inst); 978 vpu_write_reg(inst->dev, W5_USE_SEC_AXI, reg_val); 979 980 /* set attributes of user buffer */ 981 vpu_write_reg(inst->dev, W5_CMD_DEC_USER_MASK, p_dec_info->user_data_enable); 982 983 vpu_write_reg(inst->dev, W5_COMMAND_OPTION, DEC_PIC_NORMAL); 984 vpu_write_reg(inst->dev, W5_CMD_DEC_TEMPORAL_ID_PLUS1, 985 (p_dec_info->target_spatial_id << 9) | 986 (p_dec_info->temp_id_select_mode << 8) | p_dec_info->target_temp_id); 987 vpu_write_reg(inst->dev, W5_CMD_SEQ_CHANGE_ENABLE_FLAG, p_dec_info->seq_change_mask); 988 /* When reordering is disabled we force the latency of the framebuffers */ 989 vpu_write_reg(inst->dev, W5_CMD_DEC_FORCE_FB_LATENCY_PLUS1, !p_dec_info->reorder_enable); 990 991 ret = send_firmware_command(inst, W5_DEC_ENC_PIC, true, ®_val, fail_res); 992 if (ret == -ETIMEDOUT) 993 return ret; 994 995 p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; 996 p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); 997 998 dev_dbg(inst->dev->dev, "%s: dec pic sent (queue %u : %u)\n", __func__, 999 p_dec_info->instance_queue_count, p_dec_info->report_queue_count); 1000 1001 if (ret) 1002 return ret; 1003 1004 return 0; 1005} 1006 1007int wave5_vpu_dec_get_result(struct vpu_instance *inst, struct dec_output_info *result) 1008{ 1009 int ret; 1010 u32 index, nal_unit_type, reg_val, sub_layer_info; 1011 struct dec_info *p_dec_info = &inst->codec_info->dec_info; 1012 struct vpu_device *vpu_dev = inst->dev; 1013 1014 vpu_write_reg(inst->dev, W5_CMD_DEC_ADDR_REPORT_BASE, p_dec_info->user_data_buf_addr); 1015 vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_SIZE, p_dec_info->user_data_buf_size); 1016 vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_PARAM, REPORT_PARAM_ENDIANNESS_BIG_ENDIAN); 1017 1018 /* send QUERY cmd */ 1019 ret = wave5_send_query(vpu_dev, inst, GET_RESULT); 1020 if (ret) 1021 return ret; 1022 1023 reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); 1024 1025 p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; 1026 p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); 1027 1028 dev_dbg(inst->dev->dev, "%s: dec pic complete (queue %u : %u)\n", __func__, 1029 p_dec_info->instance_queue_count, p_dec_info->report_queue_count); 1030 1031 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_TYPE); 1032 1033 nal_unit_type = (reg_val >> 4) & 0x3f; 1034 1035 if (inst->std == W_HEVC_DEC) { 1036 if (reg_val & 0x04) 1037 result->pic_type = PIC_TYPE_B; 1038 else if (reg_val & 0x02) 1039 result->pic_type = PIC_TYPE_P; 1040 else if (reg_val & 0x01) 1041 result->pic_type = PIC_TYPE_I; 1042 else 1043 result->pic_type = PIC_TYPE_MAX; 1044 if ((nal_unit_type == 19 || nal_unit_type == 20) && result->pic_type == PIC_TYPE_I) 1045 /* IDR_W_RADL, IDR_N_LP */ 1046 result->pic_type = PIC_TYPE_IDR; 1047 } else if (inst->std == W_AVC_DEC) { 1048 if (reg_val & 0x04) 1049 result->pic_type = PIC_TYPE_B; 1050 else if (reg_val & 0x02) 1051 result->pic_type = PIC_TYPE_P; 1052 else if (reg_val & 0x01) 1053 result->pic_type = PIC_TYPE_I; 1054 else 1055 result->pic_type = PIC_TYPE_MAX; 1056 if (nal_unit_type == 5 && result->pic_type == PIC_TYPE_I) 1057 result->pic_type = PIC_TYPE_IDR; 1058 } 1059 index = vpu_read_reg(inst->dev, W5_RET_DEC_DISPLAY_INDEX); 1060 result->index_frame_display = index; 1061 index = vpu_read_reg(inst->dev, W5_RET_DEC_DECODED_INDEX); 1062 result->index_frame_decoded = index; 1063 result->index_frame_decoded_for_tiled = index; 1064 1065 sub_layer_info = vpu_read_reg(inst->dev, W5_RET_DEC_SUB_LAYER_INFO); 1066 result->temporal_id = sub_layer_info & 0x7; 1067 1068 if (inst->std == W_HEVC_DEC || inst->std == W_AVC_DEC) { 1069 result->decoded_poc = -1; 1070 if (result->index_frame_decoded >= 0 || 1071 result->index_frame_decoded == DECODED_IDX_FLAG_SKIP) 1072 result->decoded_poc = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_POC); 1073 } 1074 1075 result->sequence_changed = vpu_read_reg(inst->dev, W5_RET_DEC_NOTIFICATION); 1076 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_SIZE); 1077 result->dec_pic_width = reg_val >> 16; 1078 result->dec_pic_height = reg_val & 0xffff; 1079 1080 if (result->sequence_changed) { 1081 memcpy((void *)&p_dec_info->new_seq_info, (void *)&p_dec_info->initial_info, 1082 sizeof(struct dec_initial_info)); 1083 wave5_get_dec_seq_result(inst, &p_dec_info->new_seq_info); 1084 } 1085 1086 result->dec_host_cmd_tick = vpu_read_reg(inst->dev, W5_RET_DEC_HOST_CMD_TICK); 1087 result->dec_decode_end_tick = vpu_read_reg(inst->dev, W5_RET_DEC_DECODING_ENC_TICK); 1088 1089 if (!p_dec_info->first_cycle_check) { 1090 result->frame_cycle = 1091 (result->dec_decode_end_tick - result->dec_host_cmd_tick) * 1092 p_dec_info->cycle_per_tick; 1093 vpu_dev->last_performance_cycles = result->dec_decode_end_tick; 1094 p_dec_info->first_cycle_check = true; 1095 } else if (result->index_frame_decoded_for_tiled != -1) { 1096 result->frame_cycle = 1097 (result->dec_decode_end_tick - vpu_dev->last_performance_cycles) * 1098 p_dec_info->cycle_per_tick; 1099 vpu_dev->last_performance_cycles = result->dec_decode_end_tick; 1100 if (vpu_dev->last_performance_cycles < result->dec_host_cmd_tick) 1101 result->frame_cycle = 1102 (result->dec_decode_end_tick - result->dec_host_cmd_tick) * 1103 p_dec_info->cycle_per_tick; 1104 } 1105 1106 /* no remaining command. reset frame cycle. */ 1107 if (p_dec_info->instance_queue_count == 0 && p_dec_info->report_queue_count == 0) 1108 p_dec_info->first_cycle_check = false; 1109 1110 return 0; 1111} 1112 1113int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size) 1114{ 1115 struct vpu_buf *common_vb; 1116 dma_addr_t code_base, temp_base; 1117 dma_addr_t old_code_base, temp_size; 1118 u32 code_size, reason_code; 1119 u32 reg_val; 1120 struct vpu_device *vpu_dev = dev_get_drvdata(dev); 1121 1122 common_vb = &vpu_dev->common_mem; 1123 1124 code_base = common_vb->daddr; 1125 1126 if (vpu_dev->product_code == WAVE515_CODE) 1127 code_size = WAVE515_MAX_CODE_BUF_SIZE; 1128 else 1129 code_size = WAVE521_MAX_CODE_BUF_SIZE; 1130 1131 /* ALIGN TO 4KB */ 1132 code_size &= ~0xfff; 1133 if (code_size < size * 2) 1134 return -EINVAL; 1135 1136 temp_base = code_base + code_size; 1137 temp_size = WAVE5_TEMPBUF_SIZE; 1138 1139 old_code_base = vpu_read_reg(vpu_dev, W5_VPU_REMAP_PADDR); 1140 1141 if (old_code_base != code_base + W5_REMAP_INDEX1 * W5_REMAP_MAX_SIZE) { 1142 int ret; 1143 1144 ret = wave5_vdi_write_memory(vpu_dev, common_vb, 0, fw, size); 1145 if (ret < 0) { 1146 dev_err(vpu_dev->dev, 1147 "VPU init, Writing firmware to common buffer, fail: %d\n", ret); 1148 return ret; 1149 } 1150 1151 vpu_write_reg(vpu_dev, W5_PO_CONF, 0); 1152 1153 ret = wave5_vpu_reset(dev, SW_RESET_ON_BOOT); 1154 if (ret < 0) { 1155 dev_err(vpu_dev->dev, "VPU init, Resetting the VPU, fail: %d\n", ret); 1156 return ret; 1157 } 1158 1159 remap_page(vpu_dev, code_base, W5_REMAP_INDEX0); 1160 remap_page(vpu_dev, code_base, W5_REMAP_INDEX1); 1161 1162 vpu_write_reg(vpu_dev, W5_ADDR_CODE_BASE, code_base); 1163 vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size); 1164 vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID << 4) | 0); 1165 vpu_write_reg(vpu_dev, W5_ADDR_TEMP_BASE, temp_base); 1166 vpu_write_reg(vpu_dev, W5_TEMP_SIZE, temp_size); 1167 1168 /* These register must be reset explicitly */ 1169 vpu_write_reg(vpu_dev, W5_HW_OPTION, 0); 1170 1171 if (vpu_dev->product_code != WAVE515_CODE) { 1172 wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0); 1173 wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0); 1174 vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0); 1175 } 1176 1177 reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); 1178 if (FIELD_GET(W521_FEATURE_BACKBONE, reg_val)) { 1179 reg_val = ((WAVE5_PROC_AXI_ID << 28) | 1180 (WAVE5_PRP_AXI_ID << 24) | 1181 (WAVE5_FBD_Y_AXI_ID << 20) | 1182 (WAVE5_FBC_Y_AXI_ID << 16) | 1183 (WAVE5_FBD_C_AXI_ID << 12) | 1184 (WAVE5_FBC_C_AXI_ID << 8) | 1185 (WAVE5_PRI_AXI_ID << 4) | 1186 WAVE5_SEC_AXI_ID); 1187 wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val); 1188 } 1189 1190 if (vpu_dev->product_code == WAVE515_CODE) { 1191 dma_addr_t task_buf_base; 1192 u32 i; 1193 1194 vpu_write_reg(vpu_dev, W5_CMD_INIT_NUM_TASK_BUF, 1195 WAVE515_COMMAND_QUEUE_DEPTH); 1196 vpu_write_reg(vpu_dev, W5_CMD_INIT_TASK_BUF_SIZE, 1197 WAVE515_ONE_TASKBUF_SIZE); 1198 1199 for (i = 0; i < WAVE515_COMMAND_QUEUE_DEPTH; i++) { 1200 task_buf_base = temp_base + temp_size + 1201 (i * WAVE515_ONE_TASKBUF_SIZE); 1202 vpu_write_reg(vpu_dev, 1203 W5_CMD_INIT_ADDR_TASK_BUF0 + (i * 4), 1204 task_buf_base); 1205 } 1206 1207 vpu_write_reg(vpu_dev, W515_CMD_ADDR_SEC_AXI, 1208 vpu_dev->sram_buf.daddr); 1209 vpu_write_reg(vpu_dev, W515_CMD_SEC_AXI_SIZE, 1210 vpu_dev->sram_buf.size); 1211 } 1212 1213 vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); 1214 vpu_write_reg(vpu_dev, W5_COMMAND, W5_INIT_VPU); 1215 vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1); 1216 1217 ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); 1218 if (ret) { 1219 dev_err(vpu_dev->dev, "VPU reinit(W5_VPU_REMAP_CORE_START) timeout\n"); 1220 return ret; 1221 } 1222 1223 ret = wave5_vpu_firmware_command_queue_error_check(vpu_dev, &reason_code); 1224 if (ret) 1225 return ret; 1226 } 1227 1228 return setup_wave5_properties(dev); 1229} 1230 1231int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uint16_t *code, 1232 size_t size) 1233{ 1234 u32 reg_val; 1235 struct vpu_buf *common_vb; 1236 dma_addr_t code_base, temp_base; 1237 u32 code_size, temp_size, reason_code; 1238 struct vpu_device *vpu_dev = dev_get_drvdata(dev); 1239 int ret; 1240 1241 if (i_sleep_wake) { 1242 ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); 1243 if (ret) 1244 return ret; 1245 1246 /* 1247 * Declare who has ownership for the host interface access 1248 * 1 = VPU 1249 * 0 = Host processor 1250 */ 1251 vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); 1252 vpu_write_reg(vpu_dev, W5_COMMAND, W5_SLEEP_VPU); 1253 /* Send an interrupt named HOST to the VPU */ 1254 vpu_write_reg(vpu_dev, W5_VPU_HOST_INT_REQ, 1); 1255 1256 ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); 1257 if (ret) 1258 return ret; 1259 1260 ret = wave5_vpu_firmware_command_queue_error_check(vpu_dev, &reason_code); 1261 if (ret) 1262 return ret; 1263 } else { /* restore */ 1264 common_vb = &vpu_dev->common_mem; 1265 1266 code_base = common_vb->daddr; 1267 1268 if (vpu_dev->product_code == WAVE515_CODE) 1269 code_size = WAVE515_MAX_CODE_BUF_SIZE; 1270 else 1271 code_size = WAVE521_MAX_CODE_BUF_SIZE; 1272 1273 /* ALIGN TO 4KB */ 1274 code_size &= ~0xfff; 1275 if (code_size < size * 2) { 1276 dev_err(dev, "size too small\n"); 1277 return -EINVAL; 1278 } 1279 1280 temp_base = code_base + code_size; 1281 temp_size = WAVE5_TEMPBUF_SIZE; 1282 1283 /* Power on without DEBUG mode */ 1284 vpu_write_reg(vpu_dev, W5_PO_CONF, 0); 1285 1286 remap_page(vpu_dev, code_base, W5_REMAP_INDEX0); 1287 remap_page(vpu_dev, code_base, W5_REMAP_INDEX1); 1288 1289 vpu_write_reg(vpu_dev, W5_ADDR_CODE_BASE, code_base); 1290 vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size); 1291 vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID << 4) | 0); 1292 1293 /* These register must be reset explicitly */ 1294 vpu_write_reg(vpu_dev, W5_HW_OPTION, 0); 1295 1296 if (vpu_dev->product_code != WAVE515_CODE) { 1297 wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0); 1298 wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0); 1299 vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0); 1300 } 1301 1302 setup_wave5_interrupts(vpu_dev); 1303 1304 reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); 1305 if (FIELD_GET(W521_FEATURE_BACKBONE, reg_val)) { 1306 reg_val = ((WAVE5_PROC_AXI_ID << 28) | 1307 (WAVE5_PRP_AXI_ID << 24) | 1308 (WAVE5_FBD_Y_AXI_ID << 20) | 1309 (WAVE5_FBC_Y_AXI_ID << 16) | 1310 (WAVE5_FBD_C_AXI_ID << 12) | 1311 (WAVE5_FBC_C_AXI_ID << 8) | 1312 (WAVE5_PRI_AXI_ID << 4) | 1313 WAVE5_SEC_AXI_ID); 1314 wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val); 1315 } 1316 1317 if (vpu_dev->product_code == WAVE515_CODE) { 1318 dma_addr_t task_buf_base; 1319 u32 i; 1320 1321 vpu_write_reg(vpu_dev, W5_CMD_INIT_NUM_TASK_BUF, 1322 WAVE515_COMMAND_QUEUE_DEPTH); 1323 vpu_write_reg(vpu_dev, W5_CMD_INIT_TASK_BUF_SIZE, 1324 WAVE515_ONE_TASKBUF_SIZE); 1325 1326 for (i = 0; i < WAVE515_COMMAND_QUEUE_DEPTH; i++) { 1327 task_buf_base = temp_base + temp_size + 1328 (i * WAVE515_ONE_TASKBUF_SIZE); 1329 vpu_write_reg(vpu_dev, 1330 W5_CMD_INIT_ADDR_TASK_BUF0 + (i * 4), 1331 task_buf_base); 1332 } 1333 1334 vpu_write_reg(vpu_dev, W515_CMD_ADDR_SEC_AXI, 1335 vpu_dev->sram_buf.daddr); 1336 vpu_write_reg(vpu_dev, W515_CMD_SEC_AXI_SIZE, 1337 vpu_dev->sram_buf.size); 1338 } 1339 1340 vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); 1341 vpu_write_reg(vpu_dev, W5_COMMAND, W5_WAKEUP_VPU); 1342 /* Start VPU after settings */ 1343 vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1); 1344 1345 ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); 1346 if (ret) { 1347 dev_err(vpu_dev->dev, "VPU wakeup(W5_VPU_REMAP_CORE_START) timeout\n"); 1348 return ret; 1349 } 1350 1351 return wave5_vpu_firmware_command_queue_error_check(vpu_dev, &reason_code); 1352 } 1353 1354 return 0; 1355} 1356 1357int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode) 1358{ 1359 u32 val = 0; 1360 int ret = 0; 1361 struct vpu_device *vpu_dev = dev_get_drvdata(dev); 1362 struct vpu_attr *p_attr = &vpu_dev->attr; 1363 /* VPU doesn't send response. force to set BUSY flag to 0. */ 1364 vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 0); 1365 1366 if (reset_mode == SW_RESET_SAFETY) { 1367 ret = wave5_vpu_sleep_wake(dev, true, NULL, 0); 1368 if (ret) 1369 return ret; 1370 } 1371 1372 val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); 1373 if ((val >> 16) & 0x1) 1374 p_attr->support_backbone = true; 1375 if ((val >> 22) & 0x1) 1376 p_attr->support_vcore_backbone = true; 1377 if ((val >> 28) & 0x1) 1378 p_attr->support_vcpu_backbone = true; 1379 1380 /* waiting for completion of bus transaction */ 1381 if (p_attr->support_backbone) { 1382 dev_dbg(dev, "%s: backbone supported\n", __func__); 1383 1384 if (p_attr->support_vcore_backbone) { 1385 if (p_attr->support_vcpu_backbone) { 1386 /* step1 : disable request */ 1387 wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCPU, 0xFF); 1388 1389 /* step2 : waiting for completion of bus transaction */ 1390 ret = wave5_wait_vcpu_bus_busy(vpu_dev, 1391 W5_BACKBONE_BUS_STATUS_VCPU); 1392 if (ret) { 1393 wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCPU, 0x00); 1394 return ret; 1395 } 1396 } 1397 /* step1 : disable request */ 1398 wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x7); 1399 1400 /* step2 : waiting for completion of bus transaction */ 1401 if (wave5_wait_bus_busy(vpu_dev, W5_BACKBONE_BUS_STATUS_VCORE0)) { 1402 wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00); 1403 return -EBUSY; 1404 } 1405 } else { 1406 /* step1 : disable request */ 1407 wave5_fio_writel(vpu_dev, W5_COMBINED_BACKBONE_BUS_CTRL, 0x7); 1408 1409 /* step2 : waiting for completion of bus transaction */ 1410 if (wave5_wait_bus_busy(vpu_dev, W5_COMBINED_BACKBONE_BUS_STATUS)) { 1411 wave5_fio_writel(vpu_dev, W5_COMBINED_BACKBONE_BUS_CTRL, 0x00); 1412 return -EBUSY; 1413 } 1414 } 1415 } else { 1416 dev_dbg(dev, "%s: backbone NOT supported\n", __func__); 1417 /* step1 : disable request */ 1418 wave5_fio_writel(vpu_dev, W5_GDI_BUS_CTRL, 0x100); 1419 1420 /* step2 : waiting for completion of bus transaction */ 1421 ret = wave5_wait_bus_busy(vpu_dev, W5_GDI_BUS_STATUS); 1422 if (ret) { 1423 wave5_fio_writel(vpu_dev, W5_GDI_BUS_CTRL, 0x00); 1424 return ret; 1425 } 1426 } 1427 1428 switch (reset_mode) { 1429 case SW_RESET_ON_BOOT: 1430 case SW_RESET_FORCE: 1431 case SW_RESET_SAFETY: 1432 val = W5_RST_BLOCK_ALL; 1433 break; 1434 default: 1435 return -EINVAL; 1436 } 1437 1438 if (val) { 1439 vpu_write_reg(vpu_dev, W5_VPU_RESET_REQ, val); 1440 1441 ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_RESET_STATUS); 1442 if (ret) { 1443 vpu_write_reg(vpu_dev, W5_VPU_RESET_REQ, 0); 1444 return ret; 1445 } 1446 vpu_write_reg(vpu_dev, W5_VPU_RESET_REQ, 0); 1447 } 1448 /* step3 : must clear GDI_BUS_CTRL after done SW_RESET */ 1449 if (p_attr->support_backbone) { 1450 if (p_attr->support_vcore_backbone) { 1451 if (p_attr->support_vcpu_backbone) 1452 wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCPU, 0x00); 1453 wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00); 1454 } else { 1455 wave5_fio_writel(vpu_dev, W5_COMBINED_BACKBONE_BUS_CTRL, 0x00); 1456 } 1457 } else { 1458 wave5_fio_writel(vpu_dev, W5_GDI_BUS_CTRL, 0x00); 1459 } 1460 if (reset_mode == SW_RESET_SAFETY || reset_mode == SW_RESET_FORCE) 1461 ret = wave5_vpu_sleep_wake(dev, false, NULL, 0); 1462 1463 return ret; 1464} 1465 1466int wave5_vpu_dec_finish_seq(struct vpu_instance *inst, u32 *fail_res) 1467{ 1468 return send_firmware_command(inst, W5_DESTROY_INSTANCE, true, NULL, fail_res); 1469} 1470 1471int wave5_vpu_dec_set_bitstream_flag(struct vpu_instance *inst, bool eos) 1472{ 1473 struct dec_info *p_dec_info = &inst->codec_info->dec_info; 1474 1475 p_dec_info->stream_endflag = eos ? 1 : 0; 1476 vpu_write_reg(inst->dev, W5_BS_OPTION, get_bitstream_options(p_dec_info)); 1477 vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); 1478 1479 return send_firmware_command(inst, W5_UPDATE_BS, true, NULL, NULL); 1480} 1481 1482int wave5_dec_clr_disp_flag(struct vpu_instance *inst, unsigned int index) 1483{ 1484 struct dec_info *p_dec_info = &inst->codec_info->dec_info; 1485 int ret; 1486 1487 vpu_write_reg(inst->dev, W5_CMD_DEC_CLR_DISP_IDC, BIT(index)); 1488 vpu_write_reg(inst->dev, W5_CMD_DEC_SET_DISP_IDC, 0); 1489 1490 ret = wave5_send_query(inst->dev, inst, UPDATE_DISP_FLAG); 1491 if (ret) 1492 return ret; 1493 1494 p_dec_info->frame_display_flag = vpu_read_reg(inst->dev, W5_RET_DEC_DISP_IDC); 1495 1496 return 0; 1497} 1498 1499int wave5_dec_set_disp_flag(struct vpu_instance *inst, unsigned int index) 1500{ 1501 int ret; 1502 1503 vpu_write_reg(inst->dev, W5_CMD_DEC_CLR_DISP_IDC, 0); 1504 vpu_write_reg(inst->dev, W5_CMD_DEC_SET_DISP_IDC, BIT(index)); 1505 1506 ret = wave5_send_query(inst->dev, inst, UPDATE_DISP_FLAG); 1507 if (ret) 1508 return ret; 1509 1510 return 0; 1511} 1512 1513int wave5_vpu_clear_interrupt(struct vpu_instance *inst, u32 flags) 1514{ 1515 u32 interrupt_reason; 1516 1517 interrupt_reason = vpu_read_reg(inst->dev, W5_VPU_VINT_REASON_USR); 1518 interrupt_reason &= ~flags; 1519 vpu_write_reg(inst->dev, W5_VPU_VINT_REASON_USR, interrupt_reason); 1520 1521 return 0; 1522} 1523 1524dma_addr_t wave5_dec_get_rd_ptr(struct vpu_instance *inst) 1525{ 1526 int ret; 1527 1528 ret = wave5_send_query(inst->dev, inst, GET_BS_RD_PTR); 1529 if (ret) 1530 return inst->codec_info->dec_info.stream_rd_ptr; 1531 1532 return vpu_read_reg(inst->dev, W5_RET_QUERY_DEC_BS_RD_PTR); 1533} 1534 1535int wave5_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr) 1536{ 1537 int ret; 1538 1539 vpu_write_reg(inst->dev, W5_RET_QUERY_DEC_SET_BS_RD_PTR, addr); 1540 1541 ret = wave5_send_query(inst->dev, inst, SET_BS_RD_PTR); 1542 1543 return ret; 1544} 1545 1546/************************************************************************/ 1547/* ENCODER functions */ 1548/************************************************************************/ 1549 1550int wave5_vpu_build_up_enc_param(struct device *dev, struct vpu_instance *inst, 1551 struct enc_open_param *open_param) 1552{ 1553 int ret; 1554 struct enc_info *p_enc_info = &inst->codec_info->enc_info; 1555 u32 reg_val; 1556 struct vpu_device *vpu_dev = dev_get_drvdata(dev); 1557 dma_addr_t buffer_addr; 1558 size_t buffer_size; 1559 1560 p_enc_info->cycle_per_tick = 256; 1561 if (vpu_dev->sram_buf.size) { 1562 p_enc_info->sec_axi_info.use_enc_rdo_enable = 1; 1563 p_enc_info->sec_axi_info.use_enc_lf_enable = 1; 1564 } 1565 1566 p_enc_info->vb_work.size = WAVE521ENC_WORKBUF_SIZE; 1567 ret = wave5_vdi_allocate_dma_memory(vpu_dev, &p_enc_info->vb_work); 1568 if (ret) { 1569 memset(&p_enc_info->vb_work, 0, sizeof(p_enc_info->vb_work)); 1570 return ret; 1571 } 1572 1573 wave5_vdi_clear_memory(vpu_dev, &p_enc_info->vb_work); 1574 1575 vpu_write_reg(inst->dev, W5_ADDR_WORK_BASE, p_enc_info->vb_work.daddr); 1576 vpu_write_reg(inst->dev, W5_WORK_SIZE, p_enc_info->vb_work.size); 1577 1578 vpu_write_reg(inst->dev, W5_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr); 1579 vpu_write_reg(inst->dev, W5_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size); 1580 1581 reg_val = (open_param->line_buf_int_en << 6) | BITSTREAM_ENDIANNESS_BIG_ENDIAN; 1582 vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, reg_val); 1583 vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, 0); 1584 vpu_write_reg(inst->dev, W5_CMD_NUM_CQ_DEPTH_M1, WAVE521_COMMAND_QUEUE_DEPTH - 1); 1585 1586 /* This register must be reset explicitly */ 1587 vpu_write_reg(inst->dev, W5_CMD_ENC_SRC_OPTIONS, 0); 1588 vpu_write_reg(inst->dev, W5_CMD_ENC_VCORE_INFO, 1); 1589 1590 ret = send_firmware_command(inst, W5_CREATE_INSTANCE, true, NULL, NULL); 1591 if (ret) 1592 goto free_vb_work; 1593 1594 buffer_addr = open_param->bitstream_buffer; 1595 buffer_size = open_param->bitstream_buffer_size; 1596 p_enc_info->stream_rd_ptr = buffer_addr; 1597 p_enc_info->stream_wr_ptr = buffer_addr; 1598 p_enc_info->line_buf_int_en = open_param->line_buf_int_en; 1599 p_enc_info->stream_buf_start_addr = buffer_addr; 1600 p_enc_info->stream_buf_size = buffer_size; 1601 p_enc_info->stream_buf_end_addr = buffer_addr + buffer_size; 1602 p_enc_info->stride = 0; 1603 p_enc_info->initial_info_obtained = false; 1604 p_enc_info->product_code = vpu_read_reg(inst->dev, W5_PRODUCT_NUMBER); 1605 1606 return 0; 1607free_vb_work: 1608 if (wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_work)) 1609 memset(&p_enc_info->vb_work, 0, sizeof(p_enc_info->vb_work)); 1610 return ret; 1611} 1612 1613static void wave5_set_enc_crop_info(u32 codec, struct enc_wave_param *param, int rot_mode, 1614 int src_width, int src_height) 1615{ 1616 int aligned_width = (codec == W_HEVC_ENC) ? ALIGN(src_width, 32) : ALIGN(src_width, 16); 1617 int aligned_height = (codec == W_HEVC_ENC) ? ALIGN(src_height, 32) : ALIGN(src_height, 16); 1618 int pad_right, pad_bot; 1619 int crop_right, crop_left, crop_top, crop_bot; 1620 int prp_mode = rot_mode >> 1; /* remove prp_enable bit */ 1621 1622 if (codec == W_HEVC_ENC && 1623 (!rot_mode || prp_mode == 14)) /* prp_mode 14 : hor_mir && ver_mir && rot_180 */ 1624 return; 1625 1626 pad_right = aligned_width - src_width; 1627 pad_bot = aligned_height - src_height; 1628 1629 if (param->conf_win_right > 0) 1630 crop_right = param->conf_win_right + pad_right; 1631 else 1632 crop_right = pad_right; 1633 1634 if (param->conf_win_bot > 0) 1635 crop_bot = param->conf_win_bot + pad_bot; 1636 else 1637 crop_bot = pad_bot; 1638 1639 crop_top = param->conf_win_top; 1640 crop_left = param->conf_win_left; 1641 1642 param->conf_win_top = crop_top; 1643 param->conf_win_left = crop_left; 1644 param->conf_win_bot = crop_bot; 1645 param->conf_win_right = crop_right; 1646 1647 switch (prp_mode) { 1648 case 0: 1649 return; 1650 case 1: 1651 case 15: 1652 param->conf_win_top = crop_right; 1653 param->conf_win_left = crop_top; 1654 param->conf_win_bot = crop_left; 1655 param->conf_win_right = crop_bot; 1656 break; 1657 case 2: 1658 case 12: 1659 param->conf_win_top = crop_bot; 1660 param->conf_win_left = crop_right; 1661 param->conf_win_bot = crop_top; 1662 param->conf_win_right = crop_left; 1663 break; 1664 case 3: 1665 case 13: 1666 param->conf_win_top = crop_left; 1667 param->conf_win_left = crop_bot; 1668 param->conf_win_bot = crop_right; 1669 param->conf_win_right = crop_top; 1670 break; 1671 case 4: 1672 case 10: 1673 param->conf_win_top = crop_bot; 1674 param->conf_win_bot = crop_top; 1675 break; 1676 case 8: 1677 case 6: 1678 param->conf_win_left = crop_right; 1679 param->conf_win_right = crop_left; 1680 break; 1681 case 5: 1682 case 11: 1683 param->conf_win_top = crop_left; 1684 param->conf_win_left = crop_top; 1685 param->conf_win_bot = crop_right; 1686 param->conf_win_right = crop_bot; 1687 break; 1688 case 7: 1689 case 9: 1690 param->conf_win_top = crop_right; 1691 param->conf_win_left = crop_bot; 1692 param->conf_win_bot = crop_left; 1693 param->conf_win_right = crop_top; 1694 break; 1695 default: 1696 WARN(1, "Invalid prp_mode: %d, must be in range of 1 - 15\n", prp_mode); 1697 } 1698} 1699 1700int wave5_vpu_enc_init_seq(struct vpu_instance *inst) 1701{ 1702 u32 reg_val = 0, rot_mir_mode, fixed_cu_size_mode = 0x7; 1703 struct enc_info *p_enc_info = &inst->codec_info->enc_info; 1704 struct enc_open_param *p_open_param = &p_enc_info->open_param; 1705 struct enc_wave_param *p_param = &p_open_param->wave_param; 1706 1707 /* 1708 * OPT_COMMON: 1709 * the last SET_PARAM command should be called with OPT_COMMON 1710 */ 1711 rot_mir_mode = 0; 1712 if (p_enc_info->rotation_enable) { 1713 switch (p_enc_info->rotation_angle) { 1714 case 0: 1715 rot_mir_mode |= NONE_ROTATE; 1716 break; 1717 case 90: 1718 rot_mir_mode |= ROT_CLOCKWISE_90; 1719 break; 1720 case 180: 1721 rot_mir_mode |= ROT_CLOCKWISE_180; 1722 break; 1723 case 270: 1724 rot_mir_mode |= ROT_CLOCKWISE_270; 1725 break; 1726 } 1727 } 1728 1729 if (p_enc_info->mirror_enable) { 1730 switch (p_enc_info->mirror_direction) { 1731 case MIRDIR_NONE: 1732 rot_mir_mode |= NONE_ROTATE; 1733 break; 1734 case MIRDIR_VER: 1735 rot_mir_mode |= MIR_VER_FLIP; 1736 break; 1737 case MIRDIR_HOR: 1738 rot_mir_mode |= MIR_HOR_FLIP; 1739 break; 1740 case MIRDIR_HOR_VER: 1741 rot_mir_mode |= MIR_HOR_VER_FLIP; 1742 break; 1743 } 1744 } 1745 1746 wave5_set_enc_crop_info(inst->std, p_param, rot_mir_mode, p_open_param->pic_width, 1747 p_open_param->pic_height); 1748 1749 /* SET_PARAM + COMMON */ 1750 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SET_PARAM_OPTION, OPT_COMMON); 1751 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SRC_SIZE, p_open_param->pic_height << 16 1752 | p_open_param->pic_width); 1753 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MAP_ENDIAN, VDI_LITTLE_ENDIAN); 1754 1755 reg_val = p_param->profile | 1756 (p_param->level << 3) | 1757 (p_param->internal_bit_depth << 14); 1758 if (inst->std == W_HEVC_ENC) 1759 reg_val |= (p_param->tier << 12) | 1760 (p_param->tmvp_enable << 23) | 1761 (p_param->sao_enable << 24) | 1762 (p_param->skip_intra_trans << 25) | 1763 (p_param->strong_intra_smooth_enable << 27) | 1764 (p_param->en_still_picture << 30); 1765 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SPS_PARAM, reg_val); 1766 1767 reg_val = (p_param->lossless_enable) | 1768 (p_param->const_intra_pred_flag << 1) | 1769 (p_param->lf_cross_slice_boundary_enable << 2) | 1770 (p_param->wpp_enable << 4) | 1771 (p_param->disable_deblk << 5) | 1772 ((p_param->beta_offset_div2 & 0xF) << 6) | 1773 ((p_param->tc_offset_div2 & 0xF) << 10) | 1774 ((p_param->chroma_cb_qp_offset & 0x1F) << 14) | 1775 ((p_param->chroma_cr_qp_offset & 0x1F) << 19) | 1776 (p_param->transform8x8_enable << 29) | 1777 (p_param->entropy_coding_mode << 30); 1778 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_PPS_PARAM, reg_val); 1779 1780 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_GOP_PARAM, p_param->gop_preset_idx); 1781 1782 if (inst->std == W_AVC_ENC) 1783 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, p_param->intra_qp | 1784 ((p_param->intra_period & ENC_AVC_INTRA_IDR_PARAM_MASK) 1785 << ENC_AVC_INTRA_PERIOD_SHIFT) | 1786 ((p_param->avc_idr_period & ENC_AVC_INTRA_IDR_PARAM_MASK) 1787 << ENC_AVC_IDR_PERIOD_SHIFT) | 1788 (p_param->forced_idr_header_enable 1789 << ENC_AVC_FORCED_IDR_HEADER_SHIFT)); 1790 else if (inst->std == W_HEVC_ENC) 1791 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, 1792 p_param->decoding_refresh_type | 1793 (p_param->intra_qp << ENC_HEVC_INTRA_QP_SHIFT) | 1794 (p_param->forced_idr_header_enable 1795 << ENC_HEVC_FORCED_IDR_HEADER_SHIFT) | 1796 (p_param->intra_period << ENC_HEVC_INTRA_PERIOD_SHIFT)); 1797 1798 reg_val = (p_param->rdo_skip << 2) | 1799 (p_param->lambda_scaling_enable << 3) | 1800 (fixed_cu_size_mode << 5) | 1801 (p_param->intra_nx_n_enable << 8) | 1802 (p_param->max_num_merge << 18); 1803 1804 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RDO_PARAM, reg_val); 1805 1806 if (inst->std == W_AVC_ENC) 1807 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_REFRESH, 1808 p_param->intra_mb_refresh_arg << 16 | p_param->intra_mb_refresh_mode); 1809 else if (inst->std == W_HEVC_ENC) 1810 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_REFRESH, 1811 p_param->intra_refresh_arg << 16 | p_param->intra_refresh_mode); 1812 1813 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_FRAME_RATE, p_open_param->frame_rate_info); 1814 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_TARGET_RATE, p_open_param->bit_rate); 1815 1816 reg_val = p_open_param->rc_enable | 1817 (p_param->hvs_qp_enable << 2) | 1818 (p_param->hvs_qp_scale << 4) | 1819 ((p_param->initial_rc_qp & 0x3F) << 14) | 1820 (p_open_param->vbv_buffer_size << 20); 1821 if (inst->std == W_AVC_ENC) 1822 reg_val |= (p_param->mb_level_rc_enable << 1); 1823 else if (inst->std == W_HEVC_ENC) 1824 reg_val |= (p_param->cu_level_rc_enable << 1); 1825 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_PARAM, reg_val); 1826 1827 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_WEIGHT_PARAM, 1828 p_param->rc_weight_buf << 8 | p_param->rc_weight_param); 1829 1830 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_MIN_MAX_QP, p_param->min_qp_i | 1831 (p_param->max_qp_i << 6) | (p_param->hvs_max_delta_qp << 12)); 1832 1833 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_INTER_MIN_MAX_QP, p_param->min_qp_p | 1834 (p_param->max_qp_p << 6) | (p_param->min_qp_b << 12) | 1835 (p_param->max_qp_b << 18)); 1836 1837 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_0_3, 0); 1838 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7, 0); 1839 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_ROT_PARAM, rot_mir_mode); 1840 1841 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_BG_PARAM, 0); 1842 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR, 0); 1843 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CONF_WIN_TOP_BOT, 1844 p_param->conf_win_bot << 16 | p_param->conf_win_top); 1845 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CONF_WIN_LEFT_RIGHT, 1846 p_param->conf_win_right << 16 | p_param->conf_win_left); 1847 1848 if (inst->std == W_AVC_ENC) 1849 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE, 1850 p_param->avc_slice_arg << 16 | p_param->avc_slice_mode); 1851 else if (inst->std == W_HEVC_ENC) 1852 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE, 1853 p_param->independ_slice_mode_arg << 16 | 1854 p_param->independ_slice_mode); 1855 1856 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_USER_SCALING_LIST_ADDR, 0); 1857 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NUM_UNITS_IN_TICK, 0); 1858 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_TIME_SCALE, 0); 1859 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NUM_TICKS_POC_DIFF_ONE, 0); 1860 1861 if (inst->std == W_HEVC_ENC) { 1862 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU04, 0); 1863 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU08, 0); 1864 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU16, 0); 1865 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU32, 0); 1866 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU08, 0); 1867 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU16, 0); 1868 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU32, 0); 1869 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_DEPENDENT_SLICE, 1870 p_param->depend_slice_mode_arg << 16 | p_param->depend_slice_mode); 1871 1872 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NR_PARAM, 0); 1873 1874 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NR_WEIGHT, 1875 p_param->nr_intra_weight_y | 1876 (p_param->nr_intra_weight_cb << 5) | 1877 (p_param->nr_intra_weight_cr << 10) | 1878 (p_param->nr_inter_weight_y << 15) | 1879 (p_param->nr_inter_weight_cb << 20) | 1880 (p_param->nr_inter_weight_cr << 25)); 1881 } 1882 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_VUI_HRD_PARAM, 0); 1883 1884 return send_firmware_command(inst, W5_ENC_SET_PARAM, true, NULL, NULL); 1885} 1886 1887int wave5_vpu_enc_get_seq_info(struct vpu_instance *inst, struct enc_initial_info *info) 1888{ 1889 int ret; 1890 u32 reg_val; 1891 struct enc_info *p_enc_info = &inst->codec_info->enc_info; 1892 1893 /* send QUERY cmd */ 1894 ret = wave5_send_query(inst->dev, inst, GET_RESULT); 1895 if (ret) 1896 return ret; 1897 1898 dev_dbg(inst->dev->dev, "%s: init seq\n", __func__); 1899 1900 reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); 1901 1902 p_enc_info->instance_queue_count = (reg_val >> 16) & 0xff; 1903 p_enc_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); 1904 1905 if (vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_SUCCESS) != 1) { 1906 info->seq_init_err_reason = vpu_read_reg(inst->dev, W5_RET_ENC_ERR_INFO); 1907 ret = -EIO; 1908 } else { 1909 info->warn_info = vpu_read_reg(inst->dev, W5_RET_ENC_WARN_INFO); 1910 } 1911 1912 info->min_frame_buffer_count = vpu_read_reg(inst->dev, W5_RET_ENC_NUM_REQUIRED_FB); 1913 info->min_src_frame_count = vpu_read_reg(inst->dev, W5_RET_ENC_MIN_SRC_BUF_NUM); 1914 info->vlc_buf_size = vpu_read_reg(inst->dev, W5_RET_VLC_BUF_SIZE); 1915 info->param_buf_size = vpu_read_reg(inst->dev, W5_RET_PARAM_BUF_SIZE); 1916 p_enc_info->vlc_buf_size = info->vlc_buf_size; 1917 p_enc_info->param_buf_size = info->param_buf_size; 1918 1919 return ret; 1920} 1921 1922static u32 calculate_luma_stride(u32 width, u32 bit_depth) 1923{ 1924 return ALIGN(ALIGN(width, 16) * ((bit_depth > 8) ? 5 : 4), 32); 1925} 1926 1927static u32 calculate_chroma_stride(u32 width, u32 bit_depth) 1928{ 1929 return ALIGN(ALIGN(width / 2, 16) * ((bit_depth > 8) ? 5 : 4), 32); 1930} 1931 1932int wave5_vpu_enc_register_framebuffer(struct device *dev, struct vpu_instance *inst, 1933 struct frame_buffer *fb_arr, enum tiled_map_type map_type, 1934 unsigned int count) 1935{ 1936 struct vpu_device *vpu_dev = dev_get_drvdata(dev); 1937 int ret = 0; 1938 u32 stride; 1939 u32 start_no, end_no; 1940 size_t remain, idx, j, i, cnt_8_chunk; 1941 u32 reg_val = 0, pic_size = 0, mv_col_size, fbc_y_tbl_size, fbc_c_tbl_size; 1942 u32 sub_sampled_size = 0; 1943 u32 luma_stride, chroma_stride; 1944 u32 buf_height = 0, buf_width = 0; 1945 u32 bit_depth; 1946 bool avc_encoding = (inst->std == W_AVC_ENC); 1947 struct vpu_buf vb_mv = {0}; 1948 struct vpu_buf vb_fbc_y_tbl = {0}; 1949 struct vpu_buf vb_fbc_c_tbl = {0}; 1950 struct vpu_buf vb_sub_sam_buf = {0}; 1951 struct vpu_buf vb_task = {0}; 1952 struct enc_open_param *p_open_param; 1953 struct enc_info *p_enc_info = &inst->codec_info->enc_info; 1954 1955 p_open_param = &p_enc_info->open_param; 1956 mv_col_size = 0; 1957 fbc_y_tbl_size = 0; 1958 fbc_c_tbl_size = 0; 1959 stride = p_enc_info->stride; 1960 bit_depth = p_open_param->wave_param.internal_bit_depth; 1961 1962 if (avc_encoding) { 1963 buf_width = ALIGN(p_open_param->pic_width, 16); 1964 buf_height = ALIGN(p_open_param->pic_height, 16); 1965 1966 if ((p_enc_info->rotation_angle || p_enc_info->mirror_direction) && 1967 !(p_enc_info->rotation_angle == 180 && 1968 p_enc_info->mirror_direction == MIRDIR_HOR_VER)) { 1969 buf_width = ALIGN(p_open_param->pic_width, 16); 1970 buf_height = ALIGN(p_open_param->pic_height, 16); 1971 } 1972 1973 if (p_enc_info->rotation_angle == 90 || p_enc_info->rotation_angle == 270) { 1974 buf_width = ALIGN(p_open_param->pic_height, 16); 1975 buf_height = ALIGN(p_open_param->pic_width, 16); 1976 } 1977 } else { 1978 buf_width = ALIGN(p_open_param->pic_width, 8); 1979 buf_height = ALIGN(p_open_param->pic_height, 8); 1980 1981 if ((p_enc_info->rotation_angle || p_enc_info->mirror_direction) && 1982 !(p_enc_info->rotation_angle == 180 && 1983 p_enc_info->mirror_direction == MIRDIR_HOR_VER)) { 1984 buf_width = ALIGN(p_open_param->pic_width, 32); 1985 buf_height = ALIGN(p_open_param->pic_height, 32); 1986 } 1987 1988 if (p_enc_info->rotation_angle == 90 || p_enc_info->rotation_angle == 270) { 1989 buf_width = ALIGN(p_open_param->pic_height, 32); 1990 buf_height = ALIGN(p_open_param->pic_width, 32); 1991 } 1992 } 1993 1994 pic_size = (buf_width << 16) | buf_height; 1995 1996 if (avc_encoding) { 1997 mv_col_size = WAVE5_ENC_AVC_BUF_SIZE(buf_width, buf_height); 1998 vb_mv.daddr = 0; 1999 vb_mv.size = ALIGN(mv_col_size * count, BUFFER_MARGIN) + BUFFER_MARGIN; 2000 } else { 2001 mv_col_size = WAVE5_ENC_HEVC_BUF_SIZE(buf_width, buf_height); 2002 mv_col_size = ALIGN(mv_col_size, 16); 2003 vb_mv.daddr = 0; 2004 vb_mv.size = ALIGN(mv_col_size * count, BUFFER_MARGIN) + BUFFER_MARGIN; 2005 } 2006 2007 ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_mv); 2008 if (ret) 2009 return ret; 2010 2011 p_enc_info->vb_mv = vb_mv; 2012 2013 fbc_y_tbl_size = ALIGN(WAVE5_FBC_LUMA_TABLE_SIZE(buf_width, buf_height), 16); 2014 fbc_c_tbl_size = ALIGN(WAVE5_FBC_CHROMA_TABLE_SIZE(buf_width, buf_height), 16); 2015 2016 vb_fbc_y_tbl.daddr = 0; 2017 vb_fbc_y_tbl.size = ALIGN(fbc_y_tbl_size * count, BUFFER_MARGIN) + BUFFER_MARGIN; 2018 ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_fbc_y_tbl); 2019 if (ret) 2020 goto free_vb_fbc_y_tbl; 2021 2022 p_enc_info->vb_fbc_y_tbl = vb_fbc_y_tbl; 2023 2024 vb_fbc_c_tbl.daddr = 0; 2025 vb_fbc_c_tbl.size = ALIGN(fbc_c_tbl_size * count, BUFFER_MARGIN) + BUFFER_MARGIN; 2026 ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_fbc_c_tbl); 2027 if (ret) 2028 goto free_vb_fbc_c_tbl; 2029 2030 p_enc_info->vb_fbc_c_tbl = vb_fbc_c_tbl; 2031 2032 if (avc_encoding) 2033 sub_sampled_size = WAVE5_SUBSAMPLED_ONE_SIZE_AVC(buf_width, buf_height); 2034 else 2035 sub_sampled_size = WAVE5_SUBSAMPLED_ONE_SIZE(buf_width, buf_height); 2036 vb_sub_sam_buf.size = ALIGN(sub_sampled_size * count, BUFFER_MARGIN) + BUFFER_MARGIN; 2037 vb_sub_sam_buf.daddr = 0; 2038 ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_sub_sam_buf); 2039 if (ret) 2040 goto free_vb_sam_buf; 2041 2042 p_enc_info->vb_sub_sam_buf = vb_sub_sam_buf; 2043 2044 vb_task.size = (p_enc_info->vlc_buf_size * VLC_BUF_NUM) + 2045 (p_enc_info->param_buf_size * WAVE521_COMMAND_QUEUE_DEPTH); 2046 vb_task.daddr = 0; 2047 if (p_enc_info->vb_task.size == 0) { 2048 ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_task); 2049 if (ret) 2050 goto free_vb_task; 2051 2052 p_enc_info->vb_task = vb_task; 2053 2054 vpu_write_reg(inst->dev, W5_CMD_SET_FB_ADDR_TASK_BUF, 2055 p_enc_info->vb_task.daddr); 2056 vpu_write_reg(inst->dev, W5_CMD_SET_FB_TASK_BUF_SIZE, vb_task.size); 2057 } 2058 2059 /* set sub-sampled buffer base addr */ 2060 vpu_write_reg(inst->dev, W5_ADDR_SUB_SAMPLED_FB_BASE, vb_sub_sam_buf.daddr); 2061 /* set sub-sampled buffer size for one frame */ 2062 vpu_write_reg(inst->dev, W5_SUB_SAMPLED_ONE_FB_SIZE, sub_sampled_size); 2063 2064 vpu_write_reg(inst->dev, W5_PIC_SIZE, pic_size); 2065 2066 /* set stride of luma/chroma for compressed buffer */ 2067 if ((p_enc_info->rotation_angle || p_enc_info->mirror_direction) && 2068 !(p_enc_info->rotation_angle == 180 && 2069 p_enc_info->mirror_direction == MIRDIR_HOR_VER)) { 2070 luma_stride = calculate_luma_stride(buf_width, bit_depth); 2071 chroma_stride = calculate_chroma_stride(buf_width / 2, bit_depth); 2072 } else { 2073 luma_stride = calculate_luma_stride(p_open_param->pic_width, bit_depth); 2074 chroma_stride = calculate_chroma_stride(p_open_param->pic_width / 2, bit_depth); 2075 } 2076 2077 vpu_write_reg(inst->dev, W5_FBC_STRIDE, luma_stride << 16 | chroma_stride); 2078 vpu_write_reg(inst->dev, W5_COMMON_PIC_INFO, stride); 2079 2080 remain = count; 2081 cnt_8_chunk = DIV_ROUND_UP(count, 8); 2082 idx = 0; 2083 for (j = 0; j < cnt_8_chunk; j++) { 2084 reg_val = (j == cnt_8_chunk - 1) << 4 | ((j == 0) << 3); 2085 vpu_write_reg(inst->dev, W5_SFB_OPTION, reg_val); 2086 start_no = j * 8; 2087 end_no = start_no + ((remain >= 8) ? 8 : remain) - 1; 2088 2089 vpu_write_reg(inst->dev, W5_SET_FB_NUM, (start_no << 8) | end_no); 2090 2091 for (i = 0; i < 8 && i < remain; i++) { 2092 vpu_write_reg(inst->dev, W5_ADDR_LUMA_BASE0 + (i << 4), fb_arr[i + 2093 start_no].buf_y); 2094 vpu_write_reg(inst->dev, W5_ADDR_CB_BASE0 + (i << 4), 2095 fb_arr[i + start_no].buf_cb); 2096 /* luma FBC offset table */ 2097 vpu_write_reg(inst->dev, W5_ADDR_FBC_Y_OFFSET0 + (i << 4), 2098 vb_fbc_y_tbl.daddr + idx * fbc_y_tbl_size); 2099 /* chroma FBC offset table */ 2100 vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4), 2101 vb_fbc_c_tbl.daddr + idx * fbc_c_tbl_size); 2102 2103 vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2), 2104 vb_mv.daddr + idx * mv_col_size); 2105 idx++; 2106 } 2107 remain -= i; 2108 2109 ret = send_firmware_command(inst, W5_SET_FB, false, NULL, NULL); 2110 if (ret) 2111 goto free_vb_mem; 2112 } 2113 2114 ret = wave5_vpu_firmware_command_queue_error_check(vpu_dev, NULL); 2115 if (ret) 2116 goto free_vb_mem; 2117 2118 return ret; 2119 2120free_vb_mem: 2121 wave5_vdi_free_dma_memory(vpu_dev, &vb_task); 2122free_vb_task: 2123 wave5_vdi_free_dma_memory(vpu_dev, &vb_sub_sam_buf); 2124free_vb_sam_buf: 2125 wave5_vdi_free_dma_memory(vpu_dev, &vb_fbc_c_tbl); 2126free_vb_fbc_c_tbl: 2127 wave5_vdi_free_dma_memory(vpu_dev, &vb_fbc_y_tbl); 2128free_vb_fbc_y_tbl: 2129 wave5_vdi_free_dma_memory(vpu_dev, &vb_mv); 2130 return ret; 2131} 2132 2133static u32 wave5_vpu_enc_validate_sec_axi(struct vpu_instance *inst) 2134{ 2135 struct enc_info *p_enc_info = &inst->codec_info->enc_info; 2136 u32 rdo_size = 0, lf_size = 0, ret = 0; 2137 u32 sram_size = inst->dev->sram_size; 2138 2139 if (!sram_size) 2140 return 0; 2141 2142 /* 2143 * TODO: calculate rdo_size and lf_size from inst->src_fmt.width and 2144 * inst->codec_info->enc_info.open_param.wave_param.internal_bit_depth 2145 */ 2146 2147 if (p_enc_info->sec_axi_info.use_enc_rdo_enable && sram_size >= rdo_size) { 2148 ret |= BIT(11); 2149 sram_size -= rdo_size; 2150 } 2151 2152 if (p_enc_info->sec_axi_info.use_enc_lf_enable && sram_size >= lf_size) 2153 ret |= BIT(15); 2154 2155 return ret; 2156} 2157 2158int wave5_vpu_encode(struct vpu_instance *inst, struct enc_param *option, u32 *fail_res) 2159{ 2160 u32 src_frame_format; 2161 u32 reg_val = 0; 2162 u32 src_stride_c = 0; 2163 struct enc_info *p_enc_info = &inst->codec_info->enc_info; 2164 struct frame_buffer *p_src_frame = option->source_frame; 2165 struct enc_open_param *p_open_param = &p_enc_info->open_param; 2166 bool justified = WTL_RIGHT_JUSTIFIED; 2167 u32 format_no = WTL_PIXEL_8BIT; 2168 int ret; 2169 2170 vpu_write_reg(inst->dev, W5_CMD_ENC_BS_START_ADDR, option->pic_stream_buffer_addr); 2171 vpu_write_reg(inst->dev, W5_CMD_ENC_BS_SIZE, option->pic_stream_buffer_size); 2172 p_enc_info->stream_buf_start_addr = option->pic_stream_buffer_addr; 2173 p_enc_info->stream_buf_size = option->pic_stream_buffer_size; 2174 p_enc_info->stream_buf_end_addr = 2175 option->pic_stream_buffer_addr + option->pic_stream_buffer_size; 2176 2177 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_AXI_SEL, DEFAULT_SRC_AXI); 2178 /* secondary AXI */ 2179 reg_val = wave5_vpu_enc_validate_sec_axi(inst); 2180 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_USE_SEC_AXI, reg_val); 2181 2182 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_REPORT_PARAM, 0); 2183 2184 /* 2185 * CODEOPT_ENC_VCL is used to implicitly encode header/headers to generate bitstream. 2186 * (use ENC_PUT_VIDEO_HEADER for give_command to encode only a header) 2187 */ 2188 if (option->code_option.implicit_header_encode) 2189 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CODE_OPTION, 2190 CODEOPT_ENC_HEADER_IMPLICIT | CODEOPT_ENC_VCL | 2191 (option->code_option.encode_aud << 5) | 2192 (option->code_option.encode_eos << 6) | 2193 (option->code_option.encode_eob << 7)); 2194 else 2195 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CODE_OPTION, 2196 option->code_option.implicit_header_encode | 2197 (option->code_option.encode_vcl << 1) | 2198 (option->code_option.encode_vps << 2) | 2199 (option->code_option.encode_sps << 3) | 2200 (option->code_option.encode_pps << 4) | 2201 (option->code_option.encode_aud << 5) | 2202 (option->code_option.encode_eos << 6) | 2203 (option->code_option.encode_eob << 7)); 2204 2205 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PIC_PARAM, 0); 2206 2207 if (option->src_end_flag) 2208 /* no more source images. */ 2209 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_PIC_IDX, 0xFFFFFFFF); 2210 else 2211 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_PIC_IDX, option->src_idx); 2212 2213 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_Y, p_src_frame->buf_y); 2214 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_U, p_src_frame->buf_cb); 2215 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_V, p_src_frame->buf_cr); 2216 2217 switch (p_open_param->src_format) { 2218 case FORMAT_420: 2219 case FORMAT_422: 2220 case FORMAT_YUYV: 2221 case FORMAT_YVYU: 2222 case FORMAT_UYVY: 2223 case FORMAT_VYUY: 2224 justified = WTL_LEFT_JUSTIFIED; 2225 format_no = WTL_PIXEL_8BIT; 2226 src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : 2227 (p_src_frame->stride / 2); 2228 src_stride_c = (p_open_param->src_format == FORMAT_422) ? src_stride_c * 2 : 2229 src_stride_c; 2230 break; 2231 case FORMAT_420_P10_16BIT_MSB: 2232 case FORMAT_422_P10_16BIT_MSB: 2233 case FORMAT_YUYV_P10_16BIT_MSB: 2234 case FORMAT_YVYU_P10_16BIT_MSB: 2235 case FORMAT_UYVY_P10_16BIT_MSB: 2236 case FORMAT_VYUY_P10_16BIT_MSB: 2237 justified = WTL_RIGHT_JUSTIFIED; 2238 format_no = WTL_PIXEL_16BIT; 2239 src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : 2240 (p_src_frame->stride / 2); 2241 src_stride_c = (p_open_param->src_format == 2242 FORMAT_422_P10_16BIT_MSB) ? src_stride_c * 2 : src_stride_c; 2243 break; 2244 case FORMAT_420_P10_16BIT_LSB: 2245 case FORMAT_422_P10_16BIT_LSB: 2246 case FORMAT_YUYV_P10_16BIT_LSB: 2247 case FORMAT_YVYU_P10_16BIT_LSB: 2248 case FORMAT_UYVY_P10_16BIT_LSB: 2249 case FORMAT_VYUY_P10_16BIT_LSB: 2250 justified = WTL_LEFT_JUSTIFIED; 2251 format_no = WTL_PIXEL_16BIT; 2252 src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : 2253 (p_src_frame->stride / 2); 2254 src_stride_c = (p_open_param->src_format == 2255 FORMAT_422_P10_16BIT_LSB) ? src_stride_c * 2 : src_stride_c; 2256 break; 2257 case FORMAT_420_P10_32BIT_MSB: 2258 case FORMAT_422_P10_32BIT_MSB: 2259 case FORMAT_YUYV_P10_32BIT_MSB: 2260 case FORMAT_YVYU_P10_32BIT_MSB: 2261 case FORMAT_UYVY_P10_32BIT_MSB: 2262 case FORMAT_VYUY_P10_32BIT_MSB: 2263 justified = WTL_RIGHT_JUSTIFIED; 2264 format_no = WTL_PIXEL_32BIT; 2265 src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : 2266 ALIGN(p_src_frame->stride / 2, 16) * BIT(inst->cbcr_interleave); 2267 src_stride_c = (p_open_param->src_format == 2268 FORMAT_422_P10_32BIT_MSB) ? src_stride_c * 2 : src_stride_c; 2269 break; 2270 case FORMAT_420_P10_32BIT_LSB: 2271 case FORMAT_422_P10_32BIT_LSB: 2272 case FORMAT_YUYV_P10_32BIT_LSB: 2273 case FORMAT_YVYU_P10_32BIT_LSB: 2274 case FORMAT_UYVY_P10_32BIT_LSB: 2275 case FORMAT_VYUY_P10_32BIT_LSB: 2276 justified = WTL_LEFT_JUSTIFIED; 2277 format_no = WTL_PIXEL_32BIT; 2278 src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : 2279 ALIGN(p_src_frame->stride / 2, 16) * BIT(inst->cbcr_interleave); 2280 src_stride_c = (p_open_param->src_format == 2281 FORMAT_422_P10_32BIT_LSB) ? src_stride_c * 2 : src_stride_c; 2282 break; 2283 default: 2284 return -EINVAL; 2285 } 2286 2287 src_frame_format = (inst->cbcr_interleave << 1) | (inst->nv21); 2288 switch (p_open_param->packed_format) { 2289 case PACKED_YUYV: 2290 src_frame_format = 4; 2291 break; 2292 case PACKED_YVYU: 2293 src_frame_format = 5; 2294 break; 2295 case PACKED_UYVY: 2296 src_frame_format = 6; 2297 break; 2298 case PACKED_VYUY: 2299 src_frame_format = 7; 2300 break; 2301 default: 2302 break; 2303 } 2304 2305 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_STRIDE, 2306 (p_src_frame->stride << 16) | src_stride_c); 2307 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_FORMAT, src_frame_format | 2308 (format_no << 3) | (justified << 5) | (PIC_SRC_ENDIANNESS_BIG_ENDIAN << 6)); 2309 2310 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR, 0); 2311 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM, 0); 2312 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_LONGTERM_PIC, 0); 2313 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_Y, 0); 2314 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_C, 0); 2315 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_Y, 0); 2316 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_C, 0); 2317 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PREFIX_SEI_INFO, 0); 2318 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR, 0); 2319 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SUFFIX_SEI_INFO, 0); 2320 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR, 0); 2321 2322 ret = send_firmware_command(inst, W5_DEC_ENC_PIC, true, ®_val, fail_res); 2323 if (ret == -ETIMEDOUT) 2324 return ret; 2325 2326 p_enc_info->instance_queue_count = (reg_val >> 16) & 0xff; 2327 p_enc_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); 2328 2329 if (ret) 2330 return ret; 2331 2332 return 0; 2333} 2334 2335int wave5_vpu_enc_get_result(struct vpu_instance *inst, struct enc_output_info *result) 2336{ 2337 int ret; 2338 u32 encoding_success; 2339 u32 reg_val; 2340 struct enc_info *p_enc_info = &inst->codec_info->enc_info; 2341 struct vpu_device *vpu_dev = inst->dev; 2342 2343 ret = wave5_send_query(inst->dev, inst, GET_RESULT); 2344 if (ret) 2345 return ret; 2346 2347 dev_dbg(inst->dev->dev, "%s: enc pic complete\n", __func__); 2348 2349 reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); 2350 2351 p_enc_info->instance_queue_count = (reg_val >> 16) & 0xff; 2352 p_enc_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); 2353 2354 encoding_success = vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_SUCCESS); 2355 if (!encoding_success) { 2356 result->error_reason = vpu_read_reg(inst->dev, W5_RET_ENC_ERR_INFO); 2357 return -EIO; 2358 } 2359 2360 result->warn_info = vpu_read_reg(inst->dev, W5_RET_ENC_WARN_INFO); 2361 2362 reg_val = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_TYPE); 2363 result->pic_type = reg_val & 0xFFFF; 2364 2365 result->enc_vcl_nut = vpu_read_reg(inst->dev, W5_RET_ENC_VCL_NUT); 2366 /* 2367 * To get the reconstructed frame use the following index on 2368 * inst->frame_buf 2369 */ 2370 result->recon_frame_index = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_IDX); 2371 result->enc_pic_byte = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_BYTE); 2372 result->enc_src_idx = vpu_read_reg(inst->dev, W5_RET_ENC_USED_SRC_IDX); 2373 p_enc_info->stream_wr_ptr = vpu_read_reg(inst->dev, W5_RET_ENC_WR_PTR); 2374 p_enc_info->stream_rd_ptr = vpu_read_reg(inst->dev, W5_RET_ENC_RD_PTR); 2375 2376 result->bitstream_buffer = vpu_read_reg(inst->dev, W5_RET_ENC_RD_PTR); 2377 result->rd_ptr = p_enc_info->stream_rd_ptr; 2378 result->wr_ptr = p_enc_info->stream_wr_ptr; 2379 2380 /*result for header only(no vcl) encoding */ 2381 if (result->recon_frame_index == RECON_IDX_FLAG_HEADER_ONLY) 2382 result->bitstream_size = result->enc_pic_byte; 2383 else if (result->recon_frame_index < 0) 2384 result->bitstream_size = 0; 2385 else 2386 result->bitstream_size = result->enc_pic_byte; 2387 2388 result->enc_host_cmd_tick = vpu_read_reg(inst->dev, W5_RET_ENC_HOST_CMD_TICK); 2389 result->enc_encode_end_tick = vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_END_TICK); 2390 2391 if (!p_enc_info->first_cycle_check) { 2392 result->frame_cycle = (result->enc_encode_end_tick - result->enc_host_cmd_tick) * 2393 p_enc_info->cycle_per_tick; 2394 p_enc_info->first_cycle_check = true; 2395 } else { 2396 result->frame_cycle = 2397 (result->enc_encode_end_tick - vpu_dev->last_performance_cycles) * 2398 p_enc_info->cycle_per_tick; 2399 if (vpu_dev->last_performance_cycles < result->enc_host_cmd_tick) 2400 result->frame_cycle = (result->enc_encode_end_tick - 2401 result->enc_host_cmd_tick) * p_enc_info->cycle_per_tick; 2402 } 2403 vpu_dev->last_performance_cycles = result->enc_encode_end_tick; 2404 2405 return 0; 2406} 2407 2408int wave5_vpu_enc_finish_seq(struct vpu_instance *inst, u32 *fail_res) 2409{ 2410 return send_firmware_command(inst, W5_DESTROY_INSTANCE, true, NULL, fail_res); 2411} 2412 2413static bool wave5_vpu_enc_check_common_param_valid(struct vpu_instance *inst, 2414 struct enc_open_param *open_param) 2415{ 2416 bool low_delay = true; 2417 struct enc_wave_param *param = &open_param->wave_param; 2418 struct vpu_device *vpu_dev = inst->dev; 2419 struct device *dev = vpu_dev->dev; 2420 u32 num_ctu_row = (open_param->pic_height + 64 - 1) / 64; 2421 u32 num_ctu_col = (open_param->pic_width + 64 - 1) / 64; 2422 u32 ctu_sz = num_ctu_col * num_ctu_row; 2423 2424 if (inst->std == W_HEVC_ENC && low_delay && 2425 param->decoding_refresh_type == DEC_REFRESH_TYPE_CRA) { 2426 dev_warn(dev, 2427 "dec_refresh_type(CRA) shouldn't be used together with low delay GOP\n"); 2428 dev_warn(dev, "Suggested configuration parameter: decoding refresh type (IDR)\n"); 2429 param->decoding_refresh_type = 2; 2430 } 2431 2432 if (param->wpp_enable && param->independ_slice_mode) { 2433 unsigned int num_ctb_in_width = ALIGN(open_param->pic_width, 64) >> 6; 2434 2435 if (param->independ_slice_mode_arg % num_ctb_in_width) { 2436 dev_err(dev, "independ_slice_mode_arg %u must be a multiple of %u\n", 2437 param->independ_slice_mode_arg, num_ctb_in_width); 2438 return false; 2439 } 2440 } 2441 2442 /* multi-slice & wpp */ 2443 if (param->wpp_enable && param->depend_slice_mode) { 2444 dev_err(dev, "wpp_enable && depend_slice_mode cannot be used simultaneously\n"); 2445 return false; 2446 } 2447 2448 if (!param->independ_slice_mode && param->depend_slice_mode) { 2449 dev_err(dev, "depend_slice_mode requires independ_slice_mode\n"); 2450 return false; 2451 } else if (param->independ_slice_mode && 2452 param->depend_slice_mode == DEPEND_SLICE_MODE_RECOMMENDED && 2453 param->independ_slice_mode_arg < param->depend_slice_mode_arg) { 2454 dev_err(dev, "independ_slice_mode_arg: %u must be smaller than %u\n", 2455 param->independ_slice_mode_arg, param->depend_slice_mode_arg); 2456 return false; 2457 } 2458 2459 if (param->independ_slice_mode && param->independ_slice_mode_arg > 65535) { 2460 dev_err(dev, "independ_slice_mode_arg: %u must be smaller than 65535\n", 2461 param->independ_slice_mode_arg); 2462 return false; 2463 } 2464 2465 if (param->depend_slice_mode && param->depend_slice_mode_arg > 65535) { 2466 dev_err(dev, "depend_slice_mode_arg: %u must be smaller than 65535\n", 2467 param->depend_slice_mode_arg); 2468 return false; 2469 } 2470 2471 if (param->conf_win_top % 2) { 2472 dev_err(dev, "conf_win_top: %u, must be a multiple of 2\n", param->conf_win_top); 2473 return false; 2474 } 2475 2476 if (param->conf_win_bot % 2) { 2477 dev_err(dev, "conf_win_bot: %u, must be a multiple of 2\n", param->conf_win_bot); 2478 return false; 2479 } 2480 2481 if (param->conf_win_left % 2) { 2482 dev_err(dev, "conf_win_left: %u, must be a multiple of 2\n", param->conf_win_left); 2483 return false; 2484 } 2485 2486 if (param->conf_win_right % 2) { 2487 dev_err(dev, "conf_win_right: %u, Must be a multiple of 2\n", 2488 param->conf_win_right); 2489 return false; 2490 } 2491 2492 if (param->lossless_enable && open_param->rc_enable) { 2493 dev_err(dev, "option rate_control cannot be used with lossless_coding\n"); 2494 return false; 2495 } 2496 2497 if (param->lossless_enable && !param->skip_intra_trans) { 2498 dev_err(dev, "option intra_trans_skip must be enabled with lossless_coding\n"); 2499 return false; 2500 } 2501 2502 /* intra refresh */ 2503 if (param->intra_refresh_mode && param->intra_refresh_arg == 0) { 2504 dev_err(dev, "Invalid refresh argument, mode: %u, refresh: %u must be > 0\n", 2505 param->intra_refresh_mode, param->intra_refresh_arg); 2506 return false; 2507 } 2508 switch (param->intra_refresh_mode) { 2509 case REFRESH_MODE_CTU_ROWS: 2510 if (param->intra_mb_refresh_arg > num_ctu_row) 2511 goto invalid_refresh_argument; 2512 break; 2513 case REFRESH_MODE_CTU_COLUMNS: 2514 if (param->intra_refresh_arg > num_ctu_col) 2515 goto invalid_refresh_argument; 2516 break; 2517 case REFRESH_MODE_CTU_STEP_SIZE: 2518 if (param->intra_refresh_arg > ctu_sz) 2519 goto invalid_refresh_argument; 2520 break; 2521 case REFRESH_MODE_CTUS: 2522 if (param->intra_refresh_arg > ctu_sz) 2523 goto invalid_refresh_argument; 2524 if (param->lossless_enable) { 2525 dev_err(dev, "mode: %u cannot be used lossless_enable", 2526 param->intra_refresh_mode); 2527 return false; 2528 } 2529 } 2530 return true; 2531 2532invalid_refresh_argument: 2533 dev_err(dev, "Invalid refresh argument, mode: %u, refresh: %u > W(%u)xH(%u)\n", 2534 param->intra_refresh_mode, param->intra_refresh_arg, 2535 num_ctu_row, num_ctu_col); 2536 return false; 2537} 2538 2539static bool wave5_vpu_enc_check_param_valid(struct vpu_device *vpu_dev, 2540 struct enc_open_param *open_param) 2541{ 2542 struct enc_wave_param *param = &open_param->wave_param; 2543 2544 if (open_param->rc_enable) { 2545 if (param->min_qp_i > param->max_qp_i || param->min_qp_p > param->max_qp_p || 2546 param->min_qp_b > param->max_qp_b) { 2547 dev_err(vpu_dev->dev, "Configuration failed because min_qp is greater than max_qp\n"); 2548 dev_err(vpu_dev->dev, "Suggested configuration parameters: min_qp = max_qp\n"); 2549 return false; 2550 } 2551 2552 if (open_param->bit_rate <= (int)open_param->frame_rate_info) { 2553 dev_err(vpu_dev->dev, 2554 "enc_bit_rate: %u must be greater than the frame_rate: %u\n", 2555 open_param->bit_rate, (int)open_param->frame_rate_info); 2556 return false; 2557 } 2558 } 2559 2560 return true; 2561} 2562 2563int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_param *open_param) 2564{ 2565 u32 pic_width; 2566 u32 pic_height; 2567 s32 product_id = inst->dev->product; 2568 struct vpu_attr *p_attr = &inst->dev->attr; 2569 struct enc_wave_param *param; 2570 2571 if (!open_param) 2572 return -EINVAL; 2573 2574 param = &open_param->wave_param; 2575 pic_width = open_param->pic_width; 2576 pic_height = open_param->pic_height; 2577 2578 if (inst->id >= MAX_NUM_INSTANCE) { 2579 dev_err(inst->dev->dev, "Too many simultaneous instances: %d (max: %u)\n", 2580 inst->id, MAX_NUM_INSTANCE); 2581 return -EOPNOTSUPP; 2582 } 2583 2584 if (inst->std != W_HEVC_ENC && 2585 !(inst->std == W_AVC_ENC && product_id == PRODUCT_ID_521)) { 2586 dev_err(inst->dev->dev, "Unsupported encoder-codec & product combination\n"); 2587 return -EOPNOTSUPP; 2588 } 2589 2590 if (param->internal_bit_depth == 10) { 2591 if (inst->std == W_HEVC_ENC && !p_attr->support_hevc10bit_enc) { 2592 dev_err(inst->dev->dev, 2593 "Flag support_hevc10bit_enc must be set to encode 10bit HEVC\n"); 2594 return -EOPNOTSUPP; 2595 } else if (inst->std == W_AVC_ENC && !p_attr->support_avc10bit_enc) { 2596 dev_err(inst->dev->dev, 2597 "Flag support_avc10bit_enc must be set to encode 10bit AVC\n"); 2598 return -EOPNOTSUPP; 2599 } 2600 } 2601 2602 if (!open_param->frame_rate_info) { 2603 dev_err(inst->dev->dev, "No frame rate information.\n"); 2604 return -EINVAL; 2605 } 2606 2607 if (open_param->bit_rate > MAX_BIT_RATE) { 2608 dev_err(inst->dev->dev, "Invalid encoding bit-rate: %u (valid: 0-%u)\n", 2609 open_param->bit_rate, MAX_BIT_RATE); 2610 return -EINVAL; 2611 } 2612 2613 if (pic_width < W5_MIN_ENC_PIC_WIDTH || pic_width > W5_MAX_ENC_PIC_WIDTH || 2614 pic_height < W5_MIN_ENC_PIC_HEIGHT || pic_height > W5_MAX_ENC_PIC_HEIGHT) { 2615 dev_err(inst->dev->dev, "Invalid encoding dimension: %ux%u\n", 2616 pic_width, pic_height); 2617 return -EINVAL; 2618 } 2619 2620 if (param->profile) { 2621 if (inst->std == W_HEVC_ENC) { 2622 if ((param->profile != HEVC_PROFILE_MAIN || 2623 (param->profile == HEVC_PROFILE_MAIN && 2624 param->internal_bit_depth > 8)) && 2625 (param->profile != HEVC_PROFILE_MAIN10 || 2626 (param->profile == HEVC_PROFILE_MAIN10 && 2627 param->internal_bit_depth < 10)) && 2628 param->profile != HEVC_PROFILE_STILLPICTURE) { 2629 dev_err(inst->dev->dev, 2630 "Invalid HEVC encoding profile: %u (bit-depth: %u)\n", 2631 param->profile, param->internal_bit_depth); 2632 return -EINVAL; 2633 } 2634 } else if (inst->std == W_AVC_ENC) { 2635 if ((param->internal_bit_depth > 8 && 2636 param->profile != H264_PROFILE_HIGH10)) { 2637 dev_err(inst->dev->dev, 2638 "Invalid AVC encoding profile: %u (bit-depth: %u)\n", 2639 param->profile, param->internal_bit_depth); 2640 return -EINVAL; 2641 } 2642 } 2643 } 2644 2645 if (param->decoding_refresh_type > DEC_REFRESH_TYPE_IDR) { 2646 dev_err(inst->dev->dev, "Invalid decoding refresh type: %u (valid: 0-2)\n", 2647 param->decoding_refresh_type); 2648 return -EINVAL; 2649 } 2650 2651 if (param->intra_refresh_mode > REFRESH_MODE_CTUS) { 2652 dev_err(inst->dev->dev, "Invalid intra refresh mode: %d (valid: 0-4)\n", 2653 param->intra_refresh_mode); 2654 return -EINVAL; 2655 } 2656 2657 if (inst->std == W_HEVC_ENC && param->independ_slice_mode && 2658 param->depend_slice_mode > DEPEND_SLICE_MODE_BOOST) { 2659 dev_err(inst->dev->dev, 2660 "Can't combine slice modes: independent and fast dependent for HEVC\n"); 2661 return -EINVAL; 2662 } 2663 2664 if (!param->disable_deblk) { 2665 if (param->beta_offset_div2 < -6 || param->beta_offset_div2 > 6) { 2666 dev_err(inst->dev->dev, "Invalid beta offset: %d (valid: -6-6)\n", 2667 param->beta_offset_div2); 2668 return -EINVAL; 2669 } 2670 2671 if (param->tc_offset_div2 < -6 || param->tc_offset_div2 > 6) { 2672 dev_err(inst->dev->dev, "Invalid tc offset: %d (valid: -6-6)\n", 2673 param->tc_offset_div2); 2674 return -EINVAL; 2675 } 2676 } 2677 2678 if (param->intra_qp > MAX_INTRA_QP) { 2679 dev_err(inst->dev->dev, 2680 "Invalid intra quantization parameter: %u (valid: 0-%u)\n", 2681 param->intra_qp, MAX_INTRA_QP); 2682 return -EINVAL; 2683 } 2684 2685 if (open_param->rc_enable) { 2686 if (param->min_qp_i > MAX_INTRA_QP || param->max_qp_i > MAX_INTRA_QP || 2687 param->min_qp_p > MAX_INTRA_QP || param->max_qp_p > MAX_INTRA_QP || 2688 param->min_qp_b > MAX_INTRA_QP || param->max_qp_b > MAX_INTRA_QP) { 2689 dev_err(inst->dev->dev, 2690 "Invalid quantization parameter min/max values: " 2691 "I: %u-%u, P: %u-%u, B: %u-%u (valid for each: 0-%u)\n", 2692 param->min_qp_i, param->max_qp_i, param->min_qp_p, param->max_qp_p, 2693 param->min_qp_b, param->max_qp_b, MAX_INTRA_QP); 2694 return -EINVAL; 2695 } 2696 2697 if (param->hvs_qp_enable && param->hvs_max_delta_qp > MAX_HVS_MAX_DELTA_QP) { 2698 dev_err(inst->dev->dev, 2699 "Invalid HVS max delta quantization parameter: %u (valid: 0-%u)\n", 2700 param->hvs_max_delta_qp, MAX_HVS_MAX_DELTA_QP); 2701 return -EINVAL; 2702 } 2703 2704 if (open_param->vbv_buffer_size < MIN_VBV_BUFFER_SIZE || 2705 open_param->vbv_buffer_size > MAX_VBV_BUFFER_SIZE) { 2706 dev_err(inst->dev->dev, "VBV buffer size: %u (valid: %u-%u)\n", 2707 open_param->vbv_buffer_size, MIN_VBV_BUFFER_SIZE, 2708 MAX_VBV_BUFFER_SIZE); 2709 return -EINVAL; 2710 } 2711 } 2712 2713 if (!wave5_vpu_enc_check_common_param_valid(inst, open_param)) 2714 return -EINVAL; 2715 2716 if (!wave5_vpu_enc_check_param_valid(inst->dev, open_param)) 2717 return -EINVAL; 2718 2719 if (param->chroma_cb_qp_offset < -12 || param->chroma_cb_qp_offset > 12) { 2720 dev_err(inst->dev->dev, 2721 "Invalid chroma Cb quantization parameter offset: %d (valid: -12-12)\n", 2722 param->chroma_cb_qp_offset); 2723 return -EINVAL; 2724 } 2725 2726 if (param->chroma_cr_qp_offset < -12 || param->chroma_cr_qp_offset > 12) { 2727 dev_err(inst->dev->dev, 2728 "Invalid chroma Cr quantization parameter offset: %d (valid: -12-12)\n", 2729 param->chroma_cr_qp_offset); 2730 return -EINVAL; 2731 } 2732 2733 if (param->intra_refresh_mode == REFRESH_MODE_CTU_STEP_SIZE && !param->intra_refresh_arg) { 2734 dev_err(inst->dev->dev, 2735 "Intra refresh mode CTU step-size requires an argument\n"); 2736 return -EINVAL; 2737 } 2738 2739 if (inst->std == W_HEVC_ENC) { 2740 if (param->nr_intra_weight_y > MAX_INTRA_WEIGHT || 2741 param->nr_intra_weight_cb > MAX_INTRA_WEIGHT || 2742 param->nr_intra_weight_cr > MAX_INTRA_WEIGHT) { 2743 dev_err(inst->dev->dev, 2744 "Invalid intra weight Y(%u) Cb(%u) Cr(%u) (valid: %u)\n", 2745 param->nr_intra_weight_y, param->nr_intra_weight_cb, 2746 param->nr_intra_weight_cr, MAX_INTRA_WEIGHT); 2747 return -EINVAL; 2748 } 2749 2750 if (param->nr_inter_weight_y > MAX_INTER_WEIGHT || 2751 param->nr_inter_weight_cb > MAX_INTER_WEIGHT || 2752 param->nr_inter_weight_cr > MAX_INTER_WEIGHT) { 2753 dev_err(inst->dev->dev, 2754 "Invalid inter weight Y(%u) Cb(%u) Cr(%u) (valid: %u)\n", 2755 param->nr_inter_weight_y, param->nr_inter_weight_cb, 2756 param->nr_inter_weight_cr, MAX_INTER_WEIGHT); 2757 return -EINVAL; 2758 } 2759 } 2760 2761 return 0; 2762}
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