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aspeed-video.c
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linux-6.19.14/drivers/media/platform/aspeed/aspeed-video.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2// Copyright 2020 IBM Corp. 3// Copyright (c) 2019-2020 Intel Corporation 4 5#include <linux/atomic.h> 6#include <linux/bitfield.h> 7#include <linux/cleanup.h> 8#include <linux/clk.h> 9#include <linux/delay.h> 10#include <linux/device.h> 11#include <linux/dma-mapping.h> 12#include <linux/interrupt.h> 13#include <linux/jiffies.h> 14#include <linux/module.h> 15#include <linux/mutex.h> 16#include <linux/of.h> 17#include <linux/of_irq.h> 18#include <linux/of_reserved_mem.h> 19#include <linux/platform_device.h> 20#include <linux/sched.h> 21#include <linux/spinlock.h> 22#include <linux/string.h> 23#include <linux/v4l2-controls.h> 24#include <linux/videodev2.h> 25#include <linux/wait.h> 26#include <linux/workqueue.h> 27#include <linux/debugfs.h> 28#include <linux/ktime.h> 29#include <linux/regmap.h> 30#include <linux/mfd/syscon.h> 31#include <media/v4l2-ctrls.h> 32#include <media/v4l2-dev.h> 33#include <media/v4l2-device.h> 34#include <media/v4l2-dv-timings.h> 35#include <media/v4l2-event.h> 36#include <media/v4l2-ioctl.h> 37#include <media/videobuf2-dma-contig.h> 38#include <uapi/linux/aspeed-video.h> 39 40#define ASPEED_VIDEO_V4L2_MIN_BUF_REQ 3 41 42#define DEVICE_NAME "aspeed-video" 43 44#define ASPEED_VIDEO_JPEG_NUM_QUALITIES 12 45#define ASPEED_VIDEO_JPEG_HEADER_SIZE 10 46#define ASPEED_VIDEO_JPEG_QUANT_SIZE 116 47#define ASPEED_VIDEO_JPEG_DCT_SIZE 34 48 49#define MAX_FRAME_RATE 60 50#define MAX_HEIGHT 1200 51#define MAX_WIDTH 1920 52#define MIN_HEIGHT 480 53#define MIN_WIDTH 640 54 55#define NUM_POLARITY_CHECKS 10 56#define INVALID_RESOLUTION_RETRIES 2 57#define INVALID_RESOLUTION_DELAY msecs_to_jiffies(250) 58#define RESOLUTION_CHANGE_DELAY msecs_to_jiffies(500) 59#define MODE_DETECT_TIMEOUT msecs_to_jiffies(500) 60#define STOP_TIMEOUT msecs_to_jiffies(1000) 61#define DIRECT_FETCH_THRESHOLD 0x0c0000 /* 1024 * 768 */ 62 63#define VE_MAX_SRC_BUFFER_SIZE 0x8ca000 /* 1920 * 1200, 32bpp */ 64#define VE_JPEG_HEADER_SIZE 0x006000 /* 512 * 12 * 4 */ 65#define VE_BCD_BUFF_SIZE 0x9000 /* (1920/8) * (1200/8) */ 66 67#define VE_PROTECTION_KEY 0x000 68#define VE_PROTECTION_KEY_UNLOCK 0x1a038aa8 69 70#define VE_SEQ_CTRL 0x004 71#define VE_SEQ_CTRL_TRIG_MODE_DET BIT(0) 72#define VE_SEQ_CTRL_TRIG_CAPTURE BIT(1) 73#define VE_SEQ_CTRL_FORCE_IDLE BIT(2) 74#define VE_SEQ_CTRL_MULT_FRAME BIT(3) 75#define VE_SEQ_CTRL_TRIG_COMP BIT(4) 76#define VE_SEQ_CTRL_AUTO_COMP BIT(5) 77#define VE_SEQ_CTRL_EN_WATCHDOG BIT(7) 78#define VE_SEQ_CTRL_YUV420 BIT(10) 79#define VE_SEQ_CTRL_COMP_FMT GENMASK(11, 10) 80#define VE_SEQ_CTRL_HALT BIT(12) 81#define VE_SEQ_CTRL_EN_WATCHDOG_COMP BIT(14) 82#define VE_SEQ_CTRL_TRIG_JPG BIT(15) 83#define VE_SEQ_CTRL_CAP_BUSY BIT(16) 84#define VE_SEQ_CTRL_COMP_BUSY BIT(18) 85 86#define AST2500_VE_SEQ_CTRL_JPEG_MODE BIT(13) 87#define AST2400_VE_SEQ_CTRL_JPEG_MODE BIT(8) 88 89#define VE_CTRL 0x008 90#define VE_CTRL_HSYNC_POL BIT(0) 91#define VE_CTRL_VSYNC_POL BIT(1) 92#define VE_CTRL_SOURCE BIT(2) 93#define VE_CTRL_INT_DE BIT(4) 94#define VE_CTRL_DIRECT_FETCH BIT(5) 95#define VE_CTRL_CAPTURE_FMT GENMASK(7, 6) 96#define VE_CTRL_AUTO_OR_CURSOR BIT(8) 97#define VE_CTRL_CLK_INVERSE BIT(11) 98#define VE_CTRL_CLK_DELAY GENMASK(11, 9) 99#define VE_CTRL_INTERLACE BIT(14) 100#define VE_CTRL_HSYNC_POL_CTRL BIT(15) 101#define VE_CTRL_FRC GENMASK(23, 16) 102 103#define VE_TGS_0 0x00c 104#define VE_TGS_1 0x010 105#define VE_TGS_FIRST GENMASK(28, 16) 106#define VE_TGS_LAST GENMASK(12, 0) 107 108#define VE_SCALING_FACTOR 0x014 109#define VE_SCALING_FILTER0 0x018 110#define VE_SCALING_FILTER1 0x01c 111#define VE_SCALING_FILTER2 0x020 112#define VE_SCALING_FILTER3 0x024 113 114#define VE_BCD_CTRL 0x02C 115#define VE_BCD_CTRL_EN_BCD BIT(0) 116#define VE_BCD_CTRL_EN_ABCD BIT(1) 117#define VE_BCD_CTRL_EN_CB BIT(2) 118#define VE_BCD_CTRL_THR GENMASK(23, 16) 119#define VE_BCD_CTRL_ABCD_THR GENMASK(31, 24) 120 121#define VE_CAP_WINDOW 0x030 122#define VE_COMP_WINDOW 0x034 123#define VE_COMP_PROC_OFFSET 0x038 124#define VE_COMP_OFFSET 0x03c 125#define VE_JPEG_ADDR 0x040 126#define VE_SRC0_ADDR 0x044 127#define VE_SRC_SCANLINE_OFFSET 0x048 128#define VE_SRC1_ADDR 0x04c 129#define VE_BCD_ADDR 0x050 130#define VE_COMP_ADDR 0x054 131 132#define VE_STREAM_BUF_SIZE 0x058 133#define VE_STREAM_BUF_SIZE_N_PACKETS GENMASK(5, 3) 134#define VE_STREAM_BUF_SIZE_P_SIZE GENMASK(2, 0) 135 136#define VE_COMP_CTRL 0x060 137#define VE_COMP_CTRL_VQ_DCT_ONLY BIT(0) 138#define VE_COMP_CTRL_VQ_4COLOR BIT(1) 139#define VE_COMP_CTRL_QUANTIZE BIT(2) 140#define VE_COMP_CTRL_EN_BQ BIT(4) 141#define VE_COMP_CTRL_EN_CRYPTO BIT(5) 142#define VE_COMP_CTRL_DCT_CHR GENMASK(10, 6) 143#define VE_COMP_CTRL_DCT_LUM GENMASK(15, 11) 144#define VE_COMP_CTRL_EN_HQ BIT(16) 145#define VE_COMP_CTRL_RSVD BIT(19) 146#define VE_COMP_CTRL_ENCODE GENMASK(21, 20) 147#define VE_COMP_CTRL_HQ_DCT_CHR GENMASK(26, 22) 148#define VE_COMP_CTRL_HQ_DCT_LUM GENMASK(31, 27) 149 150#define VE_CB_ADDR 0x06C 151 152#define AST2400_VE_COMP_SIZE_READ_BACK 0x078 153#define AST2600_VE_COMP_SIZE_READ_BACK 0x084 154 155#define VE_SRC_LR_EDGE_DET 0x090 156#define VE_SRC_LR_EDGE_DET_LEFT GENMASK(11, 0) 157#define VE_SRC_LR_EDGE_DET_NO_V BIT(12) 158#define VE_SRC_LR_EDGE_DET_NO_H BIT(13) 159#define VE_SRC_LR_EDGE_DET_NO_DISP BIT(14) 160#define VE_SRC_LR_EDGE_DET_NO_CLK BIT(15) 161#define VE_SRC_LR_EDGE_DET_RT GENMASK(27, 16) 162#define VE_SRC_LR_EDGE_DET_INTERLACE BIT(31) 163 164#define VE_SRC_TB_EDGE_DET 0x094 165#define VE_SRC_TB_EDGE_DET_TOP GENMASK(12, 0) 166#define VE_SRC_TB_EDGE_DET_BOT GENMASK(28, 16) 167 168#define VE_MODE_DETECT_STATUS 0x098 169#define VE_MODE_DETECT_H_PERIOD GENMASK(11, 0) 170#define VE_MODE_DETECT_EXTSRC_ADC BIT(12) 171#define VE_MODE_DETECT_H_STABLE BIT(13) 172#define VE_MODE_DETECT_V_STABLE BIT(14) 173#define VE_MODE_DETECT_V_LINES GENMASK(27, 16) 174#define VE_MODE_DETECT_STATUS_VSYNC BIT(28) 175#define VE_MODE_DETECT_STATUS_HSYNC BIT(29) 176#define VE_MODE_DETECT_VSYNC_RDY BIT(30) 177#define VE_MODE_DETECT_HSYNC_RDY BIT(31) 178 179#define VE_SYNC_STATUS 0x09c 180#define VE_SYNC_STATUS_HSYNC GENMASK(11, 0) 181#define VE_SYNC_STATUS_VSYNC GENMASK(27, 16) 182 183#define VE_H_TOTAL_PIXELS 0x0A0 184 185#define VE_INTERRUPT_CTRL 0x304 186#define VE_INTERRUPT_STATUS 0x308 187#define VE_INTERRUPT_MODE_DETECT_WD BIT(0) 188#define VE_INTERRUPT_CAPTURE_COMPLETE BIT(1) 189#define VE_INTERRUPT_COMP_READY BIT(2) 190#define VE_INTERRUPT_COMP_COMPLETE BIT(3) 191#define VE_INTERRUPT_MODE_DETECT BIT(4) 192#define VE_INTERRUPT_FRAME_COMPLETE BIT(5) 193#define VE_INTERRUPT_DECODE_ERR BIT(6) 194#define VE_INTERRUPT_HALT_READY BIT(8) 195#define VE_INTERRUPT_HANG_WD BIT(9) 196#define VE_INTERRUPT_STREAM_DESC BIT(10) 197#define VE_INTERRUPT_VSYNC_DESC BIT(11) 198 199#define VE_MODE_DETECT 0x30c 200#define VE_MODE_DT_HOR_TOLER GENMASK(31, 28) 201#define VE_MODE_DT_VER_TOLER GENMASK(27, 24) 202#define VE_MODE_DT_HOR_STABLE GENMASK(23, 20) 203#define VE_MODE_DT_VER_STABLE GENMASK(19, 16) 204#define VE_MODE_DT_EDG_THROD GENMASK(15, 8) 205 206#define VE_MEM_RESTRICT_START 0x310 207#define VE_MEM_RESTRICT_END 0x314 208 209/* SCU's registers */ 210#define SCU_MISC_CTRL 0xC0 211#define SCU_DPLL_SOURCE BIT(20) 212 213/* GFX's registers */ 214#define GFX_CTRL 0x60 215#define GFX_CTRL_ENABLE BIT(0) 216#define GFX_CTRL_FMT GENMASK(9, 7) 217 218#define GFX_H_DISPLAY 0x70 219#define GFX_H_DISPLAY_DE GENMASK(28, 16) 220#define GFX_H_DISPLAY_TOTAL GENMASK(12, 0) 221 222#define GFX_V_DISPLAY 0x78 223#define GFX_V_DISPLAY_DE GENMASK(27, 16) 224#define GFX_V_DISPLAY_TOTAL GENMASK(11, 0) 225 226#define GFX_DISPLAY_ADDR 0x80 227 228/* 229 * VIDEO_MODE_DETECT_DONE: a flag raised if signal lock 230 * VIDEO_RES_CHANGE: a flag raised if res_change work on-going 231 * VIDEO_RES_DETECT: a flag raised if res. detection on-going 232 * VIDEO_STREAMING: a flag raised if user requires stream-on 233 * VIDEO_FRAME_INPRG: a flag raised if hw working on a frame 234 * VIDEO_STOPPED: a flag raised if device release 235 * VIDEO_CLOCKS_ON: a flag raised if clk is on 236 */ 237enum { 238 VIDEO_MODE_DETECT_DONE, 239 VIDEO_RES_CHANGE, 240 VIDEO_RES_DETECT, 241 VIDEO_STREAMING, 242 VIDEO_FRAME_INPRG, 243 VIDEO_STOPPED, 244 VIDEO_CLOCKS_ON, 245}; 246 247enum aspeed_video_format { 248 VIDEO_FMT_STANDARD = 0, 249 VIDEO_FMT_ASPEED, 250 VIDEO_FMT_MAX = VIDEO_FMT_ASPEED 251}; 252 253// for VE_CTRL_CAPTURE_FMT 254enum aspeed_video_capture_format { 255 VIDEO_CAP_FMT_YUV_STUDIO_SWING = 0, 256 VIDEO_CAP_FMT_YUV_FULL_SWING, 257 VIDEO_CAP_FMT_RGB, 258 VIDEO_CAP_FMT_GRAY, 259 VIDEO_CAP_FMT_MAX 260}; 261 262struct aspeed_video_addr { 263 unsigned int size; 264 dma_addr_t dma; 265 void *virt; 266}; 267 268struct aspeed_video_buffer { 269 struct vb2_v4l2_buffer vb; 270 struct list_head link; 271}; 272 273struct aspeed_video_perf { 274 ktime_t last_sample; 275 u32 totaltime; 276 u32 duration; 277 u32 duration_min; 278 u32 duration_max; 279}; 280 281#define to_aspeed_video_buffer(x) \ 282 container_of((x), struct aspeed_video_buffer, vb) 283 284/* 285 * struct aspeed_video - driver data 286 * 287 * version: holds the version of aspeed SoC 288 * res_work: holds the delayed_work for res-detection if unlock 289 * buffers: holds the list of buffer queued from user 290 * flags: holds the state of video 291 * sequence: holds the last number of frame completed 292 * max_compressed_size: holds max compressed stream's size 293 * srcs: holds the buffer information for srcs 294 * jpeg: holds the buffer information for jpeg header 295 * bcd: holds the buffer information for bcd work 296 * yuv420: a flag raised if JPEG subsampling is 420 297 * format: holds the video format 298 * hq_mode: a flag raised if HQ is enabled. Only for VIDEO_FMT_ASPEED 299 * input: holds the video input 300 * frame_rate: holds the frame_rate 301 * jpeg_quality: holds jpeq's quality (0~11) 302 * jpeg_hq_quality: holds hq's quality (1~12) only if hq_mode enabled 303 * frame_bottom: end position of video data in vertical direction 304 * frame_left: start position of video data in horizontal direction 305 * frame_right: end position of video data in horizontal direction 306 * frame_top: start position of video data in vertical direction 307 * perf: holds the statistics primary for debugfs 308 */ 309struct aspeed_video { 310 void __iomem *base; 311 struct clk *eclk; 312 struct clk *vclk; 313 314 struct device *dev; 315 struct v4l2_ctrl_handler ctrl_handler; 316 struct v4l2_device v4l2_dev; 317 struct v4l2_pix_format pix_fmt; 318 struct v4l2_bt_timings active_timings; 319 struct v4l2_bt_timings detected_timings; 320 u32 v4l2_input_status; 321 struct vb2_queue queue; 322 struct video_device vdev; 323 struct mutex video_lock; /* v4l2 and videobuf2 lock */ 324 325 struct regmap *scu; 326 struct regmap *gfx; 327 u32 version; 328 u32 jpeg_mode; 329 u32 comp_size_read; 330 331 wait_queue_head_t wait; 332 spinlock_t lock; /* buffer list lock */ 333 struct delayed_work res_work; 334 struct list_head buffers; 335 unsigned long flags; 336 unsigned int sequence; 337 338 unsigned int max_compressed_size; 339 struct aspeed_video_addr srcs[2]; 340 struct aspeed_video_addr jpeg; 341 struct aspeed_video_addr bcd; 342 343 bool yuv420; 344 enum aspeed_video_format format; 345 bool hq_mode; 346 enum aspeed_video_input input; 347 unsigned int frame_rate; 348 unsigned int jpeg_quality; 349 unsigned int jpeg_hq_quality; 350 351 unsigned int frame_bottom; 352 unsigned int frame_left; 353 unsigned int frame_right; 354 unsigned int frame_top; 355 356 struct aspeed_video_perf perf; 357}; 358 359#define to_aspeed_video(x) container_of((x), struct aspeed_video, v4l2_dev) 360 361struct aspeed_video_config { 362 u32 version; 363 u32 jpeg_mode; 364 u32 comp_size_read; 365}; 366 367static const struct aspeed_video_config ast2400_config = { 368 .version = 4, 369 .jpeg_mode = AST2400_VE_SEQ_CTRL_JPEG_MODE, 370 .comp_size_read = AST2400_VE_COMP_SIZE_READ_BACK, 371}; 372 373static const struct aspeed_video_config ast2500_config = { 374 .version = 5, 375 .jpeg_mode = AST2500_VE_SEQ_CTRL_JPEG_MODE, 376 .comp_size_read = AST2400_VE_COMP_SIZE_READ_BACK, 377}; 378 379static const struct aspeed_video_config ast2600_config = { 380 .version = 6, 381 .jpeg_mode = AST2500_VE_SEQ_CTRL_JPEG_MODE, 382 .comp_size_read = AST2600_VE_COMP_SIZE_READ_BACK, 383}; 384 385static const u32 aspeed_video_jpeg_header[ASPEED_VIDEO_JPEG_HEADER_SIZE] = { 386 0xe0ffd8ff, 0x464a1000, 0x01004649, 0x60000101, 0x00006000, 0x0f00feff, 387 0x00002d05, 0x00000000, 0x00000000, 0x00dbff00 388}; 389 390static const u32 aspeed_video_jpeg_quant[ASPEED_VIDEO_JPEG_QUANT_SIZE] = { 391 0x081100c0, 0x00000000, 0x00110103, 0x03011102, 0xc4ff0111, 0x00001f00, 392 0x01010501, 0x01010101, 0x00000000, 0x00000000, 0x04030201, 0x08070605, 393 0xff0b0a09, 0x10b500c4, 0x03010200, 0x03040203, 0x04040505, 0x7d010000, 394 0x00030201, 0x12051104, 0x06413121, 0x07615113, 0x32147122, 0x08a19181, 395 0xc1b14223, 0xf0d15215, 0x72623324, 0x160a0982, 0x1a191817, 0x28272625, 396 0x35342a29, 0x39383736, 0x4544433a, 0x49484746, 0x5554534a, 0x59585756, 397 0x6564635a, 0x69686766, 0x7574736a, 0x79787776, 0x8584837a, 0x89888786, 398 0x9493928a, 0x98979695, 0xa3a29a99, 0xa7a6a5a4, 0xb2aaa9a8, 0xb6b5b4b3, 399 0xbab9b8b7, 0xc5c4c3c2, 0xc9c8c7c6, 0xd4d3d2ca, 0xd8d7d6d5, 0xe2e1dad9, 400 0xe6e5e4e3, 0xeae9e8e7, 0xf4f3f2f1, 0xf8f7f6f5, 0xc4fffaf9, 0x00011f00, 401 0x01010103, 0x01010101, 0x00000101, 0x00000000, 0x04030201, 0x08070605, 402 0xff0b0a09, 0x11b500c4, 0x02010200, 0x04030404, 0x04040507, 0x77020100, 403 0x03020100, 0x21050411, 0x41120631, 0x71610751, 0x81322213, 0x91421408, 404 0x09c1b1a1, 0xf0523323, 0xd1726215, 0x3424160a, 0x17f125e1, 0x261a1918, 405 0x2a292827, 0x38373635, 0x44433a39, 0x48474645, 0x54534a49, 0x58575655, 406 0x64635a59, 0x68676665, 0x74736a69, 0x78777675, 0x83827a79, 0x87868584, 407 0x928a8988, 0x96959493, 0x9a999897, 0xa5a4a3a2, 0xa9a8a7a6, 0xb4b3b2aa, 408 0xb8b7b6b5, 0xc3c2bab9, 0xc7c6c5c4, 0xd2cac9c8, 0xd6d5d4d3, 0xdad9d8d7, 409 0xe5e4e3e2, 0xe9e8e7e6, 0xf4f3f2ea, 0xf8f7f6f5, 0xdafffaf9, 0x01030c00, 410 0x03110200, 0x003f0011 411}; 412 413static const u32 aspeed_video_jpeg_dct[ASPEED_VIDEO_JPEG_NUM_QUALITIES] 414 [ASPEED_VIDEO_JPEG_DCT_SIZE] = { 415 { 0x0d140043, 0x0c0f110f, 0x11101114, 0x17141516, 0x1e20321e, 416 0x3d1e1b1b, 0x32242e2b, 0x4b4c3f48, 0x44463f47, 0x61735a50, 417 0x566c5550, 0x88644644, 0x7a766c65, 0x4d808280, 0x8c978d60, 418 0x7e73967d, 0xdbff7b80, 0x1f014300, 0x272d2121, 0x3030582d, 419 0x697bb958, 0xb8b9b97b, 0xb9b8a6a6, 0xb9b9b9b9, 0xb9b9b9b9, 420 0xb9b9b9b9, 0xb9b9b9b9, 0xb9b9b9b9, 0xb9b9b9b9, 0xb9b9b9b9, 421 0xb9b9b9b9, 0xb9b9b9b9, 0xb9b9b9b9, 0xffb9b9b9 }, 422 { 0x0c110043, 0x0a0d0f0d, 0x0f0e0f11, 0x14111213, 0x1a1c2b1a, 423 0x351a1818, 0x2b1f2826, 0x4142373f, 0x3c3d373e, 0x55644e46, 424 0x4b5f4a46, 0x77573d3c, 0x6b675f58, 0x43707170, 0x7a847b54, 425 0x6e64836d, 0xdbff6c70, 0x1b014300, 0x22271d1d, 0x2a2a4c27, 426 0x5b6ba04c, 0xa0a0a06b, 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, 427 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, 428 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, 0xffa0a0a0 }, 429 { 0x090e0043, 0x090a0c0a, 0x0c0b0c0e, 0x110e0f10, 0x15172415, 430 0x2c151313, 0x241a211f, 0x36372e34, 0x31322e33, 0x4653413a, 431 0x3e4e3d3a, 0x62483231, 0x58564e49, 0x385d5e5d, 0x656d6645, 432 0x5b536c5a, 0xdbff595d, 0x16014300, 0x1c201818, 0x22223f20, 433 0x4b58853f, 0x85858558, 0x85858585, 0x85858585, 0x85858585, 434 0x85858585, 0x85858585, 0x85858585, 0x85858585, 0x85858585, 435 0x85858585, 0x85858585, 0x85858585, 0xff858585 }, 436 { 0x070b0043, 0x07080a08, 0x0a090a0b, 0x0d0b0c0c, 0x11121c11, 437 0x23110f0f, 0x1c141a19, 0x2b2b2429, 0x27282428, 0x3842332e, 438 0x313e302e, 0x4e392827, 0x46443e3a, 0x2c4a4a4a, 0x50565137, 439 0x48425647, 0xdbff474a, 0x12014300, 0x161a1313, 0x1c1c331a, 440 0x3d486c33, 0x6c6c6c48, 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, 441 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, 442 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, 0xff6c6c6c }, 443 { 0x06090043, 0x05060706, 0x07070709, 0x0a09090a, 0x0d0e160d, 444 0x1b0d0c0c, 0x16101413, 0x21221c20, 0x1e1f1c20, 0x2b332824, 445 0x26302624, 0x3d2d1f1e, 0x3735302d, 0x22393a39, 0x3f443f2b, 446 0x38334338, 0xdbff3739, 0x0d014300, 0x11130e0e, 0x15152613, 447 0x2d355026, 0x50505035, 0x50505050, 0x50505050, 0x50505050, 448 0x50505050, 0x50505050, 0x50505050, 0x50505050, 0x50505050, 449 0x50505050, 0x50505050, 0x50505050, 0xff505050 }, 450 { 0x04060043, 0x03040504, 0x05040506, 0x07060606, 0x09090f09, 451 0x12090808, 0x0f0a0d0d, 0x16161315, 0x14151315, 0x1d221b18, 452 0x19201918, 0x281e1514, 0x2423201e, 0x17262726, 0x2a2d2a1c, 453 0x25222d25, 0xdbff2526, 0x09014300, 0x0b0d0a0a, 0x0e0e1a0d, 454 0x1f25371a, 0x37373725, 0x37373737, 0x37373737, 0x37373737, 455 0x37373737, 0x37373737, 0x37373737, 0x37373737, 0x37373737, 456 0x37373737, 0x37373737, 0x37373737, 0xff373737 }, 457 { 0x02030043, 0x01020202, 0x02020203, 0x03030303, 0x04040704, 458 0x09040404, 0x07050606, 0x0b0b090a, 0x0a0a090a, 0x0e110d0c, 459 0x0c100c0c, 0x140f0a0a, 0x1211100f, 0x0b131313, 0x1516150e, 460 0x12111612, 0xdbff1213, 0x04014300, 0x05060505, 0x07070d06, 461 0x0f121b0d, 0x1b1b1b12, 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, 462 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, 463 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, 0xff1b1b1b }, 464 { 0x01020043, 0x01010101, 0x01010102, 0x02020202, 0x03030503, 465 0x06030202, 0x05030404, 0x07070607, 0x06070607, 0x090b0908, 466 0x080a0808, 0x0d0a0706, 0x0c0b0a0a, 0x070c0d0c, 0x0e0f0e09, 467 0x0c0b0f0c, 0xdbff0c0c, 0x03014300, 0x03040303, 0x04040804, 468 0x0a0c1208, 0x1212120c, 0x12121212, 0x12121212, 0x12121212, 469 0x12121212, 0x12121212, 0x12121212, 0x12121212, 0x12121212, 470 0x12121212, 0x12121212, 0x12121212, 0xff121212 }, 471 { 0x01020043, 0x01010101, 0x01010102, 0x02020202, 0x03030503, 472 0x06030202, 0x05030404, 0x07070607, 0x06070607, 0x090b0908, 473 0x080a0808, 0x0d0a0706, 0x0c0b0a0a, 0x070c0d0c, 0x0e0f0e09, 474 0x0c0b0f0c, 0xdbff0c0c, 0x02014300, 0x03030202, 0x04040703, 475 0x080a0f07, 0x0f0f0f0a, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 476 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 477 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0xff0f0f0f }, 478 { 0x01010043, 0x01010101, 0x01010101, 0x01010101, 0x02020302, 479 0x04020202, 0x03020303, 0x05050405, 0x05050405, 0x07080606, 480 0x06080606, 0x0a070505, 0x09080807, 0x05090909, 0x0a0b0a07, 481 0x09080b09, 0xdbff0909, 0x02014300, 0x02030202, 0x03030503, 482 0x07080c05, 0x0c0c0c08, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 483 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 484 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0xff0c0c0c }, 485 { 0x01010043, 0x01010101, 0x01010101, 0x01010101, 0x01010201, 486 0x03010101, 0x02010202, 0x03030303, 0x03030303, 0x04050404, 487 0x04050404, 0x06050303, 0x06050505, 0x03060606, 0x07070704, 488 0x06050706, 0xdbff0606, 0x01014300, 0x01020101, 0x02020402, 489 0x05060904, 0x09090906, 0x09090909, 0x09090909, 0x09090909, 490 0x09090909, 0x09090909, 0x09090909, 0x09090909, 0x09090909, 491 0x09090909, 0x09090909, 0x09090909, 0xff090909 }, 492 { 0x01010043, 0x01010101, 0x01010101, 0x01010101, 0x01010101, 493 0x01010101, 0x01010101, 0x01010101, 0x01010101, 0x02020202, 494 0x02020202, 0x03020101, 0x03020202, 0x01030303, 0x03030302, 495 0x03020303, 0xdbff0403, 0x01014300, 0x01010101, 0x01010201, 496 0x03040602, 0x06060604, 0x06060606, 0x06060606, 0x06060606, 497 0x06060606, 0x06060606, 0x06060606, 0x06060606, 0x06060606, 498 0x06060606, 0x06060606, 0x06060606, 0xff060606 } 499}; 500 501static const struct v4l2_dv_timings_cap aspeed_video_timings_cap = { 502 .type = V4L2_DV_BT_656_1120, 503 .bt = { 504 .min_width = MIN_WIDTH, 505 .max_width = MAX_WIDTH, 506 .min_height = MIN_HEIGHT, 507 .max_height = MAX_HEIGHT, 508 .min_pixelclock = 6574080, /* 640 x 480 x 24Hz */ 509 .max_pixelclock = 138240000, /* 1920 x 1200 x 60Hz */ 510 .standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 511 V4L2_DV_BT_STD_CVT | V4L2_DV_BT_STD_GTF, 512 .capabilities = V4L2_DV_BT_CAP_PROGRESSIVE | 513 V4L2_DV_BT_CAP_REDUCED_BLANKING | 514 V4L2_DV_BT_CAP_CUSTOM, 515 }, 516}; 517 518static const char * const format_str[] = {"Standard JPEG", 519 "Aspeed JPEG"}; 520static const char * const input_str[] = {"HOST VGA", "BMC GFX"}; 521 522static unsigned int debug; 523 524static bool aspeed_video_alloc_buf(struct aspeed_video *video, 525 struct aspeed_video_addr *addr, 526 unsigned int size); 527 528static void aspeed_video_free_buf(struct aspeed_video *video, 529 struct aspeed_video_addr *addr); 530 531static void aspeed_video_init_jpeg_table(u32 *table, bool yuv420) 532{ 533 int i; 534 unsigned int base; 535 536 for (i = 0; i < ASPEED_VIDEO_JPEG_NUM_QUALITIES; i++) { 537 base = 256 * i; /* AST HW requires this header spacing */ 538 memcpy(&table[base], aspeed_video_jpeg_header, 539 sizeof(aspeed_video_jpeg_header)); 540 541 base += ASPEED_VIDEO_JPEG_HEADER_SIZE; 542 memcpy(&table[base], aspeed_video_jpeg_dct[i], 543 sizeof(aspeed_video_jpeg_dct[i])); 544 545 base += ASPEED_VIDEO_JPEG_DCT_SIZE; 546 memcpy(&table[base], aspeed_video_jpeg_quant, 547 sizeof(aspeed_video_jpeg_quant)); 548 549 if (yuv420) 550 table[base + 2] = 0x00220103; 551 } 552} 553 554// just update jpeg dct table per 420/444 555static void aspeed_video_update_jpeg_table(u32 *table, bool yuv420) 556{ 557 int i; 558 unsigned int base; 559 560 for (i = 0; i < ASPEED_VIDEO_JPEG_NUM_QUALITIES; i++) { 561 base = 256 * i; /* AST HW requires this header spacing */ 562 base += ASPEED_VIDEO_JPEG_HEADER_SIZE + 563 ASPEED_VIDEO_JPEG_DCT_SIZE; 564 565 table[base + 2] = (yuv420) ? 0x00220103 : 0x00110103; 566 } 567} 568 569static void aspeed_video_update(struct aspeed_video *video, u32 reg, u32 clear, 570 u32 bits) 571{ 572 u32 t = readl(video->base + reg); 573 u32 before = t; 574 575 t &= ~clear; 576 t |= bits; 577 writel(t, video->base + reg); 578 v4l2_dbg(3, debug, &video->v4l2_dev, "update %03x[%08x -> %08x]\n", 579 reg, before, readl(video->base + reg)); 580} 581 582static u32 aspeed_video_read(struct aspeed_video *video, u32 reg) 583{ 584 u32 t = readl(video->base + reg); 585 586 v4l2_dbg(3, debug, &video->v4l2_dev, "read %03x[%08x]\n", reg, t); 587 return t; 588} 589 590static void aspeed_video_write(struct aspeed_video *video, u32 reg, u32 val) 591{ 592 writel(val, video->base + reg); 593 v4l2_dbg(3, debug, &video->v4l2_dev, "write %03x[%08x]\n", reg, 594 readl(video->base + reg)); 595} 596 597static void update_perf(struct aspeed_video_perf *p) 598{ 599 struct aspeed_video *v = container_of(p, struct aspeed_video, 600 perf); 601 602 p->duration = 603 ktime_to_ms(ktime_sub(ktime_get(), p->last_sample)); 604 p->totaltime += p->duration; 605 606 p->duration_max = max(p->duration, p->duration_max); 607 p->duration_min = min(p->duration, p->duration_min); 608 v4l2_dbg(2, debug, &v->v4l2_dev, "time consumed: %d ms\n", 609 p->duration); 610} 611 612static int aspeed_video_start_frame(struct aspeed_video *video) 613{ 614 dma_addr_t addr; 615 unsigned long flags; 616 struct aspeed_video_buffer *buf; 617 u32 seq_ctrl = aspeed_video_read(video, VE_SEQ_CTRL); 618 bool bcd_buf_need = (video->format != VIDEO_FMT_STANDARD); 619 620 if (video->v4l2_input_status) { 621 v4l2_dbg(1, debug, &video->v4l2_dev, "No signal; don't start frame\n"); 622 return 0; 623 } 624 625 if (!(seq_ctrl & VE_SEQ_CTRL_COMP_BUSY) || 626 !(seq_ctrl & VE_SEQ_CTRL_CAP_BUSY)) { 627 v4l2_dbg(1, debug, &video->v4l2_dev, "Engine busy; don't start frame\n"); 628 return -EBUSY; 629 } 630 631 if (bcd_buf_need && !video->bcd.size) { 632 if (!aspeed_video_alloc_buf(video, &video->bcd, 633 VE_BCD_BUFF_SIZE)) { 634 dev_err(video->dev, "Failed to allocate BCD buffer\n"); 635 dev_err(video->dev, "don't start frame\n"); 636 return -ENOMEM; 637 } 638 aspeed_video_write(video, VE_BCD_ADDR, video->bcd.dma); 639 v4l2_dbg(1, debug, &video->v4l2_dev, "bcd addr(%pad) size(%d)\n", 640 &video->bcd.dma, video->bcd.size); 641 } else if (!bcd_buf_need && video->bcd.size) { 642 aspeed_video_free_buf(video, &video->bcd); 643 } 644 645 if (video->input == VIDEO_INPUT_GFX) { 646 u32 val; 647 648 // update input buffer address as gfx's 649 regmap_read(video->gfx, GFX_DISPLAY_ADDR, &val); 650 aspeed_video_write(video, VE_TGS_0, val); 651 } 652 653 spin_lock_irqsave(&video->lock, flags); 654 buf = list_first_entry_or_null(&video->buffers, 655 struct aspeed_video_buffer, link); 656 if (!buf) { 657 spin_unlock_irqrestore(&video->lock, flags); 658 v4l2_dbg(1, debug, &video->v4l2_dev, "No buffers; don't start frame\n"); 659 return -EPROTO; 660 } 661 662 set_bit(VIDEO_FRAME_INPRG, &video->flags); 663 addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0); 664 spin_unlock_irqrestore(&video->lock, flags); 665 666 aspeed_video_write(video, VE_COMP_PROC_OFFSET, 0); 667 aspeed_video_write(video, VE_COMP_OFFSET, 0); 668 aspeed_video_write(video, VE_COMP_ADDR, addr); 669 670 aspeed_video_update(video, VE_INTERRUPT_CTRL, 0, 671 VE_INTERRUPT_COMP_COMPLETE); 672 673 video->perf.last_sample = ktime_get(); 674 675 aspeed_video_update(video, VE_SEQ_CTRL, 0, 676 VE_SEQ_CTRL_TRIG_CAPTURE | VE_SEQ_CTRL_TRIG_COMP); 677 678 return 0; 679} 680 681static void aspeed_video_enable_mode_detect(struct aspeed_video *video) 682{ 683 /* Enable mode detect interrupts */ 684 aspeed_video_update(video, VE_INTERRUPT_CTRL, 0, 685 VE_INTERRUPT_MODE_DETECT); 686 687 /* Disable mode detect in order to re-trigger */ 688 aspeed_video_update(video, VE_SEQ_CTRL, 689 VE_SEQ_CTRL_TRIG_MODE_DET, 0); 690 691 /* Trigger mode detect */ 692 aspeed_video_update(video, VE_SEQ_CTRL, 0, VE_SEQ_CTRL_TRIG_MODE_DET); 693} 694 695static void aspeed_video_off(struct aspeed_video *video) 696{ 697 if (!test_bit(VIDEO_CLOCKS_ON, &video->flags)) 698 return; 699 700 /* Disable interrupts */ 701 aspeed_video_write(video, VE_INTERRUPT_CTRL, 0); 702 aspeed_video_write(video, VE_INTERRUPT_STATUS, 0xffffffff); 703 704 /* Turn off the relevant clocks */ 705 clk_disable(video->eclk); 706 clk_disable(video->vclk); 707 708 clear_bit(VIDEO_CLOCKS_ON, &video->flags); 709} 710 711static void aspeed_video_on(struct aspeed_video *video) 712{ 713 if (test_bit(VIDEO_CLOCKS_ON, &video->flags)) 714 return; 715 716 /* Turn on the relevant clocks */ 717 clk_enable(video->vclk); 718 clk_enable(video->eclk); 719 720 set_bit(VIDEO_CLOCKS_ON, &video->flags); 721} 722 723static void aspeed_video_bufs_done(struct aspeed_video *video, 724 enum vb2_buffer_state state) 725{ 726 unsigned long flags; 727 struct aspeed_video_buffer *buf; 728 729 spin_lock_irqsave(&video->lock, flags); 730 list_for_each_entry(buf, &video->buffers, link) 731 vb2_buffer_done(&buf->vb.vb2_buf, state); 732 INIT_LIST_HEAD(&video->buffers); 733 spin_unlock_irqrestore(&video->lock, flags); 734} 735 736static void aspeed_video_irq_res_change(struct aspeed_video *video, ulong delay) 737{ 738 v4l2_dbg(1, debug, &video->v4l2_dev, "Resolution changed; resetting\n"); 739 740 set_bit(VIDEO_RES_CHANGE, &video->flags); 741 clear_bit(VIDEO_FRAME_INPRG, &video->flags); 742 743 video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL; 744 745 aspeed_video_off(video); 746 aspeed_video_bufs_done(video, VB2_BUF_STATE_ERROR); 747 748 schedule_delayed_work(&video->res_work, delay); 749} 750 751static void aspeed_video_swap_src_buf(struct aspeed_video *v) 752{ 753 if (v->format == VIDEO_FMT_STANDARD) 754 return; 755 756 /* Reset bcd buffer to have a full frame update every 8 frames. */ 757 if (IS_ALIGNED(v->sequence, 8)) 758 memset((u8 *)v->bcd.virt, 0x00, VE_BCD_BUFF_SIZE); 759 760 if (v->sequence & 0x01) { 761 aspeed_video_write(v, VE_SRC0_ADDR, v->srcs[1].dma); 762 aspeed_video_write(v, VE_SRC1_ADDR, v->srcs[0].dma); 763 } else { 764 aspeed_video_write(v, VE_SRC0_ADDR, v->srcs[0].dma); 765 aspeed_video_write(v, VE_SRC1_ADDR, v->srcs[1].dma); 766 } 767} 768 769static irqreturn_t aspeed_video_irq(int irq, void *arg) 770{ 771 struct aspeed_video *video = arg; 772 u32 sts = aspeed_video_read(video, VE_INTERRUPT_STATUS); 773 774 /* 775 * Hardware sometimes asserts interrupts that we haven't actually 776 * enabled; ignore them if so. 777 */ 778 sts &= aspeed_video_read(video, VE_INTERRUPT_CTRL); 779 780 v4l2_dbg(2, debug, &video->v4l2_dev, "irq sts=%#x %s%s%s%s\n", sts, 781 sts & VE_INTERRUPT_MODE_DETECT_WD ? ", unlock" : "", 782 sts & VE_INTERRUPT_MODE_DETECT ? ", lock" : "", 783 sts & VE_INTERRUPT_CAPTURE_COMPLETE ? ", capture-done" : "", 784 sts & VE_INTERRUPT_COMP_COMPLETE ? ", comp-done" : ""); 785 786 /* 787 * Resolution changed or signal was lost; reset the engine and 788 * re-initialize 789 */ 790 if (sts & VE_INTERRUPT_MODE_DETECT_WD) { 791 aspeed_video_irq_res_change(video, 0); 792 return IRQ_HANDLED; 793 } 794 795 if (sts & VE_INTERRUPT_MODE_DETECT) { 796 if (test_bit(VIDEO_RES_DETECT, &video->flags)) { 797 aspeed_video_update(video, VE_INTERRUPT_CTRL, 798 VE_INTERRUPT_MODE_DETECT, 0); 799 aspeed_video_write(video, VE_INTERRUPT_STATUS, 800 VE_INTERRUPT_MODE_DETECT); 801 sts &= ~VE_INTERRUPT_MODE_DETECT; 802 set_bit(VIDEO_MODE_DETECT_DONE, &video->flags); 803 wake_up_interruptible_all(&video->wait); 804 } else { 805 /* 806 * Signal acquired while NOT doing resolution 807 * detection; reset the engine and re-initialize 808 */ 809 aspeed_video_irq_res_change(video, 810 RESOLUTION_CHANGE_DELAY); 811 return IRQ_HANDLED; 812 } 813 } 814 815 if (sts & VE_INTERRUPT_COMP_COMPLETE) { 816 struct aspeed_video_buffer *buf; 817 bool empty = true; 818 u32 frame_size = aspeed_video_read(video, 819 video->comp_size_read); 820 821 update_perf(&video->perf); 822 823 spin_lock(&video->lock); 824 clear_bit(VIDEO_FRAME_INPRG, &video->flags); 825 buf = list_first_entry_or_null(&video->buffers, 826 struct aspeed_video_buffer, 827 link); 828 if (buf) { 829 vb2_set_plane_payload(&buf->vb.vb2_buf, 0, frame_size); 830 831 /* 832 * aspeed_jpeg requires continuous update. 833 * On the contrary, standard jpeg can keep last buffer 834 * to always have the latest result. 835 */ 836 if (video->format == VIDEO_FMT_STANDARD && 837 list_is_last(&buf->link, &video->buffers)) { 838 empty = false; 839 v4l2_dbg(1, debug, &video->v4l2_dev, "skip to keep last frame updated\n"); 840 } else { 841 buf->vb.vb2_buf.timestamp = ktime_get_ns(); 842 buf->vb.sequence = video->sequence++; 843 buf->vb.field = V4L2_FIELD_NONE; 844 vb2_buffer_done(&buf->vb.vb2_buf, 845 VB2_BUF_STATE_DONE); 846 list_del(&buf->link); 847 empty = list_empty(&video->buffers); 848 } 849 } 850 spin_unlock(&video->lock); 851 852 aspeed_video_update(video, VE_SEQ_CTRL, 853 VE_SEQ_CTRL_TRIG_CAPTURE | 854 VE_SEQ_CTRL_FORCE_IDLE | 855 VE_SEQ_CTRL_TRIG_COMP, 0); 856 aspeed_video_update(video, VE_INTERRUPT_CTRL, 857 VE_INTERRUPT_COMP_COMPLETE, 0); 858 aspeed_video_write(video, VE_INTERRUPT_STATUS, 859 VE_INTERRUPT_COMP_COMPLETE); 860 sts &= ~VE_INTERRUPT_COMP_COMPLETE; 861 862 aspeed_video_swap_src_buf(video); 863 864 if (test_bit(VIDEO_STREAMING, &video->flags) && !empty) 865 aspeed_video_start_frame(video); 866 } 867 868 return sts ? IRQ_NONE : IRQ_HANDLED; 869} 870 871static void aspeed_video_check_and_set_polarity(struct aspeed_video *video) 872{ 873 int i; 874 int hsync_counter = 0; 875 int vsync_counter = 0; 876 u32 sts, ctrl; 877 878 for (i = 0; i < NUM_POLARITY_CHECKS; ++i) { 879 sts = aspeed_video_read(video, VE_MODE_DETECT_STATUS); 880 if (sts & VE_MODE_DETECT_STATUS_VSYNC) 881 vsync_counter--; 882 else 883 vsync_counter++; 884 885 if (sts & VE_MODE_DETECT_STATUS_HSYNC) 886 hsync_counter--; 887 else 888 hsync_counter++; 889 } 890 891 ctrl = aspeed_video_read(video, VE_CTRL); 892 893 if (hsync_counter < 0) { 894 ctrl |= VE_CTRL_HSYNC_POL; 895 video->detected_timings.polarities &= 896 ~V4L2_DV_HSYNC_POS_POL; 897 } else { 898 ctrl &= ~VE_CTRL_HSYNC_POL; 899 video->detected_timings.polarities |= 900 V4L2_DV_HSYNC_POS_POL; 901 } 902 903 if (vsync_counter < 0) { 904 ctrl |= VE_CTRL_VSYNC_POL; 905 video->detected_timings.polarities &= 906 ~V4L2_DV_VSYNC_POS_POL; 907 } else { 908 ctrl &= ~VE_CTRL_VSYNC_POL; 909 video->detected_timings.polarities |= 910 V4L2_DV_VSYNC_POS_POL; 911 } 912 913 aspeed_video_write(video, VE_CTRL, ctrl); 914} 915 916static bool aspeed_video_alloc_buf(struct aspeed_video *video, 917 struct aspeed_video_addr *addr, 918 unsigned int size) 919{ 920 addr->virt = dma_alloc_coherent(video->dev, size, &addr->dma, 921 GFP_KERNEL); 922 if (!addr->virt) 923 return false; 924 925 addr->size = size; 926 return true; 927} 928 929static void aspeed_video_free_buf(struct aspeed_video *video, 930 struct aspeed_video_addr *addr) 931{ 932 dma_free_coherent(video->dev, addr->size, addr->virt, addr->dma); 933 addr->size = 0; 934 addr->dma = 0ULL; 935 addr->virt = NULL; 936} 937 938/* 939 * Get the minimum HW-supported compression buffer size for the frame size. 940 * Assume worst-case JPEG compression size is 1/8 raw size. This should be 941 * plenty even for maximum quality; any worse and the engine will simply return 942 * incomplete JPEGs. 943 */ 944static void aspeed_video_calc_compressed_size(struct aspeed_video *video, 945 unsigned int frame_size) 946{ 947 int i, j; 948 u32 compression_buffer_size_reg = 0; 949 unsigned int size; 950 const unsigned int num_compression_packets = 4; 951 const unsigned int compression_packet_size = 1024; 952 const unsigned int max_compressed_size = frame_size / 2; /* 4bpp / 8 */ 953 954 video->max_compressed_size = UINT_MAX; 955 956 for (i = 0; i < 6; ++i) { 957 for (j = 0; j < 8; ++j) { 958 size = (num_compression_packets << i) * 959 (compression_packet_size << j); 960 if (size < max_compressed_size) 961 continue; 962 963 if (size < video->max_compressed_size) { 964 compression_buffer_size_reg = (i << 3) | j; 965 video->max_compressed_size = size; 966 } 967 } 968 } 969 970 aspeed_video_write(video, VE_STREAM_BUF_SIZE, 971 compression_buffer_size_reg); 972 973 v4l2_dbg(1, debug, &video->v4l2_dev, "Max compressed size: %#x\n", 974 video->max_compressed_size); 975} 976 977/* 978 * Update v4l2_bt_timings per current status. 979 * frame_top/frame_bottom/frame_left/frame_right need to be ready. 980 * 981 * The following registers start counting from sync's rising edge: 982 * 1. VR090: frame edge's left and right 983 * 2. VR094: frame edge's top and bottom 984 * 3. VR09C: counting from sync's rising edge to falling edge 985 * 986 * [Vertical timing] 987 * +--+ +-------------------+ +--+ 988 * | | | v i d e o | | | 989 * +--+ +-----+ +-----+ +---+ 990 * vsync+--+ 991 * frame_top+--------+ 992 * frame_bottom+----------------------------+ 993 * 994 * +-------------------+ 995 * | v i d e o | 996 * +--+ +-----+ +-----+ +---+ 997 * | | | | 998 * +--+ +--+ 999 * vsync+-------------------------------+ 1000 * frame_top+-----+ 1001 * frame_bottom+-------------------------+ 1002 * 1003 * [Horizontal timing] 1004 * +--+ +-------------------+ +--+ 1005 * | | | v i d e o | | | 1006 * +--+ +-----+ +-----+ +---+ 1007 * hsync+--+ 1008 * frame_left+--------+ 1009 * frame_right+----------------------------+ 1010 * 1011 * +-------------------+ 1012 * | v i d e o | 1013 * +--+ +-----+ +-----+ +---+ 1014 * | | | | 1015 * +--+ +--+ 1016 * hsync+-------------------------------+ 1017 * frame_left+-----+ 1018 * frame_right+-------------------------+ 1019 * 1020 * @v: the struct of aspeed_video 1021 * @det: v4l2_bt_timings to be updated. 1022 */ 1023static void aspeed_video_get_timings(struct aspeed_video *v, 1024 struct v4l2_bt_timings *det) 1025{ 1026 u32 mds, sync, htotal, vtotal, vsync, hsync; 1027 1028 mds = aspeed_video_read(v, VE_MODE_DETECT_STATUS); 1029 sync = aspeed_video_read(v, VE_SYNC_STATUS); 1030 htotal = aspeed_video_read(v, VE_H_TOTAL_PIXELS); 1031 vtotal = FIELD_GET(VE_MODE_DETECT_V_LINES, mds); 1032 vsync = FIELD_GET(VE_SYNC_STATUS_VSYNC, sync); 1033 hsync = FIELD_GET(VE_SYNC_STATUS_HSYNC, sync); 1034 1035 /* 1036 * This is a workaround for polarity detection. 1037 * Because ast-soc counts sync from sync's rising edge, the reg value 1038 * of sync would be larger than video's active area if negative. 1039 */ 1040 if (vsync > det->height) 1041 det->polarities &= ~V4L2_DV_VSYNC_POS_POL; 1042 else 1043 det->polarities |= V4L2_DV_VSYNC_POS_POL; 1044 if (hsync > det->width) 1045 det->polarities &= ~V4L2_DV_HSYNC_POS_POL; 1046 else 1047 det->polarities |= V4L2_DV_HSYNC_POS_POL; 1048 1049 if (det->polarities & V4L2_DV_VSYNC_POS_POL) { 1050 det->vbackporch = v->frame_top - vsync; 1051 det->vfrontporch = vtotal - v->frame_bottom; 1052 det->vsync = vsync; 1053 } else { 1054 det->vbackporch = v->frame_top; 1055 det->vfrontporch = vsync - v->frame_bottom; 1056 det->vsync = vtotal - vsync; 1057 } 1058 1059 if (det->polarities & V4L2_DV_HSYNC_POS_POL) { 1060 det->hbackporch = v->frame_left - hsync; 1061 det->hfrontporch = htotal - v->frame_right; 1062 det->hsync = hsync; 1063 } else { 1064 det->hbackporch = v->frame_left; 1065 det->hfrontporch = hsync - v->frame_right; 1066 det->hsync = htotal - hsync; 1067 } 1068} 1069 1070static void aspeed_video_get_resolution_gfx(struct aspeed_video *video, 1071 struct v4l2_bt_timings *det) 1072{ 1073 u32 h_val, v_val; 1074 1075 regmap_read(video->gfx, GFX_H_DISPLAY, &h_val); 1076 regmap_read(video->gfx, GFX_V_DISPLAY, &v_val); 1077 1078 det->width = FIELD_GET(GFX_H_DISPLAY_DE, h_val) + 1; 1079 det->height = FIELD_GET(GFX_V_DISPLAY_DE, v_val) + 1; 1080 video->v4l2_input_status = 0; 1081} 1082 1083#define res_check(v) test_and_clear_bit(VIDEO_MODE_DETECT_DONE, &(v)->flags) 1084 1085static void aspeed_video_get_resolution_vga(struct aspeed_video *video, 1086 struct v4l2_bt_timings *det) 1087{ 1088 bool invalid_resolution = true; 1089 int rc; 1090 int tries = 0; 1091 u32 mds; 1092 u32 src_lr_edge; 1093 u32 src_tb_edge; 1094 1095 det->width = MIN_WIDTH; 1096 det->height = MIN_HEIGHT; 1097 video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL; 1098 memset(&video->perf, 0, sizeof(video->perf)); 1099 1100 do { 1101 if (tries) { 1102 set_current_state(TASK_INTERRUPTIBLE); 1103 if (schedule_timeout(INVALID_RESOLUTION_DELAY)) 1104 return; 1105 } 1106 1107 set_bit(VIDEO_RES_DETECT, &video->flags); 1108 aspeed_video_update(video, VE_CTRL, 1109 VE_CTRL_VSYNC_POL | VE_CTRL_HSYNC_POL, 0); 1110 aspeed_video_enable_mode_detect(video); 1111 1112 rc = wait_event_interruptible_timeout(video->wait, 1113 res_check(video), 1114 MODE_DETECT_TIMEOUT); 1115 if (!rc) { 1116 v4l2_dbg(1, debug, &video->v4l2_dev, "Timed out; first mode detect\n"); 1117 clear_bit(VIDEO_RES_DETECT, &video->flags); 1118 return; 1119 } 1120 1121 mds = aspeed_video_read(video, VE_MODE_DETECT_STATUS); 1122 // try detection again if current signal isn't stable 1123 if (!(mds & VE_MODE_DETECT_H_STABLE) || 1124 !(mds & VE_MODE_DETECT_V_STABLE) || 1125 (mds & VE_MODE_DETECT_EXTSRC_ADC)) 1126 continue; 1127 1128 aspeed_video_check_and_set_polarity(video); 1129 1130 aspeed_video_enable_mode_detect(video); 1131 1132 rc = wait_event_interruptible_timeout(video->wait, 1133 res_check(video), 1134 MODE_DETECT_TIMEOUT); 1135 clear_bit(VIDEO_RES_DETECT, &video->flags); 1136 if (!rc) { 1137 v4l2_dbg(1, debug, &video->v4l2_dev, "Timed out; second mode detect\n"); 1138 return; 1139 } 1140 1141 src_lr_edge = aspeed_video_read(video, VE_SRC_LR_EDGE_DET); 1142 src_tb_edge = aspeed_video_read(video, VE_SRC_TB_EDGE_DET); 1143 1144 video->frame_bottom = FIELD_GET(VE_SRC_TB_EDGE_DET_BOT, src_tb_edge); 1145 video->frame_top = FIELD_GET(VE_SRC_TB_EDGE_DET_TOP, src_tb_edge); 1146 1147 if (video->frame_top > video->frame_bottom) 1148 continue; 1149 1150 video->frame_right = FIELD_GET(VE_SRC_LR_EDGE_DET_RT, src_lr_edge); 1151 video->frame_left = FIELD_GET(VE_SRC_LR_EDGE_DET_LEFT, src_lr_edge); 1152 1153 if (video->frame_left > video->frame_right) 1154 continue; 1155 1156 invalid_resolution = false; 1157 } while (invalid_resolution && (tries++ < INVALID_RESOLUTION_RETRIES)); 1158 1159 if (invalid_resolution) { 1160 v4l2_dbg(1, debug, &video->v4l2_dev, "Invalid resolution detected\n"); 1161 return; 1162 } 1163 1164 det->height = (video->frame_bottom - video->frame_top) + 1; 1165 det->width = (video->frame_right - video->frame_left) + 1; 1166 video->v4l2_input_status = 0; 1167 1168 aspeed_video_get_timings(video, det); 1169 1170 /* Enable mode-detect watchdog, resolution-change watchdog */ 1171 aspeed_video_update(video, VE_INTERRUPT_CTRL, 0, 1172 VE_INTERRUPT_MODE_DETECT_WD); 1173 aspeed_video_update(video, VE_SEQ_CTRL, 0, VE_SEQ_CTRL_EN_WATCHDOG); 1174} 1175 1176static void aspeed_video_get_resolution(struct aspeed_video *video) 1177{ 1178 struct v4l2_bt_timings *det = &video->detected_timings; 1179 1180 if (video->input == VIDEO_INPUT_GFX) 1181 aspeed_video_get_resolution_gfx(video, det); 1182 else 1183 aspeed_video_get_resolution_vga(video, det); 1184 1185 v4l2_dbg(1, debug, &video->v4l2_dev, "Got resolution: %dx%d\n", 1186 det->width, det->height); 1187} 1188 1189static void aspeed_video_set_resolution(struct aspeed_video *video) 1190{ 1191 struct v4l2_bt_timings *act = &video->active_timings; 1192 unsigned int size = act->width * ALIGN(act->height, 8); 1193 1194 /* Set capture/compression frame sizes */ 1195 aspeed_video_calc_compressed_size(video, size); 1196 1197 if (!IS_ALIGNED(act->width, 64)) { 1198 /* 1199 * This is a workaround to fix a AST2500 silicon bug on A1 and 1200 * A2 revisions. Since it doesn't break capturing operation of 1201 * other revisions, use it for all revisions without checking 1202 * the revision ID. It picked new width which is a very next 1203 * 64-pixels aligned value to minimize memory bandwidth 1204 * and to get better access speed from video engine. 1205 */ 1206 u32 width = ALIGN(act->width, 64); 1207 1208 aspeed_video_write(video, VE_CAP_WINDOW, width << 16 | act->height); 1209 size = width * ALIGN(act->height, 8); 1210 } else { 1211 aspeed_video_write(video, VE_CAP_WINDOW, 1212 act->width << 16 | act->height); 1213 } 1214 aspeed_video_write(video, VE_COMP_WINDOW, 1215 act->width << 16 | act->height); 1216 aspeed_video_write(video, VE_SRC_SCANLINE_OFFSET, act->width * 4); 1217 1218 /* Don't use direct mode below 1024 x 768 (irqs don't fire) */ 1219 if (video->input == VIDEO_INPUT_VGA && size < DIRECT_FETCH_THRESHOLD) { 1220 v4l2_dbg(1, debug, &video->v4l2_dev, "Capture: Sync Mode\n"); 1221 aspeed_video_write(video, VE_TGS_0, 1222 FIELD_PREP(VE_TGS_FIRST, 1223 video->frame_left - 1) | 1224 FIELD_PREP(VE_TGS_LAST, 1225 video->frame_right)); 1226 aspeed_video_write(video, VE_TGS_1, 1227 FIELD_PREP(VE_TGS_FIRST, video->frame_top) | 1228 FIELD_PREP(VE_TGS_LAST, 1229 video->frame_bottom + 1)); 1230 aspeed_video_update(video, VE_CTRL, 1231 VE_CTRL_INT_DE | VE_CTRL_DIRECT_FETCH, 1232 VE_CTRL_INT_DE); 1233 } else { 1234 u32 ctrl, val, bpp; 1235 1236 v4l2_dbg(1, debug, &video->v4l2_dev, "Capture: Direct Mode\n"); 1237 ctrl = VE_CTRL_DIRECT_FETCH; 1238 if (video->input == VIDEO_INPUT_GFX) { 1239 regmap_read(video->gfx, GFX_CTRL, &val); 1240 bpp = FIELD_GET(GFX_CTRL_FMT, val) ? 32 : 16; 1241 if (bpp == 16) 1242 ctrl |= VE_CTRL_INT_DE; 1243 aspeed_video_write(video, VE_TGS_1, act->width * (bpp >> 3)); 1244 } 1245 aspeed_video_update(video, VE_CTRL, 1246 VE_CTRL_INT_DE | VE_CTRL_DIRECT_FETCH, 1247 ctrl); 1248 } 1249 1250 size *= 4; 1251 1252 if (size != video->srcs[0].size) { 1253 if (video->srcs[0].size) 1254 aspeed_video_free_buf(video, &video->srcs[0]); 1255 if (video->srcs[1].size) 1256 aspeed_video_free_buf(video, &video->srcs[1]); 1257 1258 if (!aspeed_video_alloc_buf(video, &video->srcs[0], size)) 1259 goto err_mem; 1260 if (!aspeed_video_alloc_buf(video, &video->srcs[1], size)) 1261 goto err_mem; 1262 1263 v4l2_dbg(1, debug, &video->v4l2_dev, "src buf0 addr(%pad) size(%d)\n", 1264 &video->srcs[0].dma, video->srcs[0].size); 1265 v4l2_dbg(1, debug, &video->v4l2_dev, "src buf1 addr(%pad) size(%d)\n", 1266 &video->srcs[1].dma, video->srcs[1].size); 1267 aspeed_video_write(video, VE_SRC0_ADDR, video->srcs[0].dma); 1268 aspeed_video_write(video, VE_SRC1_ADDR, video->srcs[1].dma); 1269 } 1270 1271 return; 1272 1273err_mem: 1274 dev_err(video->dev, "Failed to allocate source buffers\n"); 1275 1276 if (video->srcs[0].size) 1277 aspeed_video_free_buf(video, &video->srcs[0]); 1278} 1279 1280/* 1281 * Update relative parameters when timing changed. 1282 * 1283 * @video: the struct of aspeed_video 1284 * @timings: the new timings 1285 */ 1286static void aspeed_video_update_timings(struct aspeed_video *video, struct v4l2_bt_timings *timings) 1287{ 1288 video->active_timings = *timings; 1289 aspeed_video_set_resolution(video); 1290 1291 video->pix_fmt.width = timings->width; 1292 video->pix_fmt.height = timings->height; 1293 video->pix_fmt.sizeimage = video->max_compressed_size; 1294} 1295 1296static void aspeed_video_update_regs(struct aspeed_video *video) 1297{ 1298 u8 jpeg_hq_quality = clamp((int)video->jpeg_hq_quality - 1, 0, 1299 ASPEED_VIDEO_JPEG_NUM_QUALITIES - 1); 1300 u32 comp_ctrl = FIELD_PREP(VE_COMP_CTRL_DCT_LUM, video->jpeg_quality) | 1301 FIELD_PREP(VE_COMP_CTRL_DCT_CHR, video->jpeg_quality | 0x10) | 1302 FIELD_PREP(VE_COMP_CTRL_EN_HQ, video->hq_mode) | 1303 FIELD_PREP(VE_COMP_CTRL_HQ_DCT_LUM, jpeg_hq_quality) | 1304 FIELD_PREP(VE_COMP_CTRL_HQ_DCT_CHR, jpeg_hq_quality | 0x10); 1305 u32 ctrl = 0; 1306 u32 seq_ctrl = 0; 1307 1308 v4l2_dbg(1, debug, &video->v4l2_dev, "input(%s)\n", 1309 input_str[video->input]); 1310 v4l2_dbg(1, debug, &video->v4l2_dev, "framerate(%d)\n", 1311 video->frame_rate); 1312 v4l2_dbg(1, debug, &video->v4l2_dev, "jpeg format(%s) subsample(%s)\n", 1313 format_str[video->format], 1314 video->yuv420 ? "420" : "444"); 1315 v4l2_dbg(1, debug, &video->v4l2_dev, "compression quality(%d)\n", 1316 video->jpeg_quality); 1317 v4l2_dbg(1, debug, &video->v4l2_dev, "hq_mode(%s) hq_quality(%d)\n", 1318 video->hq_mode ? "on" : "off", video->jpeg_hq_quality); 1319 1320 if (video->format == VIDEO_FMT_ASPEED) 1321 aspeed_video_update(video, VE_BCD_CTRL, 0, VE_BCD_CTRL_EN_BCD); 1322 else 1323 aspeed_video_update(video, VE_BCD_CTRL, VE_BCD_CTRL_EN_BCD, 0); 1324 1325 if (video->input == VIDEO_INPUT_VGA) 1326 ctrl |= VE_CTRL_AUTO_OR_CURSOR; 1327 1328 if (video->frame_rate) 1329 ctrl |= FIELD_PREP(VE_CTRL_FRC, video->frame_rate); 1330 1331 if (video->format == VIDEO_FMT_STANDARD) { 1332 comp_ctrl &= ~FIELD_PREP(VE_COMP_CTRL_EN_HQ, video->hq_mode); 1333 seq_ctrl |= video->jpeg_mode; 1334 } 1335 1336 if (video->yuv420) 1337 seq_ctrl |= VE_SEQ_CTRL_YUV420; 1338 1339 if (video->jpeg.virt) 1340 aspeed_video_update_jpeg_table(video->jpeg.virt, video->yuv420); 1341 1342 /* Set control registers */ 1343 aspeed_video_update(video, VE_SEQ_CTRL, 1344 video->jpeg_mode | VE_SEQ_CTRL_YUV420, 1345 seq_ctrl); 1346 aspeed_video_update(video, VE_CTRL, 1347 VE_CTRL_FRC | VE_CTRL_AUTO_OR_CURSOR | 1348 VE_CTRL_SOURCE, ctrl); 1349 aspeed_video_update(video, VE_COMP_CTRL, 1350 VE_COMP_CTRL_DCT_LUM | VE_COMP_CTRL_DCT_CHR | 1351 VE_COMP_CTRL_EN_HQ | VE_COMP_CTRL_HQ_DCT_LUM | 1352 VE_COMP_CTRL_HQ_DCT_CHR | VE_COMP_CTRL_VQ_4COLOR | 1353 VE_COMP_CTRL_VQ_DCT_ONLY, 1354 comp_ctrl); 1355} 1356 1357static void aspeed_video_init_regs(struct aspeed_video *video) 1358{ 1359 u32 ctrl = VE_CTRL_AUTO_OR_CURSOR | 1360 FIELD_PREP(VE_CTRL_CAPTURE_FMT, VIDEO_CAP_FMT_YUV_FULL_SWING); 1361 1362 /* Unlock VE registers */ 1363 aspeed_video_write(video, VE_PROTECTION_KEY, VE_PROTECTION_KEY_UNLOCK); 1364 1365 /* Disable interrupts */ 1366 aspeed_video_write(video, VE_INTERRUPT_CTRL, 0); 1367 aspeed_video_write(video, VE_INTERRUPT_STATUS, 0xffffffff); 1368 1369 /* Clear the offset */ 1370 aspeed_video_write(video, VE_COMP_PROC_OFFSET, 0); 1371 aspeed_video_write(video, VE_COMP_OFFSET, 0); 1372 1373 aspeed_video_write(video, VE_JPEG_ADDR, video->jpeg.dma); 1374 1375 /* Set control registers */ 1376 aspeed_video_write(video, VE_SEQ_CTRL, VE_SEQ_CTRL_AUTO_COMP); 1377 aspeed_video_write(video, VE_CTRL, ctrl); 1378 aspeed_video_write(video, VE_COMP_CTRL, VE_COMP_CTRL_RSVD); 1379 1380 /* Don't downscale */ 1381 aspeed_video_write(video, VE_SCALING_FACTOR, 0x10001000); 1382 aspeed_video_write(video, VE_SCALING_FILTER0, 0x00200000); 1383 aspeed_video_write(video, VE_SCALING_FILTER1, 0x00200000); 1384 aspeed_video_write(video, VE_SCALING_FILTER2, 0x00200000); 1385 aspeed_video_write(video, VE_SCALING_FILTER3, 0x00200000); 1386 1387 /* Set mode detection defaults */ 1388 aspeed_video_write(video, VE_MODE_DETECT, 1389 FIELD_PREP(VE_MODE_DT_HOR_TOLER, 2) | 1390 FIELD_PREP(VE_MODE_DT_VER_TOLER, 2) | 1391 FIELD_PREP(VE_MODE_DT_HOR_STABLE, 6) | 1392 FIELD_PREP(VE_MODE_DT_VER_STABLE, 6) | 1393 FIELD_PREP(VE_MODE_DT_EDG_THROD, 0x65)); 1394 1395 aspeed_video_write(video, VE_BCD_CTRL, 0); 1396} 1397 1398static void aspeed_video_start(struct aspeed_video *video) 1399{ 1400 aspeed_video_on(video); 1401 1402 aspeed_video_init_regs(video); 1403 1404 /* Resolution set to 640x480 if no signal found */ 1405 aspeed_video_get_resolution(video); 1406 1407 /* Set timings since the device is being opened for the first time */ 1408 aspeed_video_update_timings(video, &video->detected_timings); 1409} 1410 1411static void aspeed_video_stop(struct aspeed_video *video) 1412{ 1413 set_bit(VIDEO_STOPPED, &video->flags); 1414 cancel_delayed_work_sync(&video->res_work); 1415 1416 aspeed_video_off(video); 1417 1418 if (video->srcs[0].size) 1419 aspeed_video_free_buf(video, &video->srcs[0]); 1420 1421 if (video->srcs[1].size) 1422 aspeed_video_free_buf(video, &video->srcs[1]); 1423 1424 if (video->bcd.size) 1425 aspeed_video_free_buf(video, &video->bcd); 1426 1427 video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL; 1428 video->flags = 0; 1429} 1430 1431static int aspeed_video_querycap(struct file *file, void *fh, 1432 struct v4l2_capability *cap) 1433{ 1434 strscpy(cap->driver, DEVICE_NAME, sizeof(cap->driver)); 1435 strscpy(cap->card, "Aspeed Video Engine", sizeof(cap->card)); 1436 snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", 1437 DEVICE_NAME); 1438 1439 return 0; 1440} 1441 1442static int aspeed_video_enum_format(struct file *file, void *fh, 1443 struct v4l2_fmtdesc *f) 1444{ 1445 struct aspeed_video *video = video_drvdata(file); 1446 1447 if (f->index) 1448 return -EINVAL; 1449 1450 f->pixelformat = video->pix_fmt.pixelformat; 1451 1452 return 0; 1453} 1454 1455static int aspeed_video_get_format(struct file *file, void *fh, 1456 struct v4l2_format *f) 1457{ 1458 struct aspeed_video *video = video_drvdata(file); 1459 1460 f->fmt.pix = video->pix_fmt; 1461 1462 return 0; 1463} 1464 1465static int aspeed_video_set_format(struct file *file, void *fh, 1466 struct v4l2_format *f) 1467{ 1468 struct aspeed_video *video = video_drvdata(file); 1469 1470 if (vb2_is_busy(&video->queue)) 1471 return -EBUSY; 1472 1473 switch (f->fmt.pix.pixelformat) { 1474 case V4L2_PIX_FMT_JPEG: 1475 video->format = VIDEO_FMT_STANDARD; 1476 break; 1477 case V4L2_PIX_FMT_AJPG: 1478 video->format = VIDEO_FMT_ASPEED; 1479 break; 1480 default: 1481 return -EINVAL; 1482 } 1483 video->pix_fmt.pixelformat = f->fmt.pix.pixelformat; 1484 1485 return 0; 1486} 1487 1488static int aspeed_video_enum_input(struct file *file, void *fh, 1489 struct v4l2_input *inp) 1490{ 1491 struct aspeed_video *video = video_drvdata(file); 1492 1493 if (inp->index >= VIDEO_INPUT_MAX) 1494 return -EINVAL; 1495 1496 sprintf(inp->name, "%s capture", input_str[inp->index]); 1497 inp->type = V4L2_INPUT_TYPE_CAMERA; 1498 inp->capabilities = V4L2_IN_CAP_DV_TIMINGS; 1499 inp->status = video->v4l2_input_status; 1500 1501 return 0; 1502} 1503 1504static int aspeed_video_get_input(struct file *file, void *fh, unsigned int *i) 1505{ 1506 struct aspeed_video *video = video_drvdata(file); 1507 1508 *i = video->input; 1509 1510 return 0; 1511} 1512 1513static int aspeed_video_set_input(struct file *file, void *fh, unsigned int i) 1514{ 1515 struct aspeed_video *video = video_drvdata(file); 1516 1517 if (i >= VIDEO_INPUT_MAX) 1518 return -EINVAL; 1519 1520 if (i == video->input) 1521 return 0; 1522 1523 if (vb2_is_busy(&video->queue)) 1524 return -EBUSY; 1525 1526 if (IS_ERR(video->scu)) { 1527 v4l2_dbg(1, debug, &video->v4l2_dev, 1528 "%s: scu isn't ready for input-control\n", __func__); 1529 return -EINVAL; 1530 } 1531 1532 if (IS_ERR(video->gfx) && i == VIDEO_INPUT_GFX) { 1533 v4l2_dbg(1, debug, &video->v4l2_dev, 1534 "%s: gfx isn't ready for GFX input\n", __func__); 1535 return -EINVAL; 1536 } 1537 1538 video->input = i; 1539 1540 if (video->version == 6) { 1541 /* modify dpll source per current input */ 1542 if (video->input == VIDEO_INPUT_VGA) 1543 regmap_update_bits(video->scu, SCU_MISC_CTRL, 1544 SCU_DPLL_SOURCE, 0); 1545 else 1546 regmap_update_bits(video->scu, SCU_MISC_CTRL, 1547 SCU_DPLL_SOURCE, SCU_DPLL_SOURCE); 1548 } 1549 1550 aspeed_video_update_regs(video); 1551 1552 /* update signal status */ 1553 aspeed_video_get_resolution(video); 1554 if (!video->v4l2_input_status) 1555 aspeed_video_update_timings(video, &video->detected_timings); 1556 1557 return 0; 1558} 1559 1560static int aspeed_video_get_parm(struct file *file, void *fh, 1561 struct v4l2_streamparm *a) 1562{ 1563 struct aspeed_video *video = video_drvdata(file); 1564 1565 a->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; 1566 a->parm.capture.readbuffers = ASPEED_VIDEO_V4L2_MIN_BUF_REQ; 1567 a->parm.capture.timeperframe.numerator = 1; 1568 if (!video->frame_rate) 1569 a->parm.capture.timeperframe.denominator = MAX_FRAME_RATE; 1570 else 1571 a->parm.capture.timeperframe.denominator = video->frame_rate; 1572 1573 return 0; 1574} 1575 1576static int aspeed_video_set_parm(struct file *file, void *fh, 1577 struct v4l2_streamparm *a) 1578{ 1579 unsigned int frame_rate = 0; 1580 struct aspeed_video *video = video_drvdata(file); 1581 1582 a->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; 1583 a->parm.capture.readbuffers = ASPEED_VIDEO_V4L2_MIN_BUF_REQ; 1584 1585 if (a->parm.capture.timeperframe.numerator) 1586 frame_rate = a->parm.capture.timeperframe.denominator / 1587 a->parm.capture.timeperframe.numerator; 1588 1589 if (!frame_rate || frame_rate > MAX_FRAME_RATE) { 1590 frame_rate = 0; 1591 a->parm.capture.timeperframe.denominator = MAX_FRAME_RATE; 1592 a->parm.capture.timeperframe.numerator = 1; 1593 } 1594 1595 if (video->frame_rate != frame_rate) { 1596 video->frame_rate = frame_rate; 1597 aspeed_video_update(video, VE_CTRL, VE_CTRL_FRC, 1598 FIELD_PREP(VE_CTRL_FRC, frame_rate)); 1599 } 1600 1601 return 0; 1602} 1603 1604static int aspeed_video_enum_framesizes(struct file *file, void *fh, 1605 struct v4l2_frmsizeenum *fsize) 1606{ 1607 struct aspeed_video *video = video_drvdata(file); 1608 1609 if (fsize->index) 1610 return -EINVAL; 1611 1612 if (fsize->pixel_format != V4L2_PIX_FMT_JPEG) 1613 return -EINVAL; 1614 1615 fsize->discrete.width = video->pix_fmt.width; 1616 fsize->discrete.height = video->pix_fmt.height; 1617 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; 1618 1619 return 0; 1620} 1621 1622static int aspeed_video_enum_frameintervals(struct file *file, void *fh, 1623 struct v4l2_frmivalenum *fival) 1624{ 1625 struct aspeed_video *video = video_drvdata(file); 1626 1627 if (fival->index) 1628 return -EINVAL; 1629 1630 if (fival->width != video->detected_timings.width || 1631 fival->height != video->detected_timings.height) 1632 return -EINVAL; 1633 1634 if (fival->pixel_format != V4L2_PIX_FMT_JPEG) 1635 return -EINVAL; 1636 1637 fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS; 1638 1639 fival->stepwise.min.denominator = MAX_FRAME_RATE; 1640 fival->stepwise.min.numerator = 1; 1641 fival->stepwise.max.denominator = 1; 1642 fival->stepwise.max.numerator = 1; 1643 fival->stepwise.step = fival->stepwise.max; 1644 1645 return 0; 1646} 1647 1648static int aspeed_video_set_dv_timings(struct file *file, void *fh, 1649 struct v4l2_dv_timings *timings) 1650{ 1651 struct aspeed_video *video = video_drvdata(file); 1652 1653 if (timings->bt.width == video->active_timings.width && 1654 timings->bt.height == video->active_timings.height) 1655 return 0; 1656 1657 if (vb2_is_busy(&video->queue)) 1658 return -EBUSY; 1659 1660 aspeed_video_update_timings(video, &timings->bt); 1661 1662 timings->type = V4L2_DV_BT_656_1120; 1663 1664 v4l2_dbg(1, debug, &video->v4l2_dev, "set new timings(%dx%d)\n", 1665 timings->bt.width, timings->bt.height); 1666 1667 return 0; 1668} 1669 1670static int aspeed_video_get_dv_timings(struct file *file, void *fh, 1671 struct v4l2_dv_timings *timings) 1672{ 1673 struct aspeed_video *video = video_drvdata(file); 1674 1675 timings->type = V4L2_DV_BT_656_1120; 1676 timings->bt = video->active_timings; 1677 1678 return 0; 1679} 1680 1681static int aspeed_video_query_dv_timings(struct file *file, void *fh, 1682 struct v4l2_dv_timings *timings) 1683{ 1684 int rc; 1685 struct aspeed_video *video = video_drvdata(file); 1686 1687 /* 1688 * This blocks only if the driver is currently in the process of 1689 * detecting a new resolution; in the event of no signal or timeout 1690 * this function is woken up. 1691 */ 1692 if (file->f_flags & O_NONBLOCK) { 1693 if (test_bit(VIDEO_RES_CHANGE, &video->flags)) 1694 return -EAGAIN; 1695 } else { 1696 rc = wait_event_interruptible(video->wait, 1697 !test_bit(VIDEO_RES_CHANGE, 1698 &video->flags)); 1699 if (rc) 1700 return -EINTR; 1701 } 1702 1703 timings->type = V4L2_DV_BT_656_1120; 1704 timings->bt = video->detected_timings; 1705 1706 return video->v4l2_input_status ? -ENOLINK : 0; 1707} 1708 1709static int aspeed_video_enum_dv_timings(struct file *file, void *fh, 1710 struct v4l2_enum_dv_timings *timings) 1711{ 1712 return v4l2_enum_dv_timings_cap(timings, &aspeed_video_timings_cap, 1713 NULL, NULL); 1714} 1715 1716static int aspeed_video_dv_timings_cap(struct file *file, void *fh, 1717 struct v4l2_dv_timings_cap *cap) 1718{ 1719 *cap = aspeed_video_timings_cap; 1720 1721 return 0; 1722} 1723 1724static int aspeed_video_sub_event(struct v4l2_fh *fh, 1725 const struct v4l2_event_subscription *sub) 1726{ 1727 switch (sub->type) { 1728 case V4L2_EVENT_SOURCE_CHANGE: 1729 return v4l2_src_change_event_subscribe(fh, sub); 1730 } 1731 1732 return v4l2_ctrl_subscribe_event(fh, sub); 1733} 1734 1735static const struct v4l2_ioctl_ops aspeed_video_ioctl_ops = { 1736 .vidioc_querycap = aspeed_video_querycap, 1737 1738 .vidioc_enum_fmt_vid_cap = aspeed_video_enum_format, 1739 .vidioc_g_fmt_vid_cap = aspeed_video_get_format, 1740 .vidioc_s_fmt_vid_cap = aspeed_video_set_format, 1741 .vidioc_try_fmt_vid_cap = aspeed_video_get_format, 1742 1743 .vidioc_reqbufs = vb2_ioctl_reqbufs, 1744 .vidioc_querybuf = vb2_ioctl_querybuf, 1745 .vidioc_qbuf = vb2_ioctl_qbuf, 1746 .vidioc_expbuf = vb2_ioctl_expbuf, 1747 .vidioc_dqbuf = vb2_ioctl_dqbuf, 1748 .vidioc_create_bufs = vb2_ioctl_create_bufs, 1749 .vidioc_prepare_buf = vb2_ioctl_prepare_buf, 1750 .vidioc_streamon = vb2_ioctl_streamon, 1751 .vidioc_streamoff = vb2_ioctl_streamoff, 1752 1753 .vidioc_enum_input = aspeed_video_enum_input, 1754 .vidioc_g_input = aspeed_video_get_input, 1755 .vidioc_s_input = aspeed_video_set_input, 1756 1757 .vidioc_g_parm = aspeed_video_get_parm, 1758 .vidioc_s_parm = aspeed_video_set_parm, 1759 .vidioc_enum_framesizes = aspeed_video_enum_framesizes, 1760 .vidioc_enum_frameintervals = aspeed_video_enum_frameintervals, 1761 1762 .vidioc_s_dv_timings = aspeed_video_set_dv_timings, 1763 .vidioc_g_dv_timings = aspeed_video_get_dv_timings, 1764 .vidioc_query_dv_timings = aspeed_video_query_dv_timings, 1765 .vidioc_enum_dv_timings = aspeed_video_enum_dv_timings, 1766 .vidioc_dv_timings_cap = aspeed_video_dv_timings_cap, 1767 1768 .vidioc_subscribe_event = aspeed_video_sub_event, 1769 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1770}; 1771 1772static int aspeed_video_set_ctrl(struct v4l2_ctrl *ctrl) 1773{ 1774 struct aspeed_video *video = container_of(ctrl->handler, 1775 struct aspeed_video, 1776 ctrl_handler); 1777 1778 switch (ctrl->id) { 1779 case V4L2_CID_JPEG_COMPRESSION_QUALITY: 1780 video->jpeg_quality = ctrl->val; 1781 if (test_bit(VIDEO_STREAMING, &video->flags)) 1782 aspeed_video_update_regs(video); 1783 break; 1784 case V4L2_CID_JPEG_CHROMA_SUBSAMPLING: 1785 video->yuv420 = (ctrl->val == V4L2_JPEG_CHROMA_SUBSAMPLING_420); 1786 if (test_bit(VIDEO_STREAMING, &video->flags)) 1787 aspeed_video_update_regs(video); 1788 break; 1789 case V4L2_CID_ASPEED_HQ_MODE: 1790 video->hq_mode = ctrl->val; 1791 if (test_bit(VIDEO_STREAMING, &video->flags)) 1792 aspeed_video_update_regs(video); 1793 break; 1794 case V4L2_CID_ASPEED_HQ_JPEG_QUALITY: 1795 video->jpeg_hq_quality = ctrl->val; 1796 if (test_bit(VIDEO_STREAMING, &video->flags)) 1797 aspeed_video_update_regs(video); 1798 break; 1799 default: 1800 return -EINVAL; 1801 } 1802 1803 return 0; 1804} 1805 1806static const struct v4l2_ctrl_ops aspeed_video_ctrl_ops = { 1807 .s_ctrl = aspeed_video_set_ctrl, 1808}; 1809 1810static const struct v4l2_ctrl_config aspeed_ctrl_HQ_mode = { 1811 .ops = &aspeed_video_ctrl_ops, 1812 .id = V4L2_CID_ASPEED_HQ_MODE, 1813 .name = "Aspeed HQ Mode", 1814 .type = V4L2_CTRL_TYPE_BOOLEAN, 1815 .min = false, 1816 .max = true, 1817 .step = 1, 1818 .def = false, 1819}; 1820 1821static const struct v4l2_ctrl_config aspeed_ctrl_HQ_jpeg_quality = { 1822 .ops = &aspeed_video_ctrl_ops, 1823 .id = V4L2_CID_ASPEED_HQ_JPEG_QUALITY, 1824 .name = "Aspeed HQ Quality", 1825 .type = V4L2_CTRL_TYPE_INTEGER, 1826 .min = 1, 1827 .max = ASPEED_VIDEO_JPEG_NUM_QUALITIES, 1828 .step = 1, 1829 .def = 1, 1830}; 1831 1832static void aspeed_video_resolution_work(struct work_struct *work) 1833{ 1834 struct delayed_work *dwork = to_delayed_work(work); 1835 struct aspeed_video *video = container_of(dwork, struct aspeed_video, 1836 res_work); 1837 1838 aspeed_video_on(video); 1839 1840 /* Exit early in case no clients remain */ 1841 if (test_bit(VIDEO_STOPPED, &video->flags)) 1842 goto done; 1843 1844 aspeed_video_init_regs(video); 1845 1846 aspeed_video_update_regs(video); 1847 1848 aspeed_video_get_resolution(video); 1849 1850 if (video->detected_timings.width != video->active_timings.width || 1851 video->detected_timings.height != video->active_timings.height) { 1852 static const struct v4l2_event ev = { 1853 .type = V4L2_EVENT_SOURCE_CHANGE, 1854 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 1855 }; 1856 1857 v4l2_dbg(1, debug, &video->v4l2_dev, "fire source change event\n"); 1858 v4l2_event_queue(&video->vdev, &ev); 1859 } else if (test_bit(VIDEO_STREAMING, &video->flags)) { 1860 /* No resolution change so just restart streaming */ 1861 aspeed_video_start_frame(video); 1862 } 1863 1864done: 1865 clear_bit(VIDEO_RES_CHANGE, &video->flags); 1866 wake_up_interruptible_all(&video->wait); 1867} 1868 1869static int aspeed_video_open(struct file *file) 1870{ 1871 int rc; 1872 struct aspeed_video *video = video_drvdata(file); 1873 1874 mutex_lock(&video->video_lock); 1875 1876 rc = v4l2_fh_open(file); 1877 if (rc) { 1878 mutex_unlock(&video->video_lock); 1879 return rc; 1880 } 1881 1882 if (v4l2_fh_is_singular_file(file)) 1883 aspeed_video_start(video); 1884 1885 mutex_unlock(&video->video_lock); 1886 1887 return 0; 1888} 1889 1890static int aspeed_video_release(struct file *file) 1891{ 1892 int rc; 1893 struct aspeed_video *video = video_drvdata(file); 1894 1895 mutex_lock(&video->video_lock); 1896 1897 if (v4l2_fh_is_singular_file(file)) 1898 aspeed_video_stop(video); 1899 1900 rc = _vb2_fop_release(file, NULL); 1901 1902 mutex_unlock(&video->video_lock); 1903 1904 return rc; 1905} 1906 1907static const struct v4l2_file_operations aspeed_video_v4l2_fops = { 1908 .owner = THIS_MODULE, 1909 .read = vb2_fop_read, 1910 .poll = vb2_fop_poll, 1911 .unlocked_ioctl = video_ioctl2, 1912 .mmap = vb2_fop_mmap, 1913 .open = aspeed_video_open, 1914 .release = aspeed_video_release, 1915}; 1916 1917static int aspeed_video_queue_setup(struct vb2_queue *q, 1918 unsigned int *num_buffers, 1919 unsigned int *num_planes, 1920 unsigned int sizes[], 1921 struct device *alloc_devs[]) 1922{ 1923 struct aspeed_video *video = vb2_get_drv_priv(q); 1924 1925 if (*num_planes) { 1926 if (sizes[0] < video->max_compressed_size) 1927 return -EINVAL; 1928 1929 return 0; 1930 } 1931 1932 *num_planes = 1; 1933 sizes[0] = video->max_compressed_size; 1934 1935 return 0; 1936} 1937 1938static int aspeed_video_buf_prepare(struct vb2_buffer *vb) 1939{ 1940 struct aspeed_video *video = vb2_get_drv_priv(vb->vb2_queue); 1941 1942 if (vb2_plane_size(vb, 0) < video->max_compressed_size) 1943 return -EINVAL; 1944 1945 return 0; 1946} 1947 1948static int aspeed_video_start_streaming(struct vb2_queue *q, 1949 unsigned int count) 1950{ 1951 int rc; 1952 struct aspeed_video *video = vb2_get_drv_priv(q); 1953 1954 video->sequence = 0; 1955 video->perf.duration_max = 0; 1956 video->perf.duration_min = 0xffffffff; 1957 1958 aspeed_video_update_regs(video); 1959 1960 rc = aspeed_video_start_frame(video); 1961 if (rc) { 1962 aspeed_video_bufs_done(video, VB2_BUF_STATE_QUEUED); 1963 return rc; 1964 } 1965 1966 set_bit(VIDEO_STREAMING, &video->flags); 1967 return 0; 1968} 1969 1970static void aspeed_video_stop_streaming(struct vb2_queue *q) 1971{ 1972 int rc; 1973 struct aspeed_video *video = vb2_get_drv_priv(q); 1974 1975 clear_bit(VIDEO_STREAMING, &video->flags); 1976 1977 rc = wait_event_timeout(video->wait, 1978 !test_bit(VIDEO_FRAME_INPRG, &video->flags), 1979 STOP_TIMEOUT); 1980 if (!rc) { 1981 v4l2_dbg(1, debug, &video->v4l2_dev, "Timed out when stopping streaming\n"); 1982 1983 /* 1984 * Need to force stop any DMA and try and get HW into a good 1985 * state for future calls to start streaming again. 1986 */ 1987 aspeed_video_off(video); 1988 aspeed_video_on(video); 1989 1990 aspeed_video_init_regs(video); 1991 1992 aspeed_video_get_resolution(video); 1993 } 1994 1995 aspeed_video_bufs_done(video, VB2_BUF_STATE_ERROR); 1996} 1997 1998static void aspeed_video_buf_queue(struct vb2_buffer *vb) 1999{ 2000 bool empty; 2001 struct aspeed_video *video = vb2_get_drv_priv(vb->vb2_queue); 2002 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 2003 struct aspeed_video_buffer *avb = to_aspeed_video_buffer(vbuf); 2004 unsigned long flags; 2005 2006 spin_lock_irqsave(&video->lock, flags); 2007 empty = list_empty(&video->buffers); 2008 list_add_tail(&avb->link, &video->buffers); 2009 spin_unlock_irqrestore(&video->lock, flags); 2010 2011 if (test_bit(VIDEO_STREAMING, &video->flags) && 2012 !test_bit(VIDEO_FRAME_INPRG, &video->flags) && empty) 2013 aspeed_video_start_frame(video); 2014} 2015 2016static const struct vb2_ops aspeed_video_vb2_ops = { 2017 .queue_setup = aspeed_video_queue_setup, 2018 .buf_prepare = aspeed_video_buf_prepare, 2019 .start_streaming = aspeed_video_start_streaming, 2020 .stop_streaming = aspeed_video_stop_streaming, 2021 .buf_queue = aspeed_video_buf_queue, 2022}; 2023 2024#ifdef CONFIG_DEBUG_FS 2025static int aspeed_video_debugfs_show(struct seq_file *s, void *data) 2026{ 2027 struct aspeed_video *v = s->private; 2028 u32 val08; 2029 2030 seq_puts(s, "\n"); 2031 2032 seq_puts(s, "Capture:\n"); 2033 val08 = aspeed_video_read(v, VE_CTRL); 2034 if (FIELD_GET(VE_CTRL_DIRECT_FETCH, val08)) { 2035 seq_printf(s, " %-20s:\tDirect fetch\n", "Mode"); 2036 seq_printf(s, " %-20s:\t%s\n", "Input", input_str[v->input]); 2037 seq_printf(s, " %-20s:\t%s\n", "VGA bpp mode", 2038 FIELD_GET(VE_CTRL_INT_DE, val08) ? "16" : "32"); 2039 } else { 2040 seq_printf(s, " %-20s:\tSync\n", "Mode"); 2041 seq_printf(s, " %-20s:\t%s\n", "Video source", 2042 FIELD_GET(VE_CTRL_SOURCE, val08) ? 2043 "external" : "internal"); 2044 seq_printf(s, " %-20s:\t%s\n", "DE source", 2045 FIELD_GET(VE_CTRL_INT_DE, val08) ? 2046 "internal" : "external"); 2047 seq_printf(s, " %-20s:\t%s\n", "Cursor overlay", 2048 FIELD_GET(VE_CTRL_AUTO_OR_CURSOR, val08) ? 2049 "Without" : "With"); 2050 } 2051 2052 seq_printf(s, " %-20s:\t%s\n", "Signal", 2053 v->v4l2_input_status ? "Unlock" : "Lock"); 2054 seq_printf(s, " %-20s:\t%d\n", "Width", v->pix_fmt.width); 2055 seq_printf(s, " %-20s:\t%d\n", "Height", v->pix_fmt.height); 2056 seq_printf(s, " %-20s:\t%d\n", "FRC", v->frame_rate); 2057 2058 seq_puts(s, "\n"); 2059 2060 seq_puts(s, "Compression:\n"); 2061 seq_printf(s, " %-20s:\t%s\n", "Format", format_str[v->format]); 2062 seq_printf(s, " %-20s:\t%s\n", "Subsampling", 2063 v->yuv420 ? "420" : "444"); 2064 seq_printf(s, " %-20s:\t%d\n", "Quality", v->jpeg_quality); 2065 if (v->format == VIDEO_FMT_ASPEED) { 2066 seq_printf(s, " %-20s:\t%s\n", "HQ Mode", 2067 v->hq_mode ? "on" : "off"); 2068 seq_printf(s, " %-20s:\t%d\n", "HQ Quality", 2069 v->hq_mode ? v->jpeg_hq_quality : 0); 2070 } 2071 2072 seq_puts(s, "\n"); 2073 2074 seq_puts(s, "Performance:\n"); 2075 seq_printf(s, " %-20s:\t%d\n", "Frame#", v->sequence); 2076 seq_printf(s, " %-20s:\n", "Frame Duration(ms)"); 2077 seq_printf(s, " %-18s:\t%d\n", "Now", v->perf.duration); 2078 seq_printf(s, " %-18s:\t%d\n", "Min", v->perf.duration_min); 2079 seq_printf(s, " %-18s:\t%d\n", "Max", v->perf.duration_max); 2080 seq_printf(s, " %-20s:\t%d\n", "FPS", 2081 (v->perf.totaltime && v->sequence) ? 2082 1000 / (v->perf.totaltime / v->sequence) : 0); 2083 2084 return 0; 2085} 2086DEFINE_SHOW_ATTRIBUTE(aspeed_video_debugfs); 2087 2088static struct dentry *debugfs_entry; 2089 2090static void aspeed_video_debugfs_remove(struct aspeed_video *video) 2091{ 2092 debugfs_remove_recursive(debugfs_entry); 2093 debugfs_entry = NULL; 2094} 2095 2096static void aspeed_video_debugfs_create(struct aspeed_video *video) 2097{ 2098 debugfs_entry = debugfs_create_file(DEVICE_NAME, 0444, NULL, 2099 video, 2100 &aspeed_video_debugfs_fops); 2101} 2102#else 2103static void aspeed_video_debugfs_remove(struct aspeed_video *video) { } 2104static void aspeed_video_debugfs_create(struct aspeed_video *video) { } 2105#endif /* CONFIG_DEBUG_FS */ 2106 2107static int aspeed_video_setup_video(struct aspeed_video *video) 2108{ 2109 const u64 mask = ~(BIT(V4L2_JPEG_CHROMA_SUBSAMPLING_444) | 2110 BIT(V4L2_JPEG_CHROMA_SUBSAMPLING_420)); 2111 struct v4l2_device *v4l2_dev = &video->v4l2_dev; 2112 struct vb2_queue *vbq = &video->queue; 2113 struct video_device *vdev = &video->vdev; 2114 struct v4l2_ctrl_handler *hdl = &video->ctrl_handler; 2115 int rc; 2116 2117 video->pix_fmt.pixelformat = V4L2_PIX_FMT_JPEG; 2118 video->pix_fmt.field = V4L2_FIELD_NONE; 2119 video->pix_fmt.colorspace = V4L2_COLORSPACE_SRGB; 2120 video->pix_fmt.quantization = V4L2_QUANTIZATION_FULL_RANGE; 2121 video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL; 2122 2123 rc = v4l2_device_register(video->dev, v4l2_dev); 2124 if (rc) { 2125 dev_err(video->dev, "Failed to register v4l2 device\n"); 2126 return rc; 2127 } 2128 2129 v4l2_ctrl_handler_init(hdl, 4); 2130 v4l2_ctrl_new_std(hdl, &aspeed_video_ctrl_ops, 2131 V4L2_CID_JPEG_COMPRESSION_QUALITY, 0, 2132 ASPEED_VIDEO_JPEG_NUM_QUALITIES - 1, 1, 0); 2133 v4l2_ctrl_new_std_menu(hdl, &aspeed_video_ctrl_ops, 2134 V4L2_CID_JPEG_CHROMA_SUBSAMPLING, 2135 V4L2_JPEG_CHROMA_SUBSAMPLING_420, mask, 2136 V4L2_JPEG_CHROMA_SUBSAMPLING_444); 2137 v4l2_ctrl_new_custom(hdl, &aspeed_ctrl_HQ_mode, NULL); 2138 v4l2_ctrl_new_custom(hdl, &aspeed_ctrl_HQ_jpeg_quality, NULL); 2139 2140 rc = hdl->error; 2141 if (rc) { 2142 v4l2_ctrl_handler_free(&video->ctrl_handler); 2143 v4l2_device_unregister(v4l2_dev); 2144 2145 dev_err(video->dev, "Failed to init controls: %d\n", rc); 2146 return rc; 2147 } 2148 2149 v4l2_dev->ctrl_handler = hdl; 2150 2151 vbq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 2152 vbq->io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF; 2153 vbq->dev = v4l2_dev->dev; 2154 vbq->lock = &video->video_lock; 2155 vbq->ops = &aspeed_video_vb2_ops; 2156 vbq->mem_ops = &vb2_dma_contig_memops; 2157 vbq->drv_priv = video; 2158 vbq->buf_struct_size = sizeof(struct aspeed_video_buffer); 2159 vbq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 2160 vbq->min_queued_buffers = ASPEED_VIDEO_V4L2_MIN_BUF_REQ; 2161 2162 rc = vb2_queue_init(vbq); 2163 if (rc) { 2164 v4l2_ctrl_handler_free(&video->ctrl_handler); 2165 v4l2_device_unregister(v4l2_dev); 2166 2167 dev_err(video->dev, "Failed to init vb2 queue\n"); 2168 return rc; 2169 } 2170 2171 vdev->queue = vbq; 2172 vdev->fops = &aspeed_video_v4l2_fops; 2173 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | 2174 V4L2_CAP_STREAMING; 2175 vdev->v4l2_dev = v4l2_dev; 2176 strscpy(vdev->name, DEVICE_NAME, sizeof(vdev->name)); 2177 vdev->vfl_type = VFL_TYPE_VIDEO; 2178 vdev->vfl_dir = VFL_DIR_RX; 2179 vdev->release = video_device_release_empty; 2180 vdev->ioctl_ops = &aspeed_video_ioctl_ops; 2181 vdev->lock = &video->video_lock; 2182 2183 video_set_drvdata(vdev, video); 2184 rc = video_register_device(vdev, VFL_TYPE_VIDEO, 0); 2185 if (rc) { 2186 v4l2_ctrl_handler_free(&video->ctrl_handler); 2187 v4l2_device_unregister(v4l2_dev); 2188 2189 dev_err(video->dev, "Failed to register video device\n"); 2190 return rc; 2191 } 2192 2193 return 0; 2194} 2195 2196/* 2197 * Get regmap without checking res, such as clk/reset, that could lead to 2198 * conflict. 2199 */ 2200static struct regmap *aspeed_regmap_lookup(struct device_node *np, const char *property) 2201{ 2202 struct device_node *syscon_np __free(device_node) = of_parse_phandle(np, property, 0); 2203 2204 if (!syscon_np) 2205 return ERR_PTR(-ENODEV); 2206 2207 return device_node_to_regmap(syscon_np); 2208} 2209 2210static int aspeed_video_init(struct aspeed_video *video) 2211{ 2212 int irq; 2213 int rc; 2214 struct device *dev = video->dev; 2215 2216 video->scu = aspeed_regmap_lookup(dev->of_node, "aspeed,scu"); 2217 video->gfx = aspeed_regmap_lookup(dev->of_node, "aspeed,gfx"); 2218 2219 irq = irq_of_parse_and_map(dev->of_node, 0); 2220 if (!irq) { 2221 dev_err(dev, "Unable to find IRQ\n"); 2222 return -ENODEV; 2223 } 2224 2225 rc = devm_request_threaded_irq(dev, irq, NULL, aspeed_video_irq, 2226 IRQF_ONESHOT, DEVICE_NAME, video); 2227 if (rc < 0) { 2228 dev_err(dev, "Unable to request IRQ %d\n", irq); 2229 return rc; 2230 } 2231 dev_info(video->dev, "irq %d\n", irq); 2232 2233 video->eclk = devm_clk_get(dev, "eclk"); 2234 if (IS_ERR(video->eclk)) { 2235 dev_err(dev, "Unable to get ECLK\n"); 2236 return PTR_ERR(video->eclk); 2237 } 2238 2239 rc = clk_prepare(video->eclk); 2240 if (rc) 2241 return rc; 2242 2243 video->vclk = devm_clk_get(dev, "vclk"); 2244 if (IS_ERR(video->vclk)) { 2245 dev_err(dev, "Unable to get VCLK\n"); 2246 rc = PTR_ERR(video->vclk); 2247 goto err_unprepare_eclk; 2248 } 2249 2250 rc = clk_prepare(video->vclk); 2251 if (rc) 2252 goto err_unprepare_eclk; 2253 2254 of_reserved_mem_device_init(dev); 2255 2256 rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 2257 if (rc) { 2258 dev_err(dev, "Failed to set DMA mask\n"); 2259 goto err_release_reserved_mem; 2260 } 2261 2262 if (!aspeed_video_alloc_buf(video, &video->jpeg, 2263 VE_JPEG_HEADER_SIZE)) { 2264 dev_err(dev, "Failed to allocate DMA for JPEG header\n"); 2265 rc = -ENOMEM; 2266 goto err_release_reserved_mem; 2267 } 2268 dev_info(video->dev, "alloc mem size(%d) at %pad for jpeg header\n", 2269 VE_JPEG_HEADER_SIZE, &video->jpeg.dma); 2270 2271 aspeed_video_init_jpeg_table(video->jpeg.virt, video->yuv420); 2272 2273 return 0; 2274 2275err_release_reserved_mem: 2276 of_reserved_mem_device_release(dev); 2277 clk_unprepare(video->vclk); 2278err_unprepare_eclk: 2279 clk_unprepare(video->eclk); 2280 2281 return rc; 2282} 2283 2284static const struct of_device_id aspeed_video_of_match[] = { 2285 { .compatible = "aspeed,ast2400-video-engine", .data = &ast2400_config }, 2286 { .compatible = "aspeed,ast2500-video-engine", .data = &ast2500_config }, 2287 { .compatible = "aspeed,ast2600-video-engine", .data = &ast2600_config }, 2288 {} 2289}; 2290MODULE_DEVICE_TABLE(of, aspeed_video_of_match); 2291 2292static int aspeed_video_probe(struct platform_device *pdev) 2293{ 2294 const struct aspeed_video_config *config; 2295 struct aspeed_video *video; 2296 int rc; 2297 2298 video = devm_kzalloc(&pdev->dev, sizeof(*video), GFP_KERNEL); 2299 if (!video) 2300 return -ENOMEM; 2301 2302 video->base = devm_platform_ioremap_resource(pdev, 0); 2303 if (IS_ERR(video->base)) 2304 return PTR_ERR(video->base); 2305 2306 config = of_device_get_match_data(&pdev->dev); 2307 if (!config) 2308 return -ENODEV; 2309 2310 video->version = config->version; 2311 video->jpeg_mode = config->jpeg_mode; 2312 video->comp_size_read = config->comp_size_read; 2313 2314 video->frame_rate = 30; 2315 video->jpeg_hq_quality = 1; 2316 video->dev = &pdev->dev; 2317 spin_lock_init(&video->lock); 2318 mutex_init(&video->video_lock); 2319 init_waitqueue_head(&video->wait); 2320 INIT_DELAYED_WORK(&video->res_work, aspeed_video_resolution_work); 2321 INIT_LIST_HEAD(&video->buffers); 2322 2323 rc = aspeed_video_init(video); 2324 if (rc) 2325 return rc; 2326 2327 rc = aspeed_video_setup_video(video); 2328 if (rc) { 2329 aspeed_video_free_buf(video, &video->jpeg); 2330 clk_unprepare(video->vclk); 2331 clk_unprepare(video->eclk); 2332 return rc; 2333 } 2334 2335 aspeed_video_debugfs_create(video); 2336 2337 return 0; 2338} 2339 2340static void aspeed_video_remove(struct platform_device *pdev) 2341{ 2342 struct device *dev = &pdev->dev; 2343 struct v4l2_device *v4l2_dev = dev_get_drvdata(dev); 2344 struct aspeed_video *video = to_aspeed_video(v4l2_dev); 2345 2346 aspeed_video_off(video); 2347 2348 aspeed_video_debugfs_remove(video); 2349 2350 clk_unprepare(video->vclk); 2351 clk_unprepare(video->eclk); 2352 2353 vb2_video_unregister_device(&video->vdev); 2354 2355 v4l2_ctrl_handler_free(&video->ctrl_handler); 2356 2357 v4l2_device_unregister(v4l2_dev); 2358 2359 aspeed_video_free_buf(video, &video->jpeg); 2360 2361 of_reserved_mem_device_release(dev); 2362} 2363 2364static struct platform_driver aspeed_video_driver = { 2365 .driver = { 2366 .name = DEVICE_NAME, 2367 .of_match_table = aspeed_video_of_match, 2368 }, 2369 .probe = aspeed_video_probe, 2370 .remove = aspeed_video_remove, 2371}; 2372 2373module_platform_driver(aspeed_video_driver); 2374 2375module_param(debug, int, 0644); 2376MODULE_PARM_DESC(debug, "Debug level (0=off,1=info,2=debug,3=reg ops)"); 2377 2378MODULE_DESCRIPTION("ASPEED Video Engine Driver"); 2379MODULE_AUTHOR("Eddie James"); 2380MODULE_LICENSE("GPL v2");
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