mali-c55-registers.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * ARM Mali-C55 ISP Driver - Register definitions
  4 *
  5 * Copyright (C) 2025 Ideas on Board Oy
  6 */
  7
  8#ifndef _MALI_C55_REGISTERS_H
  9#define _MALI_C55_REGISTERS_H
 10
 11#include <linux/bits.h>
 12
 13/* ISP Common 0x00000 - 0x000ff */
 14
 15#define MALI_C55_REG_API				0x00000
 16#define MALI_C55_REG_PRODUCT				0x00004
 17#define MALI_C55_REG_VERSION				0x00008
 18#define MALI_C55_REG_REVISION				0x0000c
 19#define MALI_C55_REG_PULSE_MODE				0x0003c
 20#define MALI_C55_REG_INPUT_MODE_REQUEST			0x0009c
 21#define MALI_C55_INPUT_SAFE_STOP			0x00
 22#define MALI_C55_INPUT_SAFE_START			0x01
 23#define MALI_C55_REG_MODE_STATUS			0x000a0
 24#define MALI_C55_REG_INTERRUPT_MASK_VECTOR		0x00030
 25#define MALI_C55_INTERRUPT_MASK_ALL			GENMASK(31, 0)
 26
 27#define MALI_C55_REG_GLOBAL_MONITOR			0x00050
 28
 29#define MALI_C55_REG_GEN_VIDEO				0x00080
 30#define MALI_C55_REG_GEN_VIDEO_ON_MASK			BIT(0)
 31#define MALI_C55_REG_GEN_VIDEO_MULTI_MASK		BIT(1)
 32#define MALI_C55_REG_GEN_PREFETCH_MASK			GENMASK(31, 16)
 33
 34#define MALI_C55_REG_MCU_CONFIG				0x00020
 35#define MALI_C55_REG_MCU_CONFIG_OVERRIDE_MASK		BIT(0)
 36#define MALI_C55_REG_MCU_CONFIG_WRITE_MASK		BIT(1)
 37#define MALI_C55_MCU_CONFIG_WRITE(x)			((x) << 1)
 38#define MALI_C55_REG_MCU_CONFIG_WRITE_PING		BIT(1)
 39#define MALI_C55_REG_MCU_CONFIG_WRITE_PONG		0x00
 40#define MALI_C55_REG_MULTI_CONTEXT_MODE_MASK		BIT(8)
 41#define MALI_C55_REG_PING_PONG_READ			0x00024
 42#define MALI_C55_REG_PING_PONG_READ_MASK		BIT(2)
 43
 44#define MALI_C55_REG_INTERRUPT_CLEAR_VECTOR		0x00034
 45#define MALI_C55_REG_INTERRUPT_CLEAR			0x00040
 46#define MALI_C55_REG_INTERRUPT_STATUS_VECTOR		0x00044
 47
 48enum mali_c55_interrupts {
 49	MALI_C55_IRQ_ISP_START,
 50	MALI_C55_IRQ_ISP_DONE,
 51	MALI_C55_IRQ_MCM_ERROR,
 52	MALI_C55_IRQ_BROKEN_FRAME_ERROR,
 53	MALI_C55_IRQ_MET_AF_DONE,
 54	MALI_C55_IRQ_MET_AEXP_DONE,
 55	MALI_C55_IRQ_MET_AWB_DONE,
 56	MALI_C55_IRQ_AEXP_1024_DONE,
 57	MALI_C55_IRQ_IRIDIX_MET_DONE,
 58	MALI_C55_IRQ_LUT_INIT_DONE,
 59	MALI_C55_IRQ_FR_Y_DONE,
 60	MALI_C55_IRQ_FR_UV_DONE,
 61	MALI_C55_IRQ_DS_Y_DONE,
 62	MALI_C55_IRQ_DS_UV_DONE,
 63	MALI_C55_IRQ_LINEARIZATION_DONE,
 64	MALI_C55_IRQ_RAW_FRONTEND_DONE,
 65	MALI_C55_IRQ_NOISE_REDUCTION_DONE,
 66	MALI_C55_IRQ_IRIDIX_DONE,
 67	MALI_C55_IRQ_BAYER2RGB_DONE,
 68	MALI_C55_IRQ_WATCHDOG_TIMER,
 69	MALI_C55_IRQ_FRAME_COLLISION,
 70	MALI_C55_IRQ_UNUSED,
 71	MALI_C55_IRQ_DMA_ERROR,
 72	MALI_C55_IRQ_INPUT_STOPPED,
 73	MALI_C55_IRQ_MET_AWB_TARGET1_HIT,
 74	MALI_C55_IRQ_MET_AWB_TARGET2_HIT,
 75	MALI_C55_NUM_IRQ_BITS
 76};
 77
 78#define MALI_C55_INTERRUPT_BIT(x)			BIT(x)
 79
 80#define MALI_C55_REG_GLOBAL_PARAMETER_STATUS		0x00068
 81#define MALI_C55_GPS_PONG_FITTED			BIT(0)
 82#define MALI_C55_GPS_WDR_FITTED				BIT(1)
 83#define MALI_C55_GPS_COMPRESSION_FITTED			BIT(2)
 84#define MALI_C55_GPS_TEMPER_FITTED			BIT(3)
 85#define MALI_C55_GPS_SINTER_LITE_FITTED			BIT(4)
 86#define MALI_C55_GPS_SINTER_FITTED			BIT(5)
 87#define MALI_C55_GPS_IRIDIX_LTM_FITTED			BIT(6)
 88#define MALI_C55_GPS_IRIDIX_GTM_FITTED			BIT(7)
 89#define MALI_C55_GPS_CNR_FITTED				BIT(8)
 90#define MALI_C55_GPS_FRSCALER_FITTED			BIT(9)
 91#define MALI_C55_GPS_DS_PIPE_FITTED			BIT(10)
 92
 93#define MALI_C55_REG_BLANKING				0x00084
 94#define MALI_C55_REG_HBLANK_MASK			GENMASK(15, 0)
 95#define MALI_C55_REG_VBLANK_MASK			GENMASK(31, 16)
 96#define MALI_C55_VBLANK(x)				((x) << 16)
 97
 98#define MALI_C55_REG_HC_START				0x00088
 99#define MALI_C55_HC_START(h)				(((h) & 0xffff) << 16)
100#define MALI_C55_REG_HC_SIZE				0x0008c
101#define MALI_C55_HC_SIZE(h)				((h) & 0xffff)
102#define MALI_C55_REG_VC_START_SIZE			0x00094
103#define MALI_C55_VC_START(v)				((v) & 0xffff)
104#define MALI_C55_VC_SIZE(v)				(((v) & 0xffff) << 16)
105
106#define MALI_C55_REG_1024BIN_HIST			0x054a8
107#define MALI_C55_1024BIN_HIST_SIZE			4096
108
109/* Ping/Pong Configuration Space */
110#define MALI_C55_REG_BASE_ADDR				0x18e88
111#define MALI_C55_REG_BYPASS_0				0x18eac
112#define MALI_C55_REG_BYPASS_0_VIDEO_TEST		BIT(0)
113#define MALI_C55_REG_BYPASS_0_INPUT_FMT			BIT(1)
114#define MALI_C55_REG_BYPASS_0_DECOMPANDER		BIT(2)
115#define MALI_C55_REG_BYPASS_0_SENSOR_OFFSET_WDR		BIT(3)
116#define MALI_C55_REG_BYPASS_0_GAIN_WDR			BIT(4)
117#define MALI_C55_REG_BYPASS_0_FRAME_STITCH		BIT(5)
118#define MALI_C55_REG_BYPASS_1				0x18eb0
119#define MALI_C55_REG_BYPASS_1_DIGI_GAIN			BIT(0)
120#define MALI_C55_REG_BYPASS_1_FE_SENSOR_OFFS		BIT(1)
121#define MALI_C55_REG_BYPASS_1_FE_SQRT			BIT(2)
122#define MALI_C55_REG_BYPASS_1_RAW_FE			BIT(3)
123#define MALI_C55_REG_BYPASS_2				0x18eb8
124#define MALI_C55_REG_BYPASS_2_SINTER			BIT(0)
125#define MALI_C55_REG_BYPASS_2_TEMPER			BIT(1)
126#define MALI_C55_REG_BYPASS_3				0x18ebc
127#define MALI_C55_REG_BYPASS_3_SQUARE_BE			BIT(0)
128#define MALI_C55_REG_BYPASS_3_SENSOR_OFFSET_PRE_SH	BIT(1)
129#define MALI_C55_REG_BYPASS_3_MESH_SHADING		BIT(3)
130#define MALI_C55_REG_BYPASS_3_WHITE_BALANCE		BIT(4)
131#define MALI_C55_REG_BYPASS_3_IRIDIX			BIT(5)
132#define MALI_C55_REG_BYPASS_3_IRIDIX_GAIN		BIT(6)
133#define MALI_C55_REG_BYPASS_4				0x18ec0
134#define MALI_C55_REG_BYPASS_4_DEMOSAIC_RGB		BIT(1)
135#define MALI_C55_REG_BYPASS_4_PF_CORRECTION		BIT(3)
136#define MALI_C55_REG_BYPASS_4_CCM			BIT(4)
137#define MALI_C55_REG_BYPASS_4_CNR			BIT(5)
138#define MALI_C55_REG_FR_BYPASS				0x18ec4
139#define MALI_C55_REG_DS_BYPASS				0x18ec8
140#define MALI_C55_BYPASS_CROP				BIT(0)
141#define MALI_C55_BYPASS_SCALER				BIT(1)
142#define MALI_C55_BYPASS_GAMMA_RGB			BIT(2)
143#define MALI_C55_BYPASS_SHARPEN				BIT(3)
144#define MALI_C55_BYPASS_CS_CONV				BIT(4)
145#define MALI_C55_REG_ISP_RAW_BYPASS			0x18ecc
146#define MALI_C55_ISP_RAW_BYPASS_BYPASS_MASK		BIT(0)
147#define MALI_C55_ISP_RAW_BYPASS_FR_BYPASS_MASK		GENMASK(9, 8)
148#define MALI_C55_ISP_RAW_BYPASS_RAW_FR_BYPASS		(2 << 8)
149#define MALI_C55_ISP_RAW_BYPASS_RGB_FR_BYPASS		(1 << 8)
150#define MALI_C55_ISP_RAW_BYPASS_DS_PIPE_DISABLE		BIT(1)
151#define MALI_C55_ISP_RAW_BYPASS_RAW_BYPASS		BIT(0)
152
153#define MALI_C55_REG_ACTIVE_WIDTH_MASK			0xffff
154#define MALI_C55_REG_ACTIVE_HEIGHT_MASK			0xffff0000
155#define MALI_C55_REG_BAYER_ORDER			0x18e8c
156#define MALI_C55_BAYER_ORDER_MASK			GENMASK(1, 0)
157#define MALI_C55_BAYER_ORDER_RGGB			0
158#define MALI_C55_BAYER_ORDER_GRBG			1
159#define MALI_C55_BAYER_ORDER_GBRG			2
160#define MALI_C55_BAYER_ORDER_BGGR			3
161
162#define MALI_C55_REG_METERING_CONFIG			0x18ed0
163#define MALI_C55_5BIN_HIST_DISABLE_MASK			BIT(0)
164#define MALI_C55_5BIN_HIST_SWITCH_MASK			GENMASK(2, 1)
165#define MALI_C55_5BIN_HIST_SWITCH(x)			((x) << 1)
166#define MALI_C55_AF_DISABLE_MASK			BIT(4)
167#define MALI_C55_AF_SWITCH_MASK				BIT(5)
168#define MALI_C55_AWB_DISABLE_MASK			BIT(8)
169#define MALI_C55_AWB_SWITCH_MASK			BIT(9)
170#define MALI_C55_AWB_SWITCH(x)				((x) << 9)
171#define MALI_C55_AEXP_HIST_DISABLE_MASK			BIT(12)
172#define MALI_C55_AEXP_HIST_DISABLE			(0x01 << 12)
173#define MALI_C55_AEXP_HIST_SWITCH_MASK			GENMASK(14, 13)
174#define MALI_C55_AEXP_HIST_SWITCH(x)			((x) << 13)
175#define MALI_C55_AEXP_IHIST_DISABLE_MASK		BIT(16)
176#define MALI_C55_AEXP_IHIST_DISABLE			(0x01 << 12)
177#define MALI_C55_AEXP_SRC_MASK				BIT(24)
178
179#define MALI_C55_REG_TPG_CH0				0x18ed8
180#define MALI_C55_TEST_PATTERN_ON_OFF			BIT(0)
181#define MALI_C55_TEST_PATTERN_RGB_MASK			BIT(1)
182#define MALI_C55_TEST_PATTERN_RGB(x)			((x) << 1)
183#define MALI_C55_REG_TPG_R_BACKGROUND			0x18ee0
184#define MALI_C55_REG_TPG_G_BACKGROUND			0x18ee4
185#define MALI_C55_REG_TPG_B_BACKGROUND			0x18ee8
186#define MALI_C55_TPG_BACKGROUND_MAX			0xfffff
187#define MALI_C55_REG_INPUT_WIDTH			0x18f98
188#define MALI_C55_INPUT_WIDTH_MASK			GENMASK(18, 16)
189#define MALI_C55_INPUT_WIDTH_8BIT			(0 << 16)
190#define MALI_C55_INPUT_WIDTH_10BIT			(1 << 16)
191#define MALI_C55_INPUT_WIDTH_12BIT			(2 << 16)
192#define MALI_C55_INPUT_WIDTH_14BIT			(3 << 16)
193#define MALI_C55_INPUT_WIDTH_16BIT			(4 << 16)
194#define MALI_C55_INPUT_WIDTH_20BIT			(5 << 16)
195#define MALI_C55_REG_SPACE_SIZE				0x4000
196#define MALI_C55_REG_CONFIG_SPACES_OFFSET		0x0ab6c
197#define MALI_C55_CONFIG_SPACE_SIZE			0x1231c
198
199#define MALI_C55_REG_DIGITAL_GAIN			0x1926c
200#define MALI_C55_DIGITAL_GAIN_MASK			GENMASK(12, 0)
201#define MALI_C55_REG_DIGITAL_GAIN_OFFSET		0x19270
202#define MALI_C55_DIGITAL_GAIN_OFFSET_MASK		GENMASK(19, 0)
203
204#define MALI_C55_REG_SINTER_CONFIG			0x19348
205#define MALI_C55_SINTER_VIEW_FILTER_MASK		GENMASK(1, 0)
206#define MALI_C55_SINTER_SCALE_MODE_MASK			GENMASK(3, 2)
207#define MALI_C55_SINTER_ENABLE_MASK			BIT(4)
208#define MALI_C55_SINTER_FILTER_SELECT_MASK		BIT(5)
209#define MALI_C55_SINTER_INT_SELECT_MASK			BIT(6)
210#define MALI_C55_SINTER_RM_ENABLE_MASK			BIT(7)
211
212/* Temper DMA */
213#define MALI_C55_REG_TEMPER_DMA_IO			0x1ab78
214#define MALI_C55_TEMPER_DMA_WRITE_ON			BIT(0)
215#define MALI_C55_TEMPER_DMA_READ_ON			BIT(1)
216
217/* Black Level Correction Configuration */
218#define MALI_C55_REG_SENSOR_OFF_PRE_SHA_00		0x1abcc
219#define MALI_C55_REG_SENSOR_OFF_PRE_SHA_01		0x1abd0
220#define MALI_C55_REG_SENSOR_OFF_PRE_SHA_10		0x1abd4
221#define MALI_C55_REG_SENSOR_OFF_PRE_SHA_11		0x1abd8
222#define MALI_C55_SENSOR_OFF_PRE_SHA_MASK		0xfffff
223
224/* Lens Mesh Shading Configuration */
225#define MALI_C55_REG_MESH_SHADING_TABLES		0x13074
226#define MALI_C55_REG_MESH_SHADING_CONFIG		0x1abfc
227#define MALI_C55_MESH_SHADING_ENABLE_MASK		BIT(0)
228#define MALI_C55_MESH_SHADING_MESH_SHOW_MASK		BIT(1)
229#define MALI_C55_MESH_SHADING_MESH_SHOW(x)		((x) << 1)
230#define MALI_C55_MESH_SHADING_SCALE_MASK		GENMASK(4, 2)
231#define MALI_C55_MESH_SHADING_SCALE(x)			((x) << 2)
232#define MALI_C55_MESH_SHADING_PAGE_R_MASK		GENMASK(9, 8)
233#define MALI_C55_MESH_SHADING_PAGE_R(x)			((x) << 8)
234#define MALI_C55_MESH_SHADING_PAGE_G_MASK		GENMASK(11, 10)
235#define MALI_C55_MESH_SHADING_PAGE_G(x)			((x) << 10)
236#define MALI_C55_MESH_SHADING_PAGE_B_MASK		GENMASK(13, 12)
237#define MALI_C55_MESH_SHADING_PAGE_B(x)			((x) << 12)
238#define MALI_C55_MESH_SHADING_MESH_WIDTH_MASK		GENMASK(21, 16)
239#define MALI_C55_MESH_SHADING_MESH_WIDTH(x)		((x) << 16)
240#define MALI_C55_MESH_SHADING_MESH_HEIGHT_MASK		GENMASK(29, 24)
241#define MALI_C55_MESH_SHADING_MESH_HEIGHT(x)		((x) << 24)
242
243#define MALI_C55_REG_MESH_SHADING_ALPHA_BANK		0x1ac04
244#define MALI_C55_MESH_SHADING_ALPHA_BANK_R_MASK		GENMASK(2, 0)
245#define MALI_C55_MESH_SHADING_ALPHA_BANK_G_MASK		GENMASK(5, 3)
246#define MALI_C55_MESH_SHADING_ALPHA_BANK_G(x)		((x) << 3)
247#define MALI_C55_MESH_SHADING_ALPHA_BANK_B_MASK		GENMASK(8, 6)
248#define MALI_C55_MESH_SHADING_ALPHA_BANK_B(x)		((x) << 6)
249#define MALI_C55_REG_MESH_SHADING_ALPHA			0x1ac08
250#define MALI_C55_MESH_SHADING_ALPHA_R_MASK		GENMASK(7, 0)
251#define MALI_C55_MESH_SHADING_ALPHA_G_MASK		GENMASK(15, 8)
252#define MALI_C55_MESH_SHADING_ALPHA_G(x)		((x) << 8)
253#define MALI_C55_MESH_SHADING_ALPHA_B_MASK		GENMASK(23, 16)
254#define MALI_C55_MESH_SHADING_ALPHA_B(x)		((x) << 16)
255#define MALI_C55_REG_MESH_SHADING_MESH_STRENGTH		0x1ac0c
256#define MALI_c55_MESH_STRENGTH_MASK			GENMASK(15, 0)
257
258/* AWB Gains Configuration */
259#define MALI_C55_REG_AWB_GAINS1				0x1ac10
260#define MALI_C55_AWB_GAIN00_MASK			GENMASK(11, 0)
261#define MALI_C55_AWB_GAIN01_MASK			GENMASK(27, 16)
262#define MALI_C55_AWB_GAIN01(x)				((x) << 16)
263#define MALI_C55_REG_AWB_GAINS2				0x1ac14
264#define MALI_C55_AWB_GAIN10_MASK			GENMASK(11, 0)
265#define MALI_C55_AWB_GAIN11_MASK			GENMASK(27, 16)
266#define MALI_C55_AWB_GAIN11(x)				((x) << 16)
267#define MALI_C55_REG_AWB_GAINS1_AEXP			0x1ac18
268#define MALI_C55_REG_AWB_GAINS2_AEXP			0x1ac1c
269
270/* Colour Correction Matrix Configuration */
271#define MALI_C55_REG_CCM_ENABLE				0x1b07c
272#define MALI_C55_CCM_ENABLE_MASK			BIT(0)
273#define MALI_C55_REG_CCM_COEF_R_R			0x1b080
274#define MALI_C55_REG_CCM_COEF_R_G			0x1b084
275#define MALI_C55_REG_CCM_COEF_R_B			0x1b088
276#define MALI_C55_REG_CCM_COEF_G_R			0x1b090
277#define MALI_C55_REG_CCM_COEF_G_G			0x1b094
278#define MALI_C55_REG_CCM_COEF_G_B			0x1b098
279#define MALI_C55_REG_CCM_COEF_B_R			0x1b0a0
280#define MALI_C55_REG_CCM_COEF_B_G			0x1b0a4
281#define MALI_C55_REG_CCM_COEF_B_B			0x1b0a8
282#define MALI_C55_CCM_COEF_MASK				GENMASK(12, 0)
283#define MALI_C55_REG_CCM_ANTIFOG_GAIN_R			0x1b0b0
284#define MALI_C55_REG_CCM_ANTIFOG_GAIN_G			0x1b0b4
285#define MALI_C55_REG_CCM_ANTIFOG_GAIN_B			0x1b0b8
286#define MALI_C55_CCM_ANTIFOG_GAIN_MASK			GENMASK(11, 0)
287#define MALI_C55_REG_CCM_ANTIFOG_OFFSET_R		0x1b0c0
288#define MALI_C55_REG_CCM_ANTIFOG_OFFSET_G		0x1b0c4
289#define MALI_C55_REG_CCM_ANTIFOG_OFFSET_B		0x1b0c8
290#define MALI_C55_CCM_ANTIFOG_OFFSET_MASK		GENMASK(11, 0)
291
292/* AWB Statistics Configuration */
293#define MALI_C55_REG_AWB_STATS_MODE			0x1b29c
294#define MALI_C55_AWB_STATS_MODE_MASK			BIT(0)
295#define MALI_C55_REG_AWB_WHITE_LEVEL			0x1b2a0
296#define MALI_C55_AWB_WHITE_LEVEL_MASK			GENMASK(9, 0)
297#define MALI_C55_REG_AWB_BLACK_LEVEL			0x1b2a4
298#define MALI_C55_AWB_BLACK_LEVEL_MASK			GENMASK(9, 0)
299#define MALI_C55_REG_AWB_CR_MAX				0x1b2a8
300#define MALI_C55_AWB_CR_MAX_MASK			GENMASK(11, 0)
301#define MALI_C55_REG_AWB_CR_MIN				0x1b2ac
302#define MALI_C55_AWB_CR_MIN_MASK			GENMASK(11, 0)
303#define MALI_C55_REG_AWB_CB_MAX				0x1b2b0
304#define MALI_C55_AWB_CB_MAX_MASK			GENMASK(11, 0)
305#define MALI_C55_REG_AWB_CB_MIN				0x1b2b4
306#define MALI_C55_AWB_CB_MIN_MASK			GENMASK(11, 0)
307#define MALI_C55_REG_AWB_NODES_USED			0x1b2c4
308#define MALI_C55_AWB_NODES_USED_HORIZ_MASK		GENMASK(7, 0)
309#define MALI_C55_AWB_NODES_USED_VERT_MASK		GENMASK(15, 8)
310#define MALI_C55_AWB_NODES_USED_VERT(x)			((x) << 8)
311#define MALI_C55_REG_AWB_CR_HIGH			0x1b2c8
312#define MALI_C55_AWB_CR_HIGH_MASK			GENMASK(11, 0)
313#define MALI_C55_REG_AWB_CR_LOW				0x1b2cc
314#define MALI_C55_AWB_CR_LOW_MASK			GENMASK(11, 0)
315#define MALI_C55_REG_AWB_CB_HIGH			0x1b2d0
316#define MALI_C55_AWB_CB_HIGH_MASK			GENMASK(11, 0)
317#define MALI_C55_REG_AWB_CB_LOW				0x1b2d4
318#define MALI_C55_AWB_CB_LOW_MASK			GENMASK(11, 0)
319
320/* AEXP Metering Histogram Configuration */
321#define MALI_C55_REG_AEXP_HIST_BASE			0x1b730
322#define MALI_C55_REG_AEXP_IHIST_BASE			0x1bbac
323#define MALI_C55_AEXP_HIST_SKIP_OFFSET			0
324#define MALI_C55_AEXP_HIST_SKIP_X_MASK			GENMASK(2, 0)
325#define MALI_C55_AEXP_HIST_SKIP_X(x)			((x) << 0)
326#define MALI_C55_AEXP_HIST_OFFSET_X_MASK		BIT(3)
327#define MALI_C55_AEXP_HIST_OFFSET_X(x)			((x) << 3)
328#define MALI_C55_AEXP_HIST_SKIP_Y_MASK			GENMASK(6, 4)
329#define MALI_C55_AEXP_HIST_SKIP_Y(x)			((x) << 4)
330#define MALI_C55_AEXP_HIST_OFFSET_Y_MASK		BIT(7)
331#define MALI_C55_AEXP_HIST_OFFSET_Y(x)			((x) << 7)
332#define MALI_C55_AEXP_HIST_SCALE_OFFSET			4
333#define MALI_C55_AEXP_HIST_SCALE_BOTTOM_MASK		GENMASK(3, 0)
334#define MALI_C55_AEXP_HIST_SCALE_TOP_MASK		GENMASK(7, 4)
335#define MALI_C55_AEXP_HIST_SCALE_TOP(x)			((x) << 4)
336#define MALI_C55_AEXP_HIST_PLANE_MODE_OFFSET		16
337#define MALI_C55_AEXP_HIST_PLANE_MODE_MASK		GENMASK(2, 0)
338#define MALI_C55_AEXP_HIST_NODES_USED_OFFSET		52
339#define MALI_C55_AEXP_HIST_NODES_USED_HORIZ_MASK	GENMASK(7, 0)
340#define MALI_C55_AEXP_HIST_NODES_USED_VERT_MASK		GENMASK(15, 8)
341#define MALI_C55_AEXP_HIST_NODES_USED_VERT(x)		((x) << 8)
342#define MALI_C55_AEXP_HIST_ZONE_WEIGHTS_OFFSET		56
343#define MALI_C55_AEXP_HIST_ZONE_WEIGHT_MASK		0x0f0f0f0f
344
345/*
346 * The Mali-C55 ISP has up to two output pipes; known as full resolution and
347 * down scaled. The register space for these is laid out identically, but offset
348 * by 372 bytes.
349 */
350#define MALI_C55_CAP_DEV_FR_REG_OFFSET		0x0
351#define MALI_C55_CAP_DEV_DS_REG_OFFSET		0x174
352
353#define MALI_C55_REG_CS_CONV_CONFIG			0x1c098
354#define MALI_C55_CS_CONV_MATRIX_MASK			BIT(0)
355#define MALI_C55_CS_CONV_FILTER_MASK			BIT(1)
356#define MALI_C55_CS_CONV_HORZ_DOWNSAMPLE_MASK		BIT(2)
357#define MALI_C55_CS_CONV_VERT_DOWNSAMPLE_MASK		BIT(3)
358#define MALI_C55_CS_CONV_FILTER_ENABLE			(0x01 << 1)
359#define MALI_C55_CS_CONV_HORZ_DOWNSAMPLE_ENABLE		(0x01 << 2)
360#define MALI_C55_CS_CONV_VERT_DOWNSAMPLE_ENABLE		(0x01 << 3)
361#define MALI_C55_REG_Y_WRITER_MODE			0x1c0ec
362#define MALI_C55_REG_UV_WRITER_MODE			0x1c144
363#define MALI_C55_WRITER_MODE_MASK			GENMASK(4, 0)
364#define MALI_C55_OUTPUT_DISABLED			0
365#define MALI_C55_OUTPUT_RGB32				1
366#define MALI_C55_OUTPUT_A2R10G10B10			2
367#define MALI_C55_OUTPUT_RGB565				3
368#define MALI_C55_OUTPUT_RGB24				4
369#define MALI_C55_OUTPUT_GEN32				5
370#define MALI_C55_OUTPUT_RAW16				6
371#define MALI_C55_OUTPUT_AYUV				8
372#define MALI_C55_OUTPUT_Y410				9
373#define MALI_C55_OUTPUT_YUY2				10
374#define MALI_C55_OUTPUT_UYVY				11
375#define MALI_C55_OUTPUT_Y210				12
376#define MALI_C55_OUTPUT_NV12_21				13
377#define MALI_C55_OUTPUT_YUV_420_422			17
378#define MALI_C55_OUTPUT_P210_P010			19
379#define MALI_C55_OUTPUT_YUV422				20
380#define MALI_C55_WRITER_SUBMODE_MASK			GENMASK(7, 6)
381#define MALI_C55_WRITER_SUBMODE(x)			((x) << 6)
382#define MALI_C55_OUTPUT_PLANE_ALT0			0
383#define MALI_C55_OUTPUT_PLANE_ALT1			1
384#define MALI_C55_OUTPUT_PLANE_ALT2			2
385#define MALI_C55_WRITER_FRAME_WRITE_MASK		BIT(9)
386#define MALI_C55_WRITER_FRAME_WRITE_ENABLE		(0x01 << 9)
387#define MALI_C55_REG_ACTIVE_OUT_Y_SIZE			0x1c0f0
388#define MALI_C55_REG_ACTIVE_OUT_UV_SIZE			0x1c148
389#define MALI_C55_REG_ACTIVE_OUT_SIZE_W(w)		((w) << 0)
390#define MALI_C55_REG_ACTIVE_OUT_SIZE_H(h)		((h) << 16)
391#define MALI_C55_REG_Y_WRITER_BANKS_BASE		0x1c0f4
392#define MALI_C55_REG_Y_WRITER_BANKS_CONFIG		0x1c108
393#define MALI_C55_REG_Y_WRITER_MAX_BANKS_MASK		GENMASK(2, 0)
394#define MALI_C55_REG_Y_WRITER_BANKS_RESTART		BIT(3)
395#define MALI_C55_REG_Y_WRITER_OFFSET			0x1c10c
396#define MALI_C55_REG_UV_WRITER_BANKS_BASE		0x1c14c
397#define MALI_C55_REG_UV_WRITER_BANKS_CONFIG		0x1c160
398#define MALI_C55_REG_UV_WRITER_MAX_BANKS_MASK		GENMASK(2, 0)
399#define MALI_C55_REG_UV_WRITER_BANKS_RESTART		BIT(3)
400#define MALI_C55_REG_UV_WRITER_OFFSET			0x1c164
401
402#define MALI_C55_REG_TEST_GEN_CH0_OFF_ON
403#define MALI_C55_REG_TEST_GEN_CH0_PATTERN_TYPE		0x18edc
404
405#define MALI_C55_REG_CROP_EN				0x1c028
406#define MALI_C55_CROP_ENABLE				BIT(0)
407#define MALI_C55_REG_CROP_X_START			0x1c02c
408#define MALI_C55_REG_CROP_Y_START			0x1c030
409#define MALI_C55_REG_CROP_X_SIZE			0x1c034
410#define MALI_C55_REG_CROP_Y_SIZE			0x1c038
411#define MALI_C55_REG_SCALER_TIMEOUT_EN			0x1c040
412#define MALI_C55_SCALER_TIMEOUT_EN			BIT(4)
413#define MALI_C55_SCALER_TIMEOUT(t)			((t) << 16)
414#define MALI_C55_REG_SCALER_IN_WIDTH			0x1c044
415#define MALI_C55_REG_SCALER_IN_HEIGHT			0x1c048
416#define MALI_C55_REG_SCALER_OUT_WIDTH			0x1c04c
417#define MALI_C55_REG_SCALER_OUT_HEIGHT			0x1c050
418#define MALI_C55_REG_SCALER_HFILT_TINC			0x1c054
419#define MALI_C55_REG_SCALER_HFILT_COEF			0x1c058
420#define MALI_C55_REG_SCALER_VFILT_TINC			0x1c05c
421#define MALI_C55_REG_SCALER_VFILT_COEF			0x1c060
422
423#define MALI_C55_REG_GAMMA_RGB_ENABLE			0x1c064
424#define MALI_C55_GAMMA_ENABLE_MASK			BIT(0)
425#define MALI_C55_REG_GAMMA_GAINS_1			0x1c068
426#define MALI_C55_GAMMA_GAIN_R_MASK			GENMASK(11, 0)
427#define MALI_C55_GAMMA_GAIN_G_MASK			GENMASK(27, 16)
428#define MALI_C55_REG_GAMMA_GAINS_2			0x1c06c
429#define MALI_C55_GAMMA_GAIN_B_MASK			GENMASK(11, 0)
430#define MALI_C55_REG_GAMMA_OFFSETS_1			0x1c070
431#define MALI_C55_GAMMA_OFFSET_R_MASK			GENMASK(11, 0)
432#define MALI_C55_GAMMA_OFFSET_G_MASK			GENMASK(27, 16)
433#define MALI_C55_REG_GAMMA_OFFSETS_2			0x1c074
434#define MALI_C55_GAMMA_OFFSET_B_MASK			GENMASK(11, 0)
435
436/*
437 * A re-definition of an above register. These will usually be written on a per
438 * capture device basis and handled with mali_c55_cap_dev_write(), but on
439 * startup is written by core.c
440 */
441#define MALI_C55_REG_FR_GAMMA_RGB_ENABLE		0x1c064
442#define MALI_C55_REG_DS_GAMMA_RGB_ENABLE		0x1c1d8
443
444#define MALI_C55_REG_FR_SCALER_HFILT			0x34a8
445#define MALI_C55_REG_FR_SCALER_VFILT			0x44a8
446#define MALI_C55_REG_DS_SCALER_HFILT			0x14a8
447#define MALI_C55_REG_DS_SCALER_VFILT			0x24a8
448
449#endif /* _MALI_C55_REGISTERS_H */