vpu_malone.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright 2020-2021 NXP
   4 */
   5
   6#include <linux/bitfield.h>
   7#include <linux/init.h>
   8#include <linux/interconnect.h>
   9#include <linux/ioctl.h>
  10#include <linux/list.h>
  11#include <linux/kernel.h>
  12#include <linux/module.h>
  13#include <linux/platform_device.h>
  14#include <linux/delay.h>
  15#include <linux/rational.h>
  16#include <linux/time64.h>
  17#include <media/videobuf2-v4l2.h>
  18#include <media/videobuf2-dma-contig.h>
  19#include <linux/videodev2.h>
  20#include "vpu.h"
  21#include "vpu_rpc.h"
  22#include "vpu_defs.h"
  23#include "vpu_helpers.h"
  24#include "vpu_v4l2.h"
  25#include "vpu_cmds.h"
  26#include "vpu_imx8q.h"
  27#include "vpu_malone.h"
  28
  29static bool low_latency;
  30module_param(low_latency, bool, 0644);
  31MODULE_PARM_DESC(low_latency, "Set low latency frame flush mode: 0 (disable) or 1 (enable)");
  32
  33#define CMD_SIZE			25600
  34#define MSG_SIZE			25600
  35#define CODEC_SIZE			0x1000
  36#define JPEG_SIZE			0x1000
  37#define SEQ_SIZE			0x1000
  38#define GOP_SIZE			0x1000
  39#define PIC_SIZE			0x1000
  40#define QMETER_SIZE			0x1000
  41#define DBGLOG_SIZE			0x10000
  42#define DEBUG_SIZE			0x80000
  43#define ENG_SIZE			0x1000
  44#define MALONE_SKIPPED_FRAME_ID		0x555
  45
  46#define MALONE_ALIGN_MBI		0x800
  47#define MALONE_DCP_CHUNK_BIT		16
  48#define MALONE_DCP_SIZE_MAX		0x3000000
  49#define MALONE_DCP_SIZE_MIN		0x100000
  50#define MALONE_DCP_FIXED_MB_ALLOC	250
  51
  52#define CONFIG_SET(val, cfg, pos, mask)		\
  53		(*(cfg) |= (((val) << (pos)) & (mask)))
  54//x means source data , y means destination data
  55#define STREAM_CONFIG_FORMAT_SET(x, y)		CONFIG_SET(x, y, 0, 0x0000000F)
  56#define STREAM_CONFIG_STRBUFIDX_SET(x, y)	CONFIG_SET(x, y, 8, 0x00000300)
  57#define STREAM_CONFIG_NOSEQ_SET(x, y)		CONFIG_SET(x, y, 10, 0x00000400)
  58#define STREAM_CONFIG_DEBLOCK_SET(x, y)		CONFIG_SET(x, y, 11, 0x00000800)
  59#define STREAM_CONFIG_DERING_SET(x, y)		CONFIG_SET(x, y, 12, 0x00001000)
  60#define STREAM_CONFIG_IBWAIT_SET(x, y)		CONFIG_SET(x, y, 13, 0x00002000)
  61#define STREAM_CONFIG_FBC_SET(x, y)		CONFIG_SET(x, y, 14, 0x00004000)
  62#define STREAM_CONFIG_PLAY_MODE_SET(x, y)	CONFIG_SET(x, y, 16, 0x00030000)
  63#define STREAM_CONFIG_ENABLE_DCP_SET(x, y)	CONFIG_SET(x, y, 20, 0x00100000)
  64#define STREAM_CONFIG_NUM_STR_BUF_SET(x, y)	CONFIG_SET(x, y, 21, 0x00600000)
  65#define STREAM_CONFIG_MALONE_USAGE_SET(x, y)	CONFIG_SET(x, y, 23, 0x01800000)
  66#define STREAM_CONFIG_MULTI_VID_SET(x, y)	CONFIG_SET(x, y, 25, 0x02000000)
  67#define STREAM_CONFIG_OBFUSC_EN_SET(x, y)	CONFIG_SET(x, y, 26, 0x04000000)
  68#define STREAM_CONFIG_RC4_EN_SET(x, y)		CONFIG_SET(x, y, 27, 0x08000000)
  69#define STREAM_CONFIG_MCX_SET(x, y)		CONFIG_SET(x, y, 28, 0x10000000)
  70#define STREAM_CONFIG_PES_SET(x, y)		CONFIG_SET(x, y, 29, 0x20000000)
  71#define STREAM_CONFIG_NUM_DBE_SET(x, y)		CONFIG_SET(x, y, 30, 0x40000000)
  72#define STREAM_CONFIG_FS_CTRL_MODE_SET(x, y)	CONFIG_SET(x, y, 31, 0x80000000)
  73
  74#define MALONE_DEC_FMT_RV_MASK			BIT(21)
  75
  76#define MALONE_VERSION_MASK			0xFFFFF
  77#define MALONE_VERSION(maj, min, inc)		\
  78		(FIELD_PREP(0xF0000, maj) | FIELD_PREP(0xFF00, min) | FIELD_PREP(0xFF, inc))
  79#define CHECK_VERSION(iface, maj, min)		\
  80		(FIELD_GET(MALONE_VERSION_MASK, (iface)->fw_version) >= MALONE_VERSION(maj, min, 0))
  81
  82enum vpu_malone_stream_input_mode {
  83	INVALID_MODE = 0,
  84	FRAME_LVL,
  85	NON_FRAME_LVL
  86};
  87
  88enum vpu_malone_format {
  89	MALONE_FMT_NULL = 0x0,
  90	MALONE_FMT_AVC  = 0x1,
  91	MALONE_FMT_MP2  = 0x2,
  92	MALONE_FMT_VC1  = 0x3,
  93	MALONE_FMT_AVS  = 0x4,
  94	MALONE_FMT_ASP  = 0x5,
  95	MALONE_FMT_JPG  = 0x6,
  96	MALONE_FMT_RV   = 0x7,
  97	MALONE_FMT_VP6  = 0x8,
  98	MALONE_FMT_SPK  = 0x9,
  99	MALONE_FMT_VP8  = 0xA,
 100	MALONE_FMT_HEVC = 0xB,
 101	MALONE_FMT_LAST = MALONE_FMT_HEVC
 102};
 103
 104enum {
 105	VID_API_CMD_NULL              = 0x00,
 106	VID_API_CMD_PARSE_NEXT_SEQ    = 0x01,
 107	VID_API_CMD_PARSE_NEXT_I      = 0x02,
 108	VID_API_CMD_PARSE_NEXT_IP     = 0x03,
 109	VID_API_CMD_PARSE_NEXT_ANY    = 0x04,
 110	VID_API_CMD_DEC_PIC           = 0x05,
 111	VID_API_CMD_UPDATE_ES_WR_PTR  = 0x06,
 112	VID_API_CMD_UPDATE_ES_RD_PTR  = 0x07,
 113	VID_API_CMD_UPDATE_UDATA      = 0x08,
 114	VID_API_CMD_GET_FSINFO        = 0x09,
 115	VID_API_CMD_SKIP_PIC          = 0x0a,
 116	VID_API_CMD_DEC_CHUNK         = 0x0b,
 117	VID_API_CMD_START             = 0x10,
 118	VID_API_CMD_STOP              = 0x11,
 119	VID_API_CMD_ABORT             = 0x12,
 120	VID_API_CMD_RST_BUF           = 0x13,
 121	VID_API_CMD_FS_RELEASE        = 0x15,
 122	VID_API_CMD_MEM_REGION_ATTACH = 0x16,
 123	VID_API_CMD_MEM_REGION_DETACH = 0x17,
 124	VID_API_CMD_MVC_VIEW_SELECT   = 0x18,
 125	VID_API_CMD_FS_ALLOC          = 0x19,
 126	VID_API_CMD_DBG_GET_STATUS    = 0x1C,
 127	VID_API_CMD_DBG_START_LOG     = 0x1D,
 128	VID_API_CMD_DBG_STOP_LOG      = 0x1E,
 129	VID_API_CMD_DBG_DUMP_LOG      = 0x1F,
 130	VID_API_CMD_YUV_READY         = 0x20,
 131	VID_API_CMD_TS                = 0x21,
 132
 133	VID_API_CMD_FIRM_RESET        = 0x40,
 134
 135	VID_API_CMD_SNAPSHOT          = 0xAA,
 136	VID_API_CMD_ROLL_SNAPSHOT     = 0xAB,
 137	VID_API_CMD_LOCK_SCHEDULER    = 0xAC,
 138	VID_API_CMD_UNLOCK_SCHEDULER  = 0xAD,
 139	VID_API_CMD_CQ_FIFO_DUMP      = 0xAE,
 140	VID_API_CMD_DBG_FIFO_DUMP     = 0xAF,
 141	VID_API_CMD_SVC_ILP           = 0xBB,
 142	VID_API_CMD_FW_STATUS         = 0xF0,
 143	VID_API_CMD_INVALID           = 0xFF
 144};
 145
 146enum {
 147	VID_API_EVENT_NULL			= 0x00,
 148	VID_API_EVENT_RESET_DONE		= 0x01,
 149	VID_API_EVENT_SEQ_HDR_FOUND		= 0x02,
 150	VID_API_EVENT_PIC_HDR_FOUND		= 0x03,
 151	VID_API_EVENT_PIC_DECODED		= 0x04,
 152	VID_API_EVENT_FIFO_LOW			= 0x05,
 153	VID_API_EVENT_FIFO_HIGH			= 0x06,
 154	VID_API_EVENT_FIFO_EMPTY		= 0x07,
 155	VID_API_EVENT_FIFO_FULL			= 0x08,
 156	VID_API_EVENT_BS_ERROR			= 0x09,
 157	VID_API_EVENT_UDATA_FIFO_UPTD		= 0x0A,
 158	VID_API_EVENT_RES_CHANGE		= 0x0B,
 159	VID_API_EVENT_FIFO_OVF			= 0x0C,
 160	VID_API_EVENT_CHUNK_DECODED		= 0x0D,
 161	VID_API_EVENT_REQ_FRAME_BUFF		= 0x10,
 162	VID_API_EVENT_FRAME_BUFF_RDY		= 0x11,
 163	VID_API_EVENT_REL_FRAME_BUFF		= 0x12,
 164	VID_API_EVENT_STR_BUF_RST		= 0x13,
 165	VID_API_EVENT_RET_PING			= 0x14,
 166	VID_API_EVENT_QMETER			= 0x15,
 167	VID_API_EVENT_STR_FMT_CHANGE		= 0x16,
 168	VID_API_EVENT_FIRMWARE_XCPT		= 0x17,
 169	VID_API_EVENT_START_DONE		= 0x18,
 170	VID_API_EVENT_STOPPED			= 0x19,
 171	VID_API_EVENT_ABORT_DONE		= 0x1A,
 172	VID_API_EVENT_FINISHED			= 0x1B,
 173	VID_API_EVENT_DBG_STAT_UPDATE		= 0x1C,
 174	VID_API_EVENT_DBG_LOG_STARTED		= 0x1D,
 175	VID_API_EVENT_DBG_LOG_STOPPED		= 0x1E,
 176	VID_API_EVENT_DBG_LOG_UPDATED		= 0x1F,
 177	VID_API_EVENT_DBG_MSG_DEC		= 0x20,
 178	VID_API_EVENT_DEC_SC_ERR		= 0x21,
 179	VID_API_EVENT_CQ_FIFO_DUMP		= 0x22,
 180	VID_API_EVENT_DBG_FIFO_DUMP		= 0x23,
 181	VID_API_EVENT_DEC_CHECK_RES		= 0x24,
 182	VID_API_EVENT_DEC_CFG_INFO		= 0x25,
 183	VID_API_EVENT_UNSUPPORTED_STREAM	= 0x26,
 184	VID_API_EVENT_PIC_SKIPPED		= 0x27,
 185	VID_API_EVENT_STR_SUSPENDED		= 0x30,
 186	VID_API_EVENT_SNAPSHOT_DONE		= 0x40,
 187	VID_API_EVENT_FW_STATUS                 = 0xF0,
 188	VID_API_EVENT_INVALID			= 0xFF
 189};
 190
 191struct vpu_malone_buffer_desc {
 192	struct vpu_rpc_buffer_desc buffer;
 193	u32 low;
 194	u32 high;
 195};
 196
 197struct vpu_malone_str_buffer {
 198	u32 wptr;
 199	u32 rptr;
 200	u32 start;
 201	u32 end;
 202	u32 lwm;
 203};
 204
 205struct vpu_malone_picth_info {
 206	u32 frame_pitch;
 207};
 208
 209struct vpu_malone_table_desc {
 210	u32 array_base;
 211	u32 size;
 212};
 213
 214struct vpu_malone_dbglog_desc {
 215	u32 addr;
 216	u32 size;
 217	u32 level;
 218	u32 reserved;
 219};
 220
 221struct vpu_malone_udata {
 222	u32 base;
 223	u32 total_size;
 224	u32 slot_size;
 225};
 226
 227struct vpu_malone_buffer_info {
 228	u32 stream_input_mode;
 229	u32 stream_pic_input_count;
 230	u32 stream_pic_parsed_count;
 231	u32 stream_buffer_threshold;
 232	u32 stream_pic_end_flag;
 233};
 234
 235struct vpu_malone_encrypt_info {
 236	u32 rec4key[8];
 237	u32 obfusc;
 238};
 239
 240struct malone_iface {
 241	u32 exec_base_addr;
 242	u32 exec_area_size;
 243	struct vpu_malone_buffer_desc cmd_buffer_desc;
 244	struct vpu_malone_buffer_desc msg_buffer_desc;
 245	u32 cmd_int_enable[VID_API_NUM_STREAMS];
 246	struct vpu_malone_picth_info stream_pitch_info[VID_API_NUM_STREAMS];
 247	u32 stream_config[VID_API_NUM_STREAMS];
 248	struct vpu_malone_table_desc codec_param_tab_desc;
 249	struct vpu_malone_table_desc jpeg_param_tab_desc;
 250	u32 stream_buffer_desc[VID_API_NUM_STREAMS][VID_API_MAX_BUF_PER_STR];
 251	struct vpu_malone_table_desc seq_info_tab_desc;
 252	struct vpu_malone_table_desc pic_info_tab_desc;
 253	struct vpu_malone_table_desc gop_info_tab_desc;
 254	struct vpu_malone_table_desc qmeter_info_tab_desc;
 255	u32 stream_error[VID_API_NUM_STREAMS];
 256	u32 fw_version;
 257	u32 fw_offset;
 258	u32 max_streams;
 259	struct vpu_malone_dbglog_desc dbglog_desc;
 260	struct vpu_rpc_buffer_desc api_cmd_buffer_desc[VID_API_NUM_STREAMS];
 261	struct vpu_malone_udata udata_buffer[VID_API_NUM_STREAMS];
 262	struct vpu_malone_buffer_desc debug_buffer_desc;
 263	struct vpu_malone_buffer_desc eng_access_buff_desc[VID_API_NUM_STREAMS];
 264	u32 encrypt_info[VID_API_NUM_STREAMS];
 265	struct vpu_rpc_system_config system_cfg;
 266	u32 api_version;
 267	struct vpu_malone_buffer_info stream_buff_info[VID_API_NUM_STREAMS];
 268};
 269
 270struct malone_jpg_params {
 271	u32 rotation_angle;
 272	u32 horiz_scale_factor;
 273	u32 vert_scale_factor;
 274	u32 rotation_mode;
 275	u32 rgb_mode;
 276	u32 chunk_mode; /* 0 ~ 1 */
 277	u32 last_chunk; /* 0 ~ 1 */
 278	u32 chunk_rows; /* 0 ~ 255 */
 279	u32 num_bytes;
 280	u32 jpg_crop_x;
 281	u32 jpg_crop_y;
 282	u32 jpg_crop_width;
 283	u32 jpg_crop_height;
 284	u32 jpg_mjpeg_mode;
 285	u32 jpg_mjpeg_interlaced;
 286};
 287
 288struct malone_codec_params {
 289	u32 disp_imm;
 290	u32 fourcc;
 291	u32 codec_version;
 292	u32 frame_rate;
 293	u32 dbglog_enable;
 294	u32 bsdma_lwm;
 295	u32 bbd_coring;
 296	u32 bbd_s_thr_row;
 297	u32 bbd_p_thr_row;
 298	u32 bbd_s_thr_logo_row;
 299	u32 bbd_p_thr_logo_row;
 300	u32 bbd_s_thr_col;
 301	u32 bbd_p_thr_col;
 302	u32 bbd_chr_thr_row;
 303	u32 bbd_chr_thr_col;
 304	u32 bbd_uv_mid_level;
 305	u32 bbd_excl_win_mb_left;
 306	u32 bbd_excl_win_mb_right;
 307};
 308
 309struct malone_padding_scode {
 310	u32 scode_type;
 311	u32 pixelformat;
 312	u32 data[2];
 313};
 314
 315struct malone_fmt_mapping {
 316	u32 pixelformat;
 317	enum vpu_malone_format malone_format;
 318	u32 is_disabled;
 319};
 320
 321struct malone_scode_t {
 322	struct vpu_inst *inst;
 323	struct vb2_buffer *vb;
 324	u32 wptr;
 325	u32 need_data;
 326};
 327
 328struct malone_scode_handler {
 329	u32 pixelformat;
 330	int (*insert_scode_seq)(struct malone_scode_t *scode);
 331	int (*insert_scode_pic)(struct malone_scode_t *scode);
 332};
 333
 334struct vpu_dec_ctrl {
 335	struct malone_codec_params *codec_param;
 336	struct malone_jpg_params *jpg;
 337	void *seq_mem;
 338	void *pic_mem;
 339	void *gop_mem;
 340	void *qmeter_mem;
 341	void *dbglog_mem;
 342	struct vpu_malone_str_buffer __iomem *str_buf[VID_API_NUM_STREAMS];
 343	u32 buf_addr[VID_API_NUM_STREAMS];
 344};
 345
 346static const struct malone_padding_scode *get_padding_scode(u32 type, u32 fmt);
 347
 348u32 vpu_malone_get_data_size(void)
 349{
 350	return sizeof(struct vpu_dec_ctrl);
 351}
 352
 353void vpu_malone_init_rpc(struct vpu_shared_addr *shared,
 354			 struct vpu_buffer *rpc, dma_addr_t boot_addr)
 355{
 356	struct malone_iface *iface;
 357	struct vpu_dec_ctrl *hc;
 358	unsigned long base_phy_addr;
 359	unsigned long phy_addr;
 360	unsigned long offset;
 361	unsigned int i;
 362
 363	if (rpc->phys < boot_addr)
 364		return;
 365
 366	iface = rpc->virt;
 367	base_phy_addr = rpc->phys - boot_addr;
 368	hc = shared->priv;
 369
 370	shared->iface = iface;
 371	shared->boot_addr = boot_addr;
 372
 373	iface->exec_base_addr = base_phy_addr;
 374	iface->exec_area_size = rpc->length;
 375
 376	offset = sizeof(struct malone_iface);
 377	phy_addr = base_phy_addr + offset;
 378
 379	shared->cmd_desc = &iface->cmd_buffer_desc.buffer;
 380	shared->cmd_mem_vir = rpc->virt + offset;
 381	iface->cmd_buffer_desc.buffer.start =
 382	iface->cmd_buffer_desc.buffer.rptr =
 383	iface->cmd_buffer_desc.buffer.wptr = phy_addr;
 384	iface->cmd_buffer_desc.buffer.end = iface->cmd_buffer_desc.buffer.start + CMD_SIZE;
 385	offset += CMD_SIZE;
 386	phy_addr = base_phy_addr + offset;
 387
 388	shared->msg_desc = &iface->msg_buffer_desc.buffer;
 389	shared->msg_mem_vir = rpc->virt + offset;
 390	iface->msg_buffer_desc.buffer.start =
 391	iface->msg_buffer_desc.buffer.wptr =
 392	iface->msg_buffer_desc.buffer.rptr = phy_addr;
 393	iface->msg_buffer_desc.buffer.end = iface->msg_buffer_desc.buffer.start + MSG_SIZE;
 394	offset += MSG_SIZE;
 395	phy_addr = base_phy_addr + offset;
 396
 397	iface->codec_param_tab_desc.array_base = phy_addr;
 398	hc->codec_param = rpc->virt + offset;
 399	offset += CODEC_SIZE;
 400	phy_addr = base_phy_addr + offset;
 401
 402	iface->jpeg_param_tab_desc.array_base = phy_addr;
 403	hc->jpg = rpc->virt + offset;
 404	offset += JPEG_SIZE;
 405	phy_addr = base_phy_addr + offset;
 406
 407	iface->seq_info_tab_desc.array_base = phy_addr;
 408	hc->seq_mem = rpc->virt + offset;
 409	offset += SEQ_SIZE;
 410	phy_addr = base_phy_addr + offset;
 411
 412	iface->pic_info_tab_desc.array_base = phy_addr;
 413	hc->pic_mem = rpc->virt + offset;
 414	offset += PIC_SIZE;
 415	phy_addr = base_phy_addr + offset;
 416
 417	iface->gop_info_tab_desc.array_base = phy_addr;
 418	hc->gop_mem = rpc->virt + offset;
 419	offset += GOP_SIZE;
 420	phy_addr = base_phy_addr + offset;
 421
 422	iface->qmeter_info_tab_desc.array_base = phy_addr;
 423	hc->qmeter_mem = rpc->virt + offset;
 424	offset += QMETER_SIZE;
 425	phy_addr = base_phy_addr + offset;
 426
 427	iface->dbglog_desc.addr = phy_addr;
 428	iface->dbglog_desc.size = DBGLOG_SIZE;
 429	hc->dbglog_mem = rpc->virt + offset;
 430	offset += DBGLOG_SIZE;
 431	phy_addr = base_phy_addr + offset;
 432
 433	for (i = 0; i < VID_API_NUM_STREAMS; i++) {
 434		iface->eng_access_buff_desc[i].buffer.start =
 435		iface->eng_access_buff_desc[i].buffer.wptr =
 436		iface->eng_access_buff_desc[i].buffer.rptr = phy_addr;
 437		iface->eng_access_buff_desc[i].buffer.end =
 438			iface->eng_access_buff_desc[i].buffer.start + ENG_SIZE;
 439		offset += ENG_SIZE;
 440		phy_addr = base_phy_addr + offset;
 441	}
 442
 443	for (i = 0; i < VID_API_NUM_STREAMS; i++) {
 444		iface->encrypt_info[i] = phy_addr;
 445		offset += sizeof(struct vpu_malone_encrypt_info);
 446		phy_addr = base_phy_addr + offset;
 447	}
 448
 449	rpc->bytesused = offset;
 450}
 451
 452void vpu_malone_set_log_buf(struct vpu_shared_addr *shared,
 453			    struct vpu_buffer *log)
 454{
 455	struct malone_iface *iface = shared->iface;
 456
 457	iface->debug_buffer_desc.buffer.start =
 458	iface->debug_buffer_desc.buffer.wptr =
 459	iface->debug_buffer_desc.buffer.rptr = log->phys - shared->boot_addr;
 460	iface->debug_buffer_desc.buffer.end = iface->debug_buffer_desc.buffer.start + log->length;
 461}
 462
 463static u32 get_str_buffer_offset(u32 instance)
 464{
 465	return DEC_MFD_XREG_SLV_BASE + MFD_MCX + MFD_MCX_OFF * instance;
 466}
 467
 468void vpu_malone_set_system_cfg(struct vpu_shared_addr *shared,
 469			       u32 regs_base, void __iomem *regs, u32 core_id)
 470{
 471	struct malone_iface *iface = shared->iface;
 472	struct vpu_rpc_system_config *config = &iface->system_cfg;
 473	struct vpu_dec_ctrl *hc = shared->priv;
 474	int i;
 475
 476	vpu_imx8q_set_system_cfg_common(config, regs_base, core_id);
 477	for (i = 0; i < VID_API_NUM_STREAMS; i++) {
 478		u32 offset = get_str_buffer_offset(i);
 479
 480		hc->buf_addr[i] = regs_base + offset;
 481		hc->str_buf[i] = regs + offset;
 482	}
 483}
 484
 485u32 vpu_malone_get_version(struct vpu_shared_addr *shared)
 486{
 487	struct malone_iface *iface = shared->iface;
 488
 489	vpu_malone_enable_format(V4L2_PIX_FMT_RV30, iface->fw_version & MALONE_DEC_FMT_RV_MASK);
 490	vpu_malone_enable_format(V4L2_PIX_FMT_RV40, iface->fw_version & MALONE_DEC_FMT_RV_MASK);
 491
 492	return iface->fw_version;
 493}
 494
 495int vpu_malone_get_stream_buffer_size(struct vpu_shared_addr *shared)
 496{
 497	return 0xc00000;
 498}
 499
 500int vpu_malone_config_stream_buffer(struct vpu_shared_addr *shared,
 501				    u32 instance,
 502				    struct vpu_buffer *buf)
 503{
 504	struct malone_iface *iface = shared->iface;
 505	struct vpu_dec_ctrl *hc = shared->priv;
 506	struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
 507
 508	writel(buf->phys, &str_buf->start);
 509	writel(buf->phys, &str_buf->rptr);
 510	writel(buf->phys, &str_buf->wptr);
 511	writel(buf->phys + buf->length, &str_buf->end);
 512	writel(0x1, &str_buf->lwm);
 513
 514	iface->stream_buffer_desc[instance][0] = hc->buf_addr[instance];
 515
 516	return 0;
 517}
 518
 519int vpu_malone_get_stream_buffer_desc(struct vpu_shared_addr *shared,
 520				      u32 instance,
 521				      struct vpu_rpc_buffer_desc *desc)
 522{
 523	struct vpu_dec_ctrl *hc = shared->priv;
 524	struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
 525
 526	if (desc) {
 527		desc->wptr = readl(&str_buf->wptr);
 528		desc->rptr = readl(&str_buf->rptr);
 529		desc->start = readl(&str_buf->start);
 530		desc->end = readl(&str_buf->end);
 531	}
 532
 533	return 0;
 534}
 535
 536static void vpu_malone_update_wptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 wptr)
 537{
 538	/*update wptr after data is written*/
 539	mb();
 540	writel(wptr, &str_buf->wptr);
 541}
 542
 543static void vpu_malone_update_rptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 rptr)
 544{
 545	/*update rptr after data is read*/
 546	mb();
 547	writel(rptr, &str_buf->rptr);
 548}
 549
 550int vpu_malone_update_stream_buffer(struct vpu_shared_addr *shared,
 551				    u32 instance, u32 ptr, bool write)
 552{
 553	struct vpu_dec_ctrl *hc = shared->priv;
 554	struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
 555
 556	if (write)
 557		vpu_malone_update_wptr(str_buf, ptr);
 558	else
 559		vpu_malone_update_rptr(str_buf, ptr);
 560
 561	return 0;
 562}
 563
 564static struct malone_fmt_mapping fmt_mappings[] = {
 565	{V4L2_PIX_FMT_H264,        MALONE_FMT_AVC},
 566	{V4L2_PIX_FMT_H264_MVC,    MALONE_FMT_AVC},
 567	{V4L2_PIX_FMT_HEVC,        MALONE_FMT_HEVC},
 568	{V4L2_PIX_FMT_VC1_ANNEX_G, MALONE_FMT_VC1},
 569	{V4L2_PIX_FMT_VC1_ANNEX_L, MALONE_FMT_VC1},
 570	{V4L2_PIX_FMT_MPEG2,       MALONE_FMT_MP2},
 571	{V4L2_PIX_FMT_MPEG4,       MALONE_FMT_ASP},
 572	{V4L2_PIX_FMT_XVID,        MALONE_FMT_ASP},
 573	{V4L2_PIX_FMT_H263,        MALONE_FMT_ASP},
 574	{V4L2_PIX_FMT_JPEG,        MALONE_FMT_JPG},
 575	{V4L2_PIX_FMT_VP8,         MALONE_FMT_VP8},
 576	{V4L2_PIX_FMT_SPK,         MALONE_FMT_SPK},
 577	{V4L2_PIX_FMT_RV30,        MALONE_FMT_RV},
 578	{V4L2_PIX_FMT_RV40,        MALONE_FMT_RV},
 579};
 580
 581void vpu_malone_enable_format(u32 pixelformat, int enable)
 582{
 583	u32 i;
 584
 585	for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) {
 586		if (pixelformat == fmt_mappings[i].pixelformat) {
 587			fmt_mappings[i].is_disabled = enable ? 0 : 1;
 588			return;
 589		}
 590	}
 591}
 592
 593static enum vpu_malone_format vpu_malone_format_remap(u32 pixelformat)
 594{
 595	u32 i;
 596
 597	for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) {
 598		if (fmt_mappings[i].is_disabled)
 599			continue;
 600		if (pixelformat == fmt_mappings[i].pixelformat)
 601			return fmt_mappings[i].malone_format;
 602	}
 603
 604	return MALONE_FMT_NULL;
 605}
 606
 607bool vpu_malone_check_fmt(enum vpu_core_type type, u32 pixelfmt)
 608{
 609	if (!vpu_imx8q_check_fmt(type, pixelfmt))
 610		return false;
 611
 612	if (pixelfmt == V4L2_PIX_FMT_NV12_8L128 || pixelfmt == V4L2_PIX_FMT_NV12_10BE_8L128 ||
 613	    pixelfmt == V4L2_PIX_FMT_NV12M_8L128 || pixelfmt == V4L2_PIX_FMT_NV12M_10BE_8L128)
 614		return true;
 615	if (vpu_malone_format_remap(pixelfmt) == MALONE_FMT_NULL)
 616		return false;
 617
 618	return true;
 619}
 620
 621static void vpu_malone_set_stream_cfg(struct vpu_shared_addr *shared,
 622				      u32 instance,
 623				      enum vpu_malone_format malone_format)
 624{
 625	struct malone_iface *iface = shared->iface;
 626	u32 *curr_str_cfg = &iface->stream_config[instance];
 627
 628	*curr_str_cfg = 0;
 629	STREAM_CONFIG_FORMAT_SET(malone_format, curr_str_cfg);
 630	STREAM_CONFIG_STRBUFIDX_SET(0, curr_str_cfg);
 631	STREAM_CONFIG_NOSEQ_SET(0, curr_str_cfg);
 632	STREAM_CONFIG_DEBLOCK_SET(0, curr_str_cfg);
 633	STREAM_CONFIG_DERING_SET(0, curr_str_cfg);
 634	STREAM_CONFIG_PLAY_MODE_SET(0x3, curr_str_cfg);
 635	STREAM_CONFIG_FS_CTRL_MODE_SET(0x1, curr_str_cfg);
 636	STREAM_CONFIG_ENABLE_DCP_SET(1, curr_str_cfg);
 637	STREAM_CONFIG_NUM_STR_BUF_SET(1, curr_str_cfg);
 638	STREAM_CONFIG_MALONE_USAGE_SET(1, curr_str_cfg);
 639	STREAM_CONFIG_MULTI_VID_SET(0, curr_str_cfg);
 640	STREAM_CONFIG_OBFUSC_EN_SET(0, curr_str_cfg);
 641	STREAM_CONFIG_RC4_EN_SET(0, curr_str_cfg);
 642	STREAM_CONFIG_MCX_SET(1, curr_str_cfg);
 643	STREAM_CONFIG_PES_SET(0, curr_str_cfg);
 644	STREAM_CONFIG_NUM_DBE_SET(1, curr_str_cfg);
 645}
 646
 647static int vpu_malone_set_params(struct vpu_shared_addr *shared,
 648				 u32 instance,
 649				 struct vpu_decode_params *params)
 650{
 651	struct malone_iface *iface = shared->iface;
 652	struct vpu_dec_ctrl *hc = shared->priv;
 653	enum vpu_malone_format malone_format;
 654
 655	malone_format = vpu_malone_format_remap(params->codec_format);
 656	if (WARN_ON(malone_format == MALONE_FMT_NULL))
 657		return -EINVAL;
 658	iface->udata_buffer[instance].base = params->udata.base;
 659	iface->udata_buffer[instance].slot_size = params->udata.size;
 660
 661	vpu_malone_set_stream_cfg(shared, instance, malone_format);
 662
 663	if (malone_format == MALONE_FMT_JPG) {
 664		//1:JPGD_MJPEG_MODE_A; 2:JPGD_MJPEG_MODE_B
 665		hc->jpg[instance].jpg_mjpeg_mode = 1;
 666		//0: JPGD_MJPEG_PROGRESSIVE
 667		hc->jpg[instance].jpg_mjpeg_interlaced = 0;
 668	}
 669
 670	if (params->display_delay_enable &&
 671	    get_padding_scode(SCODE_PADDING_BUFFLUSH, params->codec_format))
 672		hc->codec_param[instance].disp_imm = 1;
 673	else
 674		hc->codec_param[instance].disp_imm = 0;
 675
 676	if (params->codec_format == V4L2_PIX_FMT_HEVC && !CHECK_VERSION(iface, 1, 9))
 677		hc->codec_param[instance].disp_imm = 0;
 678
 679	hc->codec_param[instance].dbglog_enable = 0;
 680	iface->dbglog_desc.level = 0;
 681
 682	if (params->b_non_frame)
 683		iface->stream_buff_info[instance].stream_input_mode = NON_FRAME_LVL;
 684	else
 685		iface->stream_buff_info[instance].stream_input_mode = FRAME_LVL;
 686	iface->stream_buff_info[instance].stream_buffer_threshold = 0;
 687	iface->stream_buff_info[instance].stream_pic_input_count = 0;
 688
 689	return 0;
 690}
 691
 692static bool vpu_malone_is_non_frame_mode(struct vpu_shared_addr *shared, u32 instance)
 693{
 694	struct malone_iface *iface = shared->iface;
 695
 696	if (iface->stream_buff_info[instance].stream_input_mode == NON_FRAME_LVL)
 697		return true;
 698
 699	return false;
 700}
 701
 702static int vpu_malone_update_params(struct vpu_shared_addr *shared,
 703				    u32 instance,
 704				    struct vpu_decode_params *params)
 705{
 706	struct malone_iface *iface = shared->iface;
 707
 708	if (params->end_flag)
 709		iface->stream_buff_info[instance].stream_pic_end_flag = params->end_flag;
 710	params->end_flag = 0;
 711
 712	return 0;
 713}
 714
 715int vpu_malone_set_decode_params(struct vpu_shared_addr *shared,
 716				 u32 instance,
 717				 struct vpu_decode_params *params,
 718				 u32 update)
 719{
 720	if (!params)
 721		return -EINVAL;
 722
 723	if (!update)
 724		return vpu_malone_set_params(shared, instance, params);
 725	else
 726		return vpu_malone_update_params(shared, instance, params);
 727}
 728
 729static struct vpu_pair malone_cmds[] = {
 730	{VPU_CMD_ID_NOOP, VID_API_CMD_NULL},
 731	{VPU_CMD_ID_START, VID_API_CMD_START},
 732	{VPU_CMD_ID_STOP, VID_API_CMD_STOP},
 733	{VPU_CMD_ID_ABORT, VID_API_CMD_ABORT},
 734	{VPU_CMD_ID_RST_BUF, VID_API_CMD_RST_BUF},
 735	{VPU_CMD_ID_SNAPSHOT, VID_API_CMD_SNAPSHOT},
 736	{VPU_CMD_ID_FIRM_RESET, VID_API_CMD_FIRM_RESET},
 737	{VPU_CMD_ID_FS_ALLOC, VID_API_CMD_FS_ALLOC},
 738	{VPU_CMD_ID_FS_RELEASE, VID_API_CMD_FS_RELEASE},
 739	{VPU_CMD_ID_TIMESTAMP, VID_API_CMD_TS},
 740	{VPU_CMD_ID_DEBUG, VID_API_CMD_FW_STATUS},
 741};
 742
 743static struct vpu_pair malone_msgs[] = {
 744	{VPU_MSG_ID_RESET_DONE, VID_API_EVENT_RESET_DONE},
 745	{VPU_MSG_ID_START_DONE, VID_API_EVENT_START_DONE},
 746	{VPU_MSG_ID_STOP_DONE, VID_API_EVENT_STOPPED},
 747	{VPU_MSG_ID_ABORT_DONE, VID_API_EVENT_ABORT_DONE},
 748	{VPU_MSG_ID_BUF_RST, VID_API_EVENT_STR_BUF_RST},
 749	{VPU_MSG_ID_PIC_EOS, VID_API_EVENT_FINISHED},
 750	{VPU_MSG_ID_SEQ_HDR_FOUND, VID_API_EVENT_SEQ_HDR_FOUND},
 751	{VPU_MSG_ID_RES_CHANGE, VID_API_EVENT_RES_CHANGE},
 752	{VPU_MSG_ID_PIC_HDR_FOUND, VID_API_EVENT_PIC_HDR_FOUND},
 753	{VPU_MSG_ID_PIC_DECODED, VID_API_EVENT_PIC_DECODED},
 754	{VPU_MSG_ID_DEC_DONE, VID_API_EVENT_FRAME_BUFF_RDY},
 755	{VPU_MSG_ID_FRAME_REQ, VID_API_EVENT_REQ_FRAME_BUFF},
 756	{VPU_MSG_ID_FRAME_RELEASE, VID_API_EVENT_REL_FRAME_BUFF},
 757	{VPU_MSG_ID_FIFO_LOW, VID_API_EVENT_FIFO_LOW},
 758	{VPU_MSG_ID_BS_ERROR, VID_API_EVENT_BS_ERROR},
 759	{VPU_MSG_ID_UNSUPPORTED, VID_API_EVENT_UNSUPPORTED_STREAM},
 760	{VPU_MSG_ID_FIRMWARE_XCPT, VID_API_EVENT_FIRMWARE_XCPT},
 761	{VPU_MSG_ID_PIC_SKIPPED, VID_API_EVENT_PIC_SKIPPED},
 762	{VPU_MSG_ID_DBG_MSG, VID_API_EVENT_DBG_MSG_DEC},
 763};
 764
 765static void vpu_malone_pack_fs_alloc(struct vpu_rpc_event *pkt,
 766				     struct vpu_fs_info *fs)
 767{
 768	const u32 fs_type[] = {
 769		[MEM_RES_FRAME] = 0,
 770		[MEM_RES_MBI] = 1,
 771		[MEM_RES_DCP] = 2,
 772	};
 773
 774	pkt->hdr.num = 7;
 775	pkt->data[0] = fs->id | (fs->tag << 24);
 776	pkt->data[1] = fs->luma_addr;
 777	if (fs->type == MEM_RES_FRAME) {
 778		/*
 779		 * if luma_addr equal to chroma_addr,
 780		 * means luma(plane[0]) and chromau(plane[1]) used the
 781		 * same fd -- usage of NXP codec2. Need to manually
 782		 * offset chroma addr.
 783		 */
 784		if (fs->luma_addr == fs->chroma_addr)
 785			fs->chroma_addr = fs->luma_addr + fs->luma_size;
 786		pkt->data[2] = fs->luma_addr + fs->luma_size / 2;
 787		pkt->data[3] = fs->chroma_addr;
 788		pkt->data[4] = fs->chroma_addr + fs->chromau_size / 2;
 789		pkt->data[5] = fs->bytesperline;
 790	} else {
 791		pkt->data[2] = fs->luma_size;
 792		pkt->data[3] = 0;
 793		pkt->data[4] = 0;
 794		pkt->data[5] = 0;
 795	}
 796	pkt->data[6] = fs_type[fs->type];
 797}
 798
 799static void vpu_malone_pack_fs_release(struct vpu_rpc_event *pkt,
 800				       struct vpu_fs_info *fs)
 801{
 802	pkt->hdr.num = 1;
 803	pkt->data[0] = fs->id | (fs->tag << 24);
 804}
 805
 806static void vpu_malone_pack_timestamp(struct vpu_rpc_event *pkt,
 807				      struct vpu_ts_info *info)
 808{
 809	struct timespec64 ts = ns_to_timespec64(info->timestamp);
 810
 811	pkt->hdr.num = 3;
 812
 813	pkt->data[0] = ts.tv_sec;
 814	pkt->data[1] = ts.tv_nsec;
 815	pkt->data[2] = info->size;
 816}
 817
 818int vpu_malone_pack_cmd(struct vpu_rpc_event *pkt, u32 index, u32 id, void *data)
 819{
 820	int ret;
 821
 822	ret = vpu_find_dst_by_src(malone_cmds, ARRAY_SIZE(malone_cmds), id);
 823	if (ret < 0)
 824		return ret;
 825
 826	pkt->hdr.id = ret;
 827	pkt->hdr.num = 0;
 828	pkt->hdr.index = index;
 829
 830	switch (id) {
 831	case VPU_CMD_ID_FS_ALLOC:
 832		vpu_malone_pack_fs_alloc(pkt, data);
 833		break;
 834	case VPU_CMD_ID_FS_RELEASE:
 835		vpu_malone_pack_fs_release(pkt, data);
 836		break;
 837	case VPU_CMD_ID_TIMESTAMP:
 838		vpu_malone_pack_timestamp(pkt, data);
 839		break;
 840	}
 841
 842	pkt->hdr.index = index;
 843	return 0;
 844}
 845
 846int vpu_malone_convert_msg_id(u32 id)
 847{
 848	return vpu_find_src_by_dst(malone_msgs, ARRAY_SIZE(malone_msgs), id);
 849}
 850
 851static void vpu_malone_fill_planes(struct vpu_dec_codec_info *info)
 852{
 853	u32 interlaced = info->progressive ? 0 : 1;
 854
 855	info->bytesperline[0] = 0;
 856	info->sizeimage[0] = vpu_helper_get_plane_size(info->pixfmt,
 857						       info->decoded_width,
 858						       info->decoded_height,
 859						       0,
 860						       info->stride,
 861						       interlaced,
 862						       &info->bytesperline[0]);
 863	info->bytesperline[1] = 0;
 864	info->sizeimage[1] = vpu_helper_get_plane_size(info->pixfmt,
 865						       info->decoded_width,
 866						       info->decoded_height,
 867						       1,
 868						       info->stride,
 869						       interlaced,
 870						       &info->bytesperline[1]);
 871}
 872
 873static void vpu_malone_init_seq_hdr(struct vpu_dec_codec_info *info)
 874{
 875	u32 chunks = info->num_dfe_area >> MALONE_DCP_CHUNK_BIT;
 876
 877	vpu_malone_fill_planes(info);
 878
 879	info->mbi_size = (info->sizeimage[0] + info->sizeimage[1]) >> 2;
 880	info->mbi_size = ALIGN(info->mbi_size, MALONE_ALIGN_MBI);
 881
 882	info->dcp_size = MALONE_DCP_SIZE_MAX;
 883	if (chunks) {
 884		u32 mb_num;
 885		u32 mb_w;
 886		u32 mb_h;
 887
 888		mb_w = DIV_ROUND_UP(info->decoded_width, 16);
 889		mb_h = DIV_ROUND_UP(info->decoded_height, 16);
 890		mb_num = mb_w * mb_h;
 891		info->dcp_size = mb_num * MALONE_DCP_FIXED_MB_ALLOC * chunks;
 892		info->dcp_size = clamp_t(u32, info->dcp_size,
 893					 MALONE_DCP_SIZE_MIN, MALONE_DCP_SIZE_MAX);
 894	}
 895}
 896
 897static void vpu_malone_unpack_seq_hdr(struct vpu_rpc_event *pkt,
 898				      struct vpu_dec_codec_info *info)
 899{
 900	info->num_ref_frms = pkt->data[0];
 901	info->num_dpb_frms = pkt->data[1];
 902	info->num_dfe_area = pkt->data[2];
 903	info->progressive = pkt->data[3];
 904	info->width = pkt->data[5];
 905	info->height = pkt->data[4];
 906	info->decoded_width = pkt->data[12];
 907	info->decoded_height = pkt->data[11];
 908	info->frame_rate.numerator = 1000;
 909	info->frame_rate.denominator = pkt->data[8];
 910	info->dsp_asp_ratio = pkt->data[9];
 911	info->profile_idc = (pkt->data[10] >> 8) & 0xff;
 912	info->level_idc = pkt->data[10] & 0xff;
 913	info->bit_depth_luma = pkt->data[13];
 914	info->bit_depth_chroma = pkt->data[14];
 915	info->chroma_fmt = pkt->data[15];
 916	info->color_primaries = vpu_color_cvrt_primaries_i2v(pkt->data[16]);
 917	info->transfer_chars = vpu_color_cvrt_transfers_i2v(pkt->data[17]);
 918	info->matrix_coeffs = vpu_color_cvrt_matrix_i2v(pkt->data[18]);
 919	info->full_range = vpu_color_cvrt_full_range_i2v(pkt->data[19]);
 920	info->vui_present = pkt->data[20];
 921	info->mvc_num_views = pkt->data[21];
 922	info->offset_x = pkt->data[23];
 923	info->offset_y = pkt->data[25];
 924	info->tag = pkt->data[27];
 925	if (info->bit_depth_luma > 8)
 926		info->pixfmt = V4L2_PIX_FMT_NV12M_10BE_8L128;
 927	else
 928		info->pixfmt = V4L2_PIX_FMT_NV12M_8L128;
 929	if (pkt->hdr.num > 28)
 930		info->constraint_set_flags = pkt->data[28];
 931	if (info->frame_rate.numerator && info->frame_rate.denominator) {
 932		unsigned long n, d;
 933
 934		rational_best_approximation(info->frame_rate.numerator,
 935					    info->frame_rate.denominator,
 936					    info->frame_rate.numerator,
 937					    info->frame_rate.denominator,
 938					    &n, &d);
 939		info->frame_rate.numerator = n;
 940		info->frame_rate.denominator = d;
 941	}
 942	vpu_malone_init_seq_hdr(info);
 943}
 944
 945static void vpu_malone_unpack_pic_info(struct vpu_rpc_event *pkt,
 946				       struct vpu_dec_pic_info *info)
 947{
 948	info->id = pkt->data[7];
 949	info->luma = pkt->data[0];
 950	info->start = pkt->data[10];
 951	info->end = pkt->data[12];
 952	info->pic_size = pkt->data[11];
 953	info->stride = pkt->data[5];
 954	info->consumed_count = pkt->data[13];
 955	if (info->id == MALONE_SKIPPED_FRAME_ID)
 956		info->skipped = 1;
 957	else
 958		info->skipped = 0;
 959}
 960
 961static void vpu_malone_unpack_req_frame(struct vpu_rpc_event *pkt,
 962					struct vpu_fs_info *info)
 963{
 964	info->type = pkt->data[1];
 965}
 966
 967static void vpu_malone_unpack_rel_frame(struct vpu_rpc_event *pkt,
 968					struct vpu_fs_info *info)
 969{
 970	info->id = pkt->data[0];
 971	info->type = pkt->data[1];
 972	info->not_displayed = pkt->data[2];
 973}
 974
 975static void vpu_malone_unpack_buff_rdy(struct vpu_rpc_event *pkt,
 976				       struct vpu_dec_pic_info *info)
 977{
 978	struct timespec64 ts = { pkt->data[9], pkt->data[10] };
 979
 980	info->id = pkt->data[0];
 981	info->luma = pkt->data[1];
 982	info->stride = pkt->data[3];
 983	if (info->id == MALONE_SKIPPED_FRAME_ID)
 984		info->skipped = 1;
 985	else
 986		info->skipped = 0;
 987
 988	info->timestamp = timespec64_to_ns(&ts);
 989}
 990
 991int vpu_malone_unpack_msg_data(struct vpu_rpc_event *pkt, void *data)
 992{
 993	if (!pkt || !data)
 994		return -EINVAL;
 995
 996	switch (pkt->hdr.id) {
 997	case VID_API_EVENT_SEQ_HDR_FOUND:
 998		vpu_malone_unpack_seq_hdr(pkt, data);
 999		break;
1000	case VID_API_EVENT_PIC_DECODED:
1001		vpu_malone_unpack_pic_info(pkt, data);
1002		break;
1003	case VID_API_EVENT_REQ_FRAME_BUFF:
1004		vpu_malone_unpack_req_frame(pkt, data);
1005		break;
1006	case VID_API_EVENT_REL_FRAME_BUFF:
1007		vpu_malone_unpack_rel_frame(pkt, data);
1008		break;
1009	case VID_API_EVENT_FRAME_BUFF_RDY:
1010		vpu_malone_unpack_buff_rdy(pkt, data);
1011		break;
1012	}
1013
1014	return 0;
1015}
1016
1017static const struct malone_padding_scode padding_scodes[] = {
1018	{SCODE_PADDING_EOS,      V4L2_PIX_FMT_H264,        {0x0B010000, 0}},
1019	{SCODE_PADDING_EOS,      V4L2_PIX_FMT_H264_MVC,    {0x0B010000, 0}},
1020	{SCODE_PADDING_EOS,      V4L2_PIX_FMT_HEVC,        {0x4A010000, 0x20}},
1021	{SCODE_PADDING_EOS,      V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}},
1022	{SCODE_PADDING_EOS,      V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}},
1023	{SCODE_PADDING_EOS,      V4L2_PIX_FMT_MPEG2,       {0xCC010000, 0x0}},
1024	{SCODE_PADDING_EOS,      V4L2_PIX_FMT_MPEG4,       {0xb1010000, 0x0}},
1025	{SCODE_PADDING_EOS,      V4L2_PIX_FMT_XVID,        {0xb1010000, 0x0}},
1026	{SCODE_PADDING_EOS,      V4L2_PIX_FMT_H263,        {0xb1010000, 0x0}},
1027	{SCODE_PADDING_EOS,      V4L2_PIX_FMT_VP8,         {0x34010000, 0x0}},
1028	{SCODE_PADDING_EOS,      V4L2_PIX_FMT_SPK,         {0x34010000, 0x0}},
1029	{SCODE_PADDING_EOS,      V4L2_PIX_FMT_RV30,        {0x34010000, 0x0}},
1030	{SCODE_PADDING_EOS,      V4L2_PIX_FMT_RV40,        {0x34010000, 0x0}},
1031	{SCODE_PADDING_EOS,      V4L2_PIX_FMT_JPEG,        {0xefff0000, 0x0}},
1032	{SCODE_PADDING_ABORT,    V4L2_PIX_FMT_H264,        {0x0B010000, 0}},
1033	{SCODE_PADDING_ABORT,    V4L2_PIX_FMT_H264_MVC,    {0x0B010000, 0}},
1034	{SCODE_PADDING_ABORT,    V4L2_PIX_FMT_HEVC,        {0x4A010000, 0x20}},
1035	{SCODE_PADDING_ABORT,    V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}},
1036	{SCODE_PADDING_ABORT,    V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}},
1037	{SCODE_PADDING_ABORT,    V4L2_PIX_FMT_MPEG2,       {0xb7010000, 0x0}},
1038	{SCODE_PADDING_ABORT,    V4L2_PIX_FMT_MPEG4,       {0xb1010000, 0x0}},
1039	{SCODE_PADDING_ABORT,    V4L2_PIX_FMT_XVID,        {0xb1010000, 0x0}},
1040	{SCODE_PADDING_ABORT,    V4L2_PIX_FMT_H263,        {0xb1010000, 0x0}},
1041	{SCODE_PADDING_ABORT,    V4L2_PIX_FMT_VP8,         {0x34010000, 0x0}},
1042	{SCODE_PADDING_ABORT,    V4L2_PIX_FMT_SPK,         {0x34010000, 0x0}},
1043	{SCODE_PADDING_ABORT,    V4L2_PIX_FMT_RV30,        {0x34010000, 0x0}},
1044	{SCODE_PADDING_ABORT,    V4L2_PIX_FMT_RV40,        {0x34010000, 0x0}},
1045	{SCODE_PADDING_EOS,      V4L2_PIX_FMT_JPEG,        {0x0, 0x0}},
1046	{SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264,        {0x15010000, 0x0}},
1047	{SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264_MVC,    {0x15010000, 0x0}},
1048	{SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_HEVC,        {0x3e010000, 0x20}},
1049};
1050
1051static const struct malone_padding_scode padding_scode_dft = {0x0, 0x0};
1052
1053static const struct malone_padding_scode *get_padding_scode(u32 type, u32 fmt)
1054{
1055	const struct malone_padding_scode *s;
1056	int i;
1057
1058	for (i = 0; i < ARRAY_SIZE(padding_scodes); i++) {
1059		s = &padding_scodes[i];
1060
1061		if (s->scode_type == type && s->pixelformat == fmt)
1062			return s;
1063	}
1064
1065	if (type != SCODE_PADDING_BUFFLUSH)
1066		return &padding_scode_dft;
1067
1068	return NULL;
1069}
1070
1071static int vpu_malone_add_padding_scode(struct vpu_buffer *stream_buffer,
1072					struct vpu_malone_str_buffer __iomem *str_buf,
1073					u32 pixelformat, u32 scode_type)
1074{
1075	u32 wptr;
1076	int size;
1077	int total_size = 0;
1078	const struct malone_padding_scode *ps;
1079	const u32 padding_size = 4096;
1080	int ret;
1081
1082	ps = get_padding_scode(scode_type, pixelformat);
1083	if (!ps) {
1084		if (scode_type == SCODE_PADDING_BUFFLUSH)
1085			return 0;
1086		return -EINVAL;
1087	}
1088
1089	wptr = readl(&str_buf->wptr);
1090	if (wptr < stream_buffer->phys || wptr > stream_buffer->phys + stream_buffer->length)
1091		return -EINVAL;
1092	if (wptr == stream_buffer->phys + stream_buffer->length)
1093		wptr = stream_buffer->phys;
1094	size = ALIGN(wptr, 4) - wptr;
1095	if (size)
1096		vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size);
1097	total_size += size;
1098
1099	size = sizeof(ps->data);
1100	ret = vpu_helper_copy_to_stream_buffer(stream_buffer, &wptr, size, (void *)ps->data);
1101	if (ret < 0)
1102		return -EINVAL;
1103	total_size += size;
1104
1105	size = padding_size - sizeof(ps->data);
1106	vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size);
1107	total_size += size;
1108
1109	vpu_malone_update_wptr(str_buf, wptr);
1110	return total_size;
1111}
1112
1113int vpu_malone_add_scode(struct vpu_shared_addr *shared,
1114			 u32 instance,
1115			 struct vpu_buffer *stream_buffer,
1116			 u32 pixelformat,
1117			 u32 scode_type)
1118{
1119	struct vpu_dec_ctrl *hc = shared->priv;
1120	struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
1121	int ret = -EINVAL;
1122
1123	switch (scode_type) {
1124	case SCODE_PADDING_EOS:
1125	case SCODE_PADDING_ABORT:
1126	case SCODE_PADDING_BUFFLUSH:
1127		ret = vpu_malone_add_padding_scode(stream_buffer, str_buf, pixelformat, scode_type);
1128		break;
1129	default:
1130		break;
1131	}
1132
1133	return ret;
1134}
1135
1136#define MALONE_PAYLOAD_HEADER_SIZE		16
1137#define MALONE_CODEC_VERSION_ID			0x1
1138#define MALONE_CODEC_ID_VC1_SIMPLE		0x10
1139#define MALONE_CODEC_ID_VC1_MAIN		0x11
1140#define MALONE_CODEC_ID_ARV8			0x28
1141#define MALONE_CODEC_ID_ARV9			0x29
1142#define MALONE_CODEC_ID_VP6			0x36
1143#define MALONE_CODEC_ID_VP8			0x36
1144#define MALONE_CODEC_ID_DIVX3			0x38
1145#define MALONE_CODEC_ID_SPK			0x39
1146
1147#define MALONE_VP8_IVF_SEQ_HEADER_LEN		32
1148#define MALONE_VP8_IVF_FRAME_HEADER_LEN		8
1149
1150#define MALONE_VC1_RCV_CODEC_V1_VERSION		0x85
1151#define MALONE_VC1_RCV_CODEC_V2_VERSION		0xC5
1152#define MALONE_VC1_RCV_NUM_FRAMES		0xFF
1153#define MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE	4
1154#define MALONE_VC1_RCV_SEQ_HEADER_LEN		20
1155#define MALONE_VC1_RCV_PIC_HEADER_LEN		4
1156#define MALONE_VC1_NAL_HEADER_LEN		4
1157#define MALONE_VC1_CONTAIN_NAL(data)		(((data) & 0x00FFFFFF) == 0x00010000)
1158
1159static void set_payload_hdr(u8 *dst, u32 scd_type, u32 codec_id,
1160			    u32 buffer_size, u32 width, u32 height)
1161{
1162	unsigned int payload_size;
1163	/* payload_size = buffer_size + itself_size(16) - start_code(4) */
1164	payload_size = buffer_size + 12;
1165
1166	dst[0] = 0x00;
1167	dst[1] = 0x00;
1168	dst[2] = 0x01;
1169	dst[3] = scd_type;
1170
1171	/* length */
1172	dst[4] = ((payload_size >> 16) & 0xff);
1173	dst[5] = ((payload_size >> 8) & 0xff);
1174	dst[6] = 0x4e;
1175	dst[7] = ((payload_size >> 0) & 0xff);
1176
1177	/* Codec ID and Version */
1178	dst[8] = codec_id;
1179	dst[9] = MALONE_CODEC_VERSION_ID;
1180
1181	/* width */
1182	dst[10] = ((width >> 8) & 0xff);
1183	dst[11] = ((width >> 0) & 0xff);
1184	dst[12] = 0x58;
1185
1186	/* height */
1187	dst[13] = ((height >> 8) & 0xff);
1188	dst[14] = ((height >> 0) & 0xff);
1189	dst[15] = 0x50;
1190}
1191
1192static void set_vp8_ivf_seqhdr(u8 *dst, u32 width, u32 height)
1193{
1194	/* 0-3byte signature "DKIF" */
1195	dst[0] = 0x44;
1196	dst[1] = 0x4b;
1197	dst[2] = 0x49;
1198	dst[3] = 0x46;
1199	/* 4-5byte version: should be 0*/
1200	dst[4] = 0x00;
1201	dst[5] = 0x00;
1202	/* 6-7 length of Header */
1203	dst[6] = MALONE_VP8_IVF_SEQ_HEADER_LEN;
1204	dst[7] = MALONE_VP8_IVF_SEQ_HEADER_LEN >> 8;
1205	/* 8-11 VP8 fourcc */
1206	dst[8] = 0x56;
1207	dst[9] = 0x50;
1208	dst[10] = 0x38;
1209	dst[11] = 0x30;
1210	/* 12-13 width in pixels */
1211	dst[12] = width;
1212	dst[13] = width >> 8;
1213	/* 14-15 height in pixels */
1214	dst[14] = height;
1215	dst[15] = height >> 8;
1216	/* 16-19 frame rate */
1217	dst[16] = 0xe8;
1218	dst[17] = 0x03;
1219	dst[18] = 0x00;
1220	dst[19] = 0x00;
1221	/* 20-23 time scale */
1222	dst[20] = 0x01;
1223	dst[21] = 0x00;
1224	dst[22] = 0x00;
1225	dst[23] = 0x00;
1226	/* 24-27 number frames */
1227	dst[24] = 0xdf;
1228	dst[25] = 0xf9;
1229	dst[26] = 0x09;
1230	dst[27] = 0x00;
1231	/* 28-31 reserved */
1232}
1233
1234static void set_vp8_ivf_pichdr(u8 *dst, u32 frame_size)
1235{
1236	/*
1237	 * firmware just parse 64-bit timestamp(8 bytes).
1238	 * As not transfer timestamp to firmware, use default value(ZERO).
1239	 * No need to do anything here
1240	 */
1241}
1242
1243static void set_vc1_rcv_seqhdr(u8 *dst, u8 *src, u32 width, u32 height)
1244{
1245	u32 frames = MALONE_VC1_RCV_NUM_FRAMES;
1246	u32 ext_data_size = MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE;
1247
1248	/* 0-2 Number of frames, used default value 0xFF */
1249	dst[0] = frames;
1250	dst[1] = frames >> 8;
1251	dst[2] = frames >> 16;
1252
1253	/* 3 RCV version, used V1 */
1254	dst[3] = MALONE_VC1_RCV_CODEC_V1_VERSION;
1255
1256	/* 4-7 extension data size */
1257	dst[4] = ext_data_size;
1258	dst[5] = ext_data_size >> 8;
1259	dst[6] = ext_data_size >> 16;
1260	dst[7] = ext_data_size >> 24;
1261	/* 8-11 extension data */
1262	dst[8] = src[0];
1263	dst[9] = src[1];
1264	dst[10] = src[2];
1265	dst[11] = src[3];
1266
1267	/* height */
1268	dst[12] = height;
1269	dst[13] = (height >> 8) & 0xff;
1270	dst[14] = (height >> 16) & 0xff;
1271	dst[15] = (height >> 24) & 0xff;
1272	/* width */
1273	dst[16] = width;
1274	dst[17] = (width >> 8) & 0xff;
1275	dst[18] = (width >> 16) & 0xff;
1276	dst[19] = (width >> 24) & 0xff;
1277}
1278
1279static void set_vc1_rcv_pichdr(u8 *dst, u32 buffer_size)
1280{
1281	dst[0] = buffer_size;
1282	dst[1] = buffer_size >> 8;
1283	dst[2] = buffer_size >> 16;
1284	dst[3] = buffer_size >> 24;
1285}
1286
1287static void create_vc1_nal_pichdr(u8 *dst)
1288{
1289	/* need insert nal header: special ID */
1290	dst[0] = 0x0;
1291	dst[1] = 0x0;
1292	dst[2] = 0x01;
1293	dst[3] = 0x0D;
1294}
1295
1296static int vpu_malone_insert_scode_seq(struct malone_scode_t *scode, u32 codec_id, u32 ext_size)
1297{
1298	u8 hdr[MALONE_PAYLOAD_HEADER_SIZE];
1299	int ret;
1300
1301	set_payload_hdr(hdr,
1302			SCODE_SEQUENCE,
1303			codec_id,
1304			ext_size,
1305			scode->inst->out_format.width,
1306			scode->inst->out_format.height);
1307	ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1308					       &scode->wptr,
1309					       sizeof(hdr),
1310					       hdr);
1311	if (ret < 0)
1312		return ret;
1313	return sizeof(hdr);
1314}
1315
1316static int vpu_malone_insert_scode_pic(struct malone_scode_t *scode, u32 codec_id, u32 ext_size)
1317{
1318	u8 hdr[MALONE_PAYLOAD_HEADER_SIZE];
1319	int ret;
1320
1321	set_payload_hdr(hdr,
1322			SCODE_PICTURE,
1323			codec_id,
1324			ext_size + vb2_get_plane_payload(scode->vb, 0),
1325			scode->inst->out_format.width,
1326			scode->inst->out_format.height);
1327	ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1328					       &scode->wptr,
1329					       sizeof(hdr),
1330					       hdr);
1331	if (ret < 0)
1332		return ret;
1333	return sizeof(hdr);
1334}
1335
1336static int vpu_malone_insert_scode_vc1_g_seq(struct malone_scode_t *scode)
1337{
1338	if (!scode->inst->total_input_count)
1339		return 0;
1340	return 0;
1341}
1342
1343static int vpu_malone_insert_scode_vc1_g_pic(struct malone_scode_t *scode)
1344{
1345	u8 nal_hdr[MALONE_VC1_NAL_HEADER_LEN];
1346	u32 *data = NULL;
1347	int ret;
1348
1349	data = vb2_plane_vaddr(scode->vb, 0);
1350
1351	if (scode->inst->total_input_count == 0)
1352		return 0;
1353	if (MALONE_VC1_CONTAIN_NAL(*data))
1354		return 0;
1355
1356	create_vc1_nal_pichdr(nal_hdr);
1357	ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1358					       &scode->wptr,
1359					       sizeof(nal_hdr),
1360					       nal_hdr);
1361	if (ret < 0)
1362		return ret;
1363	return sizeof(nal_hdr);
1364}
1365
1366static int vpu_malone_insert_scode_vc1_l_seq(struct malone_scode_t *scode)
1367{
1368	int ret;
1369	int size = 0;
1370	u8 rcv_seqhdr[MALONE_VC1_RCV_SEQ_HEADER_LEN];
1371
1372	if (scode->inst->total_input_count)
1373		return 0;
1374	scode->need_data = 0;
1375
1376	ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VC1_SIMPLE, sizeof(rcv_seqhdr));
1377	if (ret < 0)
1378		return ret;
1379	size = ret;
1380
1381	set_vc1_rcv_seqhdr(rcv_seqhdr,
1382			   vb2_plane_vaddr(scode->vb, 0),
1383			   scode->inst->out_format.width,
1384			   scode->inst->out_format.height);
1385	ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1386					       &scode->wptr,
1387					       sizeof(rcv_seqhdr),
1388					       rcv_seqhdr);
1389
1390	if (ret < 0)
1391		return ret;
1392	size += sizeof(rcv_seqhdr);
1393	return size;
1394}
1395
1396static int vpu_malone_insert_scode_vc1_l_pic(struct malone_scode_t *scode)
1397{
1398	int ret;
1399	int size = 0;
1400	u8 rcv_pichdr[MALONE_VC1_RCV_PIC_HEADER_LEN];
1401
1402	ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VC1_SIMPLE,
1403					  sizeof(rcv_pichdr));
1404	if (ret < 0)
1405		return ret;
1406	size = ret;
1407
1408	set_vc1_rcv_pichdr(rcv_pichdr, vb2_get_plane_payload(scode->vb, 0));
1409	ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1410					       &scode->wptr,
1411					       sizeof(rcv_pichdr),
1412					       rcv_pichdr);
1413	if (ret < 0)
1414		return ret;
1415	size += sizeof(rcv_pichdr);
1416	return size;
1417}
1418
1419static int vpu_malone_insert_scode_vp8_seq(struct malone_scode_t *scode)
1420{
1421	int ret;
1422	int size = 0;
1423	u8 ivf_hdr[MALONE_VP8_IVF_SEQ_HEADER_LEN];
1424
1425	ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr));
1426	if (ret < 0)
1427		return ret;
1428	size = ret;
1429
1430	set_vp8_ivf_seqhdr(ivf_hdr,
1431			   scode->inst->out_format.width,
1432			   scode->inst->out_format.height);
1433	ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1434					       &scode->wptr,
1435					       sizeof(ivf_hdr),
1436					       ivf_hdr);
1437	if (ret < 0)
1438		return ret;
1439	size += sizeof(ivf_hdr);
1440
1441	return size;
1442}
1443
1444static int vpu_malone_insert_scode_vp8_pic(struct malone_scode_t *scode)
1445{
1446	int ret;
1447	int size = 0;
1448	u8 ivf_hdr[MALONE_VP8_IVF_FRAME_HEADER_LEN] = {0};
1449
1450	ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr));
1451	if (ret < 0)
1452		return ret;
1453	size = ret;
1454
1455	set_vp8_ivf_pichdr(ivf_hdr, vb2_get_plane_payload(scode->vb, 0));
1456	ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1457					       &scode->wptr,
1458					       sizeof(ivf_hdr),
1459					       ivf_hdr);
1460	if (ret < 0)
1461		return ret;
1462	size += sizeof(ivf_hdr);
1463
1464	return size;
1465}
1466
1467static int vpu_malone_insert_scode_spk_seq(struct malone_scode_t *scode)
1468{
1469	return vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_SPK, 0);
1470}
1471
1472static int vpu_malone_insert_scode_spk_pic(struct malone_scode_t *scode)
1473{
1474	return vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_SPK, 0);
1475}
1476
1477static const struct malone_scode_handler scode_handlers[] = {
1478	{
1479		/* fix me, need to swap return operation after gstreamer swap */
1480		.pixelformat = V4L2_PIX_FMT_VC1_ANNEX_L,
1481		.insert_scode_seq = vpu_malone_insert_scode_vc1_l_seq,
1482		.insert_scode_pic = vpu_malone_insert_scode_vc1_l_pic,
1483	},
1484	{
1485		.pixelformat = V4L2_PIX_FMT_VC1_ANNEX_G,
1486		.insert_scode_seq = vpu_malone_insert_scode_vc1_g_seq,
1487		.insert_scode_pic = vpu_malone_insert_scode_vc1_g_pic,
1488	},
1489	{
1490		.pixelformat = V4L2_PIX_FMT_VP8,
1491		.insert_scode_seq = vpu_malone_insert_scode_vp8_seq,
1492		.insert_scode_pic = vpu_malone_insert_scode_vp8_pic,
1493	},
1494	{
1495		.pixelformat = V4L2_PIX_FMT_SPK,
1496		.insert_scode_seq = vpu_malone_insert_scode_spk_seq,
1497		.insert_scode_pic = vpu_malone_insert_scode_spk_pic,
1498	},
1499};
1500
1501static const struct malone_scode_handler *get_scode_handler(u32 pixelformat)
1502{
1503	int i;
1504
1505	for (i = 0; i < ARRAY_SIZE(scode_handlers); i++) {
1506		if (scode_handlers[i].pixelformat == pixelformat)
1507			return &scode_handlers[i];
1508	}
1509
1510	return NULL;
1511}
1512
1513static int vpu_malone_insert_scode(struct malone_scode_t *scode, u32 type)
1514{
1515	const struct malone_scode_handler *handler;
1516	int ret = 0;
1517
1518	if (!scode || !scode->inst || !scode->vb)
1519		return 0;
1520
1521	scode->need_data = 1;
1522	handler = get_scode_handler(scode->inst->out_format.pixfmt);
1523	if (!handler)
1524		return 0;
1525
1526	switch (type) {
1527	case SCODE_SEQUENCE:
1528		if (handler->insert_scode_seq)
1529			ret = handler->insert_scode_seq(scode);
1530		break;
1531	case SCODE_PICTURE:
1532		if (handler->insert_scode_pic)
1533			ret = handler->insert_scode_pic(scode);
1534		break;
1535	default:
1536		break;
1537	}
1538
1539	return ret;
1540}
1541
1542static int vpu_malone_input_frame_data(struct vpu_malone_str_buffer __iomem *str_buf,
1543				       struct vpu_inst *inst, struct vb2_buffer *vb,
1544				       u32 disp_imm)
1545{
1546	struct malone_scode_t scode;
1547	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1548	u32 wptr = readl(&str_buf->wptr);
1549	int size = 0;
1550	int ret = 0;
1551
1552	/*add scode: SCODE_SEQUENCE, SCODE_PICTURE, SCODE_SLICE*/
1553	scode.inst = inst;
1554	scode.vb = vb;
1555	scode.wptr = wptr;
1556	scode.need_data = 1;
1557	if (vbuf->sequence == 0)
1558		ret = vpu_malone_insert_scode(&scode, SCODE_SEQUENCE);
1559
1560	if (ret < 0)
1561		return -ENOMEM;
1562	size += ret;
1563	wptr = scode.wptr;
1564	if (!scode.need_data) {
1565		vpu_malone_update_wptr(str_buf, wptr);
1566		return size;
1567	}
1568
1569	ret = vpu_malone_insert_scode(&scode, SCODE_PICTURE);
1570	if (ret < 0)
1571		return -ENOMEM;
1572	size += ret;
1573	wptr = scode.wptr;
1574
1575	ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer,
1576					       &wptr,
1577					       vb2_get_plane_payload(vb, 0),
1578					       vb2_plane_vaddr(vb, 0));
1579	if (ret < 0)
1580		return -ENOMEM;
1581	size += vb2_get_plane_payload(vb, 0);
1582
1583	vpu_malone_update_wptr(str_buf, wptr);
1584
1585	/*
1586	 * Enable the low latency flush mode if display delay is set to 0
1587	 * or the low latency frame flush mode if it is set to 1.
1588	 * The low latency flush mode requires some padding data to be appended to each frame,
1589	 * but there must not be any padding data between the sequence header and the frame.
1590	 * This module is currently only supported for the H264 and HEVC formats,
1591	 * for other formats, vpu_malone_add_scode() will return 0.
1592	 */
1593	if (disp_imm || low_latency) {
1594		ret = vpu_malone_add_scode(inst->core->iface,
1595					   inst->id,
1596					   &inst->stream_buffer,
1597					   inst->out_format.pixfmt,
1598					   SCODE_PADDING_BUFFLUSH);
1599		if (ret < 0)
1600			return ret;
1601		size += ret;
1602	}
1603
1604	return size;
1605}
1606
1607static int vpu_malone_input_stream_data(struct vpu_malone_str_buffer __iomem *str_buf,
1608					struct vpu_inst *inst, struct vb2_buffer *vb)
1609{
1610	u32 wptr = readl(&str_buf->wptr);
1611	int ret = 0;
1612
1613	ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer,
1614					       &wptr,
1615					       vb2_get_plane_payload(vb, 0),
1616					       vb2_plane_vaddr(vb, 0));
1617	if (ret < 0)
1618		return -ENOMEM;
1619
1620	vpu_malone_update_wptr(str_buf, wptr);
1621
1622	return ret;
1623}
1624
1625static int vpu_malone_input_ts(struct vpu_inst *inst, s64  timestamp, u32 size)
1626{
1627	struct vpu_ts_info info;
1628
1629	memset(&info, 0, sizeof(info));
1630	info.timestamp = timestamp;
1631	info.size = size;
1632
1633	return vpu_session_fill_timestamp(inst, &info);
1634}
1635
1636int vpu_malone_input_frame(struct vpu_shared_addr *shared,
1637			   struct vpu_inst *inst, struct vb2_buffer *vb)
1638{
1639	struct vpu_dec_ctrl *hc = shared->priv;
1640	struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[inst->id];
1641	u32 disp_imm = hc->codec_param[inst->id].disp_imm;
1642	u32 size;
1643	int ret;
1644
1645	if (vpu_malone_is_non_frame_mode(shared, inst->id))
1646		ret = vpu_malone_input_stream_data(str_buf, inst, vb);
1647	else
1648		ret = vpu_malone_input_frame_data(str_buf, inst, vb, disp_imm);
1649	if (ret < 0)
1650		return ret;
1651	size = ret;
1652
1653	if (inst->extra_size) {
1654		size += inst->extra_size;
1655		inst->extra_size = 0;
1656	}
1657
1658	ret = vpu_malone_input_ts(inst, vb->timestamp, size);
1659	if (ret)
1660		return ret;
1661
1662	return 0;
1663}
1664
1665static bool vpu_malone_check_ready(struct vpu_shared_addr *shared, u32 instance)
1666{
1667	struct malone_iface *iface = shared->iface;
1668	struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance];
1669	u32 size = desc->end - desc->start;
1670	u32 rptr = desc->rptr;
1671	u32 wptr = desc->wptr;
1672	u32 used;
1673
1674	if (!size)
1675		return true;
1676
1677	used = (wptr + size - rptr) % size;
1678	if (used < (size / 2))
1679		return true;
1680
1681	return false;
1682}
1683
1684bool vpu_malone_is_ready(struct vpu_shared_addr *shared, u32 instance)
1685{
1686	u32 cnt = 0;
1687
1688	while (!vpu_malone_check_ready(shared, instance)) {
1689		if (cnt > 30)
1690			return false;
1691		mdelay(1);
1692		cnt++;
1693	}
1694	return true;
1695}
1696
1697int vpu_malone_pre_cmd(struct vpu_shared_addr *shared, u32 instance)
1698{
1699	if (!vpu_malone_is_ready(shared, instance))
1700		return -EINVAL;
1701
1702	return 0;
1703}
1704
1705int vpu_malone_post_cmd(struct vpu_shared_addr *shared, u32 instance)
1706{
1707	struct malone_iface *iface = shared->iface;
1708	struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance];
1709
1710	desc->wptr++;
1711	if (desc->wptr == desc->end)
1712		desc->wptr = desc->start;
1713
1714	return 0;
1715}
1716
1717int vpu_malone_init_instance(struct vpu_shared_addr *shared, u32 instance)
1718{
1719	struct malone_iface *iface = shared->iface;
1720	struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance];
1721
1722	desc->wptr = desc->rptr;
1723	if (desc->wptr == desc->end)
1724		desc->wptr = desc->start;
1725
1726	return 0;
1727}
1728
1729u32 vpu_malone_get_max_instance_count(struct vpu_shared_addr *shared)
1730{
1731	struct malone_iface *iface = shared->iface;
1732
1733	return iface->max_streams;
1734}