c3-mipi-adap.c

  1// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
  2/*
  3 * Copyright (C) 2024 Amlogic, Inc. All rights reserved
  4 */
  5
  6#include <linux/clk.h>
  7#include <linux/device.h>
  8#include <linux/module.h>
  9#include <linux/mutex.h>
 10#include <linux/platform_device.h>
 11#include <linux/pm_runtime.h>
 12
 13#include <media/mipi-csi2.h>
 14#include <media/v4l2-async.h>
 15#include <media/v4l2-common.h>
 16#include <media/v4l2-device.h>
 17#include <media/v4l2-fwnode.h>
 18#include <media/v4l2-mc.h>
 19#include <media/v4l2-subdev.h>
 20
 21/*
 22 * Adapter Block Diagram
 23 * ---------------------
 24 *
 25 *                   +--------------------------------------------+
 26 *                   |                   Adapter                  |
 27 *                   |--------------------------------------------|
 28 * +------------+    |          |          |         |            |    +-----+
 29 * | MIPI CSI-2 |--->| Frontend -> DDR_RD0 -> PIXEL0 -> ALIGNMENT |--->| ISP |
 30 * +------------+    |          |          |         |            |    +-----+
 31 *                   +--------------------------------------------+
 32 *
 33 */
 34
 35/* C3 adapter submodule definition */
 36enum {
 37	SUBMD_TOP,
 38	SUBMD_FD,
 39	SUBMD_RD,
 40};
 41
 42#define ADAP_SUBMD_MASK		GENMASK(17, 16)
 43#define ADAP_SUBMD_SHIFT	16
 44#define ADAP_SUBMD(x)	(((x) & (ADAP_SUBMD_MASK)) >> (ADAP_SUBMD_SHIFT))
 45#define ADAP_REG_ADDR_MASK	GENMASK(15, 0)
 46#define ADAP_REG_ADDR(x)	((x) & (ADAP_REG_ADDR_MASK))
 47#define ADAP_REG_T(x)		((SUBMD_TOP << ADAP_SUBMD_SHIFT) | (x))
 48#define ADAP_REG_F(x)		((SUBMD_FD << ADAP_SUBMD_SHIFT) | (x))
 49#define ADAP_REG_R(x)		((SUBMD_RD << ADAP_SUBMD_SHIFT) | (x))
 50
 51#define MIPI_ADAP_CLOCK_NUM_MAX				3
 52#define MIPI_ADAP_SUBDEV_NAME				"c3-mipi-adapter"
 53
 54/* C3 MIPI adapter TOP register */
 55#define MIPI_TOP_CTRL0					ADAP_REG_T(0x00)
 56#define MIPI_TOP_CTRL0_RST_ADAPTER_MASK			BIT(1)
 57#define MIPI_TOP_CTRL0_RST_ADAPTER_APPLY		BIT(1)
 58#define MIPI_TOP_CTRL0_RST_ADAPTER_EXIT			(0 << 1)
 59
 60#define MIPI_ADAPT_DE_CTRL0				ADAP_REG_T(0x40)
 61#define MIPI_ADAPT_DE_CTRL0_RD_BUS_BYPASS_MASK		BIT(3)
 62#define MIPI_ADAPT_DE_CTRL0_RD_BUS_BYPASS_EN		BIT(3)
 63#define MIPI_ADAPT_DE_CTRL0_RD_BUS_BYPASS_DIS		(0 << 3)
 64#define MIPI_ADAPT_DE_CTRL0_WR_BUS_BYPASS_MASK		BIT(7)
 65#define MIPI_ADAPT_DE_CTRL0_WR_BUS_BYPASS_EN		BIT(7)
 66#define MIPI_ADAPT_DE_CTRL0_WR_BUS_BYPASS_DIS		(0 << 7)
 67
 68/* C3 MIPI adapter FRONTEND register */
 69#define CSI2_CLK_RESET					ADAP_REG_F(0x00)
 70#define CSI2_CLK_RESET_SW_RESET_MASK			BIT(0)
 71#define CSI2_CLK_RESET_SW_RESET_APPLY			BIT(0)
 72#define CSI2_CLK_RESET_SW_RESET_RELEASE			(0 << 0)
 73#define CSI2_CLK_RESET_CLK_ENABLE_MASK			BIT(1)
 74#define CSI2_CLK_RESET_CLK_ENABLE_EN			BIT(1)
 75#define CSI2_CLK_RESET_CLK_ENABLE_DIS			(0 << 1)
 76
 77#define CSI2_GEN_CTRL0					ADAP_REG_F(0x04)
 78#define CSI2_GEN_CTRL0_VC0_MASK				BIT(0)
 79#define CSI2_GEN_CTRL0_VC0_EN				BIT(0)
 80#define CSI2_GEN_CTRL0_VC0_DIS				(0 << 0)
 81#define CSI2_GEN_CTRL0_ENABLE_PACKETS_MASK		GENMASK(20, 16)
 82#define CSI2_GEN_CTRL0_ENABLE_PACKETS_RAW		BIT(16)
 83#define CSI2_GEN_CTRL0_ENABLE_PACKETS_YUV		(2 << 16)
 84
 85#define CSI2_X_START_END_ISP				ADAP_REG_F(0x0c)
 86#define CSI2_X_START_END_ISP_X_START_MASK		GENMASK(15, 0)
 87#define CSI2_X_START_END_ISP_X_START(x)			((x) << 0)
 88#define CSI2_X_START_END_ISP_X_END_MASK			GENMASK(31, 16)
 89#define CSI2_X_START_END_ISP_X_END(x)			(((x) - 1) << 16)
 90
 91#define CSI2_Y_START_END_ISP				ADAP_REG_F(0x10)
 92#define CSI2_Y_START_END_ISP_Y_START_MASK		GENMASK(15, 0)
 93#define CSI2_Y_START_END_ISP_Y_START(x)			((x) << 0)
 94#define CSI2_Y_START_END_ISP_Y_END_MASK			GENMASK(31, 16)
 95#define CSI2_Y_START_END_ISP_Y_END(x)			(((x) - 1) << 16)
 96
 97#define CSI2_VC_MODE					ADAP_REG_F(0x1c)
 98#define CSI2_VC_MODE_VS_ISP_SEL_VC_MASK			GENMASK(19, 16)
 99#define CSI2_VC_MODE_VS_ISP_SEL_VC_0			BIT(16)
100#define CSI2_VC_MODE_VS_ISP_SEL_VC_1			(2 << 16)
101#define CSI2_VC_MODE_VS_ISP_SEL_VC_2			(4 << 16)
102#define CSI2_VC_MODE_VS_ISP_SEL_VC_3			(8 << 16)
103#define CSI2_VC_MODE_HS_ISP_SEL_VC_MASK			GENMASK(23, 20)
104#define CSI2_VC_MODE_HS_ISP_SEL_VC_0			BIT(20)
105#define CSI2_VC_MODE_HS_ISP_SEL_VC_1			(2 << 20)
106#define CSI2_VC_MODE_HS_ISP_SEL_VC_2			(4 << 20)
107#define CSI2_VC_MODE_HS_ISP_SEL_VC_3			(8 << 20)
108
109/* C3 MIPI adapter READER register */
110#define MIPI_ADAPT_DDR_RD0_CNTL0			ADAP_REG_R(0x00)
111#define MIPI_ADAPT_DDR_RD0_CNTL0_MODULE_EN_MASK		BIT(0)
112#define MIPI_ADAPT_DDR_RD0_CNTL0_MODULE_EN		BIT(0)
113#define MIPI_ADAPT_DDR_RD0_CNTL0_MODULE_DIS		(0 << 0)
114
115#define MIPI_ADAPT_DDR_RD0_CNTL1			ADAP_REG_R(0x04)
116#define MIPI_ADAPT_DDR_RD0_CNTL1_PORT_SEL_MASK		GENMASK(31, 30)
117#define MIPI_ADAPT_DDR_RD0_CNTL1_PORT_SEL_DIRECT_MODE	(0 << 30)
118#define MIPI_ADAPT_DDR_RD0_CNTL1_PORT_SEL_DDR_MODE	BIT(30)
119
120#define MIPI_ADAPT_PIXEL0_CNTL0				ADAP_REG_R(0x80)
121#define MIPI_ADAPT_PIXEL0_CNTL0_WORK_MODE_MASK		GENMASK(17, 16)
122#define MIPI_ADAPT_PIXEL0_CNTL0_WORK_MODE_RAW_DDR	(0 << 16)
123#define MIPI_ADAPT_PIXEL0_CNTL0_WORK_MODE_RAW_DIRECT	BIT(16)
124#define MIPI_ADAPT_PIXEL0_CNTL0_DATA_TYPE_MASK		GENMASK(25, 20)
125#define MIPI_ADAPT_PIXEL0_CNTL0_DATA_TYPE(x)		((x) << 20)
126#define MIPI_ADAPT_PIXEL0_CNTL0_START_EN_MASK		BIT(31)
127#define MIPI_ADAPT_PIXEL0_CNTL0_START_EN		BIT(31)
128
129#define MIPI_ADAPT_ALIG_CNTL0				ADAP_REG_R(0x100)
130#define MIPI_ADAPT_ALIG_CNTL0_H_NUM_MASK		GENMASK(15, 0)
131#define MIPI_ADAPT_ALIG_CNTL0_H_NUM(x)			((x) << 0)
132#define MIPI_ADAPT_ALIG_CNTL0_V_NUM_MASK		GENMASK(31, 16)
133#define MIPI_ADAPT_ALIG_CNTL0_V_NUM(x)			((x) << 16)
134
135#define MIPI_ADAPT_ALIG_CNTL1				ADAP_REG_R(0x104)
136#define MIPI_ADAPT_ALIG_CNTL1_HPE_NUM_MASK		GENMASK(31, 16)
137#define MIPI_ADAPT_ALIG_CNTL1_HPE_NUM(x)		((x) << 16)
138
139#define MIPI_ADAPT_ALIG_CNTL2				ADAP_REG_R(0x108)
140#define MIPI_ADAPT_ALIG_CNTL2_VPE_NUM_MASK		GENMASK(31, 16)
141#define MIPI_ADAPT_ALIG_CNTL2_VPE_NUM(x)		((x) << 16)
142
143#define MIPI_ADAPT_ALIG_CNTL6				ADAP_REG_R(0x118)
144#define MIPI_ADAPT_ALIG_CNTL6_PATH0_EN_MASK		BIT(0)
145#define MIPI_ADAPT_ALIG_CNTL6_PATH0_EN			BIT(0)
146#define MIPI_ADAPT_ALIG_CNTL6_PATH0_DIS			(0 << 0)
147#define MIPI_ADAPT_ALIG_CNTL6_PIX0_DATA_MODE_MASK	BIT(4)
148#define MIPI_ADAPT_ALIG_CNTL6_PIX0_DATA_MODE_DDR	(0 << 4)
149#define MIPI_ADAPT_ALIG_CNTL6_PIX0_DATA_MODE_DIRECT	BIT(4)
150#define MIPI_ADAPT_ALIG_CNTL6_DATA0_EN_MASK		BIT(12)
151#define MIPI_ADAPT_ALIG_CNTL6_DATA0_EN			BIT(12)
152#define MIPI_ADAPT_ALIG_CNTL6_DATA0_DIS			(0 << 12)
153
154#define MIPI_ADAPT_ALIG_CNTL8				ADAP_REG_R(0x120)
155#define MIPI_ADAPT_ALIG_CNTL8_FRMAE_CONTINUE_MASK	BIT(5)
156#define MIPI_ADAPT_ALIG_CNTL8_FRMAE_CONTINUE_EN		BIT(5)
157#define MIPI_ADAPT_ALIG_CNTL8_FRMAE_CONTINUE_DIS	(0 << 5)
158#define MIPI_ADAPT_ALIG_CNTL8_EXCEED_DIS_MASK		BIT(12)
159#define MIPI_ADAPT_ALIG_CNTL8_EXCEED_HOLD		(0 << 12)
160#define MIPI_ADAPT_ALIG_CNTL8_EXCEED_NOT_HOLD		BIT(12)
161#define MIPI_ADAPT_ALIG_CNTL8_START_EN_MASK		BIT(31)
162#define MIPI_ADAPT_ALIG_CNTL8_START_EN			BIT(31)
163
164#define MIPI_ADAP_MAX_WIDTH		2888
165#define MIPI_ADAP_MIN_WIDTH		160
166#define MIPI_ADAP_MAX_HEIGHT		2240
167#define MIPI_ADAP_MIN_HEIGHT		120
168#define MIPI_ADAP_DEFAULT_WIDTH		1920
169#define MIPI_ADAP_DEFAULT_HEIGHT	1080
170#define MIPI_ADAP_DEFAULT_FMT		MEDIA_BUS_FMT_SRGGB10_1X10
171
172/* C3 MIPI adapter pad list */
173enum {
174	C3_MIPI_ADAP_PAD_SINK,
175	C3_MIPI_ADAP_PAD_SRC,
176	C3_MIPI_ADAP_PAD_MAX
177};
178
179/*
180 * struct c3_adap_info - mipi adapter information
181 *
182 * @clocks: array of mipi adapter clock names
183 * @clock_num: actual clock number
184 */
185struct c3_adap_info {
186	char *clocks[MIPI_ADAP_CLOCK_NUM_MAX];
187	u32 clock_num;
188};
189
190/*
191 * struct c3_adap_device - mipi adapter platform device
192 *
193 * @dev: pointer to the struct device
194 * @top: mipi adapter top register address
195 * @fd: mipi adapter frontend register address
196 * @rd: mipi adapter reader register address
197 * @clks: array of MIPI adapter clocks
198 * @sd: mipi adapter sub-device
199 * @pads: mipi adapter sub-device pads
200 * @notifier: notifier to register on the v4l2-async API
201 * @src_sd: source sub-device pad
202 * @info: version-specific MIPI adapter information
203 */
204struct c3_adap_device {
205	struct device *dev;
206	void __iomem *top;
207	void __iomem *fd;
208	void __iomem *rd;
209	struct clk_bulk_data clks[MIPI_ADAP_CLOCK_NUM_MAX];
210
211	struct v4l2_subdev sd;
212	struct media_pad pads[C3_MIPI_ADAP_PAD_MAX];
213	struct v4l2_async_notifier notifier;
214	struct media_pad *src_pad;
215
216	const struct c3_adap_info *info;
217};
218
219/* Format helpers */
220
221struct c3_adap_pix_format {
222	u32 code;
223	u8 type;
224};
225
226static const struct c3_adap_pix_format c3_mipi_adap_formats[] = {
227	{ MEDIA_BUS_FMT_SBGGR10_1X10, MIPI_CSI2_DT_RAW10 },
228	{ MEDIA_BUS_FMT_SGBRG10_1X10, MIPI_CSI2_DT_RAW10 },
229	{ MEDIA_BUS_FMT_SGRBG10_1X10, MIPI_CSI2_DT_RAW10 },
230	{ MEDIA_BUS_FMT_SRGGB10_1X10, MIPI_CSI2_DT_RAW10 },
231	{ MEDIA_BUS_FMT_SBGGR12_1X12, MIPI_CSI2_DT_RAW12 },
232	{ MEDIA_BUS_FMT_SGBRG12_1X12, MIPI_CSI2_DT_RAW12 },
233	{ MEDIA_BUS_FMT_SGRBG12_1X12, MIPI_CSI2_DT_RAW12 },
234	{ MEDIA_BUS_FMT_SRGGB12_1X12, MIPI_CSI2_DT_RAW12 },
235};
236
237static const struct c3_adap_pix_format *c3_mipi_adap_find_format(u32 code)
238{
239	for (unsigned int i = 0; i < ARRAY_SIZE(c3_mipi_adap_formats); i++)
240		if (code == c3_mipi_adap_formats[i].code)
241			return &c3_mipi_adap_formats[i];
242
243	return NULL;
244}
245
246/* Hardware configuration */
247
248static void c3_mipi_adap_update_bits(struct c3_adap_device *adap, u32 reg,
249				     u32 mask, u32 val)
250{
251	void __iomem *addr;
252	u32 orig, tmp;
253
254	switch (ADAP_SUBMD(reg)) {
255	case SUBMD_TOP:
256		addr = adap->top + ADAP_REG_ADDR(reg);
257		break;
258	case SUBMD_FD:
259		addr = adap->fd + ADAP_REG_ADDR(reg);
260		break;
261	case SUBMD_RD:
262		addr = adap->rd + ADAP_REG_ADDR(reg);
263		break;
264	default:
265		dev_err(adap->dev,
266			"Invalid sub-module: %lu\n", ADAP_SUBMD(reg));
267		return;
268	}
269
270	orig = readl(addr);
271	tmp = orig & ~mask;
272	tmp |= val & mask;
273
274	if (tmp != orig)
275		writel(tmp, addr);
276}
277
278/* Configure adapter top sub module */
279static void c3_mipi_adap_cfg_top(struct c3_adap_device *adap)
280{
281	/* Reset adapter */
282	c3_mipi_adap_update_bits(adap, MIPI_TOP_CTRL0,
283				 MIPI_TOP_CTRL0_RST_ADAPTER_MASK,
284				 MIPI_TOP_CTRL0_RST_ADAPTER_APPLY);
285	c3_mipi_adap_update_bits(adap, MIPI_TOP_CTRL0,
286				 MIPI_TOP_CTRL0_RST_ADAPTER_MASK,
287				 MIPI_TOP_CTRL0_RST_ADAPTER_EXIT);
288
289	/* Bypass decompress */
290	c3_mipi_adap_update_bits(adap, MIPI_ADAPT_DE_CTRL0,
291				 MIPI_ADAPT_DE_CTRL0_RD_BUS_BYPASS_MASK,
292				 MIPI_ADAPT_DE_CTRL0_RD_BUS_BYPASS_EN);
293	c3_mipi_adap_update_bits(adap, MIPI_ADAPT_DE_CTRL0,
294				 MIPI_ADAPT_DE_CTRL0_WR_BUS_BYPASS_MASK,
295				 MIPI_ADAPT_DE_CTRL0_WR_BUS_BYPASS_EN);
296}
297
298/* Configure adapter frontend sub module */
299static void c3_mipi_adap_cfg_frontend(struct c3_adap_device *adap,
300				      struct v4l2_mbus_framefmt *fmt)
301{
302	/* Reset frontend module */
303	c3_mipi_adap_update_bits(adap, CSI2_CLK_RESET,
304				 CSI2_CLK_RESET_SW_RESET_MASK,
305				 CSI2_CLK_RESET_SW_RESET_APPLY);
306	c3_mipi_adap_update_bits(adap, CSI2_CLK_RESET,
307				 CSI2_CLK_RESET_SW_RESET_MASK,
308				 CSI2_CLK_RESET_SW_RESET_RELEASE);
309	c3_mipi_adap_update_bits(adap, CSI2_CLK_RESET,
310				 CSI2_CLK_RESET_CLK_ENABLE_MASK,
311				 CSI2_CLK_RESET_CLK_ENABLE_EN);
312
313	c3_mipi_adap_update_bits(adap, CSI2_X_START_END_ISP,
314				 CSI2_X_START_END_ISP_X_START_MASK,
315				 CSI2_X_START_END_ISP_X_START(0));
316	c3_mipi_adap_update_bits(adap, CSI2_X_START_END_ISP,
317				 CSI2_X_START_END_ISP_X_END_MASK,
318				 CSI2_X_START_END_ISP_X_END(fmt->width));
319
320	c3_mipi_adap_update_bits(adap, CSI2_Y_START_END_ISP,
321				 CSI2_Y_START_END_ISP_Y_START_MASK,
322				 CSI2_Y_START_END_ISP_Y_START(0));
323	c3_mipi_adap_update_bits(adap, CSI2_Y_START_END_ISP,
324				 CSI2_Y_START_END_ISP_Y_END_MASK,
325				 CSI2_Y_START_END_ISP_Y_END(fmt->height));
326
327	/* Select VS and HS signal for direct path */
328	c3_mipi_adap_update_bits(adap, CSI2_VC_MODE,
329				 CSI2_VC_MODE_VS_ISP_SEL_VC_MASK,
330				 CSI2_VC_MODE_VS_ISP_SEL_VC_0);
331	c3_mipi_adap_update_bits(adap, CSI2_VC_MODE,
332				 CSI2_VC_MODE_HS_ISP_SEL_VC_MASK,
333				 CSI2_VC_MODE_HS_ISP_SEL_VC_0);
334
335	/* Enable to receive RAW packet */
336	c3_mipi_adap_update_bits(adap, CSI2_GEN_CTRL0,
337				 CSI2_GEN_CTRL0_ENABLE_PACKETS_MASK,
338				 CSI2_GEN_CTRL0_ENABLE_PACKETS_RAW);
339
340	/* Enable virtual channel 0 */
341	c3_mipi_adap_update_bits(adap, CSI2_GEN_CTRL0,
342				 CSI2_GEN_CTRL0_VC0_MASK,
343				 CSI2_GEN_CTRL0_VC0_EN);
344}
345
346static void c3_mipi_adap_cfg_rd0(struct c3_adap_device *adap)
347{
348	/* Select direct mode for DDR_RD0 mode */
349	c3_mipi_adap_update_bits(adap, MIPI_ADAPT_DDR_RD0_CNTL1,
350				 MIPI_ADAPT_DDR_RD0_CNTL1_PORT_SEL_MASK,
351				 MIPI_ADAPT_DDR_RD0_CNTL1_PORT_SEL_DIRECT_MODE);
352
353	/* Data can't bypass DDR_RD0 in direct mode, so enable DDR_RD0 here */
354	c3_mipi_adap_update_bits(adap, MIPI_ADAPT_DDR_RD0_CNTL0,
355				 MIPI_ADAPT_DDR_RD0_CNTL0_MODULE_EN_MASK,
356				 MIPI_ADAPT_DDR_RD0_CNTL0_MODULE_EN);
357}
358
359static void c3_mipi_adap_cfg_pixel0(struct c3_adap_device *adap,
360				    struct v4l2_mbus_framefmt *fmt)
361{
362	const struct c3_adap_pix_format *pix;
363
364	pix = c3_mipi_adap_find_format(fmt->code);
365
366	/* Set work mode and data type for PIXEL0 module */
367	c3_mipi_adap_update_bits(adap, MIPI_ADAPT_PIXEL0_CNTL0,
368				 MIPI_ADAPT_PIXEL0_CNTL0_WORK_MODE_MASK,
369				 MIPI_ADAPT_PIXEL0_CNTL0_WORK_MODE_RAW_DIRECT);
370	c3_mipi_adap_update_bits(adap, MIPI_ADAPT_PIXEL0_CNTL0,
371				 MIPI_ADAPT_PIXEL0_CNTL0_DATA_TYPE_MASK,
372				 MIPI_ADAPT_PIXEL0_CNTL0_DATA_TYPE(pix->type));
373
374	/* Start PIXEL0 module */
375	c3_mipi_adap_update_bits(adap, MIPI_ADAPT_PIXEL0_CNTL0,
376				 MIPI_ADAPT_PIXEL0_CNTL0_START_EN_MASK,
377				 MIPI_ADAPT_PIXEL0_CNTL0_START_EN);
378}
379
380static void c3_mipi_adap_cfg_alig(struct c3_adap_device *adap,
381				  struct v4l2_mbus_framefmt *fmt)
382{
383	/*
384	 * ISP hardware requires the number of horizonal blanks greater than
385	 * 64 cycles, so adding 64 here.
386	 */
387	c3_mipi_adap_update_bits(adap, MIPI_ADAPT_ALIG_CNTL0,
388				 MIPI_ADAPT_ALIG_CNTL0_H_NUM_MASK,
389				 MIPI_ADAPT_ALIG_CNTL0_H_NUM(fmt->width + 64));
390
391	/*
392	 * ISP hardware requires the number of vertical blanks greater than
393	 * 40 lines, so adding 40 here.
394	 */
395	c3_mipi_adap_update_bits(adap, MIPI_ADAPT_ALIG_CNTL0,
396				 MIPI_ADAPT_ALIG_CNTL0_V_NUM_MASK,
397				 MIPI_ADAPT_ALIG_CNTL0_V_NUM(fmt->height + 40));
398
399	/* End pixel in a line */
400	c3_mipi_adap_update_bits(adap, MIPI_ADAPT_ALIG_CNTL1,
401				 MIPI_ADAPT_ALIG_CNTL1_HPE_NUM_MASK,
402				 MIPI_ADAPT_ALIG_CNTL1_HPE_NUM(fmt->width));
403
404	/* End line in a frame */
405	c3_mipi_adap_update_bits(adap, MIPI_ADAPT_ALIG_CNTL2,
406				 MIPI_ADAPT_ALIG_CNTL2_VPE_NUM_MASK,
407				 MIPI_ADAPT_ALIG_CNTL2_VPE_NUM(fmt->height));
408
409	c3_mipi_adap_update_bits(adap, MIPI_ADAPT_ALIG_CNTL6,
410				 MIPI_ADAPT_ALIG_CNTL6_PATH0_EN_MASK,
411				 MIPI_ADAPT_ALIG_CNTL6_PATH0_EN);
412
413	/* Select direct mode for ALIG module */
414	c3_mipi_adap_update_bits(adap, MIPI_ADAPT_ALIG_CNTL6,
415				 MIPI_ADAPT_ALIG_CNTL6_PIX0_DATA_MODE_MASK,
416				 MIPI_ADAPT_ALIG_CNTL6_PIX0_DATA_MODE_DIRECT);
417
418	/* Enable to send raw data */
419	c3_mipi_adap_update_bits(adap, MIPI_ADAPT_ALIG_CNTL6,
420				 MIPI_ADAPT_ALIG_CNTL6_DATA0_EN_MASK,
421				 MIPI_ADAPT_ALIG_CNTL6_DATA0_EN);
422
423	/* Set continue mode and disable hold counter */
424	c3_mipi_adap_update_bits(adap, MIPI_ADAPT_ALIG_CNTL8,
425				 MIPI_ADAPT_ALIG_CNTL8_FRMAE_CONTINUE_MASK,
426				 MIPI_ADAPT_ALIG_CNTL8_FRMAE_CONTINUE_EN);
427	c3_mipi_adap_update_bits(adap, MIPI_ADAPT_ALIG_CNTL8,
428				 MIPI_ADAPT_ALIG_CNTL8_EXCEED_DIS_MASK,
429				 MIPI_ADAPT_ALIG_CNTL8_EXCEED_NOT_HOLD);
430
431	/* Start ALIG module */
432	c3_mipi_adap_update_bits(adap, MIPI_ADAPT_ALIG_CNTL8,
433				 MIPI_ADAPT_ALIG_CNTL8_START_EN_MASK,
434				 MIPI_ADAPT_ALIG_CNTL8_START_EN);
435}
436
437/* V4L2 subdev operations */
438
439static int c3_mipi_adap_enable_streams(struct v4l2_subdev *sd,
440				       struct v4l2_subdev_state *state,
441				       u32 pad, u64 streams_mask)
442{
443	struct c3_adap_device *adap = v4l2_get_subdevdata(sd);
444	struct v4l2_mbus_framefmt *fmt;
445	struct media_pad *sink_pad;
446	struct v4l2_subdev *src_sd;
447	int ret;
448
449	sink_pad = &adap->pads[C3_MIPI_ADAP_PAD_SINK];
450	adap->src_pad = media_pad_remote_pad_unique(sink_pad);
451	if (IS_ERR(adap->src_pad)) {
452		dev_dbg(adap->dev, "Failed to get source pad for MIPI adap\n");
453		return -EPIPE;
454	}
455
456	src_sd = media_entity_to_v4l2_subdev(adap->src_pad->entity);
457
458	pm_runtime_resume_and_get(adap->dev);
459
460	fmt = v4l2_subdev_state_get_format(state, C3_MIPI_ADAP_PAD_SINK);
461
462	c3_mipi_adap_cfg_top(adap);
463	c3_mipi_adap_cfg_frontend(adap, fmt);
464	c3_mipi_adap_cfg_rd0(adap);
465	c3_mipi_adap_cfg_pixel0(adap, fmt);
466	c3_mipi_adap_cfg_alig(adap, fmt);
467
468	ret = v4l2_subdev_enable_streams(src_sd, adap->src_pad->index, BIT(0));
469	if (ret) {
470		pm_runtime_put(adap->dev);
471		return ret;
472	}
473
474	return 0;
475}
476
477static int c3_mipi_adap_disable_streams(struct v4l2_subdev *sd,
478					struct v4l2_subdev_state *state,
479					u32 pad, u64 streams_mask)
480{
481	struct c3_adap_device *adap = v4l2_get_subdevdata(sd);
482	struct v4l2_subdev *src_sd;
483
484	if (adap->src_pad) {
485		src_sd = media_entity_to_v4l2_subdev(adap->src_pad->entity);
486		v4l2_subdev_disable_streams(src_sd, adap->src_pad->index,
487					    BIT(0));
488	}
489	adap->src_pad = NULL;
490
491	pm_runtime_put(adap->dev);
492
493	return 0;
494}
495
496static int c3_mipi_adap_enum_mbus_code(struct v4l2_subdev *sd,
497				       struct v4l2_subdev_state *state,
498				       struct v4l2_subdev_mbus_code_enum *code)
499{
500	struct v4l2_mbus_framefmt *fmt;
501
502	switch (code->pad) {
503	case C3_MIPI_ADAP_PAD_SINK:
504		if (code->index >= ARRAY_SIZE(c3_mipi_adap_formats))
505			return -EINVAL;
506
507		code->code = c3_mipi_adap_formats[code->index].code;
508		break;
509	case C3_MIPI_ADAP_PAD_SRC:
510		if (code->index)
511			return -EINVAL;
512
513		fmt = v4l2_subdev_state_get_format(state, code->pad);
514		code->code = fmt->code;
515		break;
516	default:
517		return -EINVAL;
518	}
519
520	return 0;
521}
522
523static int c3_mipi_adap_set_fmt(struct v4l2_subdev *sd,
524				struct v4l2_subdev_state *state,
525				struct v4l2_subdev_format *format)
526{
527	struct v4l2_mbus_framefmt *fmt;
528	const struct c3_adap_pix_format *pix_format;
529
530	if (format->pad != C3_MIPI_ADAP_PAD_SINK)
531		return v4l2_subdev_get_fmt(sd, state, format);
532
533	pix_format = c3_mipi_adap_find_format(format->format.code);
534	if (!pix_format)
535		pix_format = &c3_mipi_adap_formats[0];
536
537	fmt = v4l2_subdev_state_get_format(state, format->pad);
538	fmt->code = pix_format->code;
539	fmt->width = clamp_t(u32, format->format.width,
540			     MIPI_ADAP_MIN_WIDTH, MIPI_ADAP_MAX_WIDTH);
541	fmt->height = clamp_t(u32, format->format.height,
542			      MIPI_ADAP_MIN_HEIGHT, MIPI_ADAP_MAX_HEIGHT);
543	fmt->colorspace = V4L2_COLORSPACE_RAW;
544	fmt->xfer_func = V4L2_XFER_FUNC_NONE;
545	fmt->ycbcr_enc = V4L2_YCBCR_ENC_601;
546	fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
547
548	format->format = *fmt;
549
550	/* Synchronize the format to source pad */
551	fmt = v4l2_subdev_state_get_format(state, C3_MIPI_ADAP_PAD_SRC);
552	*fmt = format->format;
553
554	return 0;
555}
556
557static int c3_mipi_adap_init_state(struct v4l2_subdev *sd,
558				   struct v4l2_subdev_state *state)
559{
560	struct v4l2_mbus_framefmt *sink_fmt;
561	struct v4l2_mbus_framefmt *src_fmt;
562
563	sink_fmt = v4l2_subdev_state_get_format(state, C3_MIPI_ADAP_PAD_SINK);
564	src_fmt = v4l2_subdev_state_get_format(state, C3_MIPI_ADAP_PAD_SRC);
565
566	sink_fmt->width = MIPI_ADAP_DEFAULT_WIDTH;
567	sink_fmt->height = MIPI_ADAP_DEFAULT_HEIGHT;
568	sink_fmt->field = V4L2_FIELD_NONE;
569	sink_fmt->code = MIPI_ADAP_DEFAULT_FMT;
570	sink_fmt->colorspace = V4L2_COLORSPACE_RAW;
571	sink_fmt->xfer_func = V4L2_XFER_FUNC_NONE;
572	sink_fmt->ycbcr_enc = V4L2_YCBCR_ENC_601;
573	sink_fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
574
575	*src_fmt = *sink_fmt;
576
577	return 0;
578}
579
580static const struct v4l2_subdev_pad_ops c3_mipi_adap_pad_ops = {
581	.enum_mbus_code = c3_mipi_adap_enum_mbus_code,
582	.get_fmt = v4l2_subdev_get_fmt,
583	.set_fmt = c3_mipi_adap_set_fmt,
584	.enable_streams = c3_mipi_adap_enable_streams,
585	.disable_streams = c3_mipi_adap_disable_streams,
586};
587
588static const struct v4l2_subdev_ops c3_mipi_adap_subdev_ops = {
589	.pad = &c3_mipi_adap_pad_ops,
590};
591
592static const struct v4l2_subdev_internal_ops c3_mipi_adap_internal_ops = {
593	.init_state = c3_mipi_adap_init_state,
594};
595
596/* Media entity operations */
597static const struct media_entity_operations c3_mipi_adap_entity_ops = {
598	.link_validate = v4l2_subdev_link_validate,
599};
600
601/* PM runtime */
602
603static int c3_mipi_adap_runtime_suspend(struct device *dev)
604{
605	struct c3_adap_device *adap = dev_get_drvdata(dev);
606
607	clk_bulk_disable_unprepare(adap->info->clock_num, adap->clks);
608
609	return 0;
610}
611
612static int c3_mipi_adap_runtime_resume(struct device *dev)
613{
614	struct c3_adap_device *adap = dev_get_drvdata(dev);
615
616	return clk_bulk_prepare_enable(adap->info->clock_num, adap->clks);
617}
618
619static const struct dev_pm_ops c3_mipi_adap_pm_ops = {
620	SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
621			    pm_runtime_force_resume)
622	RUNTIME_PM_OPS(c3_mipi_adap_runtime_suspend,
623		       c3_mipi_adap_runtime_resume, NULL)
624};
625
626/* Probe/remove & platform driver */
627
628static int c3_mipi_adap_subdev_init(struct c3_adap_device *adap)
629{
630	struct v4l2_subdev *sd = &adap->sd;
631	int ret;
632
633	v4l2_subdev_init(sd, &c3_mipi_adap_subdev_ops);
634	sd->owner = THIS_MODULE;
635	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
636	sd->internal_ops = &c3_mipi_adap_internal_ops;
637	snprintf(sd->name, sizeof(sd->name), "%s", MIPI_ADAP_SUBDEV_NAME);
638
639	sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
640	sd->entity.ops = &c3_mipi_adap_entity_ops;
641
642	sd->dev = adap->dev;
643	v4l2_set_subdevdata(sd, adap);
644
645	adap->pads[C3_MIPI_ADAP_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
646	adap->pads[C3_MIPI_ADAP_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE;
647	ret = media_entity_pads_init(&sd->entity, C3_MIPI_ADAP_PAD_MAX,
648				     adap->pads);
649	if (ret)
650		return ret;
651
652	ret = v4l2_subdev_init_finalize(sd);
653	if (ret) {
654		media_entity_cleanup(&sd->entity);
655		return ret;
656	}
657
658	return 0;
659}
660
661static void c3_mipi_adap_subdev_deinit(struct c3_adap_device *adap)
662{
663	v4l2_subdev_cleanup(&adap->sd);
664	media_entity_cleanup(&adap->sd.entity);
665}
666
667/* Subdev notifier register */
668static int c3_mipi_adap_notify_bound(struct v4l2_async_notifier *notifier,
669				     struct v4l2_subdev *sd,
670				     struct v4l2_async_connection *asc)
671{
672	struct c3_adap_device *adap = v4l2_get_subdevdata(notifier->sd);
673	struct media_pad *sink = &adap->sd.entity.pads[C3_MIPI_ADAP_PAD_SINK];
674
675	return v4l2_create_fwnode_links_to_pad(sd, sink, MEDIA_LNK_FL_ENABLED |
676					       MEDIA_LNK_FL_IMMUTABLE);
677}
678
679static const struct v4l2_async_notifier_operations c3_mipi_adap_notify_ops = {
680	.bound = c3_mipi_adap_notify_bound,
681};
682
683static int c3_mipi_adap_async_register(struct c3_adap_device *adap)
684{
685	struct v4l2_async_connection *asc;
686	struct fwnode_handle *ep;
687	int ret;
688
689	v4l2_async_subdev_nf_init(&adap->notifier, &adap->sd);
690
691	ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(adap->dev), 0, 0,
692					     FWNODE_GRAPH_ENDPOINT_NEXT);
693	if (!ep)
694		return -ENOTCONN;
695
696	asc = v4l2_async_nf_add_fwnode_remote(&adap->notifier, ep,
697					      struct v4l2_async_connection);
698	if (IS_ERR(asc)) {
699		ret = PTR_ERR(asc);
700		goto err_put_handle;
701	}
702
703	adap->notifier.ops = &c3_mipi_adap_notify_ops;
704	ret = v4l2_async_nf_register(&adap->notifier);
705	if (ret)
706		goto err_cleanup_nf;
707
708	ret = v4l2_async_register_subdev(&adap->sd);
709	if (ret)
710		goto err_unregister_nf;
711
712	fwnode_handle_put(ep);
713
714	return 0;
715
716err_unregister_nf:
717	v4l2_async_nf_unregister(&adap->notifier);
718err_cleanup_nf:
719	v4l2_async_nf_cleanup(&adap->notifier);
720err_put_handle:
721	fwnode_handle_put(ep);
722	return ret;
723}
724
725static void c3_mipi_adap_async_unregister(struct c3_adap_device *adap)
726{
727	v4l2_async_unregister_subdev(&adap->sd);
728	v4l2_async_nf_unregister(&adap->notifier);
729	v4l2_async_nf_cleanup(&adap->notifier);
730}
731
732static int c3_mipi_adap_ioremap_resource(struct c3_adap_device *adap)
733{
734	struct device *dev = adap->dev;
735	struct platform_device *pdev = to_platform_device(dev);
736
737	adap->top = devm_platform_ioremap_resource_byname(pdev, "top");
738	if (IS_ERR(adap->top))
739		return PTR_ERR(adap->top);
740
741	adap->fd = devm_platform_ioremap_resource_byname(pdev, "fd");
742	if (IS_ERR(adap->fd))
743		return PTR_ERR(adap->fd);
744
745	adap->rd = devm_platform_ioremap_resource_byname(pdev, "rd");
746	if (IS_ERR(adap->rd))
747		return PTR_ERR(adap->rd);
748
749	return 0;
750}
751
752static int c3_mipi_adap_get_clocks(struct c3_adap_device *adap)
753{
754	const struct c3_adap_info *info = adap->info;
755
756	for (unsigned int i = 0; i < info->clock_num; i++)
757		adap->clks[i].id = info->clocks[i];
758
759	return devm_clk_bulk_get(adap->dev, info->clock_num, adap->clks);
760}
761
762static int c3_mipi_adap_probe(struct platform_device *pdev)
763{
764	struct device *dev = &pdev->dev;
765	struct c3_adap_device *adap;
766	int ret;
767
768	adap = devm_kzalloc(dev, sizeof(*adap), GFP_KERNEL);
769	if (!adap)
770		return -ENOMEM;
771
772	adap->info = of_device_get_match_data(dev);
773	adap->dev = dev;
774
775	ret = c3_mipi_adap_ioremap_resource(adap);
776	if (ret)
777		return dev_err_probe(dev, ret, "Failed to ioremap resource\n");
778
779	ret = c3_mipi_adap_get_clocks(adap);
780	if (ret)
781		return dev_err_probe(dev, ret, "Failed to get clocks\n");
782
783	platform_set_drvdata(pdev, adap);
784
785	pm_runtime_enable(dev);
786
787	ret = c3_mipi_adap_subdev_init(adap);
788	if (ret)
789		goto err_disable_runtime_pm;
790
791	ret = c3_mipi_adap_async_register(adap);
792	if (ret)
793		goto err_deinit_subdev;
794
795	return 0;
796
797err_deinit_subdev:
798	c3_mipi_adap_subdev_deinit(adap);
799err_disable_runtime_pm:
800	pm_runtime_disable(dev);
801	return ret;
802};
803
804static void c3_mipi_adap_remove(struct platform_device *pdev)
805{
806	struct c3_adap_device *adap = platform_get_drvdata(pdev);
807
808	c3_mipi_adap_async_unregister(adap);
809	c3_mipi_adap_subdev_deinit(adap);
810
811	pm_runtime_disable(&pdev->dev);
812};
813
814static const struct c3_adap_info c3_mipi_adap_info = {
815	.clocks = {"vapb", "isp0"},
816	.clock_num = 2
817};
818
819static const struct of_device_id c3_mipi_adap_of_match[] = {
820	{
821		.compatible = "amlogic,c3-mipi-adapter",
822		.data = &c3_mipi_adap_info
823	},
824	{ },
825};
826MODULE_DEVICE_TABLE(of, c3_mipi_adap_of_match);
827
828static struct platform_driver c3_mipi_adap_driver = {
829	.probe = c3_mipi_adap_probe,
830	.remove = c3_mipi_adap_remove,
831	.driver = {
832		.name = "c3-mipi-adapter",
833		.of_match_table = c3_mipi_adap_of_match,
834		.pm = pm_ptr(&c3_mipi_adap_pm_ops),
835	},
836};
837
838module_platform_driver(c3_mipi_adap_driver);
839
840MODULE_AUTHOR("Keke Li <keke.li@amlogic.com>");
841MODULE_DESCRIPTION("Amlogic C3 MIPI adapter");
842MODULE_LICENSE("GPL");