allegro-core.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) 2019 Pengutronix, Michael Tretter <kernel@pengutronix.de>
   4 *
   5 * Allegro DVT video encoder driver
   6 */
   7
   8#include <linux/bits.h>
   9#include <linux/clk.h>
  10#include <linux/firmware.h>
  11#include <linux/gcd.h>
  12#include <linux/interrupt.h>
  13#include <linux/io.h>
  14#include <linux/kernel.h>
  15#include <linux/log2.h>
  16#include <linux/mfd/syscon.h>
  17#include <linux/mfd/syscon/xlnx-vcu.h>
  18#include <linux/module.h>
  19#include <linux/of.h>
  20#include <linux/platform_device.h>
  21#include <linux/pm_runtime.h>
  22#include <linux/regmap.h>
  23#include <linux/sizes.h>
  24#include <linux/slab.h>
  25#include <linux/videodev2.h>
  26#include <media/v4l2-ctrls.h>
  27#include <media/v4l2-device.h>
  28#include <media/v4l2-event.h>
  29#include <media/v4l2-ioctl.h>
  30#include <media/v4l2-mem2mem.h>
  31#include <media/videobuf2-dma-contig.h>
  32#include <media/videobuf2-v4l2.h>
  33
  34#include "allegro-mail.h"
  35#include "nal-h264.h"
  36#include "nal-hevc.h"
  37
  38/*
  39 * Support up to 4k video streams. The hardware actually supports higher
  40 * resolutions, which are specified in PG252 June 6, 2018 (H.264/H.265 Video
  41 * Codec Unit v1.1) Chapter 3.
  42 */
  43#define ALLEGRO_WIDTH_MIN 128
  44#define ALLEGRO_WIDTH_DEFAULT 1920
  45#define ALLEGRO_WIDTH_MAX 3840
  46#define ALLEGRO_HEIGHT_MIN 64
  47#define ALLEGRO_HEIGHT_DEFAULT 1080
  48#define ALLEGRO_HEIGHT_MAX 2160
  49
  50#define ALLEGRO_FRAMERATE_DEFAULT ((struct v4l2_fract) { 30, 1 })
  51
  52#define ALLEGRO_GOP_SIZE_DEFAULT 25
  53#define ALLEGRO_GOP_SIZE_MAX 1000
  54
  55/*
  56 * MCU Control Registers
  57 *
  58 * The Zynq UltraScale+ Devices Register Reference documents the registers
  59 * with an offset of 0x9000, which equals the size of the SRAM and one page
  60 * gap. The driver handles SRAM and registers separately and, therefore, is
  61 * oblivious of the offset.
  62 */
  63#define AL5_MCU_RESET                   0x0000
  64#define AL5_MCU_RESET_SOFT              BIT(0)
  65#define AL5_MCU_RESET_REGS              BIT(1)
  66#define AL5_MCU_RESET_MODE              0x0004
  67#define AL5_MCU_RESET_MODE_SLEEP        BIT(0)
  68#define AL5_MCU_RESET_MODE_HALT         BIT(1)
  69#define AL5_MCU_STA                     0x0008
  70#define AL5_MCU_STA_SLEEP               BIT(0)
  71#define AL5_MCU_WAKEUP                  0x000c
  72
  73#define AL5_ICACHE_ADDR_OFFSET_MSB      0x0010
  74#define AL5_ICACHE_ADDR_OFFSET_LSB      0x0014
  75#define AL5_DCACHE_ADDR_OFFSET_MSB      0x0018
  76#define AL5_DCACHE_ADDR_OFFSET_LSB      0x001c
  77
  78#define AL5_MCU_INTERRUPT               0x0100
  79#define AL5_ITC_CPU_IRQ_MSK             0x0104
  80#define AL5_ITC_CPU_IRQ_CLR             0x0108
  81#define AL5_ITC_CPU_IRQ_STA             0x010C
  82#define AL5_ITC_CPU_IRQ_STA_TRIGGERED   BIT(0)
  83
  84#define AXI_ADDR_OFFSET_IP              0x0208
  85
  86/*
  87 * The MCU accesses the system memory with a 2G offset compared to CPU
  88 * physical addresses.
  89 */
  90#define MCU_CACHE_OFFSET SZ_2G
  91
  92/*
  93 * The driver needs to reserve some space at the beginning of capture buffers,
  94 * because it needs to write SPS/PPS NAL units. The encoder writes the actual
  95 * frame data after the offset.
  96 */
  97#define ENCODER_STREAM_OFFSET SZ_128
  98
  99#define SIZE_MACROBLOCK 16
 100
 101/* Encoding options */
 102#define LOG2_MAX_FRAME_NUM		4
 103#define LOG2_MAX_PIC_ORDER_CNT		10
 104#define BETA_OFFSET_DIV_2		-1
 105#define TC_OFFSET_DIV_2			-1
 106
 107/*
 108 * This control allows applications to explicitly disable the encoder buffer.
 109 * This value is Allegro specific.
 110 */
 111#define V4L2_CID_USER_ALLEGRO_ENCODER_BUFFER (V4L2_CID_USER_ALLEGRO_BASE + 0)
 112
 113static int debug;
 114module_param(debug, int, 0644);
 115MODULE_PARM_DESC(debug, "Debug level (0-2)");
 116
 117struct allegro_buffer {
 118	void *vaddr;
 119	dma_addr_t paddr;
 120	size_t size;
 121	struct list_head head;
 122};
 123
 124struct allegro_dev;
 125struct allegro_channel;
 126
 127struct allegro_mbox {
 128	struct allegro_dev *dev;
 129	unsigned int head;
 130	unsigned int tail;
 131	unsigned int data;
 132	size_t size;
 133	/* protect mailbox from simultaneous accesses */
 134	struct mutex lock;
 135};
 136
 137struct allegro_encoder_buffer {
 138	unsigned int size;
 139	unsigned int color_depth;
 140	unsigned int num_cores;
 141	unsigned int clk_rate;
 142};
 143
 144struct allegro_dev {
 145	struct v4l2_device v4l2_dev;
 146	struct video_device video_dev;
 147	struct v4l2_m2m_dev *m2m_dev;
 148	struct platform_device *plat_dev;
 149
 150	/* mutex protecting vb2_queue structure */
 151	struct mutex lock;
 152
 153	struct regmap *regmap;
 154	struct regmap *sram;
 155	struct regmap *settings;
 156
 157	struct clk *clk_core;
 158	struct clk *clk_mcu;
 159
 160	const struct fw_info *fw_info;
 161	struct allegro_buffer firmware;
 162	struct allegro_buffer suballocator;
 163	bool has_encoder_buffer;
 164	struct allegro_encoder_buffer encoder_buffer;
 165
 166	struct completion init_complete;
 167	bool initialized;
 168
 169	/* The mailbox interface */
 170	struct allegro_mbox *mbox_command;
 171	struct allegro_mbox *mbox_status;
 172
 173	/*
 174	 * The downstream driver limits the users to 64 users, thus I can use
 175	 * a bitfield for the user_ids that are in use. See also user_id in
 176	 * struct allegro_channel.
 177	 */
 178	unsigned long channel_user_ids;
 179	struct list_head channels;
 180	struct mutex channels_lock;
 181};
 182
 183static const struct regmap_config allegro_regmap_config = {
 184	.name = "regmap",
 185	.reg_bits = 32,
 186	.val_bits = 32,
 187	.reg_stride = 4,
 188	.max_register = 0xfff,
 189	.cache_type = REGCACHE_NONE,
 190};
 191
 192static const struct regmap_config allegro_sram_config = {
 193	.name = "sram",
 194	.reg_bits = 32,
 195	.val_bits = 32,
 196	.reg_stride = 4,
 197	.max_register = 0x7fff,
 198	.cache_type = REGCACHE_NONE,
 199};
 200
 201struct allegro_channel {
 202	struct kref ref;
 203	struct allegro_dev *dev;
 204	struct v4l2_fh fh;
 205	struct v4l2_ctrl_handler ctrl_handler;
 206
 207	unsigned int width;
 208	unsigned int height;
 209	unsigned int stride;
 210	struct v4l2_fract framerate;
 211
 212	enum v4l2_colorspace colorspace;
 213	enum v4l2_ycbcr_encoding ycbcr_enc;
 214	enum v4l2_quantization quantization;
 215	enum v4l2_xfer_func xfer_func;
 216
 217	u32 pixelformat;
 218	unsigned int sizeimage_raw;
 219	unsigned int osequence;
 220
 221	u32 codec;
 222	unsigned int sizeimage_encoded;
 223	unsigned int csequence;
 224
 225	bool frame_rc_enable;
 226	unsigned int bitrate;
 227	unsigned int bitrate_peak;
 228
 229	struct allegro_buffer config_blob;
 230
 231	unsigned int log2_max_frame_num;
 232	bool temporal_mvp_enable;
 233
 234	bool enable_loop_filter_across_tiles;
 235	bool enable_loop_filter_across_slices;
 236	bool enable_deblocking_filter_override;
 237	bool enable_reordering;
 238	bool dbf_ovr_en;
 239
 240	unsigned int num_ref_idx_l0;
 241	unsigned int num_ref_idx_l1;
 242
 243	/* Maximum range for motion estimation */
 244	int b_hrz_me_range;
 245	int b_vrt_me_range;
 246	int p_hrz_me_range;
 247	int p_vrt_me_range;
 248	/* Size limits of coding unit */
 249	int min_cu_size;
 250	int max_cu_size;
 251	/* Size limits of transform unit */
 252	int min_tu_size;
 253	int max_tu_size;
 254	int max_transfo_depth_intra;
 255	int max_transfo_depth_inter;
 256
 257	struct v4l2_ctrl *mpeg_video_h264_profile;
 258	struct v4l2_ctrl *mpeg_video_h264_level;
 259	struct v4l2_ctrl *mpeg_video_h264_i_frame_qp;
 260	struct v4l2_ctrl *mpeg_video_h264_max_qp;
 261	struct v4l2_ctrl *mpeg_video_h264_min_qp;
 262	struct v4l2_ctrl *mpeg_video_h264_p_frame_qp;
 263	struct v4l2_ctrl *mpeg_video_h264_b_frame_qp;
 264
 265	struct v4l2_ctrl *mpeg_video_hevc_profile;
 266	struct v4l2_ctrl *mpeg_video_hevc_level;
 267	struct v4l2_ctrl *mpeg_video_hevc_tier;
 268	struct v4l2_ctrl *mpeg_video_hevc_i_frame_qp;
 269	struct v4l2_ctrl *mpeg_video_hevc_max_qp;
 270	struct v4l2_ctrl *mpeg_video_hevc_min_qp;
 271	struct v4l2_ctrl *mpeg_video_hevc_p_frame_qp;
 272	struct v4l2_ctrl *mpeg_video_hevc_b_frame_qp;
 273
 274	struct v4l2_ctrl *mpeg_video_frame_rc_enable;
 275	struct { /* video bitrate mode control cluster */
 276		struct v4l2_ctrl *mpeg_video_bitrate_mode;
 277		struct v4l2_ctrl *mpeg_video_bitrate;
 278		struct v4l2_ctrl *mpeg_video_bitrate_peak;
 279	};
 280	struct v4l2_ctrl *mpeg_video_cpb_size;
 281	struct v4l2_ctrl *mpeg_video_gop_size;
 282
 283	struct v4l2_ctrl *encoder_buffer;
 284
 285	/* user_id is used to identify the channel during CREATE_CHANNEL */
 286	/* not sure, what to set here and if this is actually required */
 287	int user_id;
 288	/* channel_id is set by the mcu and used by all later commands */
 289	int mcu_channel_id;
 290
 291	struct list_head buffers_reference;
 292	struct list_head buffers_intermediate;
 293
 294	struct list_head source_shadow_list;
 295	struct list_head stream_shadow_list;
 296	/* protect shadow lists of buffers passed to firmware */
 297	struct mutex shadow_list_lock;
 298
 299	struct list_head list;
 300	struct completion completion;
 301
 302	unsigned int error;
 303};
 304
 305static inline struct allegro_channel *file_to_channel(struct file *filp)
 306{
 307	return container_of(file_to_v4l2_fh(filp), struct allegro_channel, fh);
 308}
 309
 310static inline int
 311allegro_channel_get_i_frame_qp(struct allegro_channel *channel)
 312{
 313	if (channel->codec == V4L2_PIX_FMT_HEVC)
 314		return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_i_frame_qp);
 315	else
 316		return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_i_frame_qp);
 317}
 318
 319static inline int
 320allegro_channel_get_p_frame_qp(struct allegro_channel *channel)
 321{
 322	if (channel->codec == V4L2_PIX_FMT_HEVC)
 323		return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_p_frame_qp);
 324	else
 325		return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_p_frame_qp);
 326}
 327
 328static inline int
 329allegro_channel_get_b_frame_qp(struct allegro_channel *channel)
 330{
 331	if (channel->codec == V4L2_PIX_FMT_HEVC)
 332		return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_b_frame_qp);
 333	else
 334		return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_b_frame_qp);
 335}
 336
 337static inline int
 338allegro_channel_get_min_qp(struct allegro_channel *channel)
 339{
 340	if (channel->codec == V4L2_PIX_FMT_HEVC)
 341		return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_min_qp);
 342	else
 343		return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_min_qp);
 344}
 345
 346static inline int
 347allegro_channel_get_max_qp(struct allegro_channel *channel)
 348{
 349	if (channel->codec == V4L2_PIX_FMT_HEVC)
 350		return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_max_qp);
 351	else
 352		return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_max_qp);
 353}
 354
 355struct allegro_m2m_buffer {
 356	struct v4l2_m2m_buffer buf;
 357	struct list_head head;
 358};
 359
 360#define to_allegro_m2m_buffer(__buf) \
 361	container_of(__buf, struct allegro_m2m_buffer, buf)
 362
 363struct fw_info {
 364	unsigned int id;
 365	unsigned int id_codec;
 366	char *version;
 367	unsigned int mailbox_cmd;
 368	unsigned int mailbox_status;
 369	size_t mailbox_size;
 370	enum mcu_msg_version mailbox_version;
 371	size_t suballocator_size;
 372};
 373
 374static const struct fw_info supported_firmware[] = {
 375	{
 376		.id = 18296,
 377		.id_codec = 96272,
 378		.version = "v2018.2",
 379		.mailbox_cmd = 0x7800,
 380		.mailbox_status = 0x7c00,
 381		.mailbox_size = 0x400 - 0x8,
 382		.mailbox_version = MCU_MSG_VERSION_2018_2,
 383		.suballocator_size = SZ_16M,
 384	}, {
 385		.id = 14680,
 386		.id_codec = 126572,
 387		.version = "v2019.2",
 388		.mailbox_cmd = 0x7000,
 389		.mailbox_status = 0x7800,
 390		.mailbox_size = 0x800 - 0x8,
 391		.mailbox_version = MCU_MSG_VERSION_2019_2,
 392		.suballocator_size = SZ_32M,
 393	},
 394};
 395
 396static inline u32 to_mcu_addr(struct allegro_dev *dev, dma_addr_t phys)
 397{
 398	if (upper_32_bits(phys) || (lower_32_bits(phys) & MCU_CACHE_OFFSET))
 399		v4l2_warn(&dev->v4l2_dev,
 400			  "address %pad is outside mcu window\n", &phys);
 401
 402	return lower_32_bits(phys) | MCU_CACHE_OFFSET;
 403}
 404
 405static inline u32 to_mcu_size(struct allegro_dev *dev, size_t size)
 406{
 407	return lower_32_bits(size);
 408}
 409
 410static inline u32 to_codec_addr(struct allegro_dev *dev, dma_addr_t phys)
 411{
 412	if (upper_32_bits(phys))
 413		v4l2_warn(&dev->v4l2_dev,
 414			  "address %pad cannot be used by codec\n", &phys);
 415
 416	return lower_32_bits(phys);
 417}
 418
 419static inline u64 ptr_to_u64(const void *ptr)
 420{
 421	return (uintptr_t)ptr;
 422}
 423
 424/* Helper functions for channel and user operations */
 425
 426static unsigned long allegro_next_user_id(struct allegro_dev *dev)
 427{
 428	if (dev->channel_user_ids == ~0UL)
 429		return -EBUSY;
 430
 431	return ffz(dev->channel_user_ids);
 432}
 433
 434static struct allegro_channel *
 435allegro_ref_get_channel_by_user_id(struct allegro_dev *dev,
 436				   unsigned int user_id)
 437{
 438	struct allegro_channel *channel;
 439
 440	guard(mutex)(&dev->channels_lock);
 441
 442	list_for_each_entry(channel, &dev->channels, list) {
 443		if (channel->user_id == user_id) {
 444			if (kref_get_unless_zero(&channel->ref))
 445				return channel;
 446			break;
 447		}
 448	}
 449
 450	return ERR_PTR(-EINVAL);
 451}
 452
 453static struct allegro_channel *
 454allegro_ref_get_channel_by_channel_id(struct allegro_dev *dev,
 455				      unsigned int channel_id)
 456{
 457	struct allegro_channel *channel;
 458
 459	guard(mutex)(&dev->channels_lock);
 460
 461	list_for_each_entry(channel, &dev->channels, list) {
 462		if (channel->mcu_channel_id == channel_id) {
 463			if (kref_get_unless_zero(&channel->ref))
 464				return channel;
 465			break;
 466		}
 467	}
 468
 469	return ERR_PTR(-EINVAL);
 470}
 471
 472static void allegro_free_channel(struct kref *ref)
 473{
 474	struct allegro_channel *channel = container_of(ref, struct allegro_channel, ref);
 475
 476	kfree(channel);
 477}
 478
 479static int allegro_ref_put_channel(struct allegro_channel *channel)
 480{
 481	return kref_put(&channel->ref, allegro_free_channel);
 482}
 483
 484static inline bool channel_exists(struct allegro_channel *channel)
 485{
 486	return channel->mcu_channel_id != -1;
 487}
 488
 489#define AL_ERROR			0x80
 490#define AL_ERR_INIT_FAILED		0x81
 491#define AL_ERR_NO_FRAME_DECODED		0x82
 492#define AL_ERR_RESOLUTION_CHANGE	0x85
 493#define AL_ERR_NO_MEMORY		0x87
 494#define AL_ERR_STREAM_OVERFLOW		0x88
 495#define AL_ERR_TOO_MANY_SLICES		0x89
 496#define AL_ERR_BUF_NOT_READY		0x8c
 497#define AL_ERR_NO_CHANNEL_AVAILABLE	0x8d
 498#define AL_ERR_RESOURCE_UNAVAILABLE	0x8e
 499#define AL_ERR_NOT_ENOUGH_CORES		0x8f
 500#define AL_ERR_REQUEST_MALFORMED	0x90
 501#define AL_ERR_CMD_NOT_ALLOWED		0x91
 502#define AL_ERR_INVALID_CMD_VALUE	0x92
 503
 504static inline const char *allegro_err_to_string(unsigned int err)
 505{
 506	switch (err) {
 507	case AL_ERR_INIT_FAILED:
 508		return "initialization failed";
 509	case AL_ERR_NO_FRAME_DECODED:
 510		return "no frame decoded";
 511	case AL_ERR_RESOLUTION_CHANGE:
 512		return "resolution change";
 513	case AL_ERR_NO_MEMORY:
 514		return "out of memory";
 515	case AL_ERR_STREAM_OVERFLOW:
 516		return "stream buffer overflow";
 517	case AL_ERR_TOO_MANY_SLICES:
 518		return "too many slices";
 519	case AL_ERR_BUF_NOT_READY:
 520		return "buffer not ready";
 521	case AL_ERR_NO_CHANNEL_AVAILABLE:
 522		return "no channel available";
 523	case AL_ERR_RESOURCE_UNAVAILABLE:
 524		return "resource unavailable";
 525	case AL_ERR_NOT_ENOUGH_CORES:
 526		return "not enough cores";
 527	case AL_ERR_REQUEST_MALFORMED:
 528		return "request malformed";
 529	case AL_ERR_CMD_NOT_ALLOWED:
 530		return "command not allowed";
 531	case AL_ERR_INVALID_CMD_VALUE:
 532		return "invalid command value";
 533	case AL_ERROR:
 534	default:
 535		return "unknown error";
 536	}
 537}
 538
 539static unsigned int estimate_stream_size(unsigned int width,
 540					 unsigned int height)
 541{
 542	unsigned int offset = ENCODER_STREAM_OFFSET;
 543	unsigned int num_blocks = DIV_ROUND_UP(width, SIZE_MACROBLOCK) *
 544					DIV_ROUND_UP(height, SIZE_MACROBLOCK);
 545	unsigned int pcm_size = SZ_256;
 546	unsigned int partition_table = SZ_256;
 547
 548	return round_up(offset + num_blocks * pcm_size + partition_table, 32);
 549}
 550
 551static enum v4l2_mpeg_video_h264_level
 552select_minimum_h264_level(unsigned int width, unsigned int height)
 553{
 554	unsigned int pic_width_in_mb = DIV_ROUND_UP(width, SIZE_MACROBLOCK);
 555	unsigned int frame_height_in_mb = DIV_ROUND_UP(height, SIZE_MACROBLOCK);
 556	unsigned int frame_size_in_mb = pic_width_in_mb * frame_height_in_mb;
 557	enum v4l2_mpeg_video_h264_level level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0;
 558
 559	/*
 560	 * The level limits are specified in Rec. ITU-T H.264 Annex A.3.1 and
 561	 * also specify limits regarding bit rate and CBP size. Only approximate
 562	 * the levels using the frame size.
 563	 *
 564	 * Level 5.1 allows up to 4k video resolution.
 565	 */
 566	if (frame_size_in_mb <= 99)
 567		level = V4L2_MPEG_VIDEO_H264_LEVEL_1_0;
 568	else if (frame_size_in_mb <= 396)
 569		level = V4L2_MPEG_VIDEO_H264_LEVEL_1_1;
 570	else if (frame_size_in_mb <= 792)
 571		level = V4L2_MPEG_VIDEO_H264_LEVEL_2_1;
 572	else if (frame_size_in_mb <= 1620)
 573		level = V4L2_MPEG_VIDEO_H264_LEVEL_2_2;
 574	else if (frame_size_in_mb <= 3600)
 575		level = V4L2_MPEG_VIDEO_H264_LEVEL_3_1;
 576	else if (frame_size_in_mb <= 5120)
 577		level = V4L2_MPEG_VIDEO_H264_LEVEL_3_2;
 578	else if (frame_size_in_mb <= 8192)
 579		level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0;
 580	else if (frame_size_in_mb <= 8704)
 581		level = V4L2_MPEG_VIDEO_H264_LEVEL_4_2;
 582	else if (frame_size_in_mb <= 22080)
 583		level = V4L2_MPEG_VIDEO_H264_LEVEL_5_0;
 584	else
 585		level = V4L2_MPEG_VIDEO_H264_LEVEL_5_1;
 586
 587	return level;
 588}
 589
 590static unsigned int h264_maximum_bitrate(enum v4l2_mpeg_video_h264_level level)
 591{
 592	switch (level) {
 593	case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
 594		return 64000;
 595	case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
 596		return 128000;
 597	case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
 598		return 192000;
 599	case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
 600		return 384000;
 601	case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
 602		return 768000;
 603	case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
 604		return 2000000;
 605	case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
 606		return 4000000;
 607	case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
 608		return 4000000;
 609	case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
 610		return 10000000;
 611	case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
 612		return 14000000;
 613	case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
 614		return 20000000;
 615	case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
 616		return 20000000;
 617	case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
 618		return 50000000;
 619	case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
 620		return 50000000;
 621	case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
 622		return 135000000;
 623	case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
 624	default:
 625		return 240000000;
 626	}
 627}
 628
 629static unsigned int h264_maximum_cpb_size(enum v4l2_mpeg_video_h264_level level)
 630{
 631	switch (level) {
 632	case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
 633		return 175;
 634	case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
 635		return 350;
 636	case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
 637		return 500;
 638	case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
 639		return 1000;
 640	case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
 641		return 2000;
 642	case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
 643		return 2000;
 644	case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
 645		return 4000;
 646	case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
 647		return 4000;
 648	case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
 649		return 10000;
 650	case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
 651		return 14000;
 652	case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
 653		return 20000;
 654	case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
 655		return 25000;
 656	case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
 657		return 62500;
 658	case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
 659		return 62500;
 660	case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
 661		return 135000;
 662	case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
 663	default:
 664		return 240000;
 665	}
 666}
 667
 668static enum v4l2_mpeg_video_hevc_level
 669select_minimum_hevc_level(unsigned int width, unsigned int height)
 670{
 671	unsigned int luma_picture_size = width * height;
 672	enum v4l2_mpeg_video_hevc_level level;
 673
 674	if (luma_picture_size <= 36864)
 675		level = V4L2_MPEG_VIDEO_HEVC_LEVEL_1;
 676	else if (luma_picture_size <= 122880)
 677		level = V4L2_MPEG_VIDEO_HEVC_LEVEL_2;
 678	else if (luma_picture_size <= 245760)
 679		level = V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1;
 680	else if (luma_picture_size <= 552960)
 681		level = V4L2_MPEG_VIDEO_HEVC_LEVEL_3;
 682	else if (luma_picture_size <= 983040)
 683		level = V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1;
 684	else if (luma_picture_size <= 2228224)
 685		level = V4L2_MPEG_VIDEO_HEVC_LEVEL_4;
 686	else if (luma_picture_size <= 8912896)
 687		level = V4L2_MPEG_VIDEO_HEVC_LEVEL_5;
 688	else
 689		level = V4L2_MPEG_VIDEO_HEVC_LEVEL_6;
 690
 691	return level;
 692}
 693
 694static unsigned int hevc_maximum_bitrate(enum v4l2_mpeg_video_hevc_level level)
 695{
 696	/*
 697	 * See Rec. ITU-T H.265 v5 (02/2018), A.4.2 Profile-specific level
 698	 * limits for the video profiles.
 699	 */
 700	switch (level) {
 701	case V4L2_MPEG_VIDEO_HEVC_LEVEL_1:
 702		return 128;
 703	case V4L2_MPEG_VIDEO_HEVC_LEVEL_2:
 704		return 1500;
 705	case V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1:
 706		return 3000;
 707	case V4L2_MPEG_VIDEO_HEVC_LEVEL_3:
 708		return 6000;
 709	case V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1:
 710		return 10000;
 711	case V4L2_MPEG_VIDEO_HEVC_LEVEL_4:
 712		return 12000;
 713	case V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1:
 714		return 20000;
 715	case V4L2_MPEG_VIDEO_HEVC_LEVEL_5:
 716		return 25000;
 717	default:
 718	case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1:
 719		return 40000;
 720	}
 721}
 722
 723static unsigned int hevc_maximum_cpb_size(enum v4l2_mpeg_video_hevc_level level)
 724{
 725	switch (level) {
 726	case V4L2_MPEG_VIDEO_HEVC_LEVEL_1:
 727		return 350;
 728	case V4L2_MPEG_VIDEO_HEVC_LEVEL_2:
 729		return 1500;
 730	case V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1:
 731		return 3000;
 732	case V4L2_MPEG_VIDEO_HEVC_LEVEL_3:
 733		return 6000;
 734	case V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1:
 735		return 10000;
 736	case V4L2_MPEG_VIDEO_HEVC_LEVEL_4:
 737		return 12000;
 738	case V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1:
 739		return 20000;
 740	case V4L2_MPEG_VIDEO_HEVC_LEVEL_5:
 741		return 25000;
 742	default:
 743	case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1:
 744		return 40000;
 745	}
 746}
 747
 748static const struct fw_info *
 749allegro_get_firmware_info(struct allegro_dev *dev,
 750			  const struct firmware *fw,
 751			  const struct firmware *fw_codec)
 752{
 753	int i;
 754	unsigned int id = fw->size;
 755	unsigned int id_codec = fw_codec->size;
 756
 757	for (i = 0; i < ARRAY_SIZE(supported_firmware); i++)
 758		if (supported_firmware[i].id == id &&
 759		    supported_firmware[i].id_codec == id_codec)
 760			return &supported_firmware[i];
 761
 762	return NULL;
 763}
 764
 765/*
 766 * Buffers that are used internally by the MCU.
 767 */
 768
 769static int allegro_alloc_buffer(struct allegro_dev *dev,
 770				struct allegro_buffer *buffer, size_t size)
 771{
 772	buffer->vaddr = dma_alloc_coherent(&dev->plat_dev->dev, size,
 773					   &buffer->paddr, GFP_KERNEL);
 774	if (!buffer->vaddr)
 775		return -ENOMEM;
 776	buffer->size = size;
 777
 778	return 0;
 779}
 780
 781static void allegro_free_buffer(struct allegro_dev *dev,
 782				struct allegro_buffer *buffer)
 783{
 784	if (buffer->vaddr) {
 785		dma_free_coherent(&dev->plat_dev->dev, buffer->size,
 786				  buffer->vaddr, buffer->paddr);
 787		buffer->vaddr = NULL;
 788		buffer->size = 0;
 789	}
 790}
 791
 792/*
 793 * Mailbox interface to send messages to the MCU.
 794 */
 795
 796static void allegro_mcu_interrupt(struct allegro_dev *dev);
 797static void allegro_handle_message(struct allegro_dev *dev,
 798				   union mcu_msg_response *msg);
 799
 800static struct allegro_mbox *allegro_mbox_init(struct allegro_dev *dev,
 801					      unsigned int base, size_t size)
 802{
 803	struct allegro_mbox *mbox;
 804
 805	mbox = devm_kmalloc(&dev->plat_dev->dev, sizeof(*mbox), GFP_KERNEL);
 806	if (!mbox)
 807		return ERR_PTR(-ENOMEM);
 808
 809	mbox->dev = dev;
 810
 811	mbox->head = base;
 812	mbox->tail = base + 0x4;
 813	mbox->data = base + 0x8;
 814	mbox->size = size;
 815	mutex_init(&mbox->lock);
 816
 817	regmap_write(dev->sram, mbox->head, 0);
 818	regmap_write(dev->sram, mbox->tail, 0);
 819
 820	return mbox;
 821}
 822
 823static int allegro_mbox_write(struct allegro_mbox *mbox,
 824			      const u32 *src, size_t size)
 825{
 826	struct regmap *sram = mbox->dev->sram;
 827	unsigned int tail;
 828	size_t size_no_wrap;
 829	int err = 0;
 830	int stride = regmap_get_reg_stride(sram);
 831
 832	if (!src)
 833		return -EINVAL;
 834
 835	if (size > mbox->size)
 836		return -EINVAL;
 837
 838	mutex_lock(&mbox->lock);
 839	regmap_read(sram, mbox->tail, &tail);
 840	if (tail > mbox->size) {
 841		err = -EIO;
 842		goto out;
 843	}
 844	size_no_wrap = min(size, mbox->size - (size_t)tail);
 845	regmap_bulk_write(sram, mbox->data + tail,
 846			  src, size_no_wrap / stride);
 847	regmap_bulk_write(sram, mbox->data,
 848			  src + (size_no_wrap / sizeof(*src)),
 849			  (size - size_no_wrap) / stride);
 850	regmap_write(sram, mbox->tail, (tail + size) % mbox->size);
 851
 852out:
 853	mutex_unlock(&mbox->lock);
 854
 855	return err;
 856}
 857
 858static unsigned int allegro_mbox_get_available(struct allegro_mbox *mbox)
 859{
 860	struct regmap *sram = mbox->dev->sram;
 861	unsigned int head, tail;
 862
 863	regmap_read(sram, mbox->head, &head);
 864	regmap_read(sram, mbox->tail, &tail);
 865
 866	if (tail >= head)
 867		return tail - head;
 868	else
 869		return mbox->size - (head - tail);
 870}
 871
 872static ssize_t allegro_mbox_read(struct allegro_mbox *mbox,
 873				 u32 *dst, size_t nbyte)
 874{
 875	struct {
 876		u16 length;
 877		u16 type;
 878	} __attribute__ ((__packed__)) *header;
 879	struct regmap *sram = mbox->dev->sram;
 880	unsigned int available, head;
 881	ssize_t size;
 882	size_t body_no_wrap;
 883	int stride = regmap_get_reg_stride(sram);
 884
 885	available = allegro_mbox_get_available(mbox);
 886	if (available < sizeof(*header))
 887		return -EAGAIN;
 888
 889	regmap_read(sram, mbox->head, &head);
 890	if (head > mbox->size)
 891		return -EIO;
 892
 893	/* Assume that the header does not wrap. */
 894	regmap_bulk_read(sram, mbox->data + head,
 895			 dst, sizeof(*header) / stride);
 896	header = (void *)dst;
 897	size = header->length + sizeof(*header);
 898	if (size > mbox->size || size & 0x3)
 899		return -EIO;
 900	if (size > nbyte)
 901		return -EINVAL;
 902	if (size > available)
 903		return -EAGAIN;
 904
 905	/*
 906	 * The message might wrap within the mailbox. If the message does not
 907	 * wrap, the first read will read the entire message, otherwise the
 908	 * first read will read message until the end of the mailbox and the
 909	 * second read will read the remaining bytes from the beginning of the
 910	 * mailbox.
 911	 *
 912	 * Skip the header, as was already read to get the size of the body.
 913	 */
 914	body_no_wrap = min((size_t)header->length,
 915			   (size_t)(mbox->size - (head + sizeof(*header))));
 916	regmap_bulk_read(sram, mbox->data + head + sizeof(*header),
 917			 dst + (sizeof(*header) / sizeof(*dst)),
 918			 body_no_wrap / stride);
 919	regmap_bulk_read(sram, mbox->data,
 920			 dst + (sizeof(*header) + body_no_wrap) / sizeof(*dst),
 921			 (header->length - body_no_wrap) / stride);
 922
 923	regmap_write(sram, mbox->head, (head + size) % mbox->size);
 924
 925	return size;
 926}
 927
 928/**
 929 * allegro_mbox_send() - Send a message via the mailbox
 930 * @mbox: the mailbox which is used to send the message
 931 * @msg: the message to send
 932 */
 933static int allegro_mbox_send(struct allegro_mbox *mbox, void *msg)
 934{
 935	struct allegro_dev *dev = mbox->dev;
 936	ssize_t size;
 937	int err;
 938	u32 *tmp;
 939
 940	tmp = kzalloc(mbox->size, GFP_KERNEL);
 941	if (!tmp) {
 942		err = -ENOMEM;
 943		goto out;
 944	}
 945
 946	size = allegro_encode_mail(tmp, msg);
 947
 948	err = allegro_mbox_write(mbox, tmp, size);
 949	kfree(tmp);
 950	if (err)
 951		goto out;
 952
 953	allegro_mcu_interrupt(dev);
 954
 955out:
 956	return err;
 957}
 958
 959/**
 960 * allegro_mbox_notify() - Notify the mailbox about a new message
 961 * @mbox: The allegro_mbox to notify
 962 */
 963static int allegro_mbox_notify(struct allegro_mbox *mbox)
 964{
 965	struct allegro_dev *dev = mbox->dev;
 966	union mcu_msg_response *msg;
 967	u32 *tmp;
 968	int err;
 969
 970	msg = kmalloc(sizeof(*msg), GFP_KERNEL);
 971	if (!msg)
 972		return -ENOMEM;
 973
 974	msg->header.version = dev->fw_info->mailbox_version;
 975
 976	tmp = kmalloc(mbox->size, GFP_KERNEL);
 977	if (!tmp) {
 978		err = -ENOMEM;
 979		goto out;
 980	}
 981
 982	err = allegro_mbox_read(mbox, tmp, mbox->size);
 983	if (err < 0)
 984		goto out;
 985
 986	err = allegro_decode_mail(msg, tmp);
 987	if (err)
 988		goto out;
 989
 990	allegro_handle_message(dev, msg);
 991
 992out:
 993	kfree(tmp);
 994	kfree(msg);
 995
 996	return err;
 997}
 998
 999static int allegro_encoder_buffer_init(struct allegro_dev *dev,
1000				       struct allegro_encoder_buffer *buffer)
1001{
1002	int err;
1003	struct regmap *settings = dev->settings;
1004	unsigned int supports_10_bit;
1005	unsigned int memory_depth;
1006	unsigned int num_cores;
1007	unsigned int color_depth;
1008	unsigned long clk_rate;
1009
1010	/* We don't support the encoder buffer pre Firmware version 2019.2 */
1011	if (dev->fw_info->mailbox_version < MCU_MSG_VERSION_2019_2)
1012		return -ENODEV;
1013
1014	if (!settings)
1015		return -EINVAL;
1016
1017	err = regmap_read(settings, VCU_ENC_COLOR_DEPTH, &supports_10_bit);
1018	if (err < 0)
1019		return err;
1020	err = regmap_read(settings, VCU_MEMORY_DEPTH, &memory_depth);
1021	if (err < 0)
1022		return err;
1023	err = regmap_read(settings, VCU_NUM_CORE, &num_cores);
1024	if (err < 0)
1025		return err;
1026
1027	clk_rate = clk_get_rate(dev->clk_core);
1028	if (clk_rate == 0)
1029		return -EINVAL;
1030
1031	color_depth = supports_10_bit ? 10 : 8;
1032	/* The firmware expects the encoder buffer size in bits. */
1033	buffer->size = color_depth * 32 * memory_depth;
1034	buffer->color_depth = color_depth;
1035	buffer->num_cores = num_cores;
1036	buffer->clk_rate = clk_rate;
1037
1038	v4l2_dbg(1, debug, &dev->v4l2_dev,
1039		 "using %d bits encoder buffer with %d-bit color depth\n",
1040		 buffer->size, color_depth);
1041
1042	return 0;
1043}
1044
1045static void allegro_mcu_send_init(struct allegro_dev *dev,
1046				  dma_addr_t suballoc_dma, size_t suballoc_size)
1047{
1048	struct mcu_msg_init_request msg;
1049
1050	memset(&msg, 0, sizeof(msg));
1051
1052	msg.header.type = MCU_MSG_TYPE_INIT;
1053	msg.header.version = dev->fw_info->mailbox_version;
1054
1055	msg.suballoc_dma = to_mcu_addr(dev, suballoc_dma);
1056	msg.suballoc_size = to_mcu_size(dev, suballoc_size);
1057
1058	if (dev->has_encoder_buffer) {
1059		msg.encoder_buffer_size = dev->encoder_buffer.size;
1060		msg.encoder_buffer_color_depth = dev->encoder_buffer.color_depth;
1061		msg.num_cores = dev->encoder_buffer.num_cores;
1062		msg.clk_rate = dev->encoder_buffer.clk_rate;
1063	} else {
1064		msg.encoder_buffer_size = -1;
1065		msg.encoder_buffer_color_depth = -1;
1066		msg.num_cores = -1;
1067		msg.clk_rate = -1;
1068	}
1069
1070	allegro_mbox_send(dev->mbox_command, &msg);
1071}
1072
1073static u32 v4l2_pixelformat_to_mcu_format(u32 pixelformat)
1074{
1075	switch (pixelformat) {
1076	case V4L2_PIX_FMT_NV12:
1077		/* AL_420_8BITS: 0x100 -> NV12, 0x88 -> 8 bit */
1078		return 0x100 | 0x88;
1079	default:
1080		return -EINVAL;
1081	}
1082}
1083
1084static u32 v4l2_colorspace_to_mcu_colorspace(enum v4l2_colorspace colorspace)
1085{
1086	switch (colorspace) {
1087	case V4L2_COLORSPACE_REC709:
1088		return 2;
1089	case V4L2_COLORSPACE_SMPTE170M:
1090		return 3;
1091	case V4L2_COLORSPACE_SMPTE240M:
1092		return 4;
1093	case V4L2_COLORSPACE_SRGB:
1094		return 7;
1095	default:
1096		/* UNKNOWN */
1097		return 0;
1098	}
1099}
1100
1101static u8 v4l2_profile_to_mcu_profile(enum v4l2_mpeg_video_h264_profile profile)
1102{
1103	switch (profile) {
1104	case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:
1105	default:
1106		return 66;
1107	}
1108}
1109
1110static u16 v4l2_level_to_mcu_level(enum v4l2_mpeg_video_h264_level level)
1111{
1112	switch (level) {
1113	case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
1114		return 10;
1115	case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
1116		return 11;
1117	case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
1118		return 12;
1119	case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
1120		return 13;
1121	case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
1122		return 20;
1123	case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
1124		return 21;
1125	case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
1126		return 22;
1127	case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
1128		return 30;
1129	case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
1130		return 31;
1131	case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
1132		return 32;
1133	case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
1134		return 40;
1135	case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
1136		return 41;
1137	case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
1138		return 42;
1139	case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
1140		return 50;
1141	case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
1142	default:
1143		return 51;
1144	}
1145}
1146
1147static u8 hevc_profile_to_mcu_profile(enum v4l2_mpeg_video_hevc_profile profile)
1148{
1149	switch (profile) {
1150	default:
1151	case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN:
1152		return 1;
1153	case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10:
1154		return 2;
1155	case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE:
1156		return 3;
1157	}
1158}
1159
1160static u16 hevc_level_to_mcu_level(enum v4l2_mpeg_video_hevc_level level)
1161{
1162	switch (level) {
1163	case V4L2_MPEG_VIDEO_HEVC_LEVEL_1:
1164		return 10;
1165	case V4L2_MPEG_VIDEO_HEVC_LEVEL_2:
1166		return 20;
1167	case V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1:
1168		return 21;
1169	case V4L2_MPEG_VIDEO_HEVC_LEVEL_3:
1170		return 30;
1171	case V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1:
1172		return 31;
1173	case V4L2_MPEG_VIDEO_HEVC_LEVEL_4:
1174		return 40;
1175	case V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1:
1176		return 41;
1177	case V4L2_MPEG_VIDEO_HEVC_LEVEL_5:
1178		return 50;
1179	default:
1180	case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1:
1181		return 51;
1182	}
1183}
1184
1185static u8 hevc_tier_to_mcu_tier(enum v4l2_mpeg_video_hevc_tier tier)
1186{
1187	switch (tier) {
1188	default:
1189	case V4L2_MPEG_VIDEO_HEVC_TIER_MAIN:
1190		return 0;
1191	case V4L2_MPEG_VIDEO_HEVC_TIER_HIGH:
1192		return 1;
1193	}
1194}
1195
1196static u32
1197v4l2_bitrate_mode_to_mcu_mode(enum v4l2_mpeg_video_bitrate_mode mode)
1198{
1199	switch (mode) {
1200	case V4L2_MPEG_VIDEO_BITRATE_MODE_VBR:
1201		return 2;
1202	case V4L2_MPEG_VIDEO_BITRATE_MODE_CBR:
1203	default:
1204		return 1;
1205	}
1206}
1207
1208static u32 v4l2_cpb_size_to_mcu(unsigned int cpb_size, unsigned int bitrate)
1209{
1210	unsigned int cpb_size_kbit;
1211	unsigned int bitrate_kbps;
1212
1213	/*
1214	 * The mcu expects the CPB size in units of a 90 kHz clock, but the
1215	 * channel follows the V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE and stores
1216	 * the CPB size in kilobytes.
1217	 */
1218	cpb_size_kbit = cpb_size * BITS_PER_BYTE;
1219	bitrate_kbps = bitrate / 1000;
1220
1221	return (cpb_size_kbit * 90000) / bitrate_kbps;
1222}
1223
1224static s16 get_qp_delta(int minuend, int subtrahend)
1225{
1226	if (minuend == subtrahend)
1227		return -1;
1228	else
1229		return minuend - subtrahend;
1230}
1231
1232static u32 allegro_channel_get_entropy_mode(struct allegro_channel *channel)
1233{
1234#define ALLEGRO_ENTROPY_MODE_CAVLC 0
1235#define ALLEGRO_ENTROPY_MODE_CABAC 1
1236
1237	/* HEVC always uses CABAC, but this has to be explicitly set */
1238	if (channel->codec == V4L2_PIX_FMT_HEVC)
1239		return ALLEGRO_ENTROPY_MODE_CABAC;
1240
1241	return ALLEGRO_ENTROPY_MODE_CAVLC;
1242}
1243
1244static int fill_create_channel_param(struct allegro_channel *channel,
1245				     struct create_channel_param *param)
1246{
1247	int i_frame_qp = allegro_channel_get_i_frame_qp(channel);
1248	int p_frame_qp = allegro_channel_get_p_frame_qp(channel);
1249	int b_frame_qp = allegro_channel_get_b_frame_qp(channel);
1250	int bitrate_mode = v4l2_ctrl_g_ctrl(channel->mpeg_video_bitrate_mode);
1251	unsigned int cpb_size = v4l2_ctrl_g_ctrl(channel->mpeg_video_cpb_size);
1252
1253	param->width = channel->width;
1254	param->height = channel->height;
1255	param->format = v4l2_pixelformat_to_mcu_format(channel->pixelformat);
1256	param->colorspace =
1257		v4l2_colorspace_to_mcu_colorspace(channel->colorspace);
1258	param->src_mode = 0x0;
1259
1260	param->codec = channel->codec;
1261	if (channel->codec == V4L2_PIX_FMT_H264) {
1262		enum v4l2_mpeg_video_h264_profile profile;
1263		enum v4l2_mpeg_video_h264_level level;
1264
1265		profile = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_profile);
1266		level = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_level);
1267
1268		param->profile = v4l2_profile_to_mcu_profile(profile);
1269		param->constraint_set_flags = BIT(1);
1270		param->level = v4l2_level_to_mcu_level(level);
1271	} else {
1272		enum v4l2_mpeg_video_hevc_profile profile;
1273		enum v4l2_mpeg_video_hevc_level level;
1274		enum v4l2_mpeg_video_hevc_tier tier;
1275
1276		profile = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_profile);
1277		level = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_level);
1278		tier = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_tier);
1279
1280		param->profile = hevc_profile_to_mcu_profile(profile);
1281		param->level = hevc_level_to_mcu_level(level);
1282		param->tier = hevc_tier_to_mcu_tier(tier);
1283	}
1284
1285	param->log2_max_poc = LOG2_MAX_PIC_ORDER_CNT;
1286	param->log2_max_frame_num = channel->log2_max_frame_num;
1287	param->temporal_mvp_enable = channel->temporal_mvp_enable;
1288
1289	param->dbf_ovr_en = channel->dbf_ovr_en;
1290	param->override_lf = channel->enable_deblocking_filter_override;
1291	param->enable_reordering = channel->enable_reordering;
1292	param->entropy_mode = allegro_channel_get_entropy_mode(channel);
1293	param->rdo_cost_mode = 1;
1294	param->custom_lda = 1;
1295	param->lf = 1;
1296	param->lf_x_tile = channel->enable_loop_filter_across_tiles;
1297	param->lf_x_slice = channel->enable_loop_filter_across_slices;
1298
1299	param->src_bit_depth = 8;
1300
1301	param->beta_offset = BETA_OFFSET_DIV_2;
1302	param->tc_offset = TC_OFFSET_DIV_2;
1303	param->num_slices = 1;
1304	param->me_range[0] = channel->b_hrz_me_range;
1305	param->me_range[1] = channel->b_vrt_me_range;
1306	param->me_range[2] = channel->p_hrz_me_range;
1307	param->me_range[3] = channel->p_vrt_me_range;
1308	param->max_cu_size = channel->max_cu_size;
1309	param->min_cu_size = channel->min_cu_size;
1310	param->max_tu_size = channel->max_tu_size;
1311	param->min_tu_size = channel->min_tu_size;
1312	param->max_transfo_depth_intra = channel->max_transfo_depth_intra;
1313	param->max_transfo_depth_inter = channel->max_transfo_depth_inter;
1314
1315	param->encoder_buffer_enabled = v4l2_ctrl_g_ctrl(channel->encoder_buffer);
1316	param->encoder_buffer_offset = 0;
1317
1318	param->rate_control_mode = channel->frame_rc_enable ?
1319		v4l2_bitrate_mode_to_mcu_mode(bitrate_mode) : 0;
1320
1321	param->cpb_size = v4l2_cpb_size_to_mcu(cpb_size, channel->bitrate_peak);
1322	/* Shall be ]0;cpb_size in 90 kHz units]. Use maximum value. */
1323	param->initial_rem_delay = param->cpb_size;
1324	param->framerate = DIV_ROUND_UP(channel->framerate.numerator,
1325					channel->framerate.denominator);
1326	param->clk_ratio = channel->framerate.denominator == 1001 ? 1001 : 1000;
1327	param->target_bitrate = channel->bitrate;
1328	param->max_bitrate = channel->bitrate_peak;
1329	param->initial_qp = i_frame_qp;
1330	param->min_qp = allegro_channel_get_min_qp(channel);
1331	param->max_qp = allegro_channel_get_max_qp(channel);
1332	param->ip_delta = get_qp_delta(i_frame_qp, p_frame_qp);
1333	param->pb_delta = get_qp_delta(p_frame_qp, b_frame_qp);
1334	param->golden_ref = 0;
1335	param->golden_delta = 2;
1336	param->golden_ref_frequency = 10;
1337	param->rate_control_option = 0x00000000;
1338
1339	param->num_pixel = channel->width + channel->height;
1340	param->max_psnr = 4200;
1341	param->max_pixel_value = 255;
1342
1343	param->gop_ctrl_mode = 0x00000002;
1344	param->freq_idr = v4l2_ctrl_g_ctrl(channel->mpeg_video_gop_size);
1345	param->freq_lt = 0;
1346	param->gdr_mode = 0x00000000;
1347	param->gop_length = v4l2_ctrl_g_ctrl(channel->mpeg_video_gop_size);
1348	param->subframe_latency = 0x00000000;
1349
1350	param->lda_factors[0] = 51;
1351	param->lda_factors[1] = 90;
1352	param->lda_factors[2] = 151;
1353	param->lda_factors[3] = 151;
1354	param->lda_factors[4] = 151;
1355	param->lda_factors[5] = 151;
1356
1357	param->max_num_merge_cand = 5;
1358
1359	return 0;
1360}
1361
1362static int allegro_mcu_send_create_channel(struct allegro_dev *dev,
1363					   struct allegro_channel *channel)
1364{
1365	struct mcu_msg_create_channel msg;
1366	struct allegro_buffer *blob = &channel->config_blob;
1367	struct create_channel_param param;
1368	size_t size;
1369
1370	memset(&param, 0, sizeof(param));
1371	fill_create_channel_param(channel, &param);
1372	allegro_alloc_buffer(dev, blob, sizeof(struct create_channel_param));
1373	param.version = dev->fw_info->mailbox_version;
1374	size = allegro_encode_config_blob(blob->vaddr, &param);
1375
1376	memset(&msg, 0, sizeof(msg));
1377
1378	msg.header.type = MCU_MSG_TYPE_CREATE_CHANNEL;
1379	msg.header.version = dev->fw_info->mailbox_version;
1380
1381	msg.user_id = channel->user_id;
1382
1383	msg.blob = blob->vaddr;
1384	msg.blob_size = size;
1385	msg.blob_mcu_addr = to_mcu_addr(dev, blob->paddr);
1386
1387	allegro_mbox_send(dev->mbox_command, &msg);
1388
1389	return 0;
1390}
1391
1392static int allegro_mcu_send_destroy_channel(struct allegro_dev *dev,
1393					    struct allegro_channel *channel)
1394{
1395	struct mcu_msg_destroy_channel msg;
1396
1397	memset(&msg, 0, sizeof(msg));
1398
1399	msg.header.type = MCU_MSG_TYPE_DESTROY_CHANNEL;
1400	msg.header.version = dev->fw_info->mailbox_version;
1401
1402	msg.channel_id = channel->mcu_channel_id;
1403
1404	allegro_mbox_send(dev->mbox_command, &msg);
1405
1406	return 0;
1407}
1408
1409static int allegro_mcu_send_put_stream_buffer(struct allegro_dev *dev,
1410					      struct allegro_channel *channel,
1411					      dma_addr_t paddr,
1412					      unsigned long size,
1413					      u64 dst_handle)
1414{
1415	struct mcu_msg_put_stream_buffer msg;
1416
1417	memset(&msg, 0, sizeof(msg));
1418
1419	msg.header.type = MCU_MSG_TYPE_PUT_STREAM_BUFFER;
1420	msg.header.version = dev->fw_info->mailbox_version;
1421
1422	msg.channel_id = channel->mcu_channel_id;
1423	msg.dma_addr = to_codec_addr(dev, paddr);
1424	msg.mcu_addr = to_mcu_addr(dev, paddr);
1425	msg.size = size;
1426	msg.offset = ENCODER_STREAM_OFFSET;
1427	/* copied to mcu_msg_encode_frame_response */
1428	msg.dst_handle = dst_handle;
1429
1430	allegro_mbox_send(dev->mbox_command, &msg);
1431
1432	return 0;
1433}
1434
1435static int allegro_mcu_send_encode_frame(struct allegro_dev *dev,
1436					 struct allegro_channel *channel,
1437					 dma_addr_t src_y, dma_addr_t src_uv,
1438					 u64 src_handle)
1439{
1440	struct mcu_msg_encode_frame msg;
1441	bool use_encoder_buffer = v4l2_ctrl_g_ctrl(channel->encoder_buffer);
1442
1443	memset(&msg, 0, sizeof(msg));
1444
1445	msg.header.type = MCU_MSG_TYPE_ENCODE_FRAME;
1446	msg.header.version = dev->fw_info->mailbox_version;
1447
1448	msg.channel_id = channel->mcu_channel_id;
1449	msg.encoding_options = AL_OPT_FORCE_LOAD;
1450	if (use_encoder_buffer)
1451		msg.encoding_options |= AL_OPT_USE_L2;
1452	msg.pps_qp = 26; /* qp are relative to 26 */
1453	msg.user_param = 0; /* copied to mcu_msg_encode_frame_response */
1454	/* src_handle is copied to mcu_msg_encode_frame_response */
1455	msg.src_handle = src_handle;
1456	msg.src_y = to_codec_addr(dev, src_y);
1457	msg.src_uv = to_codec_addr(dev, src_uv);
1458	msg.stride = channel->stride;
1459
1460	allegro_mbox_send(dev->mbox_command, &msg);
1461
1462	return 0;
1463}
1464
1465static int allegro_mcu_wait_for_init_timeout(struct allegro_dev *dev,
1466					     unsigned long timeout_ms)
1467{
1468	unsigned long time_left;
1469
1470	time_left = wait_for_completion_timeout(&dev->init_complete,
1471						msecs_to_jiffies(timeout_ms));
1472	if (time_left == 0)
1473		return -ETIMEDOUT;
1474
1475	reinit_completion(&dev->init_complete);
1476	return 0;
1477}
1478
1479static int allegro_mcu_push_buffer_internal(struct allegro_channel *channel,
1480					    enum mcu_msg_type type)
1481{
1482	struct allegro_dev *dev = channel->dev;
1483	struct mcu_msg_push_buffers_internal *msg;
1484	struct mcu_msg_push_buffers_internal_buffer *buffer;
1485	unsigned int num_buffers = 0;
1486	size_t size;
1487	struct allegro_buffer *al_buffer;
1488	struct list_head *list;
1489	int err;
1490
1491	switch (type) {
1492	case MCU_MSG_TYPE_PUSH_BUFFER_REFERENCE:
1493		list = &channel->buffers_reference;
1494		break;
1495	case MCU_MSG_TYPE_PUSH_BUFFER_INTERMEDIATE:
1496		list = &channel->buffers_intermediate;
1497		break;
1498	default:
1499		return -EINVAL;
1500	}
1501
1502	list_for_each_entry(al_buffer, list, head)
1503		num_buffers++;
1504	size = struct_size(msg, buffer, num_buffers);
1505
1506	msg = kmalloc(size, GFP_KERNEL);
1507	if (!msg)
1508		return -ENOMEM;
1509
1510	msg->header.type = type;
1511	msg->header.version = dev->fw_info->mailbox_version;
1512
1513	msg->channel_id = channel->mcu_channel_id;
1514	msg->num_buffers = num_buffers;
1515
1516	buffer = msg->buffer;
1517	list_for_each_entry(al_buffer, list, head) {
1518		buffer->dma_addr = to_codec_addr(dev, al_buffer->paddr);
1519		buffer->mcu_addr = to_mcu_addr(dev, al_buffer->paddr);
1520		buffer->size = to_mcu_size(dev, al_buffer->size);
1521		buffer++;
1522	}
1523
1524	err = allegro_mbox_send(dev->mbox_command, msg);
1525
1526	kfree(msg);
1527	return err;
1528}
1529
1530static int allegro_mcu_push_buffer_intermediate(struct allegro_channel *channel)
1531{
1532	enum mcu_msg_type type = MCU_MSG_TYPE_PUSH_BUFFER_INTERMEDIATE;
1533
1534	return allegro_mcu_push_buffer_internal(channel, type);
1535}
1536
1537static int allegro_mcu_push_buffer_reference(struct allegro_channel *channel)
1538{
1539	enum mcu_msg_type type = MCU_MSG_TYPE_PUSH_BUFFER_REFERENCE;
1540
1541	return allegro_mcu_push_buffer_internal(channel, type);
1542}
1543
1544static int allocate_buffers_internal(struct allegro_channel *channel,
1545				     struct list_head *list,
1546				     size_t n, size_t size)
1547{
1548	struct allegro_dev *dev = channel->dev;
1549	unsigned int i;
1550	int err;
1551	struct allegro_buffer *buffer, *tmp;
1552
1553	for (i = 0; i < n; i++) {
1554		buffer = kmalloc(sizeof(*buffer), GFP_KERNEL);
1555		if (!buffer) {
1556			err = -ENOMEM;
1557			goto err;
1558		}
1559		INIT_LIST_HEAD(&buffer->head);
1560
1561		err = allegro_alloc_buffer(dev, buffer, size);
1562		if (err) {
1563			kfree(buffer);
1564			goto err;
1565		}
1566		list_add(&buffer->head, list);
1567	}
1568
1569	return 0;
1570
1571err:
1572	list_for_each_entry_safe(buffer, tmp, list, head) {
1573		list_del(&buffer->head);
1574		allegro_free_buffer(dev, buffer);
1575		kfree(buffer);
1576	}
1577	return err;
1578}
1579
1580static void destroy_buffers_internal(struct allegro_channel *channel,
1581				     struct list_head *list)
1582{
1583	struct allegro_dev *dev = channel->dev;
1584	struct allegro_buffer *buffer, *tmp;
1585
1586	list_for_each_entry_safe(buffer, tmp, list, head) {
1587		list_del(&buffer->head);
1588		allegro_free_buffer(dev, buffer);
1589		kfree(buffer);
1590	}
1591}
1592
1593static void destroy_reference_buffers(struct allegro_channel *channel)
1594{
1595	return destroy_buffers_internal(channel, &channel->buffers_reference);
1596}
1597
1598static void destroy_intermediate_buffers(struct allegro_channel *channel)
1599{
1600	return destroy_buffers_internal(channel,
1601					&channel->buffers_intermediate);
1602}
1603
1604static int allocate_intermediate_buffers(struct allegro_channel *channel,
1605					 size_t n, size_t size)
1606{
1607	return allocate_buffers_internal(channel,
1608					 &channel->buffers_intermediate,
1609					 n, size);
1610}
1611
1612static int allocate_reference_buffers(struct allegro_channel *channel,
1613				      size_t n, size_t size)
1614{
1615	return allocate_buffers_internal(channel,
1616					 &channel->buffers_reference,
1617					 n, PAGE_ALIGN(size));
1618}
1619
1620static ssize_t allegro_h264_write_sps(struct allegro_channel *channel,
1621				      void *dest, size_t n)
1622{
1623	struct allegro_dev *dev = channel->dev;
1624	struct nal_h264_sps *sps;
1625	ssize_t size;
1626	unsigned int size_mb = SIZE_MACROBLOCK;
1627	/* Calculation of crop units in Rec. ITU-T H.264 (04/2017) p. 76 */
1628	unsigned int crop_unit_x = 2;
1629	unsigned int crop_unit_y = 2;
1630	enum v4l2_mpeg_video_h264_profile profile;
1631	enum v4l2_mpeg_video_h264_level level;
1632	unsigned int cpb_size;
1633	unsigned int cpb_size_scale;
1634
1635	sps = kzalloc(sizeof(*sps), GFP_KERNEL);
1636	if (!sps)
1637		return -ENOMEM;
1638
1639	profile = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_profile);
1640	level = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_level);
1641
1642	sps->profile_idc = nal_h264_profile(profile);
1643	sps->constraint_set0_flag = 0;
1644	sps->constraint_set1_flag = 1;
1645	sps->constraint_set2_flag = 0;
1646	sps->constraint_set3_flag = 0;
1647	sps->constraint_set4_flag = 0;
1648	sps->constraint_set5_flag = 0;
1649	sps->level_idc = nal_h264_level(level);
1650	sps->seq_parameter_set_id = 0;
1651	sps->log2_max_frame_num_minus4 = LOG2_MAX_FRAME_NUM - 4;
1652	sps->pic_order_cnt_type = 0;
1653	sps->log2_max_pic_order_cnt_lsb_minus4 = LOG2_MAX_PIC_ORDER_CNT - 4;
1654	sps->max_num_ref_frames = 3;
1655	sps->gaps_in_frame_num_value_allowed_flag = 0;
1656	sps->pic_width_in_mbs_minus1 =
1657		DIV_ROUND_UP(channel->width, size_mb) - 1;
1658	sps->pic_height_in_map_units_minus1 =
1659		DIV_ROUND_UP(channel->height, size_mb) - 1;
1660	sps->frame_mbs_only_flag = 1;
1661	sps->mb_adaptive_frame_field_flag = 0;
1662	sps->direct_8x8_inference_flag = 1;
1663	sps->frame_cropping_flag =
1664		(channel->width % size_mb) || (channel->height % size_mb);
1665	if (sps->frame_cropping_flag) {
1666		sps->crop_left = 0;
1667		sps->crop_right = (round_up(channel->width, size_mb) - channel->width) / crop_unit_x;
1668		sps->crop_top = 0;
1669		sps->crop_bottom = (round_up(channel->height, size_mb) - channel->height) / crop_unit_y;
1670	}
1671	sps->vui_parameters_present_flag = 1;
1672	sps->vui.aspect_ratio_info_present_flag = 0;
1673	sps->vui.overscan_info_present_flag = 0;
1674
1675	sps->vui.video_signal_type_present_flag = 1;
1676	sps->vui.video_format = 5; /* unspecified */
1677	sps->vui.video_full_range_flag = nal_h264_full_range(channel->quantization);
1678	sps->vui.colour_description_present_flag = 1;
1679	sps->vui.colour_primaries = nal_h264_color_primaries(channel->colorspace);
1680	sps->vui.transfer_characteristics =
1681		nal_h264_transfer_characteristics(channel->colorspace, channel->xfer_func);
1682	sps->vui.matrix_coefficients =
1683		nal_h264_matrix_coeffs(channel->colorspace, channel->ycbcr_enc);
1684
1685	sps->vui.chroma_loc_info_present_flag = 1;
1686	sps->vui.chroma_sample_loc_type_top_field = 0;
1687	sps->vui.chroma_sample_loc_type_bottom_field = 0;
1688
1689	sps->vui.timing_info_present_flag = 1;
1690	sps->vui.num_units_in_tick = channel->framerate.denominator;
1691	sps->vui.time_scale = 2 * channel->framerate.numerator;
1692
1693	sps->vui.fixed_frame_rate_flag = 1;
1694	sps->vui.nal_hrd_parameters_present_flag = 0;
1695	sps->vui.vcl_hrd_parameters_present_flag = 1;
1696	sps->vui.vcl_hrd_parameters.cpb_cnt_minus1 = 0;
1697	/* See Rec. ITU-T H.264 (04/2017) p. 410 E-53 */
1698	sps->vui.vcl_hrd_parameters.bit_rate_scale =
1699		ffs(channel->bitrate_peak) - 6;
1700	sps->vui.vcl_hrd_parameters.bit_rate_value_minus1[0] =
1701		channel->bitrate_peak / (1 << (6 + sps->vui.vcl_hrd_parameters.bit_rate_scale)) - 1;
1702	/* See Rec. ITU-T H.264 (04/2017) p. 410 E-54 */
1703	cpb_size = v4l2_ctrl_g_ctrl(channel->mpeg_video_cpb_size);
1704	cpb_size_scale = ffs(cpb_size) - 4;
1705	sps->vui.vcl_hrd_parameters.cpb_size_scale = cpb_size_scale;
1706	sps->vui.vcl_hrd_parameters.cpb_size_value_minus1[0] =
1707		(cpb_size * 1000) / (1 << (4 + cpb_size_scale)) - 1;
1708	sps->vui.vcl_hrd_parameters.cbr_flag[0] =
1709		!v4l2_ctrl_g_ctrl(channel->mpeg_video_frame_rc_enable);
1710	sps->vui.vcl_hrd_parameters.initial_cpb_removal_delay_length_minus1 = 31;
1711	sps->vui.vcl_hrd_parameters.cpb_removal_delay_length_minus1 = 31;
1712	sps->vui.vcl_hrd_parameters.dpb_output_delay_length_minus1 = 31;
1713	sps->vui.vcl_hrd_parameters.time_offset_length = 0;
1714	sps->vui.low_delay_hrd_flag = 0;
1715	sps->vui.pic_struct_present_flag = 1;
1716	sps->vui.bitstream_restriction_flag = 0;
1717
1718	size = nal_h264_write_sps(&dev->plat_dev->dev, dest, n, sps);
1719
1720	kfree(sps);
1721
1722	return size;
1723}
1724
1725static ssize_t allegro_h264_write_pps(struct allegro_channel *channel,
1726				      void *dest, size_t n)
1727{
1728	struct allegro_dev *dev = channel->dev;
1729	struct nal_h264_pps *pps;
1730	ssize_t size;
1731
1732	pps = kzalloc(sizeof(*pps), GFP_KERNEL);
1733	if (!pps)
1734		return -ENOMEM;
1735
1736	pps->pic_parameter_set_id = 0;
1737	pps->seq_parameter_set_id = 0;
1738	pps->entropy_coding_mode_flag = 0;
1739	pps->bottom_field_pic_order_in_frame_present_flag = 0;
1740	pps->num_slice_groups_minus1 = 0;
1741	pps->num_ref_idx_l0_default_active_minus1 = channel->num_ref_idx_l0 - 1;
1742	pps->num_ref_idx_l1_default_active_minus1 = channel->num_ref_idx_l1 - 1;
1743	pps->weighted_pred_flag = 0;
1744	pps->weighted_bipred_idc = 0;
1745	pps->pic_init_qp_minus26 = 0;
1746	pps->pic_init_qs_minus26 = 0;
1747	pps->chroma_qp_index_offset = 0;
1748	pps->deblocking_filter_control_present_flag = 1;
1749	pps->constrained_intra_pred_flag = 0;
1750	pps->redundant_pic_cnt_present_flag = 0;
1751	pps->transform_8x8_mode_flag = 0;
1752	pps->pic_scaling_matrix_present_flag = 0;
1753	pps->second_chroma_qp_index_offset = 0;
1754
1755	size = nal_h264_write_pps(&dev->plat_dev->dev, dest, n, pps);
1756
1757	kfree(pps);
1758
1759	return size;
1760}
1761
1762static void allegro_channel_eos_event(struct allegro_channel *channel)
1763{
1764	const struct v4l2_event eos_event = {
1765		.type = V4L2_EVENT_EOS
1766	};
1767
1768	v4l2_event_queue_fh(&channel->fh, &eos_event);
1769}
1770
1771static ssize_t allegro_hevc_write_vps(struct allegro_channel *channel,
1772				      void *dest, size_t n)
1773{
1774	struct allegro_dev *dev = channel->dev;
1775	struct nal_hevc_vps *vps;
1776	struct nal_hevc_profile_tier_level *ptl;
1777	ssize_t size;
1778	unsigned int num_ref_frames = channel->num_ref_idx_l0;
1779	s32 profile = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_profile);
1780	s32 level = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_level);
1781	s32 tier = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_tier);
1782
1783	vps = kzalloc(sizeof(*vps), GFP_KERNEL);
1784	if (!vps)
1785		return -ENOMEM;
1786
1787	vps->base_layer_internal_flag = 1;
1788	vps->base_layer_available_flag = 1;
1789	vps->temporal_id_nesting_flag = 1;
1790
1791	ptl = &vps->profile_tier_level;
1792	ptl->general_profile_idc = nal_hevc_profile(profile);
1793	ptl->general_profile_compatibility_flag[ptl->general_profile_idc] = 1;
1794	ptl->general_tier_flag = nal_hevc_tier(tier);
1795	ptl->general_progressive_source_flag = 1;
1796	ptl->general_frame_only_constraint_flag = 1;
1797	ptl->general_level_idc = nal_hevc_level(level);
1798
1799	vps->sub_layer_ordering_info_present_flag = 0;
1800	vps->max_dec_pic_buffering_minus1[0] = num_ref_frames;
1801	vps->max_num_reorder_pics[0] = num_ref_frames;
1802
1803	size = nal_hevc_write_vps(&dev->plat_dev->dev, dest, n, vps);
1804
1805	kfree(vps);
1806
1807	return size;
1808}
1809
1810static ssize_t allegro_hevc_write_sps(struct allegro_channel *channel,
1811				      void *dest, size_t n)
1812{
1813	struct allegro_dev *dev = channel->dev;
1814	struct nal_hevc_sps *sps;
1815	struct nal_hevc_profile_tier_level *ptl;
1816	struct nal_hevc_vui_parameters *vui;
1817	struct nal_hevc_hrd_parameters *hrd;
1818	ssize_t size;
1819	unsigned int cpb_size;
1820	unsigned int num_ref_frames = channel->num_ref_idx_l0;
1821	s32 profile = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_profile);
1822	s32 level = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_level);
1823	s32 tier = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_tier);
1824
1825	sps = kzalloc(sizeof(*sps), GFP_KERNEL);
1826	if (!sps)
1827		return -ENOMEM;
1828
1829	sps->temporal_id_nesting_flag = 1;
1830
1831	ptl = &sps->profile_tier_level;
1832	ptl->general_profile_idc = nal_hevc_profile(profile);
1833	ptl->general_profile_compatibility_flag[ptl->general_profile_idc] = 1;
1834	ptl->general_tier_flag = nal_hevc_tier(tier);
1835	ptl->general_progressive_source_flag = 1;
1836	ptl->general_frame_only_constraint_flag = 1;
1837	ptl->general_level_idc = nal_hevc_level(level);
1838
1839	sps->seq_parameter_set_id = 0;
1840	sps->chroma_format_idc = 1; /* Only 4:2:0 sampling supported */
1841	sps->pic_width_in_luma_samples = round_up(channel->width, 8);
1842	sps->pic_height_in_luma_samples = round_up(channel->height, 8);
1843	sps->conf_win_right_offset =
1844		sps->pic_width_in_luma_samples - channel->width;
1845	sps->conf_win_bottom_offset =
1846		sps->pic_height_in_luma_samples - channel->height;
1847	sps->conformance_window_flag =
1848		sps->conf_win_right_offset || sps->conf_win_bottom_offset;
1849
1850	sps->log2_max_pic_order_cnt_lsb_minus4 = LOG2_MAX_PIC_ORDER_CNT - 4;
1851
1852	sps->sub_layer_ordering_info_present_flag = 1;
1853	sps->max_dec_pic_buffering_minus1[0] = num_ref_frames;
1854	sps->max_num_reorder_pics[0] = num_ref_frames;
1855
1856	sps->log2_min_luma_coding_block_size_minus3 =
1857		channel->min_cu_size - 3;
1858	sps->log2_diff_max_min_luma_coding_block_size =
1859		channel->max_cu_size - channel->min_cu_size;
1860	sps->log2_min_luma_transform_block_size_minus2 =
1861		channel->min_tu_size - 2;
1862	sps->log2_diff_max_min_luma_transform_block_size =
1863		channel->max_tu_size - channel->min_tu_size;
1864	sps->max_transform_hierarchy_depth_intra =
1865		channel->max_transfo_depth_intra;
1866	sps->max_transform_hierarchy_depth_inter =
1867		channel->max_transfo_depth_inter;
1868
1869	sps->sps_temporal_mvp_enabled_flag = channel->temporal_mvp_enable;
1870	sps->strong_intra_smoothing_enabled_flag = channel->max_cu_size > 4;
1871
1872	sps->vui_parameters_present_flag = 1;
1873	vui = &sps->vui;
1874
1875	vui->video_signal_type_present_flag = 1;
1876	vui->video_format = 5; /* unspecified */
1877	vui->video_full_range_flag = nal_hevc_full_range(channel->quantization);
1878	vui->colour_description_present_flag = 1;
1879	vui->colour_primaries = nal_hevc_color_primaries(channel->colorspace);
1880	vui->transfer_characteristics = nal_hevc_transfer_characteristics(channel->colorspace,
1881									  channel->xfer_func);
1882	vui->matrix_coeffs = nal_hevc_matrix_coeffs(channel->colorspace, channel->ycbcr_enc);
1883
1884	vui->chroma_loc_info_present_flag = 1;
1885	vui->chroma_sample_loc_type_top_field = 0;
1886	vui->chroma_sample_loc_type_bottom_field = 0;
1887
1888	vui->vui_timing_info_present_flag = 1;
1889	vui->vui_num_units_in_tick = channel->framerate.denominator;
1890	vui->vui_time_scale = channel->framerate.numerator;
1891
1892	vui->bitstream_restriction_flag = 1;
1893	vui->motion_vectors_over_pic_boundaries_flag = 1;
1894	vui->restricted_ref_pic_lists_flag = 1;
1895	vui->log2_max_mv_length_horizontal = 15;
1896	vui->log2_max_mv_length_vertical = 15;
1897
1898	vui->vui_hrd_parameters_present_flag = 1;
1899	hrd = &vui->nal_hrd_parameters;
1900	hrd->vcl_hrd_parameters_present_flag = 1;
1901
1902	hrd->initial_cpb_removal_delay_length_minus1 = 31;
1903	hrd->au_cpb_removal_delay_length_minus1 = 30;
1904	hrd->dpb_output_delay_length_minus1 = 30;
1905
1906	hrd->bit_rate_scale = ffs(channel->bitrate_peak) - 6;
1907	hrd->vcl_hrd[0].bit_rate_value_minus1[0] =
1908		(channel->bitrate_peak >> (6 + hrd->bit_rate_scale)) - 1;
1909
1910	cpb_size = v4l2_ctrl_g_ctrl(channel->mpeg_video_cpb_size) * 1000;
1911	hrd->cpb_size_scale = ffs(cpb_size) - 4;
1912	hrd->vcl_hrd[0].cpb_size_value_minus1[0] = (cpb_size >> (4 + hrd->cpb_size_scale)) - 1;
1913
1914	hrd->vcl_hrd[0].cbr_flag[0] = !v4l2_ctrl_g_ctrl(channel->mpeg_video_frame_rc_enable);
1915
1916	size = nal_hevc_write_sps(&dev->plat_dev->dev, dest, n, sps);
1917
1918	kfree(sps);
1919
1920	return size;
1921}
1922
1923static ssize_t allegro_hevc_write_pps(struct allegro_channel *channel,
1924				      struct mcu_msg_encode_frame_response *msg,
1925				      void *dest, size_t n)
1926{
1927	struct allegro_dev *dev = channel->dev;
1928	struct nal_hevc_pps *pps;
1929	ssize_t size;
1930	int i;
1931
1932	pps = kzalloc(sizeof(*pps), GFP_KERNEL);
1933	if (!pps)
1934		return -ENOMEM;
1935
1936	pps->pps_pic_parameter_set_id = 0;
1937	pps->pps_seq_parameter_set_id = 0;
1938
1939	if (msg->num_column > 1 || msg->num_row > 1) {
1940		pps->tiles_enabled_flag = 1;
1941		pps->num_tile_columns_minus1 = msg->num_column - 1;
1942		pps->num_tile_rows_minus1 = msg->num_row - 1;
1943
1944		for (i = 0; i < msg->num_column; i++)
1945			pps->column_width_minus1[i] = msg->tile_width[i] - 1;
1946
1947		for (i = 0; i < msg->num_row; i++)
1948			pps->row_height_minus1[i] = msg->tile_height[i] - 1;
1949	}
1950
1951	pps->loop_filter_across_tiles_enabled_flag =
1952		channel->enable_loop_filter_across_tiles;
1953	pps->pps_loop_filter_across_slices_enabled_flag =
1954		channel->enable_loop_filter_across_slices;
1955	pps->deblocking_filter_control_present_flag = 1;
1956	pps->deblocking_filter_override_enabled_flag =
1957		channel->enable_deblocking_filter_override;
1958	pps->pps_beta_offset_div2 = BETA_OFFSET_DIV_2;
1959	pps->pps_tc_offset_div2 = TC_OFFSET_DIV_2;
1960
1961	pps->lists_modification_present_flag = channel->enable_reordering;
1962
1963	size = nal_hevc_write_pps(&dev->plat_dev->dev, dest, n, pps);
1964
1965	kfree(pps);
1966
1967	return size;
1968}
1969
1970static u64 allegro_put_buffer(struct allegro_channel *channel,
1971			      struct list_head *list,
1972			      struct vb2_v4l2_buffer *buffer)
1973{
1974	struct v4l2_m2m_buffer *b = container_of(buffer,
1975						 struct v4l2_m2m_buffer, vb);
1976	struct allegro_m2m_buffer *shadow = to_allegro_m2m_buffer(b);
1977
1978	mutex_lock(&channel->shadow_list_lock);
1979	list_add_tail(&shadow->head, list);
1980	mutex_unlock(&channel->shadow_list_lock);
1981
1982	return ptr_to_u64(buffer);
1983}
1984
1985static struct vb2_v4l2_buffer *
1986allegro_get_buffer(struct allegro_channel *channel,
1987		   struct list_head *list, u64 handle)
1988{
1989	struct allegro_m2m_buffer *shadow, *tmp;
1990	struct vb2_v4l2_buffer *buffer = NULL;
1991
1992	mutex_lock(&channel->shadow_list_lock);
1993	list_for_each_entry_safe(shadow, tmp, list, head) {
1994		if (handle == ptr_to_u64(&shadow->buf.vb)) {
1995			buffer = &shadow->buf.vb;
1996			list_del_init(&shadow->head);
1997			break;
1998		}
1999	}
2000	mutex_unlock(&channel->shadow_list_lock);
2001
2002	return buffer;
2003}
2004
2005static void allegro_channel_finish_frame(struct allegro_channel *channel,
2006		struct mcu_msg_encode_frame_response *msg)
2007{
2008	struct allegro_dev *dev = channel->dev;
2009	struct vb2_v4l2_buffer *src_buf;
2010	struct vb2_v4l2_buffer *dst_buf;
2011	struct {
2012		u32 offset;
2013		u32 size;
2014	} *partition;
2015	enum vb2_buffer_state state = VB2_BUF_STATE_ERROR;
2016	char *curr;
2017	ssize_t len;
2018	ssize_t free;
2019
2020	src_buf = allegro_get_buffer(channel, &channel->source_shadow_list,
2021				     msg->src_handle);
2022	if (!src_buf)
2023		v4l2_warn(&dev->v4l2_dev,
2024			  "channel %d: invalid source buffer\n",
2025			  channel->mcu_channel_id);
2026
2027	dst_buf = allegro_get_buffer(channel, &channel->stream_shadow_list,
2028				     msg->dst_handle);
2029	if (!dst_buf)
2030		v4l2_warn(&dev->v4l2_dev,
2031			  "channel %d: invalid stream buffer\n",
2032			  channel->mcu_channel_id);
2033
2034	if (!src_buf || !dst_buf)
2035		goto err;
2036
2037	if (v4l2_m2m_is_last_draining_src_buf(channel->fh.m2m_ctx, src_buf)) {
2038		dst_buf->flags |= V4L2_BUF_FLAG_LAST;
2039		allegro_channel_eos_event(channel);
2040		v4l2_m2m_mark_stopped(channel->fh.m2m_ctx);
2041	}
2042
2043	dst_buf->sequence = channel->csequence++;
2044
2045	if (msg->error_code & AL_ERROR) {
2046		v4l2_err(&dev->v4l2_dev,
2047			 "channel %d: failed to encode frame: %s (%x)\n",
2048			 channel->mcu_channel_id,
2049			 allegro_err_to_string(msg->error_code),
2050			 msg->error_code);
2051		goto err;
2052	}
2053
2054	if (msg->partition_table_size != 1) {
2055		v4l2_warn(&dev->v4l2_dev,
2056			  "channel %d: only handling first partition table entry (%d entries)\n",
2057			  channel->mcu_channel_id, msg->partition_table_size);
2058	}
2059
2060	if (msg->partition_table_offset +
2061	    msg->partition_table_size * sizeof(*partition) >
2062	    vb2_plane_size(&dst_buf->vb2_buf, 0)) {
2063		v4l2_err(&dev->v4l2_dev,
2064			 "channel %d: partition table outside of dst_buf\n",
2065			 channel->mcu_channel_id);
2066		goto err;
2067	}
2068
2069	partition =
2070	    vb2_plane_vaddr(&dst_buf->vb2_buf, 0) + msg->partition_table_offset;
2071	if (partition->offset + partition->size >
2072	    vb2_plane_size(&dst_buf->vb2_buf, 0)) {
2073		v4l2_err(&dev->v4l2_dev,
2074			 "channel %d: encoded frame is outside of dst_buf (offset 0x%x, size 0x%x)\n",
2075			 channel->mcu_channel_id, partition->offset,
2076			 partition->size);
2077		goto err;
2078	}
2079
2080	v4l2_dbg(2, debug, &dev->v4l2_dev,
2081		 "channel %d: encoded frame of size %d is at offset 0x%x\n",
2082		 channel->mcu_channel_id, partition->size, partition->offset);
2083
2084	/*
2085	 * The payload must include the data before the partition offset,
2086	 * because we will put the sps and pps data there.
2087	 */
2088	vb2_set_plane_payload(&dst_buf->vb2_buf, 0,
2089			      partition->offset + partition->size);
2090
2091	curr = vb2_plane_vaddr(&dst_buf->vb2_buf, 0);
2092	free = partition->offset;
2093
2094	if (channel->codec == V4L2_PIX_FMT_HEVC && msg->is_idr) {
2095		len = allegro_hevc_write_vps(channel, curr, free);
2096		if (len < 0) {
2097			v4l2_err(&dev->v4l2_dev,
2098				 "not enough space for video parameter set: %zd left\n",
2099				 free);
2100			goto err;
2101		}
2102		curr += len;
2103		free -= len;
2104		v4l2_dbg(1, debug, &dev->v4l2_dev,
2105			 "channel %d: wrote %zd byte VPS nal unit\n",
2106			 channel->mcu_channel_id, len);
2107	}
2108
2109	if (msg->is_idr) {
2110		if (channel->codec == V4L2_PIX_FMT_H264)
2111			len = allegro_h264_write_sps(channel, curr, free);
2112		else
2113			len = allegro_hevc_write_sps(channel, curr, free);
2114		if (len < 0) {
2115			v4l2_err(&dev->v4l2_dev,
2116				 "not enough space for sequence parameter set: %zd left\n",
2117				 free);
2118			goto err;
2119		}
2120		curr += len;
2121		free -= len;
2122		v4l2_dbg(1, debug, &dev->v4l2_dev,
2123			 "channel %d: wrote %zd byte SPS nal unit\n",
2124			 channel->mcu_channel_id, len);
2125	}
2126
2127	if (msg->slice_type == AL_ENC_SLICE_TYPE_I) {
2128		if (channel->codec == V4L2_PIX_FMT_H264)
2129			len = allegro_h264_write_pps(channel, curr, free);
2130		else
2131			len = allegro_hevc_write_pps(channel, msg, curr, free);
2132		if (len < 0) {
2133			v4l2_err(&dev->v4l2_dev,
2134				 "not enough space for picture parameter set: %zd left\n",
2135				 free);
2136			goto err;
2137		}
2138		curr += len;
2139		free -= len;
2140		v4l2_dbg(1, debug, &dev->v4l2_dev,
2141			 "channel %d: wrote %zd byte PPS nal unit\n",
2142			 channel->mcu_channel_id, len);
2143	}
2144
2145	if (msg->slice_type != AL_ENC_SLICE_TYPE_I && !msg->is_idr) {
2146		dst_buf->vb2_buf.planes[0].data_offset = free;
2147		free = 0;
2148	} else {
2149		if (channel->codec == V4L2_PIX_FMT_H264)
2150			len = nal_h264_write_filler(&dev->plat_dev->dev, curr, free);
2151		else
2152			len = nal_hevc_write_filler(&dev->plat_dev->dev, curr, free);
2153		if (len < 0) {
2154			v4l2_err(&dev->v4l2_dev,
2155				 "failed to write %zd filler data\n", free);
2156			goto err;
2157		}
2158		curr += len;
2159		free -= len;
2160		v4l2_dbg(2, debug, &dev->v4l2_dev,
2161			 "channel %d: wrote %zd bytes filler nal unit\n",
2162			 channel->mcu_channel_id, len);
2163	}
2164
2165	if (free != 0) {
2166		v4l2_err(&dev->v4l2_dev,
2167			 "non-VCL NAL units do not fill space until VCL NAL unit: %zd bytes left\n",
2168			 free);
2169		goto err;
2170	}
2171
2172	state = VB2_BUF_STATE_DONE;
2173
2174	v4l2_m2m_buf_copy_metadata(src_buf, dst_buf);
2175	if (msg->is_idr)
2176		dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
2177	else
2178		dst_buf->flags |= V4L2_BUF_FLAG_PFRAME;
2179
2180	v4l2_dbg(1, debug, &dev->v4l2_dev,
2181		 "channel %d: encoded frame #%03d (%s%s, QP %d, %d bytes)\n",
2182		 channel->mcu_channel_id,
2183		 dst_buf->sequence,
2184		 msg->is_idr ? "IDR, " : "",
2185		 msg->slice_type == AL_ENC_SLICE_TYPE_I ? "I slice" :
2186		 msg->slice_type == AL_ENC_SLICE_TYPE_P ? "P slice" : "unknown",
2187		 msg->qp, partition->size);
2188
2189err:
2190	if (src_buf)
2191		v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
2192
2193	if (dst_buf)
2194		v4l2_m2m_buf_done(dst_buf, state);
2195}
2196
2197static int allegro_handle_init(struct allegro_dev *dev,
2198			       struct mcu_msg_init_response *msg)
2199{
2200	complete(&dev->init_complete);
2201
2202	return 0;
2203}
2204
2205static int
2206allegro_handle_create_channel(struct allegro_dev *dev,
2207			      struct mcu_msg_create_channel_response *msg)
2208{
2209	struct allegro_channel *channel;
2210	int err = 0;
2211	struct create_channel_param param;
2212
2213	channel = allegro_ref_get_channel_by_user_id(dev, msg->user_id);
2214	if (IS_ERR(channel)) {
2215		v4l2_warn(&dev->v4l2_dev,
2216			  "received %s for unknown user %d\n",
2217			  msg_type_name(msg->header.type),
2218			  msg->user_id);
2219		return -EINVAL;
2220	}
2221
2222	if (msg->error_code) {
2223		v4l2_err(&dev->v4l2_dev,
2224			 "user %d: mcu failed to create channel: %s (%x)\n",
2225			 channel->user_id,
2226			 allegro_err_to_string(msg->error_code),
2227			 msg->error_code);
2228		err = -EIO;
2229		goto out;
2230	}
2231
2232	channel->mcu_channel_id = msg->channel_id;
2233	v4l2_dbg(1, debug, &dev->v4l2_dev,
2234		 "user %d: channel has channel id %d\n",
2235		 channel->user_id, channel->mcu_channel_id);
2236
2237	err = allegro_decode_config_blob(&param, msg, channel->config_blob.vaddr);
2238	allegro_free_buffer(channel->dev, &channel->config_blob);
2239	if (err)
2240		goto out;
2241
2242	channel->num_ref_idx_l0 = param.num_ref_idx_l0;
2243	channel->num_ref_idx_l1 = param.num_ref_idx_l1;
2244
2245	v4l2_dbg(1, debug, &dev->v4l2_dev,
2246		 "channel %d: intermediate buffers: %d x %d bytes\n",
2247		 channel->mcu_channel_id,
2248		 msg->int_buffers_count, msg->int_buffers_size);
2249	err = allocate_intermediate_buffers(channel, msg->int_buffers_count,
2250					    msg->int_buffers_size);
2251	if (err) {
2252		v4l2_err(&dev->v4l2_dev,
2253			 "channel %d: failed to allocate intermediate buffers\n",
2254			 channel->mcu_channel_id);
2255		goto out;
2256	}
2257	err = allegro_mcu_push_buffer_intermediate(channel);
2258	if (err)
2259		goto out;
2260
2261	v4l2_dbg(1, debug, &dev->v4l2_dev,
2262		 "channel %d: reference buffers: %d x %d bytes\n",
2263		 channel->mcu_channel_id,
2264		 msg->rec_buffers_count, msg->rec_buffers_size);
2265	err = allocate_reference_buffers(channel, msg->rec_buffers_count,
2266					 msg->rec_buffers_size);
2267	if (err) {
2268		v4l2_err(&dev->v4l2_dev,
2269			 "channel %d: failed to allocate reference buffers\n",
2270			 channel->mcu_channel_id);
2271		goto out;
2272	}
2273	err = allegro_mcu_push_buffer_reference(channel);
2274	if (err)
2275		goto out;
2276
2277out:
2278	channel->error = err;
2279	complete(&channel->completion);
2280	allegro_ref_put_channel(channel);
2281
2282	/* Handled successfully, error is passed via channel->error */
2283	return 0;
2284}
2285
2286static int
2287allegro_handle_destroy_channel(struct allegro_dev *dev,
2288			       struct mcu_msg_destroy_channel_response *msg)
2289{
2290	struct allegro_channel *channel;
2291
2292	channel = allegro_ref_get_channel_by_channel_id(dev, msg->channel_id);
2293	if (IS_ERR(channel)) {
2294		v4l2_err(&dev->v4l2_dev,
2295			 "received %s for unknown channel %d\n",
2296			 msg_type_name(msg->header.type),
2297			 msg->channel_id);
2298		return -EINVAL;
2299	}
2300
2301	v4l2_dbg(2, debug, &dev->v4l2_dev,
2302		 "user %d: vcu destroyed channel %d\n",
2303		 channel->user_id, channel->mcu_channel_id);
2304	complete(&channel->completion);
2305	allegro_ref_put_channel(channel);
2306
2307	return 0;
2308}
2309
2310static int
2311allegro_handle_encode_frame(struct allegro_dev *dev,
2312			    struct mcu_msg_encode_frame_response *msg)
2313{
2314	struct allegro_channel *channel;
2315
2316	channel = allegro_ref_get_channel_by_channel_id(dev, msg->channel_id);
2317	if (IS_ERR(channel)) {
2318		v4l2_err(&dev->v4l2_dev,
2319			 "received %s for unknown channel %d\n",
2320			 msg_type_name(msg->header.type),
2321			 msg->channel_id);
2322		return -EINVAL;
2323	}
2324
2325	allegro_channel_finish_frame(channel, msg);
2326	allegro_ref_put_channel(channel);
2327
2328	return 0;
2329}
2330
2331static void allegro_handle_message(struct allegro_dev *dev,
2332				   union mcu_msg_response *msg)
2333{
2334	switch (msg->header.type) {
2335	case MCU_MSG_TYPE_INIT:
2336		allegro_handle_init(dev, &msg->init);
2337		break;
2338	case MCU_MSG_TYPE_CREATE_CHANNEL:
2339		allegro_handle_create_channel(dev, &msg->create_channel);
2340		break;
2341	case MCU_MSG_TYPE_DESTROY_CHANNEL:
2342		allegro_handle_destroy_channel(dev, &msg->destroy_channel);
2343		break;
2344	case MCU_MSG_TYPE_ENCODE_FRAME:
2345		allegro_handle_encode_frame(dev, &msg->encode_frame);
2346		break;
2347	default:
2348		v4l2_warn(&dev->v4l2_dev,
2349			  "%s: unknown message %s\n",
2350			  __func__, msg_type_name(msg->header.type));
2351		break;
2352	}
2353}
2354
2355static irqreturn_t allegro_hardirq(int irq, void *data)
2356{
2357	struct allegro_dev *dev = data;
2358	unsigned int status;
2359
2360	regmap_read(dev->regmap, AL5_ITC_CPU_IRQ_STA, &status);
2361	if (!(status & AL5_ITC_CPU_IRQ_STA_TRIGGERED))
2362		return IRQ_NONE;
2363
2364	regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_CLR, status);
2365
2366	return IRQ_WAKE_THREAD;
2367}
2368
2369static irqreturn_t allegro_irq_thread(int irq, void *data)
2370{
2371	struct allegro_dev *dev = data;
2372
2373	/*
2374	 * The firmware is initialized after the mailbox is setup. We further
2375	 * check the AL5_ITC_CPU_IRQ_STA register, if the firmware actually
2376	 * triggered the interrupt. Although this should not happen, make sure
2377	 * that we ignore interrupts, if the mailbox is not initialized.
2378	 */
2379	if (!dev->mbox_status)
2380		return IRQ_NONE;
2381
2382	while (allegro_mbox_get_available(dev->mbox_status) > 0) {
2383		if (allegro_mbox_notify(dev->mbox_status))
2384			break;
2385	}
2386
2387	return IRQ_HANDLED;
2388}
2389
2390static void allegro_copy_firmware(struct allegro_dev *dev,
2391				  const u8 * const buf, size_t size)
2392{
2393	int err = 0;
2394
2395	v4l2_dbg(1, debug, &dev->v4l2_dev,
2396		 "copy mcu firmware (%zu B) to SRAM\n", size);
2397	err = regmap_bulk_write(dev->sram, 0x0, buf, size / 4);
2398	if (err)
2399		v4l2_err(&dev->v4l2_dev,
2400			 "failed to copy firmware: %d\n", err);
2401}
2402
2403static void allegro_copy_fw_codec(struct allegro_dev *dev,
2404				  const u8 * const buf, size_t size)
2405{
2406	int err;
2407	dma_addr_t icache_offset, dcache_offset;
2408
2409	/*
2410	 * The downstream allocates 600 KB for the codec firmware to have some
2411	 * extra space for "possible extensions." My tests were fine with
2412	 * allocating just enough memory for the actual firmware, but I am not
2413	 * sure that the firmware really does not use the remaining space.
2414	 */
2415	err = allegro_alloc_buffer(dev, &dev->firmware, size);
2416	if (err) {
2417		v4l2_err(&dev->v4l2_dev,
2418			 "failed to allocate %zu bytes for firmware\n", size);
2419		return;
2420	}
2421
2422	v4l2_dbg(1, debug, &dev->v4l2_dev,
2423		 "copy codec firmware (%zd B) to phys %pad\n",
2424		 size, &dev->firmware.paddr);
2425	memcpy(dev->firmware.vaddr, buf, size);
2426
2427	regmap_write(dev->regmap, AXI_ADDR_OFFSET_IP,
2428		     upper_32_bits(dev->firmware.paddr));
2429
2430	icache_offset = dev->firmware.paddr - MCU_CACHE_OFFSET;
2431	v4l2_dbg(2, debug, &dev->v4l2_dev,
2432		 "icache_offset: msb = 0x%x, lsb = 0x%x\n",
2433		 upper_32_bits(icache_offset), lower_32_bits(icache_offset));
2434	regmap_write(dev->regmap, AL5_ICACHE_ADDR_OFFSET_MSB,
2435		     upper_32_bits(icache_offset));
2436	regmap_write(dev->regmap, AL5_ICACHE_ADDR_OFFSET_LSB,
2437		     lower_32_bits(icache_offset));
2438
2439	dcache_offset =
2440	    (dev->firmware.paddr & 0xffffffff00000000ULL) - MCU_CACHE_OFFSET;
2441	v4l2_dbg(2, debug, &dev->v4l2_dev,
2442		 "dcache_offset: msb = 0x%x, lsb = 0x%x\n",
2443		 upper_32_bits(dcache_offset), lower_32_bits(dcache_offset));
2444	regmap_write(dev->regmap, AL5_DCACHE_ADDR_OFFSET_MSB,
2445		     upper_32_bits(dcache_offset));
2446	regmap_write(dev->regmap, AL5_DCACHE_ADDR_OFFSET_LSB,
2447		     lower_32_bits(dcache_offset));
2448}
2449
2450static void allegro_free_fw_codec(struct allegro_dev *dev)
2451{
2452	allegro_free_buffer(dev, &dev->firmware);
2453}
2454
2455/*
2456 * Control functions for the MCU
2457 */
2458
2459static int allegro_mcu_enable_interrupts(struct allegro_dev *dev)
2460{
2461	return regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_MSK, BIT(0));
2462}
2463
2464static int allegro_mcu_disable_interrupts(struct allegro_dev *dev)
2465{
2466	return regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_MSK, 0);
2467}
2468
2469static int allegro_mcu_wait_for_sleep(struct allegro_dev *dev)
2470{
2471	unsigned long timeout;
2472	unsigned int status;
2473
2474	timeout = jiffies + msecs_to_jiffies(100);
2475	while (regmap_read(dev->regmap, AL5_MCU_STA, &status) == 0 &&
2476	       status != AL5_MCU_STA_SLEEP) {
2477		if (time_after(jiffies, timeout))
2478			return -ETIMEDOUT;
2479		cpu_relax();
2480	}
2481
2482	return 0;
2483}
2484
2485static int allegro_mcu_start(struct allegro_dev *dev)
2486{
2487	unsigned long timeout;
2488	unsigned int status;
2489	int err;
2490
2491	err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, BIT(0));
2492	if (err)
2493		return err;
2494
2495	timeout = jiffies + msecs_to_jiffies(100);
2496	while (regmap_read(dev->regmap, AL5_MCU_STA, &status) == 0 &&
2497	       status == AL5_MCU_STA_SLEEP) {
2498		if (time_after(jiffies, timeout))
2499			return -ETIMEDOUT;
2500		cpu_relax();
2501	}
2502
2503	err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, 0);
2504	if (err)
2505		return err;
2506
2507	return 0;
2508}
2509
2510static int allegro_mcu_reset(struct allegro_dev *dev)
2511{
2512	int err;
2513
2514	/*
2515	 * Ensure that the AL5_MCU_WAKEUP bit is set to 0 otherwise the mcu
2516	 * does not go to sleep after the reset.
2517	 */
2518	err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, 0);
2519	if (err)
2520		return err;
2521
2522	err = regmap_write(dev->regmap,
2523			   AL5_MCU_RESET_MODE, AL5_MCU_RESET_MODE_SLEEP);
2524	if (err < 0)
2525		return err;
2526
2527	err = regmap_write(dev->regmap, AL5_MCU_RESET, AL5_MCU_RESET_SOFT);
2528	if (err < 0)
2529		return err;
2530
2531	return allegro_mcu_wait_for_sleep(dev);
2532}
2533
2534static void allegro_mcu_interrupt(struct allegro_dev *dev)
2535{
2536	regmap_write(dev->regmap, AL5_MCU_INTERRUPT, BIT(0));
2537}
2538
2539static void allegro_destroy_channel(struct allegro_channel *channel)
2540{
2541	struct allegro_dev *dev = channel->dev;
2542	unsigned long time_left;
2543
2544	if (channel_exists(channel)) {
2545		reinit_completion(&channel->completion);
2546		allegro_mcu_send_destroy_channel(dev, channel);
2547		time_left = wait_for_completion_timeout(&channel->completion,
2548							msecs_to_jiffies(5000));
2549		if (time_left == 0)
2550			v4l2_warn(&dev->v4l2_dev,
2551				  "channel %d: timeout while destroying\n",
2552				  channel->mcu_channel_id);
2553
2554		channel->mcu_channel_id = -1;
2555	}
2556
2557	destroy_intermediate_buffers(channel);
2558	destroy_reference_buffers(channel);
2559
2560	v4l2_ctrl_grab(channel->mpeg_video_h264_profile, false);
2561	v4l2_ctrl_grab(channel->mpeg_video_h264_level, false);
2562	v4l2_ctrl_grab(channel->mpeg_video_h264_i_frame_qp, false);
2563	v4l2_ctrl_grab(channel->mpeg_video_h264_max_qp, false);
2564	v4l2_ctrl_grab(channel->mpeg_video_h264_min_qp, false);
2565	v4l2_ctrl_grab(channel->mpeg_video_h264_p_frame_qp, false);
2566	v4l2_ctrl_grab(channel->mpeg_video_h264_b_frame_qp, false);
2567
2568	v4l2_ctrl_grab(channel->mpeg_video_hevc_profile, false);
2569	v4l2_ctrl_grab(channel->mpeg_video_hevc_level, false);
2570	v4l2_ctrl_grab(channel->mpeg_video_hevc_tier, false);
2571	v4l2_ctrl_grab(channel->mpeg_video_hevc_i_frame_qp, false);
2572	v4l2_ctrl_grab(channel->mpeg_video_hevc_max_qp, false);
2573	v4l2_ctrl_grab(channel->mpeg_video_hevc_min_qp, false);
2574	v4l2_ctrl_grab(channel->mpeg_video_hevc_p_frame_qp, false);
2575	v4l2_ctrl_grab(channel->mpeg_video_hevc_b_frame_qp, false);
2576
2577	v4l2_ctrl_grab(channel->mpeg_video_frame_rc_enable, false);
2578	v4l2_ctrl_grab(channel->mpeg_video_bitrate_mode, false);
2579	v4l2_ctrl_grab(channel->mpeg_video_bitrate, false);
2580	v4l2_ctrl_grab(channel->mpeg_video_bitrate_peak, false);
2581	v4l2_ctrl_grab(channel->mpeg_video_cpb_size, false);
2582	v4l2_ctrl_grab(channel->mpeg_video_gop_size, false);
2583
2584	v4l2_ctrl_grab(channel->encoder_buffer, false);
2585
2586	if (channel->user_id != -1) {
2587		clear_bit(channel->user_id, &dev->channel_user_ids);
2588		channel->user_id = -1;
2589	}
2590}
2591
2592/*
2593 * Create the MCU channel
2594 *
2595 * After the channel has been created, the picture size, format, colorspace
2596 * and framerate are fixed. Also the codec, profile, bitrate, etc. cannot be
2597 * changed anymore.
2598 *
2599 * The channel can be created only once. The MCU will accept source buffers
2600 * and stream buffers only after a channel has been created.
2601 */
2602static int allegro_create_channel(struct allegro_channel *channel)
2603{
2604	struct allegro_dev *dev = channel->dev;
2605	unsigned long time_left;
2606
2607	if (channel_exists(channel)) {
2608		v4l2_warn(&dev->v4l2_dev,
2609			  "channel already exists\n");
2610		return 0;
2611	}
2612
2613	channel->user_id = allegro_next_user_id(dev);
2614	if (channel->user_id < 0) {
2615		v4l2_err(&dev->v4l2_dev,
2616			 "no free channels available\n");
2617		return -EBUSY;
2618	}
2619	set_bit(channel->user_id, &dev->channel_user_ids);
2620
2621	v4l2_dbg(1, debug, &dev->v4l2_dev,
2622		 "user %d: creating channel (%4.4s, %dx%d@%d)\n",
2623		 channel->user_id,
2624		 (char *)&channel->codec, channel->width, channel->height,
2625		 DIV_ROUND_UP(channel->framerate.numerator,
2626			      channel->framerate.denominator));
2627
2628	v4l2_ctrl_grab(channel->mpeg_video_h264_profile, true);
2629	v4l2_ctrl_grab(channel->mpeg_video_h264_level, true);
2630	v4l2_ctrl_grab(channel->mpeg_video_h264_i_frame_qp, true);
2631	v4l2_ctrl_grab(channel->mpeg_video_h264_max_qp, true);
2632	v4l2_ctrl_grab(channel->mpeg_video_h264_min_qp, true);
2633	v4l2_ctrl_grab(channel->mpeg_video_h264_p_frame_qp, true);
2634	v4l2_ctrl_grab(channel->mpeg_video_h264_b_frame_qp, true);
2635
2636	v4l2_ctrl_grab(channel->mpeg_video_hevc_profile, true);
2637	v4l2_ctrl_grab(channel->mpeg_video_hevc_level, true);
2638	v4l2_ctrl_grab(channel->mpeg_video_hevc_tier, true);
2639	v4l2_ctrl_grab(channel->mpeg_video_hevc_i_frame_qp, true);
2640	v4l2_ctrl_grab(channel->mpeg_video_hevc_max_qp, true);
2641	v4l2_ctrl_grab(channel->mpeg_video_hevc_min_qp, true);
2642	v4l2_ctrl_grab(channel->mpeg_video_hevc_p_frame_qp, true);
2643	v4l2_ctrl_grab(channel->mpeg_video_hevc_b_frame_qp, true);
2644
2645	v4l2_ctrl_grab(channel->mpeg_video_frame_rc_enable, true);
2646	v4l2_ctrl_grab(channel->mpeg_video_bitrate_mode, true);
2647	v4l2_ctrl_grab(channel->mpeg_video_bitrate, true);
2648	v4l2_ctrl_grab(channel->mpeg_video_bitrate_peak, true);
2649	v4l2_ctrl_grab(channel->mpeg_video_cpb_size, true);
2650	v4l2_ctrl_grab(channel->mpeg_video_gop_size, true);
2651
2652	v4l2_ctrl_grab(channel->encoder_buffer, true);
2653
2654	reinit_completion(&channel->completion);
2655	allegro_mcu_send_create_channel(dev, channel);
2656	time_left = wait_for_completion_timeout(&channel->completion,
2657						msecs_to_jiffies(5000));
2658	if (time_left == 0) {
2659		v4l2_warn(&dev->v4l2_dev,
2660			  "user %d: timeout while creating channel\n",
2661			  channel->user_id);
2662
2663		channel->error = -ETIMEDOUT;
2664	}
2665
2666	if (channel->error)
2667		goto err;
2668
2669	v4l2_dbg(1, debug, &dev->v4l2_dev,
2670		 "channel %d: accepting buffers\n",
2671		 channel->mcu_channel_id);
2672
2673	return 0;
2674
2675err:
2676	allegro_destroy_channel(channel);
2677
2678	return channel->error;
2679}
2680
2681/**
2682 * allegro_channel_adjust() - Adjust channel parameters to current format
2683 * @channel: the channel to adjust
2684 *
2685 * Various parameters of a channel and their limits depend on the currently
2686 * set format. Adjust the parameters after a format change in one go.
2687 */
2688static void allegro_channel_adjust(struct allegro_channel *channel)
2689{
2690	struct allegro_dev *dev = channel->dev;
2691	u32 codec = channel->codec;
2692	struct v4l2_ctrl *ctrl;
2693	s64 min;
2694	s64 max;
2695
2696	channel->sizeimage_encoded =
2697		estimate_stream_size(channel->width, channel->height);
2698
2699	if (codec == V4L2_PIX_FMT_H264) {
2700		ctrl = channel->mpeg_video_h264_level;
2701		min = select_minimum_h264_level(channel->width, channel->height);
2702	} else {
2703		ctrl = channel->mpeg_video_hevc_level;
2704		min = select_minimum_hevc_level(channel->width, channel->height);
2705	}
2706	if (ctrl->minimum > min)
2707		v4l2_dbg(1, debug, &dev->v4l2_dev,
2708			 "%s.minimum: %lld -> %lld\n",
2709			 v4l2_ctrl_get_name(ctrl->id), ctrl->minimum, min);
2710	v4l2_ctrl_lock(ctrl);
2711	__v4l2_ctrl_modify_range(ctrl, min, ctrl->maximum,
2712				 ctrl->step, ctrl->default_value);
2713	v4l2_ctrl_unlock(ctrl);
2714
2715	ctrl = channel->mpeg_video_bitrate;
2716	if (codec == V4L2_PIX_FMT_H264)
2717		max = h264_maximum_bitrate(v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_level));
2718	else
2719		max = hevc_maximum_bitrate(v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_level));
2720	if (ctrl->maximum < max)
2721		v4l2_dbg(1, debug, &dev->v4l2_dev,
2722			 "%s: maximum: %lld -> %lld\n",
2723			 v4l2_ctrl_get_name(ctrl->id), ctrl->maximum, max);
2724	v4l2_ctrl_lock(ctrl);
2725	__v4l2_ctrl_modify_range(ctrl, ctrl->minimum, max,
2726				 ctrl->step, ctrl->default_value);
2727	v4l2_ctrl_unlock(ctrl);
2728
2729	ctrl = channel->mpeg_video_bitrate_peak;
2730	v4l2_ctrl_lock(ctrl);
2731	__v4l2_ctrl_modify_range(ctrl, ctrl->minimum, max,
2732				 ctrl->step, ctrl->default_value);
2733	v4l2_ctrl_unlock(ctrl);
2734
2735	v4l2_ctrl_activate(channel->mpeg_video_h264_profile,
2736			   codec == V4L2_PIX_FMT_H264);
2737	v4l2_ctrl_activate(channel->mpeg_video_h264_level,
2738			   codec == V4L2_PIX_FMT_H264);
2739	v4l2_ctrl_activate(channel->mpeg_video_h264_i_frame_qp,
2740			   codec == V4L2_PIX_FMT_H264);
2741	v4l2_ctrl_activate(channel->mpeg_video_h264_max_qp,
2742			   codec == V4L2_PIX_FMT_H264);
2743	v4l2_ctrl_activate(channel->mpeg_video_h264_min_qp,
2744			   codec == V4L2_PIX_FMT_H264);
2745	v4l2_ctrl_activate(channel->mpeg_video_h264_p_frame_qp,
2746			   codec == V4L2_PIX_FMT_H264);
2747	v4l2_ctrl_activate(channel->mpeg_video_h264_b_frame_qp,
2748			   codec == V4L2_PIX_FMT_H264);
2749
2750	v4l2_ctrl_activate(channel->mpeg_video_hevc_profile,
2751			   codec == V4L2_PIX_FMT_HEVC);
2752	v4l2_ctrl_activate(channel->mpeg_video_hevc_level,
2753			   codec == V4L2_PIX_FMT_HEVC);
2754	v4l2_ctrl_activate(channel->mpeg_video_hevc_tier,
2755			   codec == V4L2_PIX_FMT_HEVC);
2756	v4l2_ctrl_activate(channel->mpeg_video_hevc_i_frame_qp,
2757			   codec == V4L2_PIX_FMT_HEVC);
2758	v4l2_ctrl_activate(channel->mpeg_video_hevc_max_qp,
2759			   codec == V4L2_PIX_FMT_HEVC);
2760	v4l2_ctrl_activate(channel->mpeg_video_hevc_min_qp,
2761			   codec == V4L2_PIX_FMT_HEVC);
2762	v4l2_ctrl_activate(channel->mpeg_video_hevc_p_frame_qp,
2763			   codec == V4L2_PIX_FMT_HEVC);
2764	v4l2_ctrl_activate(channel->mpeg_video_hevc_b_frame_qp,
2765			   codec == V4L2_PIX_FMT_HEVC);
2766
2767	if (codec == V4L2_PIX_FMT_H264)
2768		channel->log2_max_frame_num = LOG2_MAX_FRAME_NUM;
2769	channel->temporal_mvp_enable = true;
2770	channel->dbf_ovr_en = (codec == V4L2_PIX_FMT_H264);
2771	channel->enable_deblocking_filter_override = (codec == V4L2_PIX_FMT_HEVC);
2772	channel->enable_reordering = (codec == V4L2_PIX_FMT_HEVC);
2773	channel->enable_loop_filter_across_tiles = true;
2774	channel->enable_loop_filter_across_slices = true;
2775
2776	if (codec == V4L2_PIX_FMT_H264) {
2777		channel->b_hrz_me_range = 8;
2778		channel->b_vrt_me_range = 8;
2779		channel->p_hrz_me_range = 16;
2780		channel->p_vrt_me_range = 16;
2781		channel->max_cu_size = ilog2(16);
2782		channel->min_cu_size = ilog2(8);
2783		channel->max_tu_size = ilog2(4);
2784		channel->min_tu_size = ilog2(4);
2785	} else {
2786		channel->b_hrz_me_range = 16;
2787		channel->b_vrt_me_range = 16;
2788		channel->p_hrz_me_range = 32;
2789		channel->p_vrt_me_range = 32;
2790		channel->max_cu_size = ilog2(32);
2791		channel->min_cu_size = ilog2(8);
2792		channel->max_tu_size = ilog2(32);
2793		channel->min_tu_size = ilog2(4);
2794	}
2795	channel->max_transfo_depth_intra = 1;
2796	channel->max_transfo_depth_inter = 1;
2797}
2798
2799static void allegro_set_default_params(struct allegro_channel *channel)
2800{
2801	channel->width = ALLEGRO_WIDTH_DEFAULT;
2802	channel->height = ALLEGRO_HEIGHT_DEFAULT;
2803	channel->stride = round_up(channel->width, 32);
2804	channel->framerate = ALLEGRO_FRAMERATE_DEFAULT;
2805
2806	channel->colorspace = V4L2_COLORSPACE_REC709;
2807	channel->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
2808	channel->quantization = V4L2_QUANTIZATION_DEFAULT;
2809	channel->xfer_func = V4L2_XFER_FUNC_DEFAULT;
2810
2811	channel->pixelformat = V4L2_PIX_FMT_NV12;
2812	channel->sizeimage_raw = channel->stride * channel->height * 3 / 2;
2813
2814	channel->codec = V4L2_PIX_FMT_H264;
2815}
2816
2817static int allegro_queue_setup(struct vb2_queue *vq,
2818			       unsigned int *nbuffers, unsigned int *nplanes,
2819			       unsigned int sizes[],
2820			       struct device *alloc_devs[])
2821{
2822	struct allegro_channel *channel = vb2_get_drv_priv(vq);
2823	struct allegro_dev *dev = channel->dev;
2824
2825	v4l2_dbg(2, debug, &dev->v4l2_dev,
2826		 "%s: queue setup[%s]: nplanes = %d\n",
2827		 V4L2_TYPE_IS_OUTPUT(vq->type) ? "output" : "capture",
2828		 *nplanes == 0 ? "REQBUFS" : "CREATE_BUFS", *nplanes);
2829
2830	if (*nplanes != 0) {
2831		if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
2832			if (sizes[0] < channel->sizeimage_raw)
2833				return -EINVAL;
2834		} else {
2835			if (sizes[0] < channel->sizeimage_encoded)
2836				return -EINVAL;
2837		}
2838	} else {
2839		*nplanes = 1;
2840		if (V4L2_TYPE_IS_OUTPUT(vq->type))
2841			sizes[0] = channel->sizeimage_raw;
2842		else
2843			sizes[0] = channel->sizeimage_encoded;
2844	}
2845
2846	return 0;
2847}
2848
2849static int allegro_buf_prepare(struct vb2_buffer *vb)
2850{
2851	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2852	struct allegro_channel *channel = vb2_get_drv_priv(vb->vb2_queue);
2853	struct allegro_dev *dev = channel->dev;
2854
2855	if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
2856		if (vbuf->field == V4L2_FIELD_ANY)
2857			vbuf->field = V4L2_FIELD_NONE;
2858		if (vbuf->field != V4L2_FIELD_NONE) {
2859			v4l2_err(&dev->v4l2_dev,
2860				 "channel %d: unsupported field\n",
2861				 channel->mcu_channel_id);
2862			return -EINVAL;
2863		}
2864	}
2865
2866	return 0;
2867}
2868
2869static void allegro_buf_queue(struct vb2_buffer *vb)
2870{
2871	struct allegro_channel *channel = vb2_get_drv_priv(vb->vb2_queue);
2872	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2873	struct vb2_queue *q = vb->vb2_queue;
2874
2875	if (V4L2_TYPE_IS_CAPTURE(q->type) &&
2876	    vb2_is_streaming(q) &&
2877	    v4l2_m2m_dst_buf_is_last(channel->fh.m2m_ctx)) {
2878		unsigned int i;
2879
2880		for (i = 0; i < vb->num_planes; i++)
2881			vb2_set_plane_payload(vb, i, 0);
2882
2883		vbuf->field = V4L2_FIELD_NONE;
2884		vbuf->sequence = channel->csequence++;
2885
2886		v4l2_m2m_last_buffer_done(channel->fh.m2m_ctx, vbuf);
2887		allegro_channel_eos_event(channel);
2888		return;
2889	}
2890
2891	v4l2_m2m_buf_queue(channel->fh.m2m_ctx, vbuf);
2892}
2893
2894static int allegro_start_streaming(struct vb2_queue *q, unsigned int count)
2895{
2896	struct allegro_channel *channel = vb2_get_drv_priv(q);
2897	struct allegro_dev *dev = channel->dev;
2898
2899	v4l2_dbg(2, debug, &dev->v4l2_dev,
2900		 "%s: start streaming\n",
2901		 V4L2_TYPE_IS_OUTPUT(q->type) ? "output" : "capture");
2902
2903	v4l2_m2m_update_start_streaming_state(channel->fh.m2m_ctx, q);
2904
2905	if (V4L2_TYPE_IS_OUTPUT(q->type))
2906		channel->osequence = 0;
2907	else
2908		channel->csequence = 0;
2909
2910	return 0;
2911}
2912
2913static void allegro_stop_streaming(struct vb2_queue *q)
2914{
2915	struct allegro_channel *channel = vb2_get_drv_priv(q);
2916	struct allegro_dev *dev = channel->dev;
2917	struct vb2_v4l2_buffer *buffer;
2918	struct allegro_m2m_buffer *shadow, *tmp;
2919
2920	v4l2_dbg(2, debug, &dev->v4l2_dev,
2921		 "%s: stop streaming\n",
2922		 V4L2_TYPE_IS_OUTPUT(q->type) ? "output" : "capture");
2923
2924	if (V4L2_TYPE_IS_OUTPUT(q->type)) {
2925		mutex_lock(&channel->shadow_list_lock);
2926		list_for_each_entry_safe(shadow, tmp,
2927					 &channel->source_shadow_list, head) {
2928			list_del(&shadow->head);
2929			v4l2_m2m_buf_done(&shadow->buf.vb, VB2_BUF_STATE_ERROR);
2930		}
2931		mutex_unlock(&channel->shadow_list_lock);
2932
2933		while ((buffer = v4l2_m2m_src_buf_remove(channel->fh.m2m_ctx)))
2934			v4l2_m2m_buf_done(buffer, VB2_BUF_STATE_ERROR);
2935	} else {
2936		mutex_lock(&channel->shadow_list_lock);
2937		list_for_each_entry_safe(shadow, tmp,
2938					 &channel->stream_shadow_list, head) {
2939			list_del(&shadow->head);
2940			v4l2_m2m_buf_done(&shadow->buf.vb, VB2_BUF_STATE_ERROR);
2941		}
2942		mutex_unlock(&channel->shadow_list_lock);
2943
2944		allegro_destroy_channel(channel);
2945		while ((buffer = v4l2_m2m_dst_buf_remove(channel->fh.m2m_ctx)))
2946			v4l2_m2m_buf_done(buffer, VB2_BUF_STATE_ERROR);
2947	}
2948
2949	v4l2_m2m_update_stop_streaming_state(channel->fh.m2m_ctx, q);
2950
2951	if (V4L2_TYPE_IS_OUTPUT(q->type) &&
2952	    v4l2_m2m_has_stopped(channel->fh.m2m_ctx))
2953		allegro_channel_eos_event(channel);
2954}
2955
2956static const struct vb2_ops allegro_queue_ops = {
2957	.queue_setup = allegro_queue_setup,
2958	.buf_prepare = allegro_buf_prepare,
2959	.buf_queue = allegro_buf_queue,
2960	.start_streaming = allegro_start_streaming,
2961	.stop_streaming = allegro_stop_streaming,
2962};
2963
2964static int allegro_queue_init(void *priv,
2965			      struct vb2_queue *src_vq,
2966			      struct vb2_queue *dst_vq)
2967{
2968	int err;
2969	struct allegro_channel *channel = priv;
2970
2971	src_vq->dev = &channel->dev->plat_dev->dev;
2972	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
2973	src_vq->io_modes = VB2_DMABUF | VB2_MMAP;
2974	src_vq->mem_ops = &vb2_dma_contig_memops;
2975	src_vq->drv_priv = channel;
2976	src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2977	src_vq->ops = &allegro_queue_ops;
2978	src_vq->buf_struct_size = sizeof(struct allegro_m2m_buffer);
2979	src_vq->lock = &channel->dev->lock;
2980	err = vb2_queue_init(src_vq);
2981	if (err)
2982		return err;
2983
2984	dst_vq->dev = &channel->dev->plat_dev->dev;
2985	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2986	dst_vq->io_modes = VB2_DMABUF | VB2_MMAP;
2987	dst_vq->mem_ops = &vb2_dma_contig_memops;
2988	dst_vq->drv_priv = channel;
2989	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2990	dst_vq->ops = &allegro_queue_ops;
2991	dst_vq->buf_struct_size = sizeof(struct allegro_m2m_buffer);
2992	dst_vq->lock = &channel->dev->lock;
2993	err = vb2_queue_init(dst_vq);
2994	if (err)
2995		return err;
2996
2997	return 0;
2998}
2999
3000static int allegro_clamp_qp(struct allegro_channel *channel,
3001			    struct v4l2_ctrl *ctrl)
3002{
3003	struct v4l2_ctrl *next_ctrl;
3004
3005	if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP)
3006		next_ctrl = channel->mpeg_video_h264_p_frame_qp;
3007	else if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP)
3008		next_ctrl = channel->mpeg_video_h264_b_frame_qp;
3009	else
3010		return 0;
3011
3012	/* Modify range automatically updates the value */
3013	__v4l2_ctrl_modify_range(next_ctrl, ctrl->val, 51, 1, ctrl->val);
3014
3015	return allegro_clamp_qp(channel, next_ctrl);
3016}
3017
3018static int allegro_clamp_bitrate(struct allegro_channel *channel,
3019				 struct v4l2_ctrl *ctrl)
3020{
3021	struct v4l2_ctrl *ctrl_bitrate = channel->mpeg_video_bitrate;
3022	struct v4l2_ctrl *ctrl_bitrate_peak = channel->mpeg_video_bitrate_peak;
3023
3024	if (ctrl->val == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR &&
3025	    ctrl_bitrate_peak->val < ctrl_bitrate->val)
3026		ctrl_bitrate_peak->val = ctrl_bitrate->val;
3027
3028	return 0;
3029}
3030
3031static int allegro_try_ctrl(struct v4l2_ctrl *ctrl)
3032{
3033	struct allegro_channel *channel = container_of(ctrl->handler,
3034						       struct allegro_channel,
3035						       ctrl_handler);
3036
3037	switch (ctrl->id) {
3038	case V4L2_CID_MPEG_VIDEO_BITRATE_MODE:
3039		allegro_clamp_bitrate(channel, ctrl);
3040		break;
3041	case V4L2_CID_USER_ALLEGRO_ENCODER_BUFFER:
3042		if (!channel->dev->has_encoder_buffer)
3043			ctrl->val = 0;
3044		break;
3045	}
3046
3047	return 0;
3048}
3049
3050static int allegro_s_ctrl(struct v4l2_ctrl *ctrl)
3051{
3052	struct allegro_channel *channel = container_of(ctrl->handler,
3053						       struct allegro_channel,
3054						       ctrl_handler);
3055	struct allegro_dev *dev = channel->dev;
3056
3057	v4l2_dbg(1, debug, &dev->v4l2_dev,
3058		 "s_ctrl: %s = %d\n", v4l2_ctrl_get_name(ctrl->id), ctrl->val);
3059
3060	switch (ctrl->id) {
3061	case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE:
3062		channel->frame_rc_enable = ctrl->val;
3063		break;
3064	case V4L2_CID_MPEG_VIDEO_BITRATE_MODE:
3065		channel->bitrate = channel->mpeg_video_bitrate->val;
3066		channel->bitrate_peak = channel->mpeg_video_bitrate_peak->val;
3067		v4l2_ctrl_activate(channel->mpeg_video_bitrate_peak,
3068				   ctrl->val == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR);
3069		break;
3070	case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
3071	case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
3072	case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP:
3073		allegro_clamp_qp(channel, ctrl);
3074		break;
3075	}
3076
3077	return 0;
3078}
3079
3080static const struct v4l2_ctrl_ops allegro_ctrl_ops = {
3081	.try_ctrl = allegro_try_ctrl,
3082	.s_ctrl = allegro_s_ctrl,
3083};
3084
3085static const struct v4l2_ctrl_config allegro_encoder_buffer_ctrl_config = {
3086	.id = V4L2_CID_USER_ALLEGRO_ENCODER_BUFFER,
3087	.name = "Encoder Buffer Enable",
3088	.type = V4L2_CTRL_TYPE_BOOLEAN,
3089	.min = 0,
3090	.max = 1,
3091	.step = 1,
3092	.def = 1,
3093};
3094
3095static int allegro_open(struct file *file)
3096{
3097	struct video_device *vdev = video_devdata(file);
3098	struct allegro_dev *dev = video_get_drvdata(vdev);
3099	struct allegro_channel *channel = NULL;
3100	struct v4l2_ctrl_handler *handler;
3101	u64 mask;
3102	int ret;
3103	unsigned int bitrate_max;
3104	unsigned int bitrate_def;
3105	unsigned int cpb_size_max;
3106	unsigned int cpb_size_def;
3107
3108	channel = kzalloc(sizeof(*channel), GFP_KERNEL);
3109	if (!channel)
3110		return -ENOMEM;
3111
3112	kref_init(&channel->ref);
3113
3114	v4l2_fh_init(&channel->fh, vdev);
3115
3116	init_completion(&channel->completion);
3117	INIT_LIST_HEAD(&channel->source_shadow_list);
3118	INIT_LIST_HEAD(&channel->stream_shadow_list);
3119	mutex_init(&channel->shadow_list_lock);
3120
3121	channel->dev = dev;
3122
3123	allegro_set_default_params(channel);
3124
3125	handler = &channel->ctrl_handler;
3126	v4l2_ctrl_handler_init(handler, 0);
3127	channel->mpeg_video_h264_profile = v4l2_ctrl_new_std_menu(handler,
3128			&allegro_ctrl_ops,
3129			V4L2_CID_MPEG_VIDEO_H264_PROFILE,
3130			V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, 0x0,
3131			V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE);
3132	mask = 1 << V4L2_MPEG_VIDEO_H264_LEVEL_1B;
3133	channel->mpeg_video_h264_level = v4l2_ctrl_new_std_menu(handler,
3134			&allegro_ctrl_ops,
3135			V4L2_CID_MPEG_VIDEO_H264_LEVEL,
3136			V4L2_MPEG_VIDEO_H264_LEVEL_5_1, mask,
3137			V4L2_MPEG_VIDEO_H264_LEVEL_5_1);
3138	channel->mpeg_video_h264_i_frame_qp =
3139		v4l2_ctrl_new_std(handler,
3140				  &allegro_ctrl_ops,
3141				  V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP,
3142				  0, 51, 1, 30);
3143	channel->mpeg_video_h264_max_qp =
3144		v4l2_ctrl_new_std(handler,
3145				  &allegro_ctrl_ops,
3146				  V4L2_CID_MPEG_VIDEO_H264_MAX_QP,
3147				  0, 51, 1, 51);
3148	channel->mpeg_video_h264_min_qp =
3149		v4l2_ctrl_new_std(handler,
3150				  &allegro_ctrl_ops,
3151				  V4L2_CID_MPEG_VIDEO_H264_MIN_QP,
3152				  0, 51, 1, 0);
3153	channel->mpeg_video_h264_p_frame_qp =
3154		v4l2_ctrl_new_std(handler,
3155				  &allegro_ctrl_ops,
3156				  V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP,
3157				  0, 51, 1, 30);
3158	channel->mpeg_video_h264_b_frame_qp =
3159		v4l2_ctrl_new_std(handler,
3160				  &allegro_ctrl_ops,
3161				  V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP,
3162				  0, 51, 1, 30);
3163
3164	channel->mpeg_video_hevc_profile =
3165		v4l2_ctrl_new_std_menu(handler,
3166				       &allegro_ctrl_ops,
3167				       V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
3168				       V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, 0x0,
3169				       V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN);
3170	channel->mpeg_video_hevc_level =
3171		v4l2_ctrl_new_std_menu(handler,
3172				       &allegro_ctrl_ops,
3173				       V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
3174				       V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, 0x0,
3175				       V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1);
3176	channel->mpeg_video_hevc_tier =
3177		v4l2_ctrl_new_std_menu(handler,
3178				       &allegro_ctrl_ops,
3179				       V4L2_CID_MPEG_VIDEO_HEVC_TIER,
3180				       V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, 0x0,
3181				       V4L2_MPEG_VIDEO_HEVC_TIER_MAIN);
3182	channel->mpeg_video_hevc_i_frame_qp =
3183		v4l2_ctrl_new_std(handler,
3184				  &allegro_ctrl_ops,
3185				  V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP,
3186				  0, 51, 1, 30);
3187	channel->mpeg_video_hevc_max_qp =
3188		v4l2_ctrl_new_std(handler,
3189				  &allegro_ctrl_ops,
3190				  V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP,
3191				  0, 51, 1, 51);
3192	channel->mpeg_video_hevc_min_qp =
3193		v4l2_ctrl_new_std(handler,
3194				  &allegro_ctrl_ops,
3195				  V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP,
3196				  0, 51, 1, 0);
3197	channel->mpeg_video_hevc_p_frame_qp =
3198		v4l2_ctrl_new_std(handler,
3199				  &allegro_ctrl_ops,
3200				  V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP,
3201				  0, 51, 1, 30);
3202	channel->mpeg_video_hevc_b_frame_qp =
3203		v4l2_ctrl_new_std(handler,
3204				  &allegro_ctrl_ops,
3205				  V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP,
3206				  0, 51, 1, 30);
3207
3208	channel->mpeg_video_frame_rc_enable =
3209		v4l2_ctrl_new_std(handler,
3210				  &allegro_ctrl_ops,
3211				  V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE,
3212				  false, 0x1,
3213				  true, false);
3214	channel->mpeg_video_bitrate_mode = v4l2_ctrl_new_std_menu(handler,
3215			&allegro_ctrl_ops,
3216			V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
3217			V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, 0,
3218			V4L2_MPEG_VIDEO_BITRATE_MODE_CBR);
3219
3220	if (channel->codec == V4L2_PIX_FMT_H264) {
3221		bitrate_max = h264_maximum_bitrate(V4L2_MPEG_VIDEO_H264_LEVEL_5_1);
3222		bitrate_def = h264_maximum_bitrate(V4L2_MPEG_VIDEO_H264_LEVEL_5_1);
3223		cpb_size_max = h264_maximum_cpb_size(V4L2_MPEG_VIDEO_H264_LEVEL_5_1);
3224		cpb_size_def = h264_maximum_cpb_size(V4L2_MPEG_VIDEO_H264_LEVEL_5_1);
3225	} else {
3226		bitrate_max = hevc_maximum_bitrate(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1);
3227		bitrate_def = hevc_maximum_bitrate(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1);
3228		cpb_size_max = hevc_maximum_cpb_size(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1);
3229		cpb_size_def = hevc_maximum_cpb_size(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1);
3230	}
3231	channel->mpeg_video_bitrate = v4l2_ctrl_new_std(handler,
3232			&allegro_ctrl_ops,
3233			V4L2_CID_MPEG_VIDEO_BITRATE,
3234			0, bitrate_max, 1, bitrate_def);
3235	channel->mpeg_video_bitrate_peak = v4l2_ctrl_new_std(handler,
3236			&allegro_ctrl_ops,
3237			V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
3238			0, bitrate_max, 1, bitrate_def);
3239	channel->mpeg_video_cpb_size = v4l2_ctrl_new_std(handler,
3240			&allegro_ctrl_ops,
3241			V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE,
3242			0, cpb_size_max, 1, cpb_size_def);
3243	channel->mpeg_video_gop_size = v4l2_ctrl_new_std(handler,
3244			&allegro_ctrl_ops,
3245			V4L2_CID_MPEG_VIDEO_GOP_SIZE,
3246			0, ALLEGRO_GOP_SIZE_MAX,
3247			1, ALLEGRO_GOP_SIZE_DEFAULT);
3248	channel->encoder_buffer = v4l2_ctrl_new_custom(handler,
3249			&allegro_encoder_buffer_ctrl_config, NULL);
3250	v4l2_ctrl_new_std(handler,
3251			  &allegro_ctrl_ops,
3252			  V4L2_CID_MIN_BUFFERS_FOR_OUTPUT,
3253			  1, 32,
3254			  1, 1);
3255	if (handler->error != 0) {
3256		ret = handler->error;
3257		goto error;
3258	}
3259
3260	channel->fh.ctrl_handler = handler;
3261
3262	v4l2_ctrl_cluster(3, &channel->mpeg_video_bitrate_mode);
3263
3264	v4l2_ctrl_handler_setup(handler);
3265
3266	channel->mcu_channel_id = -1;
3267	channel->user_id = -1;
3268
3269	INIT_LIST_HEAD(&channel->buffers_reference);
3270	INIT_LIST_HEAD(&channel->buffers_intermediate);
3271
3272	channel->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, channel,
3273						allegro_queue_init);
3274
3275	if (IS_ERR(channel->fh.m2m_ctx)) {
3276		ret = PTR_ERR(channel->fh.m2m_ctx);
3277		goto error;
3278	}
3279
3280	scoped_guard(mutex, &dev->channels_lock) {
3281		list_add(&channel->list, &dev->channels);
3282	}
3283
3284	v4l2_fh_add(&channel->fh, file);
3285
3286	allegro_channel_adjust(channel);
3287
3288	return 0;
3289
3290error:
3291	v4l2_ctrl_handler_free(handler);
3292	kfree(channel);
3293	return ret;
3294}
3295
3296static int allegro_release(struct file *file)
3297{
3298	struct allegro_channel *channel = file_to_channel(file);
3299	struct allegro_dev *dev = channel->dev;
3300
3301	v4l2_m2m_ctx_release(channel->fh.m2m_ctx);
3302
3303	scoped_guard(mutex, &dev->channels_lock) {
3304		list_del(&channel->list);
3305	}
3306
3307	v4l2_ctrl_handler_free(&channel->ctrl_handler);
3308
3309	v4l2_fh_del(&channel->fh, file);
3310	v4l2_fh_exit(&channel->fh);
3311
3312	allegro_ref_put_channel(channel);
3313
3314	return 0;
3315}
3316
3317static int allegro_querycap(struct file *file, void *fh,
3318			    struct v4l2_capability *cap)
3319{
3320	strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver));
3321	strscpy(cap->card, "Allegro DVT Video Encoder", sizeof(cap->card));
3322
3323	return 0;
3324}
3325
3326static int allegro_enum_fmt_vid(struct file *file, void *fh,
3327				struct v4l2_fmtdesc *f)
3328{
3329	switch (f->type) {
3330	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
3331		if (f->index >= 1)
3332			return -EINVAL;
3333		f->pixelformat = V4L2_PIX_FMT_NV12;
3334		break;
3335	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
3336		if (f->index >= 2)
3337			return -EINVAL;
3338		if (f->index == 0)
3339			f->pixelformat = V4L2_PIX_FMT_H264;
3340		if (f->index == 1)
3341			f->pixelformat = V4L2_PIX_FMT_HEVC;
3342		break;
3343	default:
3344		return -EINVAL;
3345	}
3346	return 0;
3347}
3348
3349static int allegro_g_fmt_vid_cap(struct file *file, void *fh,
3350				 struct v4l2_format *f)
3351{
3352	struct allegro_channel *channel = file_to_channel(file);
3353
3354	f->fmt.pix.field = V4L2_FIELD_NONE;
3355	f->fmt.pix.width = channel->width;
3356	f->fmt.pix.height = channel->height;
3357
3358	f->fmt.pix.colorspace = channel->colorspace;
3359	f->fmt.pix.ycbcr_enc = channel->ycbcr_enc;
3360	f->fmt.pix.quantization = channel->quantization;
3361	f->fmt.pix.xfer_func = channel->xfer_func;
3362
3363	f->fmt.pix.pixelformat = channel->codec;
3364	f->fmt.pix.bytesperline = 0;
3365	f->fmt.pix.sizeimage = channel->sizeimage_encoded;
3366
3367	return 0;
3368}
3369
3370static int allegro_try_fmt_vid_cap(struct file *file, void *fh,
3371				   struct v4l2_format *f)
3372{
3373	f->fmt.pix.field = V4L2_FIELD_NONE;
3374
3375	f->fmt.pix.width = clamp_t(__u32, f->fmt.pix.width,
3376				   ALLEGRO_WIDTH_MIN, ALLEGRO_WIDTH_MAX);
3377	f->fmt.pix.height = clamp_t(__u32, f->fmt.pix.height,
3378				    ALLEGRO_HEIGHT_MIN, ALLEGRO_HEIGHT_MAX);
3379
3380	if (f->fmt.pix.pixelformat != V4L2_PIX_FMT_HEVC &&
3381	    f->fmt.pix.pixelformat != V4L2_PIX_FMT_H264)
3382		f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264;
3383
3384	f->fmt.pix.bytesperline = 0;
3385	f->fmt.pix.sizeimage =
3386		estimate_stream_size(f->fmt.pix.width, f->fmt.pix.height);
3387
3388	return 0;
3389}
3390
3391static int allegro_s_fmt_vid_cap(struct file *file, void *fh,
3392				 struct v4l2_format *f)
3393{
3394	struct allegro_channel *channel = file_to_channel(file);
3395	struct vb2_queue *vq;
3396	int err;
3397
3398	err = allegro_try_fmt_vid_cap(file, fh, f);
3399	if (err)
3400		return err;
3401
3402	vq = v4l2_m2m_get_vq(channel->fh.m2m_ctx, f->type);
3403	if (vb2_is_busy(vq))
3404		return -EBUSY;
3405
3406	channel->codec = f->fmt.pix.pixelformat;
3407
3408	allegro_channel_adjust(channel);
3409
3410	return 0;
3411}
3412
3413static int allegro_g_fmt_vid_out(struct file *file, void *fh,
3414				 struct v4l2_format *f)
3415{
3416	struct allegro_channel *channel = file_to_channel(file);
3417
3418	f->fmt.pix.field = V4L2_FIELD_NONE;
3419
3420	f->fmt.pix.width = channel->width;
3421	f->fmt.pix.height = channel->height;
3422
3423	f->fmt.pix.colorspace = channel->colorspace;
3424	f->fmt.pix.ycbcr_enc = channel->ycbcr_enc;
3425	f->fmt.pix.quantization = channel->quantization;
3426	f->fmt.pix.xfer_func = channel->xfer_func;
3427
3428	f->fmt.pix.pixelformat = channel->pixelformat;
3429	f->fmt.pix.bytesperline = channel->stride;
3430	f->fmt.pix.sizeimage = channel->sizeimage_raw;
3431
3432	return 0;
3433}
3434
3435static int allegro_try_fmt_vid_out(struct file *file, void *fh,
3436				   struct v4l2_format *f)
3437{
3438	f->fmt.pix.field = V4L2_FIELD_NONE;
3439
3440	/*
3441	 * The firmware of the Allegro codec handles the padding internally
3442	 * and expects the visual frame size when configuring a channel.
3443	 * Therefore, unlike other encoder drivers, this driver does not round
3444	 * up the width and height to macroblock alignment and does not
3445	 * implement the selection api.
3446	 */
3447	f->fmt.pix.width = clamp_t(__u32, f->fmt.pix.width,
3448				   ALLEGRO_WIDTH_MIN, ALLEGRO_WIDTH_MAX);
3449	f->fmt.pix.height = clamp_t(__u32, f->fmt.pix.height,
3450				    ALLEGRO_HEIGHT_MIN, ALLEGRO_HEIGHT_MAX);
3451
3452	f->fmt.pix.pixelformat = V4L2_PIX_FMT_NV12;
3453	f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 32);
3454	f->fmt.pix.sizeimage =
3455		f->fmt.pix.bytesperline * f->fmt.pix.height * 3 / 2;
3456
3457	return 0;
3458}
3459
3460static int allegro_s_fmt_vid_out(struct file *file, void *fh,
3461				 struct v4l2_format *f)
3462{
3463	struct allegro_channel *channel = file_to_channel(file);
3464	int err;
3465
3466	err = allegro_try_fmt_vid_out(file, fh, f);
3467	if (err)
3468		return err;
3469
3470	channel->width = f->fmt.pix.width;
3471	channel->height = f->fmt.pix.height;
3472	channel->stride = f->fmt.pix.bytesperline;
3473	channel->sizeimage_raw = f->fmt.pix.sizeimage;
3474
3475	channel->colorspace = f->fmt.pix.colorspace;
3476	channel->ycbcr_enc = f->fmt.pix.ycbcr_enc;
3477	channel->quantization = f->fmt.pix.quantization;
3478	channel->xfer_func = f->fmt.pix.xfer_func;
3479
3480	allegro_channel_adjust(channel);
3481
3482	return 0;
3483}
3484
3485static int allegro_channel_cmd_stop(struct allegro_channel *channel)
3486{
3487	if (v4l2_m2m_has_stopped(channel->fh.m2m_ctx))
3488		allegro_channel_eos_event(channel);
3489
3490	return 0;
3491}
3492
3493static int allegro_channel_cmd_start(struct allegro_channel *channel)
3494{
3495	if (v4l2_m2m_has_stopped(channel->fh.m2m_ctx))
3496		vb2_clear_last_buffer_dequeued(&channel->fh.m2m_ctx->cap_q_ctx.q);
3497
3498	return 0;
3499}
3500
3501static int allegro_encoder_cmd(struct file *file, void *fh,
3502			       struct v4l2_encoder_cmd *cmd)
3503{
3504	struct allegro_channel *channel = file_to_channel(file);
3505	int err;
3506
3507	err = v4l2_m2m_ioctl_try_encoder_cmd(file, fh, cmd);
3508	if (err)
3509		return err;
3510
3511	err = v4l2_m2m_ioctl_encoder_cmd(file, fh, cmd);
3512	if (err)
3513		return err;
3514
3515	if (cmd->cmd == V4L2_ENC_CMD_STOP)
3516		err = allegro_channel_cmd_stop(channel);
3517
3518	if (cmd->cmd == V4L2_ENC_CMD_START)
3519		err = allegro_channel_cmd_start(channel);
3520
3521	return err;
3522}
3523
3524static int allegro_enum_framesizes(struct file *file, void *fh,
3525				   struct v4l2_frmsizeenum *fsize)
3526{
3527	switch (fsize->pixel_format) {
3528	case V4L2_PIX_FMT_HEVC:
3529	case V4L2_PIX_FMT_H264:
3530	case V4L2_PIX_FMT_NV12:
3531		break;
3532	default:
3533		return -EINVAL;
3534	}
3535
3536	if (fsize->index)
3537		return -EINVAL;
3538
3539	fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
3540	fsize->stepwise.min_width = ALLEGRO_WIDTH_MIN;
3541	fsize->stepwise.max_width = ALLEGRO_WIDTH_MAX;
3542	fsize->stepwise.step_width = 1;
3543	fsize->stepwise.min_height = ALLEGRO_HEIGHT_MIN;
3544	fsize->stepwise.max_height = ALLEGRO_HEIGHT_MAX;
3545	fsize->stepwise.step_height = 1;
3546
3547	return 0;
3548}
3549
3550static int allegro_ioctl_streamon(struct file *file, void *priv,
3551				  enum v4l2_buf_type type)
3552{
3553	struct allegro_channel *channel = file_to_channel(file);
3554	int err;
3555
3556	if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
3557		err = allegro_create_channel(channel);
3558		if (err)
3559			return err;
3560	}
3561
3562	return v4l2_m2m_streamon(file, channel->fh.m2m_ctx, type);
3563}
3564
3565static int allegro_g_parm(struct file *file, void *fh,
3566			  struct v4l2_streamparm *a)
3567{
3568	struct allegro_channel *channel = file_to_channel(file);
3569	struct v4l2_fract *timeperframe;
3570
3571	if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
3572		return -EINVAL;
3573
3574	a->parm.output.capability = V4L2_CAP_TIMEPERFRAME;
3575	timeperframe = &a->parm.output.timeperframe;
3576	timeperframe->numerator = channel->framerate.denominator;
3577	timeperframe->denominator = channel->framerate.numerator;
3578
3579	return 0;
3580}
3581
3582static int allegro_s_parm(struct file *file, void *fh,
3583			  struct v4l2_streamparm *a)
3584{
3585	struct allegro_channel *channel = file_to_channel(file);
3586	struct v4l2_fract *timeperframe;
3587	int div;
3588
3589	if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
3590		return -EINVAL;
3591
3592	a->parm.output.capability = V4L2_CAP_TIMEPERFRAME;
3593	timeperframe = &a->parm.output.timeperframe;
3594
3595	if (timeperframe->numerator == 0 || timeperframe->denominator == 0)
3596		return allegro_g_parm(file, fh, a);
3597
3598	div = gcd(timeperframe->denominator, timeperframe->numerator);
3599	channel->framerate.numerator = timeperframe->denominator / div;
3600	channel->framerate.denominator = timeperframe->numerator / div;
3601
3602	return 0;
3603}
3604
3605static int allegro_subscribe_event(struct v4l2_fh *fh,
3606				   const struct v4l2_event_subscription *sub)
3607{
3608	switch (sub->type) {
3609	case V4L2_EVENT_EOS:
3610		return v4l2_event_subscribe(fh, sub, 0, NULL);
3611	default:
3612		return v4l2_ctrl_subscribe_event(fh, sub);
3613	}
3614}
3615
3616static const struct v4l2_ioctl_ops allegro_ioctl_ops = {
3617	.vidioc_querycap = allegro_querycap,
3618	.vidioc_enum_fmt_vid_cap = allegro_enum_fmt_vid,
3619	.vidioc_enum_fmt_vid_out = allegro_enum_fmt_vid,
3620	.vidioc_g_fmt_vid_cap = allegro_g_fmt_vid_cap,
3621	.vidioc_try_fmt_vid_cap = allegro_try_fmt_vid_cap,
3622	.vidioc_s_fmt_vid_cap = allegro_s_fmt_vid_cap,
3623	.vidioc_g_fmt_vid_out = allegro_g_fmt_vid_out,
3624	.vidioc_try_fmt_vid_out = allegro_try_fmt_vid_out,
3625	.vidioc_s_fmt_vid_out = allegro_s_fmt_vid_out,
3626
3627	.vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
3628	.vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
3629
3630	.vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
3631	.vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
3632	.vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
3633	.vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
3634	.vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
3635
3636	.vidioc_streamon = allegro_ioctl_streamon,
3637	.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
3638
3639	.vidioc_try_encoder_cmd = v4l2_m2m_ioctl_try_encoder_cmd,
3640	.vidioc_encoder_cmd = allegro_encoder_cmd,
3641	.vidioc_enum_framesizes = allegro_enum_framesizes,
3642
3643	.vidioc_g_parm		= allegro_g_parm,
3644	.vidioc_s_parm		= allegro_s_parm,
3645
3646	.vidioc_subscribe_event = allegro_subscribe_event,
3647	.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
3648};
3649
3650static const struct v4l2_file_operations allegro_fops = {
3651	.owner = THIS_MODULE,
3652	.open = allegro_open,
3653	.release = allegro_release,
3654	.poll = v4l2_m2m_fop_poll,
3655	.unlocked_ioctl = video_ioctl2,
3656	.mmap = v4l2_m2m_fop_mmap,
3657};
3658
3659static int allegro_register_device(struct allegro_dev *dev)
3660{
3661	struct video_device *video_dev = &dev->video_dev;
3662
3663	strscpy(video_dev->name, "allegro", sizeof(video_dev->name));
3664	video_dev->fops = &allegro_fops;
3665	video_dev->ioctl_ops = &allegro_ioctl_ops;
3666	video_dev->release = video_device_release_empty;
3667	video_dev->lock = &dev->lock;
3668	video_dev->v4l2_dev = &dev->v4l2_dev;
3669	video_dev->vfl_dir = VFL_DIR_M2M;
3670	video_dev->device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
3671	video_set_drvdata(video_dev, dev);
3672
3673	return video_register_device(video_dev, VFL_TYPE_VIDEO, 0);
3674}
3675
3676static void allegro_device_run(void *priv)
3677{
3678	struct allegro_channel *channel = priv;
3679	struct allegro_dev *dev = channel->dev;
3680	struct vb2_v4l2_buffer *src_buf;
3681	struct vb2_v4l2_buffer *dst_buf;
3682	dma_addr_t src_y;
3683	dma_addr_t src_uv;
3684	dma_addr_t dst_addr;
3685	unsigned long dst_size;
3686	u64 src_handle;
3687	u64 dst_handle;
3688
3689	dst_buf = v4l2_m2m_dst_buf_remove(channel->fh.m2m_ctx);
3690	dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
3691	dst_size = vb2_plane_size(&dst_buf->vb2_buf, 0);
3692	dst_handle = allegro_put_buffer(channel, &channel->stream_shadow_list,
3693					dst_buf);
3694	allegro_mcu_send_put_stream_buffer(dev, channel, dst_addr, dst_size,
3695					   dst_handle);
3696
3697	src_buf = v4l2_m2m_src_buf_remove(channel->fh.m2m_ctx);
3698	src_buf->sequence = channel->osequence++;
3699	src_y = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
3700	src_uv = src_y + (channel->stride * channel->height);
3701	src_handle = allegro_put_buffer(channel, &channel->source_shadow_list,
3702					src_buf);
3703	allegro_mcu_send_encode_frame(dev, channel, src_y, src_uv, src_handle);
3704
3705	v4l2_m2m_job_finish(dev->m2m_dev, channel->fh.m2m_ctx);
3706}
3707
3708static const struct v4l2_m2m_ops allegro_m2m_ops = {
3709	.device_run = allegro_device_run,
3710};
3711
3712static int allegro_mcu_hw_init(struct allegro_dev *dev,
3713			       const struct fw_info *info)
3714{
3715	int err;
3716
3717	dev->mbox_command = allegro_mbox_init(dev, info->mailbox_cmd,
3718					      info->mailbox_size);
3719	dev->mbox_status = allegro_mbox_init(dev, info->mailbox_status,
3720					     info->mailbox_size);
3721	if (IS_ERR(dev->mbox_command) || IS_ERR(dev->mbox_status)) {
3722		v4l2_err(&dev->v4l2_dev,
3723			 "failed to initialize mailboxes\n");
3724		return -EIO;
3725	}
3726
3727	err = allegro_encoder_buffer_init(dev, &dev->encoder_buffer);
3728	dev->has_encoder_buffer = (err == 0);
3729	if (!dev->has_encoder_buffer)
3730		v4l2_info(&dev->v4l2_dev, "encoder buffer not available\n");
3731
3732	allegro_mcu_enable_interrupts(dev);
3733
3734	/* The mcu sends INIT after reset. */
3735	allegro_mcu_start(dev);
3736	err = allegro_mcu_wait_for_init_timeout(dev, 5000);
3737	if (err < 0) {
3738		v4l2_err(&dev->v4l2_dev,
3739			 "mcu did not send INIT after reset\n");
3740		err = -EIO;
3741		goto err_disable_interrupts;
3742	}
3743
3744	err = allegro_alloc_buffer(dev, &dev->suballocator,
3745				   info->suballocator_size);
3746	if (err) {
3747		v4l2_err(&dev->v4l2_dev,
3748			 "failed to allocate %zu bytes for suballocator\n",
3749			 info->suballocator_size);
3750		goto err_reset_mcu;
3751	}
3752
3753	allegro_mcu_send_init(dev, dev->suballocator.paddr,
3754			      dev->suballocator.size);
3755	err = allegro_mcu_wait_for_init_timeout(dev, 5000);
3756	if (err < 0) {
3757		v4l2_err(&dev->v4l2_dev,
3758			 "mcu failed to configure sub-allocator\n");
3759		err = -EIO;
3760		goto err_free_suballocator;
3761	}
3762
3763	return 0;
3764
3765err_free_suballocator:
3766	allegro_free_buffer(dev, &dev->suballocator);
3767err_reset_mcu:
3768	allegro_mcu_reset(dev);
3769err_disable_interrupts:
3770	allegro_mcu_disable_interrupts(dev);
3771
3772	return err;
3773}
3774
3775static int allegro_mcu_hw_deinit(struct allegro_dev *dev)
3776{
3777	int err;
3778
3779	err = allegro_mcu_reset(dev);
3780	if (err)
3781		v4l2_warn(&dev->v4l2_dev,
3782			  "mcu failed to enter sleep state\n");
3783
3784	err = allegro_mcu_disable_interrupts(dev);
3785	if (err)
3786		v4l2_warn(&dev->v4l2_dev,
3787			  "failed to disable interrupts\n");
3788
3789	allegro_free_buffer(dev, &dev->suballocator);
3790
3791	return 0;
3792}
3793
3794static void allegro_fw_callback(const struct firmware *fw, void *context)
3795{
3796	struct allegro_dev *dev = context;
3797	const char *fw_codec_name = "al5e.fw";
3798	const struct firmware *fw_codec;
3799	int err;
3800
3801	if (!fw)
3802		return;
3803
3804	v4l2_dbg(1, debug, &dev->v4l2_dev,
3805		 "requesting codec firmware '%s'\n", fw_codec_name);
3806	err = request_firmware(&fw_codec, fw_codec_name, &dev->plat_dev->dev);
3807	if (err)
3808		goto err_release_firmware;
3809
3810	dev->fw_info = allegro_get_firmware_info(dev, fw, fw_codec);
3811	if (!dev->fw_info) {
3812		v4l2_err(&dev->v4l2_dev, "firmware is not supported\n");
3813		goto err_release_firmware_codec;
3814	}
3815
3816	v4l2_info(&dev->v4l2_dev,
3817		  "using mcu firmware version '%s'\n", dev->fw_info->version);
3818
3819	pm_runtime_enable(&dev->plat_dev->dev);
3820	err = pm_runtime_resume_and_get(&dev->plat_dev->dev);
3821	if (err)
3822		goto err_release_firmware_codec;
3823
3824	/* Ensure that the mcu is sleeping at the reset vector */
3825	err = allegro_mcu_reset(dev);
3826	if (err) {
3827		v4l2_err(&dev->v4l2_dev, "failed to reset mcu\n");
3828		goto err_suspend;
3829	}
3830
3831	allegro_copy_firmware(dev, fw->data, fw->size);
3832	allegro_copy_fw_codec(dev, fw_codec->data, fw_codec->size);
3833
3834	err = allegro_mcu_hw_init(dev, dev->fw_info);
3835	if (err) {
3836		v4l2_err(&dev->v4l2_dev, "failed to initialize mcu\n");
3837		goto err_free_fw_codec;
3838	}
3839
3840	dev->m2m_dev = v4l2_m2m_init(&allegro_m2m_ops);
3841	if (IS_ERR(dev->m2m_dev)) {
3842		v4l2_err(&dev->v4l2_dev, "failed to init mem2mem device\n");
3843		goto err_mcu_hw_deinit;
3844	}
3845
3846	err = allegro_register_device(dev);
3847	if (err) {
3848		v4l2_err(&dev->v4l2_dev, "failed to register video device\n");
3849		goto err_m2m_release;
3850	}
3851
3852	v4l2_dbg(1, debug, &dev->v4l2_dev,
3853		 "allegro codec registered as /dev/video%d\n",
3854		 dev->video_dev.num);
3855
3856	dev->initialized = true;
3857
3858	release_firmware(fw_codec);
3859	release_firmware(fw);
3860
3861	return;
3862
3863err_m2m_release:
3864	v4l2_m2m_release(dev->m2m_dev);
3865	dev->m2m_dev = NULL;
3866err_mcu_hw_deinit:
3867	allegro_mcu_hw_deinit(dev);
3868err_free_fw_codec:
3869	allegro_free_fw_codec(dev);
3870err_suspend:
3871	pm_runtime_put(&dev->plat_dev->dev);
3872	pm_runtime_disable(&dev->plat_dev->dev);
3873err_release_firmware_codec:
3874	release_firmware(fw_codec);
3875err_release_firmware:
3876	release_firmware(fw);
3877}
3878
3879static int allegro_firmware_request_nowait(struct allegro_dev *dev)
3880{
3881	const char *fw = "al5e_b.fw";
3882
3883	v4l2_dbg(1, debug, &dev->v4l2_dev,
3884		 "requesting firmware '%s'\n", fw);
3885	return request_firmware_nowait(THIS_MODULE, true, fw,
3886				       &dev->plat_dev->dev, GFP_KERNEL, dev,
3887				       allegro_fw_callback);
3888}
3889
3890static int allegro_probe(struct platform_device *pdev)
3891{
3892	struct allegro_dev *dev;
3893	struct resource *res, *sram_res;
3894	int ret;
3895	int irq;
3896	void __iomem *regs, *sram_regs;
3897
3898	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
3899	if (!dev)
3900		return -ENOMEM;
3901	dev->plat_dev = pdev;
3902	init_completion(&dev->init_complete);
3903	INIT_LIST_HEAD(&dev->channels);
3904	mutex_init(&dev->channels_lock);
3905
3906	mutex_init(&dev->lock);
3907
3908	dev->initialized = false;
3909
3910	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
3911	if (!res) {
3912		dev_err(&pdev->dev,
3913			"regs resource missing from device tree\n");
3914		return -EINVAL;
3915	}
3916	regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
3917	if (!regs) {
3918		dev_err(&pdev->dev, "failed to map registers\n");
3919		return -ENOMEM;
3920	}
3921	dev->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
3922					    &allegro_regmap_config);
3923	if (IS_ERR(dev->regmap)) {
3924		dev_err(&pdev->dev, "failed to init regmap\n");
3925		return PTR_ERR(dev->regmap);
3926	}
3927
3928	sram_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
3929	if (!sram_res) {
3930		dev_err(&pdev->dev,
3931			"sram resource missing from device tree\n");
3932		return -EINVAL;
3933	}
3934	sram_regs = devm_ioremap(&pdev->dev,
3935				 sram_res->start,
3936				 resource_size(sram_res));
3937	if (!sram_regs) {
3938		dev_err(&pdev->dev, "failed to map sram\n");
3939		return -ENOMEM;
3940	}
3941	dev->sram = devm_regmap_init_mmio(&pdev->dev, sram_regs,
3942					  &allegro_sram_config);
3943	if (IS_ERR(dev->sram)) {
3944		dev_err(&pdev->dev, "failed to init sram\n");
3945		return PTR_ERR(dev->sram);
3946	}
3947
3948	dev->settings = syscon_regmap_lookup_by_compatible("xlnx,vcu-settings");
3949	if (IS_ERR(dev->settings))
3950		dev_warn(&pdev->dev, "failed to open settings\n");
3951
3952	dev->clk_core = devm_clk_get(&pdev->dev, "core_clk");
3953	if (IS_ERR(dev->clk_core))
3954		return PTR_ERR(dev->clk_core);
3955
3956	dev->clk_mcu = devm_clk_get(&pdev->dev, "mcu_clk");
3957	if (IS_ERR(dev->clk_mcu))
3958		return PTR_ERR(dev->clk_mcu);
3959
3960	irq = platform_get_irq(pdev, 0);
3961	if (irq < 0)
3962		return irq;
3963	ret = devm_request_threaded_irq(&pdev->dev, irq,
3964					allegro_hardirq,
3965					allegro_irq_thread,
3966					IRQF_SHARED, dev_name(&pdev->dev), dev);
3967	if (ret < 0) {
3968		dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
3969		return ret;
3970	}
3971
3972	ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
3973	if (ret)
3974		return ret;
3975
3976	platform_set_drvdata(pdev, dev);
3977
3978	ret = allegro_firmware_request_nowait(dev);
3979	if (ret < 0) {
3980		v4l2_err(&dev->v4l2_dev,
3981			 "failed to request firmware: %d\n", ret);
3982		v4l2_device_unregister(&dev->v4l2_dev);
3983		return ret;
3984	}
3985
3986	return 0;
3987}
3988
3989static void allegro_remove(struct platform_device *pdev)
3990{
3991	struct allegro_dev *dev = platform_get_drvdata(pdev);
3992
3993	if (dev->initialized) {
3994		video_unregister_device(&dev->video_dev);
3995		if (dev->m2m_dev)
3996			v4l2_m2m_release(dev->m2m_dev);
3997		allegro_mcu_hw_deinit(dev);
3998		allegro_free_fw_codec(dev);
3999	}
4000
4001	pm_runtime_put(&dev->plat_dev->dev);
4002	pm_runtime_disable(&dev->plat_dev->dev);
4003
4004	v4l2_device_unregister(&dev->v4l2_dev);
4005}
4006
4007static int allegro_runtime_resume(struct device *device)
4008{
4009	struct allegro_dev *dev = dev_get_drvdata(device);
4010	struct regmap *settings = dev->settings;
4011	unsigned int clk_mcu;
4012	unsigned int clk_core;
4013	int err;
4014
4015	if (!settings)
4016		return -EINVAL;
4017
4018#define MHZ_TO_HZ(freq) ((freq) * 1000 * 1000)
4019
4020	err = regmap_read(settings, VCU_CORE_CLK, &clk_core);
4021	if (err < 0)
4022		return err;
4023	err = clk_set_rate(dev->clk_core, MHZ_TO_HZ(clk_core));
4024	if (err < 0)
4025		return err;
4026	err = clk_prepare_enable(dev->clk_core);
4027	if (err)
4028		return err;
4029
4030	err = regmap_read(settings, VCU_MCU_CLK, &clk_mcu);
4031	if (err < 0)
4032		goto disable_clk_core;
4033	err = clk_set_rate(dev->clk_mcu, MHZ_TO_HZ(clk_mcu));
4034	if (err < 0)
4035		goto disable_clk_core;
4036	err = clk_prepare_enable(dev->clk_mcu);
4037	if (err)
4038		goto disable_clk_core;
4039
4040#undef MHZ_TO_HZ
4041
4042	return 0;
4043
4044disable_clk_core:
4045	clk_disable_unprepare(dev->clk_core);
4046
4047	return err;
4048}
4049
4050static int allegro_runtime_suspend(struct device *device)
4051{
4052	struct allegro_dev *dev = dev_get_drvdata(device);
4053
4054	clk_disable_unprepare(dev->clk_mcu);
4055	clk_disable_unprepare(dev->clk_core);
4056
4057	return 0;
4058}
4059
4060static const struct of_device_id allegro_dt_ids[] = {
4061	{ .compatible = "allegro,al5e-1.1" },
4062	{ /* sentinel */ }
4063};
4064
4065MODULE_DEVICE_TABLE(of, allegro_dt_ids);
4066
4067static const struct dev_pm_ops allegro_pm_ops = {
4068	.runtime_resume = allegro_runtime_resume,
4069	.runtime_suspend = allegro_runtime_suspend,
4070};
4071
4072static struct platform_driver allegro_driver = {
4073	.probe = allegro_probe,
4074	.remove = allegro_remove,
4075	.driver = {
4076		.name = "allegro",
4077		.of_match_table = allegro_dt_ids,
4078		.pm = &allegro_pm_ops,
4079	},
4080};
4081
4082module_platform_driver(allegro_driver);
4083
4084MODULE_LICENSE("GPL");
4085MODULE_AUTHOR("Michael Tretter <kernel@pengutronix.de>");
4086MODULE_DESCRIPTION("Allegro DVT encoder driver");