ipu6-platform-isys-csi2-reg.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/* Copyright (C) 2023--2024 Intel Corporation */
  3
  4#ifndef IPU6_PLATFORM_ISYS_CSI2_REG_H
  5#define IPU6_PLATFORM_ISYS_CSI2_REG_H
  6
  7#include <linux/bits.h>
  8
  9#define CSI_REG_BASE			0x220000
 10#define CSI_REG_PORT_BASE(id)		(CSI_REG_BASE + (id) * 0x1000)
 11
 12/* CSI Port Genral Purpose Registers */
 13#define CSI_REG_PORT_GPREG_SRST                 0x0
 14#define CSI_REG_PORT_GPREG_CSI2_SLV_REG_SRST    0x4
 15#define CSI_REG_PORT_GPREG_CSI2_PORT_CONTROL    0x8
 16
 17/*
 18 * Port IRQs mapping events:
 19 * IRQ0 - CSI_FE event
 20 * IRQ1 - CSI_SYNC
 21 * IRQ2 - S2M_SIDS0TO7
 22 * IRQ3 - S2M_SIDS8TO15
 23 */
 24#define CSI_PORT_REG_BASE_IRQ_CSI               0x80
 25#define CSI_PORT_REG_BASE_IRQ_CSI_SYNC          0xA0
 26#define CSI_PORT_REG_BASE_IRQ_S2M_SIDS0TOS7     0xC0
 27#define CSI_PORT_REG_BASE_IRQ_S2M_SIDS8TOS15    0xE0
 28
 29#define CSI_PORT_REG_BASE_IRQ_EDGE_OFFSET	0x0
 30#define CSI_PORT_REG_BASE_IRQ_MASK_OFFSET	0x4
 31#define CSI_PORT_REG_BASE_IRQ_STATUS_OFFSET	0x8
 32#define CSI_PORT_REG_BASE_IRQ_CLEAR_OFFSET	0xc
 33#define CSI_PORT_REG_BASE_IRQ_ENABLE_OFFSET	0x10
 34#define CSI_PORT_REG_BASE_IRQ_LEVEL_NOT_PULSE_OFFSET	0x14
 35
 36#define IPU6SE_CSI_RX_ERROR_IRQ_MASK		GENMASK(18, 0)
 37#define IPU6_CSI_RX_ERROR_IRQ_MASK		GENMASK(19, 0)
 38
 39#define CSI_RX_NUM_ERRORS_IN_IRQ		20
 40#define CSI_RX_NUM_IRQ				32
 41
 42#define IPU_CSI_RX_IRQ_FS_VC(chn)	(1 << ((chn) * 2))
 43#define IPU_CSI_RX_IRQ_FE_VC(chn)	(2 << ((chn) * 2))
 44
 45/* PPI2CSI */
 46#define CSI_REG_PPI2CSI_ENABLE				0x200
 47#define CSI_REG_PPI2CSI_CONFIG_PPI_INTF			0x204
 48#define PPI_INTF_CONFIG_NOF_ENABLED_DLANES_MASK		GENMASK(4, 3)
 49#define CSI_REG_PPI2CSI_CONFIG_CSI_FEATURE		0x208
 50
 51enum CSI_PPI2CSI_CTRL {
 52	CSI_PPI2CSI_DISABLE = 0,
 53	CSI_PPI2CSI_ENABLE = 1,
 54};
 55
 56/* CSI_FE */
 57#define CSI_REG_CSI_FE_ENABLE                   0x280
 58#define CSI_REG_CSI_FE_MODE                     0x284
 59#define CSI_REG_CSI_FE_MUX_CTRL                 0x288
 60#define CSI_REG_CSI_FE_SYNC_CNTR_SEL            0x290
 61
 62enum CSI_FE_ENABLE_TYPE {
 63	CSI_FE_DISABLE = 0,
 64	CSI_FE_ENABLE = 1,
 65};
 66
 67enum CSI_FE_MODE_TYPE {
 68	CSI_FE_DPHY_MODE = 0,
 69	CSI_FE_CPHY_MODE = 1,
 70};
 71
 72enum CSI_FE_INPUT_SELECTOR {
 73	CSI_SENSOR_INPUT = 0,
 74	CSI_MIPIGEN_INPUT = 1,
 75};
 76
 77enum CSI_FE_SYNC_CNTR_SEL_TYPE {
 78	CSI_CNTR_SENSOR_LINE_ID = BIT(0),
 79	CSI_CNTR_INT_LINE_PKT_ID = ~CSI_CNTR_SENSOR_LINE_ID,
 80	CSI_CNTR_SENSOR_FRAME_ID = BIT(1),
 81	CSI_CNTR_INT_FRAME_PKT_ID = ~CSI_CNTR_SENSOR_FRAME_ID,
 82};
 83
 84/* CSI HUB General Purpose Registers */
 85#define CSI_REG_HUB_GPREG_SRST			(CSI_REG_BASE + 0x18000)
 86#define CSI_REG_HUB_GPREG_SLV_REG_SRST		(CSI_REG_BASE + 0x18004)
 87
 88#define CSI_REG_HUB_DRV_ACCESS_PORT(id)	(CSI_REG_BASE + 0x18018 + (id) * 4)
 89#define CSI_REG_HUB_FW_ACCESS_PORT_OFS		0x17000
 90#define CSI_REG_HUB_FW_ACCESS_PORT_V6OFS	0x16000
 91#define CSI_REG_HUB_FW_ACCESS_PORT(ofs, id)	\
 92					(CSI_REG_BASE + (ofs) + (id) * 4)
 93
 94enum CSI_PORT_CLK_GATING_SWITCH {
 95	CSI_PORT_CLK_GATING_OFF = 0,
 96	CSI_PORT_CLK_GATING_ON = 1,
 97};
 98
 99#define CSI_REG_BASE_HUB_IRQ                        0x18200
100
101#define IPU6_REG_ISYS_CSI_TOP_CTRL0_IRQ_EDGE			0x238200
102#define IPU6_REG_ISYS_CSI_TOP_CTRL0_IRQ_MASK			0x238204
103#define IPU6_REG_ISYS_CSI_TOP_CTRL0_IRQ_STATUS			0x238208
104#define IPU6_REG_ISYS_CSI_TOP_CTRL0_IRQ_CLEAR			0x23820c
105#define IPU6_REG_ISYS_CSI_TOP_CTRL0_IRQ_ENABLE			0x238210
106#define IPU6_REG_ISYS_CSI_TOP_CTRL0_IRQ_LEVEL_NOT_PULSE		0x238214
107
108#define IPU6_REG_ISYS_CSI_TOP_CTRL1_IRQ_EDGE			0x238220
109#define IPU6_REG_ISYS_CSI_TOP_CTRL1_IRQ_MASK			0x238224
110#define IPU6_REG_ISYS_CSI_TOP_CTRL1_IRQ_STATUS			0x238228
111#define IPU6_REG_ISYS_CSI_TOP_CTRL1_IRQ_CLEAR			0x23822c
112#define IPU6_REG_ISYS_CSI_TOP_CTRL1_IRQ_ENABLE			0x238230
113#define IPU6_REG_ISYS_CSI_TOP_CTRL1_IRQ_LEVEL_NOT_PULSE		0x238234
114
115/* MTL IPU6V6 irq ctrl0 & ctrl1 */
116#define IPU6V6_REG_ISYS_CSI_TOP_CTRL0_IRQ_EDGE			0x238700
117#define IPU6V6_REG_ISYS_CSI_TOP_CTRL0_IRQ_MASK			0x238704
118#define IPU6V6_REG_ISYS_CSI_TOP_CTRL0_IRQ_STATUS		0x238708
119#define IPU6V6_REG_ISYS_CSI_TOP_CTRL0_IRQ_CLEAR			0x23870c
120#define IPU6V6_REG_ISYS_CSI_TOP_CTRL0_IRQ_ENABLE		0x238710
121#define IPU6V6_REG_ISYS_CSI_TOP_CTRL0_IRQ_LEVEL_NOT_PULSE	0x238714
122
123#define IPU6V6_REG_ISYS_CSI_TOP_CTRL1_IRQ_EDGE			0x238720
124#define IPU6V6_REG_ISYS_CSI_TOP_CTRL1_IRQ_MASK			0x238724
125#define IPU6V6_REG_ISYS_CSI_TOP_CTRL1_IRQ_STATUS		0x238728
126#define IPU6V6_REG_ISYS_CSI_TOP_CTRL1_IRQ_CLEAR			0x23872c
127#define IPU6V6_REG_ISYS_CSI_TOP_CTRL1_IRQ_ENABLE		0x238730
128#define IPU6V6_REG_ISYS_CSI_TOP_CTRL1_IRQ_LEVEL_NOT_PULSE	0x238734
129
130/*
131 * 3:0 CSI_PORT.irq_out[3:0] CSI_PORT_CTRL0 IRQ outputs (4bits)
132 * [0] CSI_PORT.IRQ_CTRL0_csi
133 * [1] CSI_PORT.IRQ_CTRL1_csi_sync
134 * [2] CSI_PORT.IRQ_CTRL2_s2m_sids0to7
135 * [3] CSI_PORT.IRQ_CTRL3_s2m_sids8to15
136 */
137#define IPU6_ISYS_UNISPART_IRQ_CSI2(port)		\
138				   (0x3 << ((port) * IPU6_CSI_IRQ_NUM_PER_PIPE))
139
140/*
141 * ipu6se support 2 front ends, 2 port per front end, 4 ports 0..3
142 * sip0 - 0, 1
143 * sip1 - 2, 3
144 * 0 and 2 support 4 data lanes, 1 and 3 support 2 data lanes
145 * all offset are base from isys base address
146 */
147
148#define CSI2_HUB_GPREG_SIP_SRST(sip)			(0x238038 + (sip) * 4)
149#define CSI2_HUB_GPREG_SIP_FB_PORT_CFG(sip)		(0x238050 + (sip) * 4)
150
151#define CSI2_HUB_GPREG_DPHY_TIMER_INCR			0x238040
152#define CSI2_HUB_GPREG_HPLL_FREQ			0x238044
153#define CSI2_HUB_GPREG_IS_CLK_RATIO			0x238048
154#define CSI2_HUB_GPREG_HPLL_FREQ_ISCLK_RATE_OVERRIDE	0x23804c
155#define CSI2_HUB_GPREG_PORT_CLKGATING_DISABLE		0x238058
156#define CSI2_HUB_GPREG_SIP0_CSI_RX_A_CONTROL		0x23805c
157#define CSI2_HUB_GPREG_SIP0_CSI_RX_B_CONTROL		0x238088
158#define CSI2_HUB_GPREG_SIP1_CSI_RX_A_CONTROL		0x2380a4
159#define CSI2_HUB_GPREG_SIP1_CSI_RX_B_CONTROL		0x2380d0
160
161#define CSI2_SIP_TOP_CSI_RX_BASE(sip)		(0x23805c + (sip) * 0x48)
162#define CSI2_SIP_TOP_CSI_RX_PORT_BASE_0(port)	(0x23805c + ((port) / 2) * 0x48)
163#define CSI2_SIP_TOP_CSI_RX_PORT_BASE_1(port)	(0x238088 + ((port) / 2) * 0x48)
164
165/* offset from port base */
166#define CSI2_SIP_TOP_CSI_RX_PORT_CONTROL		0x0
167#define CSI2_SIP_TOP_CSI_RX_DLY_CNT_TERMEN_CLANE	0x4
168#define CSI2_SIP_TOP_CSI_RX_DLY_CNT_SETTLE_CLANE	0x8
169#define CSI2_SIP_TOP_CSI_RX_DLY_CNT_TERMEN_DLANE(lane)	(0xc + (lane) * 8)
170#define CSI2_SIP_TOP_CSI_RX_DLY_CNT_SETTLE_DLANE(lane)	(0x10 + (lane) * 8)
171
172#endif /* IPU6_ISYS_CSI2_REG_H */