ipu6-platform-buttress-regs.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/* Copyright (C) 2023--2024 Intel Corporation */
  3
  4#ifndef IPU6_PLATFORM_BUTTRESS_REGS_H
  5#define IPU6_PLATFORM_BUTTRESS_REGS_H
  6
  7#include <linux/bits.h>
  8
  9/* IS_WORKPOINT_REQ */
 10#define IPU6_BUTTRESS_REG_IS_FREQ_CTL		0x34
 11/* PS_WORKPOINT_REQ */
 12#define IPU6_BUTTRESS_REG_PS_FREQ_CTL		0x38
 13
 14/* should be tuned for real silicon */
 15#define IPU6_IS_FREQ_CTL_DEFAULT_RATIO		0x08
 16#define IPU6SE_IS_FREQ_CTL_DEFAULT_RATIO	0x0a
 17#define IPU6_PS_FREQ_CTL_DEFAULT_RATIO		0x0d
 18
 19#define IPU6_IS_FREQ_CTL_DEFAULT_QOS_FLOOR_RATIO	0x10
 20#define IPU6_PS_FREQ_CTL_DEFAULT_QOS_FLOOR_RATIO	0x0708
 21
 22#define IPU6_BUTTRESS_PWR_STATE_IS_PWR_SHIFT	3
 23#define IPU6_BUTTRESS_PWR_STATE_IS_PWR_MASK	GENMASK(4, 3)
 24
 25#define IPU6_BUTTRESS_PWR_STATE_PS_PWR_SHIFT	6
 26#define IPU6_BUTTRESS_PWR_STATE_PS_PWR_MASK	GENMASK(7, 6)
 27
 28#define IPU6_BUTTRESS_PWR_STATE_DN_DONE		0x0
 29#define IPU6_BUTTRESS_PWR_STATE_UP_PROCESS	0x1
 30#define IPU6_BUTTRESS_PWR_STATE_DN_PROCESS	0x2
 31#define IPU6_BUTTRESS_PWR_STATE_UP_DONE		0x3
 32
 33#define IPU6_BUTTRESS_REG_FPGA_SUPPORT_0	0x270
 34#define IPU6_BUTTRESS_REG_FPGA_SUPPORT_1	0x274
 35#define IPU6_BUTTRESS_REG_FPGA_SUPPORT_2	0x278
 36#define IPU6_BUTTRESS_REG_FPGA_SUPPORT_3	0x27c
 37#define IPU6_BUTTRESS_REG_FPGA_SUPPORT_4	0x280
 38#define IPU6_BUTTRESS_REG_FPGA_SUPPORT_5	0x284
 39#define IPU6_BUTTRESS_REG_FPGA_SUPPORT_6	0x288
 40#define IPU6_BUTTRESS_REG_FPGA_SUPPORT_7	0x28c
 41
 42#define BUTTRESS_REG_WDT			0x8
 43#define BUTTRESS_REG_BTRS_CTRL			0xc
 44#define BUTTRESS_REG_BTRS_CTRL_STALL_MODE_VC0	BIT(0)
 45#define BUTTRESS_REG_BTRS_CTRL_STALL_MODE_VC1	BIT(1)
 46#define BUTTRESS_REG_BTRS_CTRL_REF_CLK_IND	GENMASK(9, 8)
 47
 48#define BUTTRESS_REG_FW_RESET_CTL	0x30
 49#define BUTTRESS_FW_RESET_CTL_START	BIT(0)
 50#define BUTTRESS_FW_RESET_CTL_DONE	BIT(1)
 51
 52#define BUTTRESS_REG_IS_FREQ_CTL	0x34
 53#define BUTTRESS_REG_PS_FREQ_CTL	0x38
 54
 55#define BUTTRESS_FREQ_CTL_START		BIT(31)
 56#define BUTTRESS_FREQ_CTL_ICCMAX_LEVEL		GENMASK(19, 16)
 57#define BUTTRESS_FREQ_CTL_QOS_FLOOR_MASK	GENMASK(15, 8)
 58#define BUTTRESS_FREQ_CTL_RATIO_MASK	GENMASK(7, 0)
 59
 60#define BUTTRESS_REG_PWR_STATE	0x5c
 61
 62#define BUTTRESS_PWR_STATE_RESET		0x0
 63#define BUTTRESS_PWR_STATE_PWR_ON_DONE		0x1
 64#define BUTTRESS_PWR_STATE_PWR_RDY		0x3
 65#define BUTTRESS_PWR_STATE_PWR_IDLE		0x4
 66
 67#define BUTTRESS_PWR_STATE_HH_STATUS_MASK	GENMASK(12, 11)
 68
 69enum {
 70	BUTTRESS_PWR_STATE_HH_STATE_IDLE,
 71	BUTTRESS_PWR_STATE_HH_STATE_IN_PRGS,
 72	BUTTRESS_PWR_STATE_HH_STATE_DONE,
 73	BUTTRESS_PWR_STATE_HH_STATE_ERR,
 74};
 75
 76#define BUTTRESS_PWR_STATE_IS_PWR_FSM_MASK	GENMASK(23, 19)
 77
 78#define BUTTRESS_PWR_STATE_IS_PWR_FSM_IDLE			0x0
 79#define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_PLL_CMP		0x1
 80#define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_CLKACK		0x2
 81#define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_PG_ACK		0x3
 82#define BUTTRESS_PWR_STATE_IS_PWR_FSM_RST_ASSRT_CYCLES		0x4
 83#define BUTTRESS_PWR_STATE_IS_PWR_FSM_STOP_CLK_CYCLES1		0x5
 84#define BUTTRESS_PWR_STATE_IS_PWR_FSM_STOP_CLK_CYCLES2		0x6
 85#define BUTTRESS_PWR_STATE_IS_PWR_FSM_RST_DEASSRT_CYCLES	0x7
 86#define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_FUSE_WR_CMP	0x8
 87#define BUTTRESS_PWR_STATE_IS_PWR_FSM_BRK_POINT			0x9
 88#define BUTTRESS_PWR_STATE_IS_PWR_FSM_IS_RDY			0xa
 89#define BUTTRESS_PWR_STATE_IS_PWR_FSM_HALT_HALTED		0xb
 90#define BUTTRESS_PWR_STATE_IS_PWR_FSM_RST_DURATION_CNT3		0xc
 91#define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_CLKACK_PD		0xd
 92#define BUTTRESS_PWR_STATE_IS_PWR_FSM_PD_BRK_POINT		0xe
 93#define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_PD_PG_ACK0		0xf
 94
 95#define BUTTRESS_PWR_STATE_PS_PWR_FSM_MASK	GENMASK(28, 24)
 96
 97#define BUTTRESS_PWR_STATE_PS_PWR_FSM_IDLE			0x0
 98#define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_PU_PLL_IP_RDY	0x1
 99#define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_RO_PRE_CNT_EXH	0x2
100#define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_PU_VGI_PWRGOOD	0x3
101#define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_RO_POST_CNT_EXH	0x4
102#define BUTTRESS_PWR_STATE_PS_PWR_FSM_WR_PLL_RATIO		0x5
103#define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_PU_PLL_CMP		0x6
104#define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_PU_CLKACK		0x7
105#define BUTTRESS_PWR_STATE_PS_PWR_FSM_RST_ASSRT_CYCLES		0x8
106#define BUTTRESS_PWR_STATE_PS_PWR_FSM_STOP_CLK_CYCLES1		0x9
107#define BUTTRESS_PWR_STATE_PS_PWR_FSM_STOP_CLK_CYCLES2		0xa
108#define BUTTRESS_PWR_STATE_PS_PWR_FSM_RST_DEASSRT_CYCLES	0xb
109#define BUTTRESS_PWR_STATE_PS_PWR_FSM_PU_BRK_PNT		0xc
110#define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_FUSE_ACCPT		0xd
111#define BUTTRESS_PWR_STATE_PS_PWR_FSM_PS_PWR_UP			0xf
112#define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_4_HALTED		0x10
113#define BUTTRESS_PWR_STATE_PS_PWR_FSM_RESET_CNT3		0x11
114#define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_PD_CLKACK		0x12
115#define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_PD_OFF_IND		0x13
116#define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_DVFS_PH4		0x14
117#define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_DVFS_PLL_CMP		0x15
118#define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_DVFS_CLKACK		0x16
119
120#define BUTTRESS_REG_SECURITY_CTL	0x300
121#define BUTTRESS_REG_SKU		0x314
122#define BUTTRESS_REG_SECURITY_TOUCH	0x318
123#define BUTTRESS_REG_CAMERA_MASK	0x84
124
125#define BUTTRESS_SECURITY_CTL_FW_SECURE_MODE	BIT(16)
126#define BUTTRESS_SECURITY_CTL_FW_SETUP_MASK	GENMASK(4, 0)
127
128#define BUTTRESS_SECURITY_CTL_FW_SETUP_DONE		BIT(0)
129#define BUTTRESS_SECURITY_CTL_AUTH_DONE			BIT(1)
130#define BUTTRESS_SECURITY_CTL_AUTH_FAILED		BIT(3)
131
132#define BUTTRESS_REG_FW_SOURCE_BASE_LO	0x78
133#define BUTTRESS_REG_FW_SOURCE_BASE_HI	0x7C
134#define BUTTRESS_REG_FW_SOURCE_SIZE	0x80
135
136#define BUTTRESS_REG_ISR_STATUS		0x90
137#define BUTTRESS_REG_ISR_ENABLED_STATUS	0x94
138#define BUTTRESS_REG_ISR_ENABLE		0x98
139#define BUTTRESS_REG_ISR_CLEAR		0x9C
140
141#define BUTTRESS_ISR_IS_IRQ			BIT(0)
142#define BUTTRESS_ISR_PS_IRQ			BIT(1)
143#define BUTTRESS_ISR_IPC_EXEC_DONE_BY_CSE	BIT(2)
144#define BUTTRESS_ISR_IPC_EXEC_DONE_BY_ISH	BIT(3)
145#define BUTTRESS_ISR_IPC_FROM_CSE_IS_WAITING	BIT(4)
146#define BUTTRESS_ISR_IPC_FROM_ISH_IS_WAITING	BIT(5)
147#define BUTTRESS_ISR_CSE_CSR_SET		BIT(6)
148#define BUTTRESS_ISR_ISH_CSR_SET		BIT(7)
149#define BUTTRESS_ISR_SPURIOUS_CMP		BIT(8)
150#define BUTTRESS_ISR_WATCHDOG_EXPIRED		BIT(9)
151#define BUTTRESS_ISR_PUNIT_2_IUNIT_IRQ		BIT(10)
152#define BUTTRESS_ISR_SAI_VIOLATION		BIT(11)
153#define BUTTRESS_ISR_HW_ASSERTION		BIT(12)
154#define BUTTRESS_ISR_IS_CORRECTABLE_MEM_ERR	BIT(13)
155#define BUTTRESS_ISR_IS_FATAL_MEM_ERR		BIT(14)
156#define BUTTRESS_ISR_IS_NON_FATAL_MEM_ERR	BIT(15)
157#define BUTTRESS_ISR_PS_CORRECTABLE_MEM_ERR	BIT(16)
158#define BUTTRESS_ISR_PS_FATAL_MEM_ERR		BIT(17)
159#define BUTTRESS_ISR_PS_NON_FATAL_MEM_ERR	BIT(18)
160#define BUTTRESS_ISR_PS_FAST_THROTTLE		BIT(19)
161#define BUTTRESS_ISR_UFI_ERROR			BIT(20)
162
163#define BUTTRESS_REG_IU2CSEDB0	0x100
164
165#define BUTTRESS_IU2CSEDB0_BUSY		BIT(31)
166#define BUTTRESS_IU2CSEDB0_IPC_CLIENT_ID_VAL	2
167
168#define BUTTRESS_REG_IU2CSEDATA0	0x104
169
170#define BUTTRESS_IU2CSEDATA0_IPC_BOOT_LOAD		1
171#define BUTTRESS_IU2CSEDATA0_IPC_AUTH_RUN		2
172#define BUTTRESS_IU2CSEDATA0_IPC_AUTH_REPLACE		3
173#define BUTTRESS_IU2CSEDATA0_IPC_UPDATE_SECURE_TOUCH	16
174
175#define BUTTRESS_CSE2IUDATA0_IPC_BOOT_LOAD_DONE			BIT(0)
176#define BUTTRESS_CSE2IUDATA0_IPC_AUTH_RUN_DONE			BIT(1)
177#define BUTTRESS_CSE2IUDATA0_IPC_AUTH_REPLACE_DONE		BIT(2)
178#define BUTTRESS_CSE2IUDATA0_IPC_UPDATE_SECURE_TOUCH_DONE	BIT(4)
179
180#define BUTTRESS_REG_IU2CSECSR		0x108
181
182#define BUTTRESS_IU2CSECSR_IPC_PEER_COMP_ACTIONS_RST_PHASE1		BIT(0)
183#define BUTTRESS_IU2CSECSR_IPC_PEER_COMP_ACTIONS_RST_PHASE2		BIT(1)
184#define BUTTRESS_IU2CSECSR_IPC_PEER_QUERIED_IP_COMP_ACTIONS_RST_PHASE	BIT(2)
185#define BUTTRESS_IU2CSECSR_IPC_PEER_ASSERTED_REG_VALID_REQ		BIT(3)
186#define BUTTRESS_IU2CSECSR_IPC_PEER_ACKED_REG_VALID			BIT(4)
187#define BUTTRESS_IU2CSECSR_IPC_PEER_DEASSERTED_REG_VALID_REQ		BIT(5)
188
189#define BUTTRESS_REG_CSE2IUDB0		0x304
190#define BUTTRESS_REG_CSE2IUCSR		0x30C
191#define BUTTRESS_REG_CSE2IUDATA0	0x308
192
193/* 0x20 == NACK, 0xf == unknown command */
194#define BUTTRESS_CSE2IUDATA0_IPC_NACK      0xf20
195#define BUTTRESS_CSE2IUDATA0_IPC_NACK_MASK GENMASK(15, 0)
196
197#define BUTTRESS_REG_ISH2IUCSR		0x50
198#define BUTTRESS_REG_ISH2IUDB0		0x54
199#define BUTTRESS_REG_ISH2IUDATA0	0x58
200
201#define BUTTRESS_REG_IU2ISHDB0		0x10C
202#define BUTTRESS_REG_IU2ISHDATA0	0x110
203#define BUTTRESS_REG_IU2ISHDATA1	0x114
204#define BUTTRESS_REG_IU2ISHCSR		0x118
205
206#define BUTTRESS_REG_FABRIC_CMD		0x88
207
208#define BUTTRESS_FABRIC_CMD_START_TSC_SYNC	BIT(0)
209#define BUTTRESS_FABRIC_CMD_IS_DRAIN		BIT(4)
210
211#define BUTTRESS_REG_TSW_CTL		0x120
212#define BUTTRESS_TSW_CTL_SOFT_RESET	BIT(8)
213
214#define BUTTRESS_REG_TSC_LO	0x164
215#define BUTTRESS_REG_TSC_HI	0x168
216
217#define BUTTRESS_IRQS		(BUTTRESS_ISR_IPC_FROM_CSE_IS_WAITING | \
218				 BUTTRESS_ISR_IPC_EXEC_DONE_BY_CSE |    \
219				 BUTTRESS_ISR_IS_IRQ | BUTTRESS_ISR_PS_IRQ)
220
221#define BUTTRESS_EVENT		 (BUTTRESS_ISR_IPC_FROM_CSE_IS_WAITING | \
222				  BUTTRESS_ISR_IPC_EXEC_DONE_BY_CSE |    \
223				  BUTTRESS_ISR_SAI_VIOLATION)
224#endif /* IPU6_PLATFORM_BUTTRESS_REGS_H */