dt3155.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/***************************************************************************
  3 *   Copyright (C) 2006-2010 by Marin Mitov                                *
  4 *   mitov@issp.bas.bg                                                     *
  5 *                                                                         *
  6 *                                                                         *
  7 ***************************************************************************/
  8
  9#include <linux/module.h>
 10#include <linux/stringify.h>
 11#include <linux/delay.h>
 12#include <linux/kthread.h>
 13#include <linux/slab.h>
 14#include <media/v4l2-dev.h>
 15#include <media/v4l2-ioctl.h>
 16#include <media/v4l2-common.h>
 17#include <media/videobuf2-dma-contig.h>
 18
 19#include "dt3155.h"
 20
 21#define DT3155_DEVICE_ID 0x1223
 22
 23/**
 24 * read_i2c_reg - reads an internal i2c register
 25 *
 26 * @addr:	dt3155 mmio base address
 27 * @index:	index (internal address) of register to read
 28 * @data:	pointer to byte the read data will be placed in
 29 *
 30 * returns:	zero on success or error code
 31 *
 32 * This function starts reading the specified (by index) register
 33 * and busy waits for the process to finish. The result is placed
 34 * in a byte pointed by data.
 35 */
 36static int read_i2c_reg(void __iomem *addr, u8 index, u8 *data)
 37{
 38	u32 tmp = index;
 39
 40	iowrite32((tmp << 17) | IIC_READ, addr + IIC_CSR2);
 41	udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */
 42	if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
 43		return -EIO; /* error: NEW_CYCLE not cleared */
 44	tmp = ioread32(addr + IIC_CSR1);
 45	if (tmp & DIRECT_ABORT) {
 46		/* reset DIRECT_ABORT bit */
 47		iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
 48		return -EIO; /* error: DIRECT_ABORT set */
 49	}
 50	*data = tmp >> 24;
 51	return 0;
 52}
 53
 54/**
 55 * write_i2c_reg - writes to an internal i2c register
 56 *
 57 * @addr:	dt3155 mmio base address
 58 * @index:	index (internal address) of register to read
 59 * @data:	data to be written
 60 *
 61 * returns:	zero on success or error code
 62 *
 63 * This function starts writing the specified (by index) register
 64 * and busy waits for the process to finish.
 65 */
 66static int write_i2c_reg(void __iomem *addr, u8 index, u8 data)
 67{
 68	u32 tmp = index;
 69
 70	iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2);
 71	udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
 72	if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
 73		return -EIO; /* error: NEW_CYCLE not cleared */
 74	if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
 75		/* reset DIRECT_ABORT bit */
 76		iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
 77		return -EIO; /* error: DIRECT_ABORT set */
 78	}
 79	return 0;
 80}
 81
 82/**
 83 * write_i2c_reg_nowait - writes to an internal i2c register
 84 *
 85 * @addr:	dt3155 mmio base address
 86 * @index:	index (internal address) of register to read
 87 * @data:	data to be written
 88 *
 89 * This function starts writing the specified (by index) register
 90 * and then returns.
 91 */
 92static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data)
 93{
 94	u32 tmp = index;
 95
 96	iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2);
 97}
 98
 99/**
100 * wait_i2c_reg - waits the read/write to finish
101 *
102 * @addr:	dt3155 mmio base address
103 *
104 * returns:	zero on success or error code
105 *
106 * This function waits reading/writing to finish.
107 */
108static int wait_i2c_reg(void __iomem *addr)
109{
110	if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
111		udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
112	if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
113		return -EIO; /* error: NEW_CYCLE not cleared */
114	if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
115		/* reset DIRECT_ABORT bit */
116		iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
117		return -EIO; /* error: DIRECT_ABORT set */
118	}
119	return 0;
120}
121
122static int
123dt3155_queue_setup(struct vb2_queue *vq,
124		unsigned int *nbuffers, unsigned int *num_planes,
125		unsigned int sizes[], struct device *alloc_devs[])
126
127{
128	struct dt3155_priv *pd = vb2_get_drv_priv(vq);
129	unsigned size = pd->width * pd->height;
130
131	if (*num_planes)
132		return sizes[0] < size ? -EINVAL : 0;
133	*num_planes = 1;
134	sizes[0] = size;
135	return 0;
136}
137
138static int dt3155_buf_prepare(struct vb2_buffer *vb)
139{
140	struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
141
142	vb2_set_plane_payload(vb, 0, pd->width * pd->height);
143	return 0;
144}
145
146static int dt3155_start_streaming(struct vb2_queue *q, unsigned count)
147{
148	struct dt3155_priv *pd = vb2_get_drv_priv(q);
149	struct vb2_buffer *vb = &pd->curr_buf->vb2_buf;
150	dma_addr_t dma_addr;
151
152	pd->sequence = 0;
153	dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
154	iowrite32(dma_addr, pd->regs + EVEN_DMA_START);
155	iowrite32(dma_addr + pd->width, pd->regs + ODD_DMA_START);
156	iowrite32(pd->width, pd->regs + EVEN_DMA_STRIDE);
157	iowrite32(pd->width, pd->regs + ODD_DMA_STRIDE);
158	/* enable interrupts, clear all irq flags */
159	iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
160			FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
161	iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
162		  FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD,
163							pd->regs + CSR1);
164	wait_i2c_reg(pd->regs);
165	write_i2c_reg(pd->regs, CONFIG, pd->config);
166	write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);
167	write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);
168
169	/*  start the board  */
170	write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);
171	return 0;
172}
173
174static void dt3155_stop_streaming(struct vb2_queue *q)
175{
176	struct dt3155_priv *pd = vb2_get_drv_priv(q);
177	struct vb2_buffer *vb;
178
179	spin_lock_irq(&pd->lock);
180	/* stop the board */
181	write_i2c_reg_nowait(pd->regs, CSR2, pd->csr2);
182	iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
183		  FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
184	/* disable interrupts, clear all irq flags */
185	iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
186	spin_unlock_irq(&pd->lock);
187
188	/*
189	 * It is not clear whether the DMA stops at once or whether it
190	 * will finish the current frame or field first. To be on the
191	 * safe side we wait a bit.
192	 */
193	msleep(45);
194
195	spin_lock_irq(&pd->lock);
196	if (pd->curr_buf) {
197		vb2_buffer_done(&pd->curr_buf->vb2_buf, VB2_BUF_STATE_ERROR);
198		pd->curr_buf = NULL;
199	}
200
201	while (!list_empty(&pd->dmaq)) {
202		vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry);
203		list_del(&vb->done_entry);
204		vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
205	}
206	spin_unlock_irq(&pd->lock);
207}
208
209static void dt3155_buf_queue(struct vb2_buffer *vb)
210{
211	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
212	struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
213
214	/*  pd->vidq.streaming = 1 when dt3155_buf_queue() is invoked  */
215	spin_lock_irq(&pd->lock);
216	if (pd->curr_buf)
217		list_add_tail(&vb->done_entry, &pd->dmaq);
218	else
219		pd->curr_buf = vbuf;
220	spin_unlock_irq(&pd->lock);
221}
222
223static const struct vb2_ops q_ops = {
224	.queue_setup = dt3155_queue_setup,
225	.buf_prepare = dt3155_buf_prepare,
226	.start_streaming = dt3155_start_streaming,
227	.stop_streaming = dt3155_stop_streaming,
228	.buf_queue = dt3155_buf_queue,
229};
230
231static irqreturn_t dt3155_irq_handler_even(int irq, void *dev_id)
232{
233	struct dt3155_priv *ipd = dev_id;
234	struct vb2_buffer *ivb;
235	dma_addr_t dma_addr;
236	u32 tmp;
237
238	tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD);
239	if (!tmp)
240		return IRQ_NONE;  /* not our irq */
241	if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) {
242		iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START,
243							ipd->regs + INT_CSR);
244		return IRQ_HANDLED; /* start of field irq */
245	}
246	tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);
247	if (tmp) {
248		iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
249						FLD_DN_ODD | FLD_DN_EVEN |
250						CAP_CONT_EVEN | CAP_CONT_ODD,
251							ipd->regs + CSR1);
252	}
253
254	spin_lock(&ipd->lock);
255	if (ipd->curr_buf && !list_empty(&ipd->dmaq)) {
256		ipd->curr_buf->vb2_buf.timestamp = ktime_get_ns();
257		ipd->curr_buf->sequence = ipd->sequence++;
258		ipd->curr_buf->field = V4L2_FIELD_NONE;
259		vb2_buffer_done(&ipd->curr_buf->vb2_buf, VB2_BUF_STATE_DONE);
260
261		ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry);
262		list_del(&ivb->done_entry);
263		ipd->curr_buf = to_vb2_v4l2_buffer(ivb);
264		dma_addr = vb2_dma_contig_plane_dma_addr(ivb, 0);
265		iowrite32(dma_addr, ipd->regs + EVEN_DMA_START);
266		iowrite32(dma_addr + ipd->width, ipd->regs + ODD_DMA_START);
267		iowrite32(ipd->width, ipd->regs + EVEN_DMA_STRIDE);
268		iowrite32(ipd->width, ipd->regs + ODD_DMA_STRIDE);
269	}
270
271	/* enable interrupts, clear all irq flags */
272	iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
273			FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
274	spin_unlock(&ipd->lock);
275	return IRQ_HANDLED;
276}
277
278static const struct v4l2_file_operations dt3155_fops = {
279	.owner = THIS_MODULE,
280	.open = v4l2_fh_open,
281	.release = vb2_fop_release,
282	.unlocked_ioctl = video_ioctl2,
283	.read = vb2_fop_read,
284	.mmap = vb2_fop_mmap,
285	.poll = vb2_fop_poll
286};
287
288static int dt3155_querycap(struct file *filp, void *p,
289			   struct v4l2_capability *cap)
290{
291	strscpy(cap->driver, DT3155_NAME, sizeof(cap->driver));
292	strscpy(cap->card, DT3155_NAME " frame grabber", sizeof(cap->card));
293	return 0;
294}
295
296static int dt3155_enum_fmt_vid_cap(struct file *filp,
297				   void *p, struct v4l2_fmtdesc *f)
298{
299	if (f->index)
300		return -EINVAL;
301	f->pixelformat = V4L2_PIX_FMT_GREY;
302	return 0;
303}
304
305static int dt3155_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
306{
307	struct dt3155_priv *pd = video_drvdata(filp);
308
309	f->fmt.pix.width = pd->width;
310	f->fmt.pix.height = pd->height;
311	f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY;
312	f->fmt.pix.field = V4L2_FIELD_NONE;
313	f->fmt.pix.bytesperline = f->fmt.pix.width;
314	f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height;
315	f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
316	return 0;
317}
318
319static int dt3155_g_std(struct file *filp, void *p, v4l2_std_id *norm)
320{
321	struct dt3155_priv *pd = video_drvdata(filp);
322
323	*norm = pd->std;
324	return 0;
325}
326
327static int dt3155_s_std(struct file *filp, void *p, v4l2_std_id norm)
328{
329	struct dt3155_priv *pd = video_drvdata(filp);
330
331	if (pd->std == norm)
332		return 0;
333	if (vb2_is_busy(&pd->vidq))
334		return -EBUSY;
335	pd->std = norm;
336	if (pd->std & V4L2_STD_525_60) {
337		pd->csr2 = VT_60HZ;
338		pd->width = 640;
339		pd->height = 480;
340	} else {
341		pd->csr2 = VT_50HZ;
342		pd->width = 768;
343		pd->height = 576;
344	}
345	return 0;
346}
347
348static int dt3155_enum_input(struct file *filp, void *p,
349			     struct v4l2_input *input)
350{
351	if (input->index > 3)
352		return -EINVAL;
353	if (input->index)
354		snprintf(input->name, sizeof(input->name), "VID%d",
355			 input->index);
356	else
357		strscpy(input->name, "J2/VID0", sizeof(input->name));
358	input->type = V4L2_INPUT_TYPE_CAMERA;
359	input->std = V4L2_STD_ALL;
360	input->status = 0;
361	return 0;
362}
363
364static int dt3155_g_input(struct file *filp, void *p, unsigned int *i)
365{
366	struct dt3155_priv *pd = video_drvdata(filp);
367
368	*i = pd->input;
369	return 0;
370}
371
372static int dt3155_s_input(struct file *filp, void *p, unsigned int i)
373{
374	struct dt3155_priv *pd = video_drvdata(filp);
375
376	if (i > 3)
377		return -EINVAL;
378	pd->input = i;
379	write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
380	write_i2c_reg(pd->regs, AD_CMD, (i << 6) | (i << 4) | SYNC_LVL_3);
381	return 0;
382}
383
384static const struct v4l2_ioctl_ops dt3155_ioctl_ops = {
385	.vidioc_querycap = dt3155_querycap,
386	.vidioc_enum_fmt_vid_cap = dt3155_enum_fmt_vid_cap,
387	.vidioc_try_fmt_vid_cap = dt3155_fmt_vid_cap,
388	.vidioc_g_fmt_vid_cap = dt3155_fmt_vid_cap,
389	.vidioc_s_fmt_vid_cap = dt3155_fmt_vid_cap,
390	.vidioc_reqbufs = vb2_ioctl_reqbufs,
391	.vidioc_create_bufs = vb2_ioctl_create_bufs,
392	.vidioc_querybuf = vb2_ioctl_querybuf,
393	.vidioc_expbuf = vb2_ioctl_expbuf,
394	.vidioc_qbuf = vb2_ioctl_qbuf,
395	.vidioc_dqbuf = vb2_ioctl_dqbuf,
396	.vidioc_streamon = vb2_ioctl_streamon,
397	.vidioc_streamoff = vb2_ioctl_streamoff,
398	.vidioc_g_std = dt3155_g_std,
399	.vidioc_s_std = dt3155_s_std,
400	.vidioc_enum_input = dt3155_enum_input,
401	.vidioc_g_input = dt3155_g_input,
402	.vidioc_s_input = dt3155_s_input,
403};
404
405static int dt3155_init_board(struct dt3155_priv *pd)
406{
407	struct pci_dev *pdev = pd->pdev;
408	int i;
409	u8 tmp = 0;
410
411	pci_set_master(pdev); /* dt3155 needs it */
412
413	/*  resetting the adapter  */
414	iowrite32(ADDR_ERR_ODD | ADDR_ERR_EVEN | FLD_CRPT_ODD | FLD_CRPT_EVEN |
415			FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
416	msleep(20);
417
418	/*  initializing adapter registers  */
419	iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
420	iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT);
421	iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT);
422	iowrite32(0x00000020, pd->regs + FIFO_TRIGGER);
423	iowrite32(0x00000103, pd->regs + XFER_MODE);
424	iowrite32(0, pd->regs + RETRY_WAIT_CNT);
425	iowrite32(0, pd->regs + INT_CSR);
426	iowrite32(1, pd->regs + EVEN_FLD_MASK);
427	iowrite32(1, pd->regs + ODD_FLD_MASK);
428	iowrite32(0, pd->regs + MASK_LENGTH);
429	iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT);
430	iowrite32(0x01010101, pd->regs + IIC_CLK_DUR);
431
432	/* verifying that we have a DT3155 board (not just a SAA7116 chip) */
433	read_i2c_reg(pd->regs, DT_ID, &tmp);
434	if (tmp != DT3155_ID)
435		return -ENODEV;
436
437	/* initialize AD LUT */
438	write_i2c_reg(pd->regs, AD_ADDR, 0);
439	for (i = 0; i < 256; i++)
440		write_i2c_reg(pd->regs, AD_LUT, i);
441
442	/* initialize ADC references */
443	/* FIXME: pos_ref & neg_ref depend on VT_50HZ */
444	write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
445	write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
446	write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF);
447	write_i2c_reg(pd->regs, AD_CMD, 34);
448	write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF);
449	write_i2c_reg(pd->regs, AD_CMD, 0);
450
451	/* initialize PM LUT */
452	write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM);
453	for (i = 0; i < 256; i++) {
454		write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
455		write_i2c_reg(pd->regs, PM_LUT_DATA, i);
456	}
457	write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL);
458	for (i = 0; i < 256; i++) {
459		write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
460		write_i2c_reg(pd->regs, PM_LUT_DATA, i);
461	}
462	write_i2c_reg(pd->regs, CONFIG, pd->config); /*  ACQ_MODE_EVEN  */
463
464	/* select channel 1 for input and set sync level */
465	write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
466	write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
467
468	/* disable all irqs, clear all irq flags */
469	iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD,
470			pd->regs + INT_CSR);
471
472	return 0;
473}
474
475static const struct video_device dt3155_vdev = {
476	.name = DT3155_NAME,
477	.fops = &dt3155_fops,
478	.ioctl_ops = &dt3155_ioctl_ops,
479	.minor = -1,
480	.release = video_device_release_empty,
481	.tvnorms = V4L2_STD_ALL,
482	.device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |
483		       V4L2_CAP_READWRITE,
484};
485
486static int dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id)
487{
488	int err;
489	struct dt3155_priv *pd;
490
491	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
492	if (err)
493		return -ENODEV;
494	pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
495	if (!pd)
496		return -ENOMEM;
497
498	err = v4l2_device_register(&pdev->dev, &pd->v4l2_dev);
499	if (err)
500		return err;
501	pd->vdev = dt3155_vdev;
502	pd->vdev.v4l2_dev = &pd->v4l2_dev;
503	video_set_drvdata(&pd->vdev, pd);  /* for use in video_fops */
504	pd->pdev = pdev;
505	pd->std = V4L2_STD_625_50;
506	pd->csr2 = VT_50HZ;
507	pd->width = 768;
508	pd->height = 576;
509	INIT_LIST_HEAD(&pd->dmaq);
510	mutex_init(&pd->mux);
511	pd->vdev.lock = &pd->mux; /* for locking v4l2_file_operations */
512	pd->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
513	pd->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
514	pd->vidq.io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
515	pd->vidq.ops = &q_ops;
516	pd->vidq.mem_ops = &vb2_dma_contig_memops;
517	pd->vidq.drv_priv = pd;
518	pd->vidq.min_queued_buffers = 2;
519	pd->vidq.gfp_flags = GFP_DMA32;
520	pd->vidq.lock = &pd->mux; /* for locking v4l2_file_operations */
521	pd->vidq.dev = &pdev->dev;
522	pd->vdev.queue = &pd->vidq;
523	err = vb2_queue_init(&pd->vidq);
524	if (err < 0)
525		goto err_v4l2_dev_unreg;
526	spin_lock_init(&pd->lock);
527	pd->config = ACQ_MODE_EVEN;
528	err = pci_enable_device(pdev);
529	if (err)
530		goto err_v4l2_dev_unreg;
531	err = pci_request_region(pdev, 0, pci_name(pdev));
532	if (err)
533		goto err_pci_disable;
534	pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0));
535	if (!pd->regs) {
536		err = -ENOMEM;
537		goto err_free_reg;
538	}
539	err = dt3155_init_board(pd);
540	if (err)
541		goto err_iounmap;
542	err = request_irq(pd->pdev->irq, dt3155_irq_handler_even,
543					IRQF_SHARED, DT3155_NAME, pd);
544	if (err)
545		goto err_iounmap;
546	err = video_register_device(&pd->vdev, VFL_TYPE_VIDEO, -1);
547	if (err)
548		goto err_free_irq;
549	dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev.minor);
550	return 0;  /*   success   */
551
552err_free_irq:
553	free_irq(pd->pdev->irq, pd);
554err_iounmap:
555	pci_iounmap(pdev, pd->regs);
556err_free_reg:
557	pci_release_region(pdev, 0);
558err_pci_disable:
559	pci_disable_device(pdev);
560err_v4l2_dev_unreg:
561	v4l2_device_unregister(&pd->v4l2_dev);
562	return err;
563}
564
565static void dt3155_remove(struct pci_dev *pdev)
566{
567	struct v4l2_device *v4l2_dev = pci_get_drvdata(pdev);
568	struct dt3155_priv *pd = container_of(v4l2_dev, struct dt3155_priv,
569					      v4l2_dev);
570
571	vb2_video_unregister_device(&pd->vdev);
572	free_irq(pd->pdev->irq, pd);
573	v4l2_device_unregister(&pd->v4l2_dev);
574	pci_iounmap(pdev, pd->regs);
575	pci_release_region(pdev, 0);
576	pci_disable_device(pdev);
577}
578
579static const struct pci_device_id pci_ids[] = {
580	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, DT3155_DEVICE_ID) },
581	{ 0, /* zero marks the end */ },
582};
583MODULE_DEVICE_TABLE(pci, pci_ids);
584
585static struct pci_driver pci_driver = {
586	.name = DT3155_NAME,
587	.id_table = pci_ids,
588	.probe = dt3155_probe,
589	.remove = dt3155_remove,
590};
591
592module_pci_driver(pci_driver);
593
594MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber");
595MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>");
596MODULE_VERSION(DT3155_VERSION);
597MODULE_LICENSE("GPL");