cx25821-sram.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 *  Driver for the Conexant CX25821 PCIe bridge
  4 *
  5 *  Copyright (C) 2009 Conexant Systems Inc.
  6 *  Authors  <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
  7 */
  8
  9#ifndef __ATHENA_SRAM_H__
 10#define __ATHENA_SRAM_H__
 11
 12/* #define RX_SRAM_START_SIZE        = 0;  //  Start of reserved SRAM */
 13#define VID_CMDS_SIZE             80	/* Video CMDS size in bytes */
 14#define AUDIO_CMDS_SIZE           80	/* AUDIO CMDS size in bytes */
 15#define MBIF_CMDS_SIZE            80	/* MBIF  CMDS size in bytes */
 16
 17/* #define RX_SRAM_POOL_START_SIZE   = 0;  //  Start of usable RX SRAM for buffers */
 18#define VID_IQ_SIZE               64	/* VID instruction queue size in bytes */
 19#define MBIF_IQ_SIZE              64
 20#define AUDIO_IQ_SIZE             64	/* AUD instruction queue size in bytes */
 21
 22#define VID_CDT_SIZE              64	/* VID cluster descriptor table size in bytes */
 23#define MBIF_CDT_SIZE             64	/* MBIF/HBI cluster descriptor table size in bytes */
 24#define AUDIO_CDT_SIZE            48	/* AUD cluster descriptor table size in bytes */
 25
 26/* #define RX_SRAM_POOL_FREE_SIZE    = 16; //  Start of available RX SRAM */
 27/* #define RX_SRAM_END_SIZE          = 0;  //  End of RX SRAM */
 28
 29/* #define TX_SRAM_POOL_START_SIZE   = 0;  //  Start of transmit pool SRAM */
 30/* #define MSI_DATA_SIZE             = 64; //  Reserved (MSI Data, RISC working stora */
 31
 32#define VID_CLUSTER_SIZE          1440	/* VID cluster data line */
 33#define AUDIO_CLUSTER_SIZE        128	/* AUDIO cluster data line */
 34#define MBIF_CLUSTER_SIZE         1440	/* MBIF/HBI cluster data line */
 35
 36/* #define TX_SRAM_POOL_FREE_SIZE    = 704;    //  Start of available TX SRAM */
 37/* #define TX_SRAM_END_SIZE          = 0;      //  End of TX SRAM */
 38
 39/* Receive SRAM */
 40#define RX_SRAM_START             0x10000
 41#define VID_A_DOWN_CMDS           0x10000
 42#define VID_B_DOWN_CMDS           0x10050
 43#define VID_C_DOWN_CMDS           0x100A0
 44#define VID_D_DOWN_CMDS           0x100F0
 45#define VID_E_DOWN_CMDS           0x10140
 46#define VID_F_DOWN_CMDS           0x10190
 47#define VID_G_DOWN_CMDS           0x101E0
 48#define VID_H_DOWN_CMDS           0x10230
 49#define VID_A_UP_CMDS             0x10280
 50#define VID_B_UP_CMDS             0x102D0
 51#define VID_C_UP_CMDS             0x10320
 52#define VID_D_UP_CMDS             0x10370
 53#define VID_E_UP_CMDS             0x103C0
 54#define VID_F_UP_CMDS             0x10410
 55#define VID_I_UP_CMDS             0x10460
 56#define VID_J_UP_CMDS             0x104B0
 57#define AUD_A_DOWN_CMDS           0x10500
 58#define AUD_B_DOWN_CMDS           0x10550
 59#define AUD_C_DOWN_CMDS           0x105A0
 60#define AUD_D_DOWN_CMDS           0x105F0
 61#define AUD_A_UP_CMDS             0x10640
 62#define AUD_B_UP_CMDS             0x10690
 63#define AUD_C_UP_CMDS             0x106E0
 64#define AUD_E_UP_CMDS             0x10730
 65#define MBIF_A_DOWN_CMDS          0x10780
 66#define MBIF_B_DOWN_CMDS          0x107D0
 67#define DMA_SCRATCH_PAD           0x10820	/* Scratch pad area from 0x10820 to 0x10B40 */
 68
 69/* #define RX_SRAM_POOL_START        = 0x105B0; */
 70
 71#define VID_A_IQ                  0x11000
 72#define VID_B_IQ                  0x11040
 73#define VID_C_IQ                  0x11080
 74#define VID_D_IQ                  0x110C0
 75#define VID_E_IQ                  0x11100
 76#define VID_F_IQ                  0x11140
 77#define VID_G_IQ                  0x11180
 78#define VID_H_IQ                  0x111C0
 79#define VID_I_IQ                  0x11200
 80#define VID_J_IQ                  0x11240
 81#define AUD_A_IQ                  0x11280
 82#define AUD_B_IQ                  0x112C0
 83#define AUD_C_IQ                  0x11300
 84#define AUD_D_IQ                  0x11340
 85#define AUD_E_IQ                  0x11380
 86#define MBIF_A_IQ                 0x11000
 87#define MBIF_B_IQ                 0x110C0
 88
 89#define VID_A_CDT                 0x10C00
 90#define VID_B_CDT                 0x10C40
 91#define VID_C_CDT                 0x10C80
 92#define VID_D_CDT                 0x10CC0
 93#define VID_E_CDT                 0x10D00
 94#define VID_F_CDT                 0x10D40
 95#define VID_G_CDT                 0x10D80
 96#define VID_H_CDT                 0x10DC0
 97#define VID_I_CDT                 0x10E00
 98#define VID_J_CDT                 0x10E40
 99#define AUD_A_CDT                 0x10E80
100#define AUD_B_CDT                 0x10EB0
101#define AUD_C_CDT                 0x10EE0
102#define AUD_D_CDT                 0x10F10
103#define AUD_E_CDT                 0x10F40
104#define MBIF_A_CDT                0x10C00
105#define MBIF_B_CDT                0x10CC0
106
107/* Cluster Buffer for RX */
108#define VID_A_UP_CLUSTER_1        0x11400
109#define VID_A_UP_CLUSTER_2        0x119A0
110#define VID_A_UP_CLUSTER_3        0x11F40
111#define VID_A_UP_CLUSTER_4        0x124E0
112
113#define VID_B_UP_CLUSTER_1        0x12A80
114#define VID_B_UP_CLUSTER_2        0x13020
115#define VID_B_UP_CLUSTER_3        0x135C0
116#define VID_B_UP_CLUSTER_4        0x13B60
117
118#define VID_C_UP_CLUSTER_1        0x14100
119#define VID_C_UP_CLUSTER_2        0x146A0
120#define VID_C_UP_CLUSTER_3        0x14C40
121#define VID_C_UP_CLUSTER_4        0x151E0
122
123#define VID_D_UP_CLUSTER_1        0x15780
124#define VID_D_UP_CLUSTER_2        0x15D20
125#define VID_D_UP_CLUSTER_3        0x162C0
126#define VID_D_UP_CLUSTER_4        0x16860
127
128#define VID_E_UP_CLUSTER_1        0x16E00
129#define VID_E_UP_CLUSTER_2        0x173A0
130#define VID_E_UP_CLUSTER_3        0x17940
131#define VID_E_UP_CLUSTER_4        0x17EE0
132
133#define VID_F_UP_CLUSTER_1        0x18480
134#define VID_F_UP_CLUSTER_2        0x18A20
135#define VID_F_UP_CLUSTER_3        0x18FC0
136#define VID_F_UP_CLUSTER_4        0x19560
137
138#define VID_I_UP_CLUSTER_1        0x19B00
139#define VID_I_UP_CLUSTER_2        0x1A0A0
140#define VID_I_UP_CLUSTER_3        0x1A640
141#define VID_I_UP_CLUSTER_4        0x1ABE0
142
143#define VID_J_UP_CLUSTER_1        0x1B180
144#define VID_J_UP_CLUSTER_2        0x1B720
145#define VID_J_UP_CLUSTER_3        0x1BCC0
146#define VID_J_UP_CLUSTER_4        0x1C260
147
148#define AUD_A_UP_CLUSTER_1        0x1C800
149#define AUD_A_UP_CLUSTER_2        0x1C880
150#define AUD_A_UP_CLUSTER_3        0x1C900
151
152#define AUD_B_UP_CLUSTER_1        0x1C980
153#define AUD_B_UP_CLUSTER_2        0x1CA00
154#define AUD_B_UP_CLUSTER_3        0x1CA80
155
156#define AUD_C_UP_CLUSTER_1        0x1CB00
157#define AUD_C_UP_CLUSTER_2        0x1CB80
158#define AUD_C_UP_CLUSTER_3        0x1CC00
159
160#define AUD_E_UP_CLUSTER_1        0x1CC80
161#define AUD_E_UP_CLUSTER_2        0x1CD00
162#define AUD_E_UP_CLUSTER_3        0x1CD80
163
164#define RX_SRAM_POOL_FREE         0x1CE00
165#define RX_SRAM_END               0x1D000
166
167/* Free Receive SRAM    144 Bytes */
168
169/* Transmit SRAM */
170#define TX_SRAM_POOL_START        0x00000
171
172#define VID_A_DOWN_CLUSTER_1      0x00040
173#define VID_A_DOWN_CLUSTER_2      0x005E0
174#define VID_A_DOWN_CLUSTER_3      0x00B80
175#define VID_A_DOWN_CLUSTER_4      0x01120
176
177#define VID_B_DOWN_CLUSTER_1      0x016C0
178#define VID_B_DOWN_CLUSTER_2      0x01C60
179#define VID_B_DOWN_CLUSTER_3      0x02200
180#define VID_B_DOWN_CLUSTER_4      0x027A0
181
182#define VID_C_DOWN_CLUSTER_1      0x02D40
183#define VID_C_DOWN_CLUSTER_2      0x032E0
184#define VID_C_DOWN_CLUSTER_3      0x03880
185#define VID_C_DOWN_CLUSTER_4      0x03E20
186
187#define VID_D_DOWN_CLUSTER_1      0x043C0
188#define VID_D_DOWN_CLUSTER_2      0x04960
189#define VID_D_DOWN_CLUSTER_3      0x04F00
190#define VID_D_DOWN_CLUSTER_4      0x054A0
191
192#define VID_E_DOWN_CLUSTER_1      0x05a40
193#define VID_E_DOWN_CLUSTER_2      0x05FE0
194#define VID_E_DOWN_CLUSTER_3      0x06580
195#define VID_E_DOWN_CLUSTER_4      0x06B20
196
197#define VID_F_DOWN_CLUSTER_1      0x070C0
198#define VID_F_DOWN_CLUSTER_2      0x07660
199#define VID_F_DOWN_CLUSTER_3      0x07C00
200#define VID_F_DOWN_CLUSTER_4      0x081A0
201
202#define VID_G_DOWN_CLUSTER_1      0x08740
203#define VID_G_DOWN_CLUSTER_2      0x08CE0
204#define VID_G_DOWN_CLUSTER_3      0x09280
205#define VID_G_DOWN_CLUSTER_4      0x09820
206
207#define VID_H_DOWN_CLUSTER_1      0x09DC0
208#define VID_H_DOWN_CLUSTER_2      0x0A360
209#define VID_H_DOWN_CLUSTER_3      0x0A900
210#define VID_H_DOWN_CLUSTER_4      0x0AEA0
211
212#define AUD_A_DOWN_CLUSTER_1      0x0B500
213#define AUD_A_DOWN_CLUSTER_2      0x0B580
214#define AUD_A_DOWN_CLUSTER_3      0x0B600
215
216#define AUD_B_DOWN_CLUSTER_1      0x0B680
217#define AUD_B_DOWN_CLUSTER_2      0x0B700
218#define AUD_B_DOWN_CLUSTER_3      0x0B780
219
220#define AUD_C_DOWN_CLUSTER_1      0x0B800
221#define AUD_C_DOWN_CLUSTER_2      0x0B880
222#define AUD_C_DOWN_CLUSTER_3      0x0B900
223
224#define AUD_D_DOWN_CLUSTER_1      0x0B980
225#define AUD_D_DOWN_CLUSTER_2      0x0BA00
226#define AUD_D_DOWN_CLUSTER_3      0x0BA80
227
228#define TX_SRAM_POOL_FREE         0x0BB00
229#define TX_SRAM_END               0x0C000
230
231#define BYTES_TO_DWORDS(bcount) ((bcount) >> 2)
232#define BYTES_TO_QWORDS(bcount) ((bcount) >> 3)
233#define BYTES_TO_OWORDS(bcount) ((bcount) >> 4)
234
235#define VID_IQ_SIZE_DW             BYTES_TO_DWORDS(VID_IQ_SIZE)
236#define VID_CDT_SIZE_QW            BYTES_TO_QWORDS(VID_CDT_SIZE)
237#define VID_CLUSTER_SIZE_OW        BYTES_TO_OWORDS(VID_CLUSTER_SIZE)
238
239#define AUDIO_IQ_SIZE_DW           BYTES_TO_DWORDS(AUDIO_IQ_SIZE)
240#define AUDIO_CDT_SIZE_QW          BYTES_TO_QWORDS(AUDIO_CDT_SIZE)
241#define AUDIO_CLUSTER_SIZE_QW      BYTES_TO_QWORDS(AUDIO_CLUSTER_SIZE)
242
243#define MBIF_IQ_SIZE_DW            BYTES_TO_DWORDS(MBIF_IQ_SIZE)
244#define MBIF_CDT_SIZE_QW           BYTES_TO_QWORDS(MBIF_CDT_SIZE)
245#define MBIF_CLUSTER_SIZE_OW       BYTES_TO_OWORDS(MBIF_CLUSTER_SIZE)
246
247#endif