tvp5150_reg.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 *
  4 * tvp5150 - Texas Instruments TVP5150A/AM1 video decoder registers
  5 *
  6 * Copyright (c) 2005,2006 Mauro Carvalho Chehab <mchehab@kernel.org>
  7 */
  8
  9#define TVP5150_VD_IN_SRC_SEL_1      0x00 /* Video input source selection #1 */
 10#define TVP5150_ANAL_CHL_CTL         0x01 /* Analog channel controls */
 11#define TVP5150_OP_MODE_CTL          0x02 /* Operation mode controls */
 12#define TVP5150_MISC_CTL             0x03 /* Miscellaneous controls */
 13#define TVP5150_MISC_CTL_VBLK_GPCL	BIT(7)
 14#define TVP5150_MISC_CTL_GPCL		BIT(6)
 15#define TVP5150_MISC_CTL_INTREQ_OE	BIT(5)
 16#define TVP5150_MISC_CTL_HVLK		BIT(4)
 17#define TVP5150_MISC_CTL_YCBCR_OE	BIT(3)
 18#define TVP5150_MISC_CTL_SYNC_OE	BIT(2)
 19#define TVP5150_MISC_CTL_VBLANK		BIT(1)
 20#define TVP5150_MISC_CTL_CLOCK_OE	BIT(0)
 21
 22#define TVP5150_AUTOSW_MSK           0x04 /* Autoswitch mask: TVP5150A / TVP5150AM */
 23
 24/* Reserved 05h */
 25
 26#define TVP5150_COLOR_KIL_THSH_CTL   0x06 /* Color killer threshold control */
 27#define TVP5150_LUMA_PROC_CTL_1      0x07 /* Luminance processing control #1 */
 28#define TVP5150_LUMA_PROC_CTL_2      0x08 /* Luminance processing control #2 */
 29#define TVP5150_BRIGHT_CTL           0x09 /* Brightness control */
 30#define TVP5150_SATURATION_CTL       0x0a /* Color saturation control */
 31#define TVP5150_HUE_CTL              0x0b /* Hue control */
 32#define TVP5150_CONTRAST_CTL         0x0c /* Contrast control */
 33#define TVP5150_DATA_RATE_SEL        0x0d /* Outputs and data rates select */
 34#define TVP5150_LUMA_PROC_CTL_3      0x0e /* Luminance processing control #3 */
 35#define TVP5150_CONF_SHARED_PIN      0x0f /* Configuration shared pins */
 36
 37/* Reserved 10h */
 38
 39#define TVP5150_ACT_VD_CROP_ST_MSB   0x11 /* Active video cropping start MSB */
 40#define TVP5150_ACT_VD_CROP_ST_LSB   0x12 /* Active video cropping start LSB */
 41#define TVP5150_ACT_VD_CROP_STP_MSB  0x13 /* Active video cropping stop MSB */
 42#define TVP5150_ACT_VD_CROP_STP_LSB  0x14 /* Active video cropping stop LSB */
 43#define TVP5150_GENLOCK              0x15 /* Genlock/RTC */
 44#define TVP5150_HORIZ_SYNC_START     0x16 /* Horizontal sync start */
 45
 46/* Reserved 17h */
 47
 48#define TVP5150_VERT_BLANKING_START 0x18 /* Vertical blanking start */
 49#define TVP5150_VERT_BLANKING_STOP  0x19 /* Vertical blanking stop */
 50#define TVP5150_CHROMA_PROC_CTL_1   0x1a /* Chrominance processing control #1 */
 51#define TVP5150_CHROMA_PROC_CTL_2   0x1b /* Chrominance processing control #2 */
 52#define TVP5150_INT_RESET_REG_B     0x1c /* Interrupt reset register B */
 53#define TVP5150_INT_ENABLE_REG_B    0x1d /* Interrupt enable register B */
 54#define TVP5150_INTT_CONFIG_REG_B   0x1e /* Interrupt configuration register B */
 55
 56/* Reserved 1Fh-27h */
 57
 58#define VIDEO_STD_MASK			 (0x07 >> 1)
 59#define TVP5150_VIDEO_STD                0x28 /* Video standard */
 60#define VIDEO_STD_AUTO_SWITCH_BIT	 0x00
 61#define VIDEO_STD_NTSC_MJ_BIT		 0x02
 62#define VIDEO_STD_PAL_BDGHIN_BIT	 0x04
 63#define VIDEO_STD_PAL_M_BIT		 0x06
 64#define VIDEO_STD_PAL_COMBINATION_N_BIT	 0x08
 65#define VIDEO_STD_NTSC_4_43_BIT		 0x0a
 66#define VIDEO_STD_SECAM_BIT		 0x0c
 67
 68#define VIDEO_STD_NTSC_MJ_BIT_AS                 0x01
 69#define VIDEO_STD_PAL_BDGHIN_BIT_AS              0x03
 70#define VIDEO_STD_PAL_M_BIT_AS			 0x05
 71#define VIDEO_STD_PAL_COMBINATION_N_BIT_AS	 0x07
 72#define VIDEO_STD_NTSC_4_43_BIT_AS		 0x09
 73#define VIDEO_STD_SECAM_BIT_AS			 0x0b
 74
 75/* Reserved 29h-2bh */
 76
 77#define TVP5150_CB_GAIN_FACT        0x2c /* Cb gain factor */
 78#define TVP5150_CR_GAIN_FACTOR      0x2d /* Cr gain factor */
 79#define TVP5150_MACROVISION_ON_CTR  0x2e /* Macrovision on counter */
 80#define TVP5150_MACROVISION_OFF_CTR 0x2f /* Macrovision off counter */
 81#define TVP5150_REV_SELECT          0x30 /* revision select (TVP5150AM1 only) */
 82
 83/* Reserved	31h-7Fh */
 84
 85#define TVP5150_MSB_DEV_ID          0x80 /* MSB of device ID */
 86#define TVP5150_LSB_DEV_ID          0x81 /* LSB of device ID */
 87#define TVP5150_ROM_MAJOR_VER       0x82 /* ROM major version */
 88#define TVP5150_ROM_MINOR_VER       0x83 /* ROM minor version */
 89#define TVP5150_VERT_LN_COUNT_MSB   0x84 /* Vertical line count MSB */
 90#define TVP5150_VERT_LN_COUNT_LSB   0x85 /* Vertical line count LSB */
 91#define TVP5150_INT_STATUS_REG_B    0x86 /* Interrupt status register B */
 92#define TVP5150_INT_ACTIVE_REG_B    0x87 /* Interrupt active register B */
 93#define TVP5150_STATUS_REG_1        0x88 /* Status register #1 */
 94#define TVP5150_STATUS_REG_2        0x89 /* Status register #2 */
 95#define TVP5150_STATUS_REG_3        0x8a /* Status register #3 */
 96#define TVP5150_STATUS_REG_4        0x8b /* Status register #4 */
 97#define TVP5150_STATUS_REG_5        0x8c /* Status register #5 */
 98/* Reserved	8Dh-8Fh */
 99 /* Closed caption data registers */
100#define TVP5150_CC_DATA_INI         0x90
101#define TVP5150_CC_DATA_END         0x93
102
103 /* WSS data registers */
104#define TVP5150_WSS_DATA_INI        0x94
105#define TVP5150_WSS_DATA_END        0x99
106
107/* VPS data registers */
108#define TVP5150_VPS_DATA_INI        0x9a
109#define TVP5150_VPS_DATA_END        0xa6
110
111/* VITC data registers */
112#define TVP5150_VITC_DATA_INI       0xa7
113#define TVP5150_VITC_DATA_END       0xaf
114
115#define TVP5150_VBI_FIFO_READ_DATA  0xb0 /* VBI FIFO read data */
116
117/* Teletext filter 1 */
118#define TVP5150_TELETEXT_FIL1_INI  0xb1
119#define TVP5150_TELETEXT_FIL1_END  0xb5
120
121/* Teletext filter 2 */
122#define TVP5150_TELETEXT_FIL2_INI  0xb6
123#define TVP5150_TELETEXT_FIL2_END  0xba
124
125#define TVP5150_TELETEXT_FIL_ENA    0xbb /* Teletext filter enable */
126/* Reserved	BCh-BFh */
127#define TVP5150_INT_STATUS_REG_A    0xc0 /* Interrupt status register A */
128#define   TVP5150_INT_A_LOCK_STATUS BIT(7)
129#define   TVP5150_INT_A_LOCK        BIT(6)
130#define TVP5150_INT_ENABLE_REG_A    0xc1 /* Interrupt enable register A */
131#define TVP5150_INT_CONF            0xc2 /* Interrupt configuration */
132#define   TVP5150_VDPOE             BIT(2)
133#define TVP5150_VDP_CONF_RAM_DATA   0xc3 /* VDP configuration RAM data */
134#define TVP5150_CONF_RAM_ADDR_LOW   0xc4 /* Configuration RAM address low byte */
135#define TVP5150_CONF_RAM_ADDR_HIGH  0xc5 /* Configuration RAM address high byte */
136#define TVP5150_VDP_STATUS_REG      0xc6 /* VDP status register */
137#define TVP5150_FIFO_WORD_COUNT     0xc7 /* FIFO word count */
138#define TVP5150_FIFO_INT_THRESHOLD  0xc8 /* FIFO interrupt threshold */
139#define TVP5150_FIFO_RESET          0xc9 /* FIFO reset */
140#define TVP5150_LINE_NUMBER_INT     0xca /* Line number interrupt */
141#define TVP5150_PIX_ALIGN_REG_LOW   0xcb /* Pixel alignment register low byte */
142#define TVP5150_PIX_ALIGN_REG_HIGH  0xcc /* Pixel alignment register high byte */
143#define TVP5150_FIFO_OUT_CTRL       0xcd /* FIFO output control */
144/* Reserved	CEh */
145#define TVP5150_FULL_FIELD_ENA      0xcf /* Full field enable 1 */
146
147/* Line mode registers */
148#define TVP5150_LINE_MODE_INI       0xd0
149#define TVP5150_LINE_MODE_END       0xfb
150
151#define TVP5150_FULL_FIELD_MODE_REG 0xfc /* Full field mode register */
152/* Reserved	FDh-FFh */