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tc358743.c
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linux-6.19.14/drivers/media/i2c/tc358743.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * tc358743 - Toshiba HDMI to CSI-2 bridge 4 * 5 * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights 6 * reserved. 7 */ 8 9/* 10 * References (c = chapter, p = page): 11 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60 12 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls 13 */ 14 15#include <linux/kernel.h> 16#include <linux/module.h> 17#include <linux/slab.h> 18#include <linux/i2c.h> 19#include <linux/clk.h> 20#include <linux/delay.h> 21#include <linux/gpio/consumer.h> 22#include <linux/interrupt.h> 23#include <linux/timer.h> 24#include <linux/of_graph.h> 25#include <linux/videodev2.h> 26#include <linux/workqueue.h> 27#include <linux/v4l2-dv-timings.h> 28#include <linux/hdmi.h> 29#include <media/cec.h> 30#include <media/v4l2-dv-timings.h> 31#include <media/v4l2-device.h> 32#include <media/v4l2-ctrls.h> 33#include <media/v4l2-event.h> 34#include <media/v4l2-fwnode.h> 35#include <media/i2c/tc358743.h> 36 37#include "tc358743_regs.h" 38 39static int debug; 40module_param(debug, int, 0644); 41MODULE_PARM_DESC(debug, " debug level (0-3)"); 42 43static int packet_type = 0x87; 44module_param(packet_type, int, 0644); 45MODULE_PARM_DESC(packet_type, 46 " Programmable Packet Type. Possible values:\n" 47 "\t\t 0x87: DRM InfoFrame (Default).\n" 48 "\t\t 0x01: Audio Clock Regeneration Packet\n" 49 "\t\t 0x02: Audio Sample Packet\n" 50 "\t\t 0x03: General Control Packet\n" 51 "\t\t 0x04: ACP Packet\n" 52 "\t\t 0x07: One Bit Audio Sample Packet\n" 53 "\t\t 0x08: DST Audio Packet\n" 54 "\t\t 0x09: High Bitrate Audio Stream Packet\n" 55 "\t\t 0x0a: Gamut Metadata Packet\n"); 56 57MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver"); 58MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>"); 59MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>"); 60MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>"); 61MODULE_LICENSE("GPL"); 62 63#define EDID_NUM_BLOCKS_MAX 8 64#define EDID_BLOCK_SIZE 128 65 66#define I2C_MAX_XFER_SIZE (EDID_BLOCK_SIZE + 2) 67 68#define POLL_INTERVAL_CEC_MS 10 69#define POLL_INTERVAL_MS 1000 70 71static const struct v4l2_dv_timings_cap tc358743_timings_cap = { 72 .type = V4L2_DV_BT_656_1120, 73 /* keep this initialization for compatibility with GCC < 4.4.6 */ 74 .reserved = { 0 }, 75 /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */ 76 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 13000000, 165000000, 77 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 78 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 79 V4L2_DV_BT_CAP_PROGRESSIVE | 80 V4L2_DV_BT_CAP_REDUCED_BLANKING | 81 V4L2_DV_BT_CAP_CUSTOM) 82}; 83 84struct tc358743_state { 85 struct tc358743_platform_data pdata; 86 struct v4l2_mbus_config_mipi_csi2 bus; 87 struct v4l2_subdev sd; 88 struct media_pad pad; 89 struct v4l2_ctrl_handler hdl; 90 struct i2c_client *i2c_client; 91 /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */ 92 struct mutex confctl_mutex; 93 94 /* controls */ 95 struct v4l2_ctrl *detect_tx_5v_ctrl; 96 struct v4l2_ctrl *audio_sampling_rate_ctrl; 97 struct v4l2_ctrl *audio_present_ctrl; 98 99 struct delayed_work delayed_work_enable_hotplug; 100 101 struct timer_list timer; 102 struct work_struct work_i2c_poll; 103 104 /* debugfs */ 105 struct dentry *debugfs_dir; 106 struct v4l2_debugfs_if *infoframes; 107 108 /* edid */ 109 u8 edid_blocks_written; 110 111 struct v4l2_dv_timings timings; 112 u32 mbus_fmt_code; 113 u8 csi_lanes_in_use; 114 115 struct gpio_desc *reset_gpio; 116 117 struct cec_adapter *cec_adap; 118}; 119 120static void tc358743_enable_interrupts(struct v4l2_subdev *sd, 121 bool cable_connected); 122static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd); 123 124static inline struct tc358743_state *to_state(struct v4l2_subdev *sd) 125{ 126 return container_of(sd, struct tc358743_state, sd); 127} 128 129/* --------------- I2C --------------- */ 130 131static int i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) 132{ 133 struct tc358743_state *state = to_state(sd); 134 struct i2c_client *client = state->i2c_client; 135 int err; 136 u8 buf[2] = { reg >> 8, reg & 0xff }; 137 struct i2c_msg msgs[] = { 138 { 139 .addr = client->addr, 140 .flags = 0, 141 .len = 2, 142 .buf = buf, 143 }, 144 { 145 .addr = client->addr, 146 .flags = I2C_M_RD, 147 .len = n, 148 .buf = values, 149 }, 150 }; 151 152 err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 153 if (err != ARRAY_SIZE(msgs)) { 154 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed: %d\n", 155 __func__, reg, client->addr, err); 156 } 157 return err != ARRAY_SIZE(msgs); 158} 159 160static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) 161{ 162 struct tc358743_state *state = to_state(sd); 163 struct i2c_client *client = state->i2c_client; 164 int err, i; 165 struct i2c_msg msg; 166 u8 data[I2C_MAX_XFER_SIZE]; 167 168 if ((2 + n) > I2C_MAX_XFER_SIZE) { 169 n = I2C_MAX_XFER_SIZE - 2; 170 v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n", 171 reg, 2 + n); 172 } 173 174 msg.addr = client->addr; 175 msg.buf = data; 176 msg.len = 2 + n; 177 msg.flags = 0; 178 179 data[0] = reg >> 8; 180 data[1] = reg & 0xff; 181 182 for (i = 0; i < n; i++) 183 data[2 + i] = values[i]; 184 185 err = i2c_transfer(client->adapter, &msg, 1); 186 if (err != 1) { 187 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed: %d\n", 188 __func__, reg, client->addr, err); 189 return; 190 } 191 192 if (debug < 3) 193 return; 194 195 switch (n) { 196 case 1: 197 v4l2_info(sd, "I2C write 0x%04x = 0x%02x", 198 reg, data[2]); 199 break; 200 case 2: 201 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x", 202 reg, data[3], data[2]); 203 break; 204 case 4: 205 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x", 206 reg, data[5], data[4], data[3], data[2]); 207 break; 208 default: 209 v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n", 210 n, reg); 211 } 212} 213 214static noinline u32 i2c_rdreg_err(struct v4l2_subdev *sd, u16 reg, u32 n, 215 int *err) 216{ 217 int error; 218 __le32 val = 0; 219 220 error = i2c_rd(sd, reg, (u8 __force *)&val, n); 221 if (err) 222 *err = error; 223 224 return le32_to_cpu(val); 225} 226 227static inline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n) 228{ 229 return i2c_rdreg_err(sd, reg, n, NULL); 230} 231 232static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n) 233{ 234 __le32 raw = cpu_to_le32(val); 235 236 i2c_wr(sd, reg, (u8 __force *)&raw, n); 237} 238 239static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg) 240{ 241 return i2c_rdreg(sd, reg, 1); 242} 243 244static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val) 245{ 246 i2c_wrreg(sd, reg, val, 1); 247} 248 249static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg, 250 u8 mask, u8 val) 251{ 252 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1); 253} 254 255static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg) 256{ 257 return i2c_rdreg(sd, reg, 2); 258} 259 260static int i2c_rd16_err(struct v4l2_subdev *sd, u16 reg, u16 *value) 261{ 262 int err; 263 *value = i2c_rdreg_err(sd, reg, 2, &err); 264 return err; 265} 266 267static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val) 268{ 269 i2c_wrreg(sd, reg, val, 2); 270} 271 272static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val) 273{ 274 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 2) & mask) | val, 2); 275} 276 277static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg) 278{ 279 return i2c_rdreg(sd, reg, 4); 280} 281 282static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val) 283{ 284 i2c_wrreg(sd, reg, val, 4); 285} 286 287/* --------------- STATUS --------------- */ 288 289static inline bool is_hdmi(struct v4l2_subdev *sd) 290{ 291 return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI; 292} 293 294static inline bool tx_5v_power_present(struct v4l2_subdev *sd) 295{ 296 return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V; 297} 298 299static inline bool no_signal(struct v4l2_subdev *sd) 300{ 301 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS); 302} 303 304static inline bool no_sync(struct v4l2_subdev *sd) 305{ 306 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC); 307} 308 309static inline bool audio_present(struct v4l2_subdev *sd) 310{ 311 return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE; 312} 313 314static int get_audio_sampling_rate(struct v4l2_subdev *sd) 315{ 316 static const int code_to_rate[] = { 317 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800, 318 88200, 768000, 96000, 705600, 176400, 0, 192000, 0 319 }; 320 321 /* Register FS_SET is not cleared when the cable is disconnected */ 322 if (no_signal(sd)) 323 return 0; 324 325 return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS]; 326} 327 328/* --------------- TIMINGS --------------- */ 329 330static inline unsigned fps(const struct v4l2_bt_timings *t) 331{ 332 if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t)) 333 return 0; 334 335 return DIV_ROUND_CLOSEST((unsigned)t->pixelclock, 336 V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t)); 337} 338 339static int tc358743_get_detected_timings(struct v4l2_subdev *sd, 340 struct v4l2_dv_timings *timings) 341{ 342 struct v4l2_bt_timings *bt = &timings->bt; 343 unsigned width, height, frame_width, frame_height, frame_interval, fps; 344 345 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 346 347 /* if HPD is low, ignore any video */ 348 if (!(i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0)) 349 return -ENOLINK; 350 351 if (no_signal(sd)) { 352 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 353 return -ENOLINK; 354 } 355 if (no_sync(sd)) { 356 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__); 357 return -ENOLCK; 358 } 359 360 timings->type = V4L2_DV_BT_656_1120; 361 bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ? 362 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 363 364 width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) + 365 i2c_rd8(sd, DE_WIDTH_H_LO); 366 height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) + 367 i2c_rd8(sd, DE_WIDTH_V_LO); 368 frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) + 369 i2c_rd8(sd, H_SIZE_LO); 370 frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) + 371 i2c_rd8(sd, V_SIZE_LO)) / 2; 372 /* frame interval in milliseconds * 10 373 * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */ 374 frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) + 375 i2c_rd8(sd, FV_CNT_LO); 376 fps = (frame_interval > 0) ? 377 DIV_ROUND_CLOSEST(10000, frame_interval) : 0; 378 379 bt->width = width; 380 bt->height = height; 381 bt->vsync = frame_height - height; 382 bt->hsync = frame_width - width; 383 bt->pixelclock = frame_width * frame_height * fps; 384 if (bt->interlaced == V4L2_DV_INTERLACED) { 385 bt->height *= 2; 386 bt->il_vsync = bt->vsync + 1; 387 bt->pixelclock /= 2; 388 } 389 390 return 0; 391} 392 393/* --------------- HOTPLUG / HDCP / EDID --------------- */ 394 395static void tc358743_delayed_work_enable_hotplug(struct work_struct *work) 396{ 397 struct delayed_work *dwork = to_delayed_work(work); 398 struct tc358743_state *state = container_of(dwork, 399 struct tc358743_state, delayed_work_enable_hotplug); 400 struct v4l2_subdev *sd = &state->sd; 401 402 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 403 404 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0); 405} 406 407static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable) 408{ 409 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ? 410 "enable" : "disable"); 411 412 if (enable) { 413 i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, KEY_RD_CMD); 414 415 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 0); 416 417 i2c_wr8_and_or(sd, HDCP_REG1, 0xff, 418 MASK_AUTH_UNAUTH_SEL_16_FRAMES | 419 MASK_AUTH_UNAUTH_AUTO); 420 421 i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET, 422 SET_AUTO_P3_RESET_FRAMES(0x0f)); 423 } else { 424 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 425 MASK_MANUAL_AUTHENTICATION); 426 } 427} 428 429static void tc358743_disable_edid(struct v4l2_subdev *sd) 430{ 431 struct tc358743_state *state = to_state(sd); 432 433 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 434 435 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 436 437 /* DDC access to EDID is also disabled when hotplug is disabled. See 438 * register DDC_CTL */ 439 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0); 440} 441 442static void tc358743_enable_edid(struct v4l2_subdev *sd) 443{ 444 struct tc358743_state *state = to_state(sd); 445 446 if (state->edid_blocks_written == 0) { 447 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__); 448 tc358743_s_ctrl_detect_tx_5v(sd); 449 return; 450 } 451 452 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 453 454 /* Enable hotplug after 143 ms. DDC access to EDID is also enabled when 455 * hotplug is enabled. See register DDC_CTL */ 456 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 7); 457 458 tc358743_enable_interrupts(sd, true); 459 tc358743_s_ctrl_detect_tx_5v(sd); 460} 461 462static void tc358743_erase_bksv(struct v4l2_subdev *sd) 463{ 464 int i; 465 466 for (i = 0; i < 5; i++) 467 i2c_wr8(sd, BKSV + i, 0); 468} 469 470/* --------------- AVI infoframe --------------- */ 471 472static ssize_t 473tc358743_debugfs_if_read(u32 type, void *priv, struct file *filp, 474 char __user *ubuf, size_t count, loff_t *ppos) 475{ 476 u8 buf[V4L2_DEBUGFS_IF_MAX_LEN] = {}; 477 struct v4l2_subdev *sd = priv; 478 int len; 479 480 if (!is_hdmi(sd)) 481 return 0; 482 483 switch (type) { 484 case V4L2_DEBUGFS_IF_AVI: 485 i2c_rd(sd, PK_AVI_0HEAD, buf, PK_AVI_LEN); 486 break; 487 case V4L2_DEBUGFS_IF_AUDIO: 488 i2c_rd(sd, PK_AUD_0HEAD, buf, PK_AUD_LEN); 489 break; 490 case V4L2_DEBUGFS_IF_SPD: 491 i2c_rd(sd, PK_SPD_0HEAD, buf, PK_SPD_LEN); 492 break; 493 case V4L2_DEBUGFS_IF_HDMI: 494 i2c_rd(sd, PK_VS_0HEAD, buf, PK_VS_LEN); 495 break; 496 case V4L2_DEBUGFS_IF_DRM: 497 i2c_rd(sd, PK_ACP_0HEAD, buf, PK_ACP_LEN); 498 break; 499 default: 500 return 0; 501 } 502 503 if (!buf[2]) 504 return -ENOENT; 505 506 len = buf[2] + 4; 507 if (len > V4L2_DEBUGFS_IF_MAX_LEN) 508 len = -ENOENT; 509 if (len > 0) 510 len = simple_read_from_buffer(ubuf, count, ppos, buf, len); 511 return len < 0 ? 0 : len; 512} 513 514static void print_infoframes(struct v4l2_subdev *sd) 515{ 516 struct i2c_client *client = v4l2_get_subdevdata(sd); 517 struct device *dev = &client->dev; 518 union hdmi_infoframe frame; 519 u8 buffer[V4L2_DEBUGFS_IF_MAX_LEN] = {}; 520 521 /* 522 * Updating the ACP TYPE here allows for dynamically 523 * changing the type you want to monitor, without having 524 * to reload the driver with a new packet_type module option value. 525 * 526 * Instead you can set it with the new value, then call 527 * VIDIOC_LOG_STATUS. 528 */ 529 i2c_wr8(sd, TYP_ACP_SET, packet_type); 530 531 if (!is_hdmi(sd)) { 532 v4l2_info(sd, "DVI-D signal - InfoFrames not supported\n"); 533 return; 534 } 535 536 i2c_rd(sd, PK_AVI_0HEAD, buffer, PK_AVI_LEN); 537 if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) >= 0) 538 hdmi_infoframe_log(KERN_INFO, dev, &frame); 539 540 i2c_rd(sd, PK_VS_0HEAD, buffer, PK_VS_LEN); 541 if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) >= 0) 542 hdmi_infoframe_log(KERN_INFO, dev, &frame); 543 544 i2c_rd(sd, PK_AUD_0HEAD, buffer, PK_AUD_LEN); 545 if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) >= 0) 546 hdmi_infoframe_log(KERN_INFO, dev, &frame); 547 548 i2c_rd(sd, PK_SPD_0HEAD, buffer, PK_SPD_LEN); 549 if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) >= 0) 550 hdmi_infoframe_log(KERN_INFO, dev, &frame); 551 552 i2c_rd(sd, PK_ACP_0HEAD, buffer, PK_ACP_LEN); 553 if (buffer[0] == packet_type) { 554 if (packet_type < 0x80) 555 v4l2_info(sd, "Packet: %*ph\n", PK_ACP_LEN, buffer); 556 else if (packet_type != 0x87) 557 v4l2_info(sd, "InfoFrame: %*ph\n", PK_ACP_LEN, buffer); 558 else if (hdmi_infoframe_unpack(&frame, buffer, 559 sizeof(buffer)) >= 0) 560 hdmi_infoframe_log(KERN_INFO, dev, &frame); 561 } 562 563 i2c_rd(sd, PK_MS_0HEAD, buffer, PK_MS_LEN); 564 if (buffer[2] && buffer[2] + 3 <= PK_MS_LEN) 565 v4l2_info(sd, "MPEG Source InfoFrame: %*ph\n", 566 buffer[2] + 3, buffer); 567 568 i2c_rd(sd, PK_ISRC1_0HEAD, buffer, PK_ISRC1_LEN); 569 if (buffer[0] == 0x05) 570 v4l2_info(sd, "ISRC1 Packet: %*ph\n", 571 PK_ISRC1_LEN, buffer); 572 573 i2c_rd(sd, PK_ISRC2_0HEAD, buffer, PK_ISRC2_LEN); 574 if (buffer[0] == 0x06) 575 v4l2_info(sd, "ISRC2 Packet: %*ph\n", 576 PK_ISRC2_LEN, buffer); 577} 578 579/* --------------- CTRLS --------------- */ 580 581static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd) 582{ 583 struct tc358743_state *state = to_state(sd); 584 585 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, 586 tx_5v_power_present(sd)); 587} 588 589static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd) 590{ 591 struct tc358743_state *state = to_state(sd); 592 593 return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl, 594 get_audio_sampling_rate(sd)); 595} 596 597static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd) 598{ 599 struct tc358743_state *state = to_state(sd); 600 601 return v4l2_ctrl_s_ctrl(state->audio_present_ctrl, 602 audio_present(sd)); 603} 604 605static int tc358743_update_controls(struct v4l2_subdev *sd) 606{ 607 int ret = 0; 608 609 ret |= tc358743_s_ctrl_detect_tx_5v(sd); 610 ret |= tc358743_s_ctrl_audio_sampling_rate(sd); 611 ret |= tc358743_s_ctrl_audio_present(sd); 612 613 return ret; 614} 615 616/* --------------- INIT --------------- */ 617 618static void tc358743_reset_phy(struct v4l2_subdev *sd) 619{ 620 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 621 622 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0); 623 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL); 624} 625 626static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask) 627{ 628 u16 sysctl = i2c_rd16(sd, SYSCTL); 629 630 i2c_wr16(sd, SYSCTL, sysctl | mask); 631 i2c_wr16(sd, SYSCTL, sysctl & ~mask); 632} 633 634static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable) 635{ 636 i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP, 637 enable ? MASK_SLEEP : 0); 638} 639 640static inline void enable_stream(struct v4l2_subdev *sd, bool enable) 641{ 642 struct tc358743_state *state = to_state(sd); 643 644 v4l2_dbg(3, debug, sd, "%s: %sable\n", 645 __func__, enable ? "en" : "dis"); 646 647 if (enable) { 648 /* It is critical for CSI receiver to see lane transition 649 * LP11->HS. Set to non-continuous mode to enable clock lane 650 * LP11 state. */ 651 i2c_wr32(sd, TXOPTIONCNTRL, 0); 652 /* Set to continuous mode to trigger LP11->HS transition */ 653 i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE); 654 /* Unmute video */ 655 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE); 656 } else { 657 /* Mute video so that all data lanes go to LSP11 state. 658 * No data is output to CSI Tx block. */ 659 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE); 660 } 661 662 mutex_lock(&state->confctl_mutex); 663 i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN), 664 enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0); 665 mutex_unlock(&state->confctl_mutex); 666} 667 668static void tc358743_set_pll(struct v4l2_subdev *sd) 669{ 670 struct tc358743_state *state = to_state(sd); 671 struct tc358743_platform_data *pdata = &state->pdata; 672 u16 pllctl0 = i2c_rd16(sd, PLLCTL0); 673 u16 pllctl1 = i2c_rd16(sd, PLLCTL1); 674 u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) | 675 SET_PLL_FBD(pdata->pll_fbd); 676 u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd; 677 678 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 679 680 /* Only rewrite when needed (new value or disabled), since rewriting 681 * triggers another format change event. */ 682 if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) { 683 u16 pll_frs; 684 685 if (hsck > 500000000) 686 pll_frs = 0x0; 687 else if (hsck > 250000000) 688 pll_frs = 0x1; 689 else if (hsck > 125000000) 690 pll_frs = 0x2; 691 else 692 pll_frs = 0x3; 693 694 v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__); 695 tc358743_sleep_mode(sd, true); 696 i2c_wr16(sd, PLLCTL0, pllctl0_new); 697 i2c_wr16_and_or(sd, PLLCTL1, 698 ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN), 699 (SET_PLL_FRS(pll_frs) | MASK_RESETB | 700 MASK_PLL_EN)); 701 udelay(10); /* REF_02, Sheet "Source HDMI" */ 702 i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN); 703 tc358743_sleep_mode(sd, false); 704 } 705} 706 707static void tc358743_set_ref_clk(struct v4l2_subdev *sd) 708{ 709 struct tc358743_state *state = to_state(sd); 710 struct tc358743_platform_data *pdata = &state->pdata; 711 u32 sys_freq; 712 u32 lockdet_ref; 713 u32 cec_freq; 714 u16 fh_min; 715 u16 fh_max; 716 717 BUG_ON(!(pdata->refclk_hz == 26000000 || 718 pdata->refclk_hz == 27000000 || 719 pdata->refclk_hz == 42000000)); 720 721 sys_freq = pdata->refclk_hz / 10000; 722 i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff); 723 i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8); 724 725 i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND, 726 (pdata->refclk_hz == 42000000) ? 727 MASK_PHY_SYSCLK_IND : 0x0); 728 729 fh_min = pdata->refclk_hz / 100000; 730 i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff); 731 i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8); 732 733 fh_max = (fh_min * 66) / 10; 734 i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff); 735 i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8); 736 737 lockdet_ref = pdata->refclk_hz / 100; 738 i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff); 739 i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8); 740 i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16); 741 742 i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD, 743 (pdata->refclk_hz == 27000000) ? 744 MASK_NCO_F0_MOD_27MHZ : 0x0); 745 746 /* 747 * Trial and error suggests that the default register value 748 * of 656 is for a 42 MHz reference clock. Use that to derive 749 * a new value based on the actual reference clock. 750 */ 751 cec_freq = (656 * sys_freq) / 4200; 752 i2c_wr16(sd, CECHCLK, cec_freq); 753 i2c_wr16(sd, CECLCLK, cec_freq); 754} 755 756static void tc358743_set_csi_color_space(struct v4l2_subdev *sd) 757{ 758 struct tc358743_state *state = to_state(sd); 759 760 switch (state->mbus_fmt_code) { 761 case MEDIA_BUS_FMT_UYVY8_1X16: 762 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__); 763 i2c_wr8_and_or(sd, VOUT_SET2, 764 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff, 765 MASK_SEL422 | MASK_VOUT_422FIL_100); 766 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff, 767 MASK_VOUT_COLOR_601_YCBCR_LIMITED); 768 mutex_lock(&state->confctl_mutex); 769 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 770 MASK_YCBCRFMT_422_8_BIT); 771 mutex_unlock(&state->confctl_mutex); 772 break; 773 case MEDIA_BUS_FMT_RGB888_1X24: 774 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__); 775 i2c_wr8_and_or(sd, VOUT_SET2, 776 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff, 777 0x00); 778 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff, 779 MASK_VOUT_COLOR_RGB_FULL); 780 mutex_lock(&state->confctl_mutex); 781 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0); 782 mutex_unlock(&state->confctl_mutex); 783 break; 784 default: 785 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n", 786 __func__, state->mbus_fmt_code); 787 } 788} 789 790static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd) 791{ 792 struct tc358743_state *state = to_state(sd); 793 struct v4l2_bt_timings *bt = &state->timings.bt; 794 struct tc358743_platform_data *pdata = &state->pdata; 795 u32 bits_pr_pixel = 796 (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24; 797 u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel; 798 u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd; 799 800 return DIV_ROUND_UP(bps, bps_pr_lane); 801} 802 803static void tc358743_set_csi(struct v4l2_subdev *sd) 804{ 805 struct tc358743_state *state = to_state(sd); 806 struct tc358743_platform_data *pdata = &state->pdata; 807 unsigned lanes = tc358743_num_csi_lanes_needed(sd); 808 809 v4l2_dbg(3, debug, sd, "%s:\n", __func__); 810 811 state->csi_lanes_in_use = lanes; 812 813 tc358743_reset(sd, MASK_CTXRST); 814 815 if (lanes < 1) 816 i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE); 817 if (lanes < 1) 818 i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE); 819 if (lanes < 2) 820 i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE); 821 if (lanes < 3) 822 i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE); 823 if (lanes < 4) 824 i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE); 825 826 i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt); 827 i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt); 828 i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt); 829 i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt); 830 i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt); 831 i2c_wr32(sd, TWAKEUP, pdata->twakeup); 832 i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt); 833 i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt); 834 i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt); 835 836 i2c_wr32(sd, HSTXVREGEN, 837 ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) | 838 ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) | 839 ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) | 840 ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) | 841 ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0)); 842 843 i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags & 844 V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK) ? 0 : MASK_CONTCLKMODE); 845 i2c_wr32(sd, STARTCNTRL, MASK_START); 846 i2c_wr32(sd, CSI_START, MASK_STRT); 847 848 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 849 MASK_ADDRESS_CSI_CONTROL | 850 MASK_CSI_MODE | 851 MASK_TXHSMD | 852 ((lanes == 4) ? MASK_NOL_4 : 853 (lanes == 3) ? MASK_NOL_3 : 854 (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1)); 855 856 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 857 MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK | 858 MASK_WCER | MASK_INER); 859 860 i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR | 861 MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK); 862 863 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 864 MASK_ADDRESS_CSI_INT_ENA | MASK_INTER); 865} 866 867static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd) 868{ 869 struct tc358743_state *state = to_state(sd); 870 struct tc358743_platform_data *pdata = &state->pdata; 871 872 /* Default settings from REF_02, sheet "Source HDMI" 873 * and custom settings as platform data */ 874 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0); 875 i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) | 876 SET_FREQ_RANGE_MODE_CYCLES(1)); 877 i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn, 878 (pdata->hdmi_phy_auto_reset_tmds_detected ? 879 MASK_PHY_AUTO_RST2 : 0) | 880 (pdata->hdmi_phy_auto_reset_tmds_in_range ? 881 MASK_PHY_AUTO_RST3 : 0) | 882 (pdata->hdmi_phy_auto_reset_tmds_valid ? 883 MASK_PHY_AUTO_RST4 : 0)); 884 i2c_wr8(sd, PHY_BIAS, 0x40); 885 i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a)); 886 i2c_wr8(sd, AVM_CTL, 45); 887 i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V, 888 pdata->hdmi_detection_delay << 4); 889 i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST), 890 (pdata->hdmi_phy_auto_reset_hsync_out_of_range ? 891 MASK_H_PI_RST : 0) | 892 (pdata->hdmi_phy_auto_reset_vsync_out_of_range ? 893 MASK_V_PI_RST : 0)); 894 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY); 895} 896 897static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd) 898{ 899 struct tc358743_state *state = to_state(sd); 900 901 /* Default settings from REF_02, sheet "Source HDMI" */ 902 i2c_wr8(sd, FORCE_MUTE, 0x00); 903 i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 | 904 MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 | 905 MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0); 906 i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9); 907 i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2); 908 i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500)); 909 i2c_wr8(sd, FS_MUTE, 0x00); 910 i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE); 911 i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE); 912 i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM); 913 i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM); 914 i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S); 915 i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100)); 916 917 mutex_lock(&state->confctl_mutex); 918 i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 | 919 MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX); 920 mutex_unlock(&state->confctl_mutex); 921} 922 923static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd) 924{ 925 /* Default settings from REF_02, sheet "Source HDMI" */ 926 i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE | 927 MASK_ACP_INT_MODE | MASK_VS_INT_MODE | 928 MASK_SPD_INT_MODE | MASK_MS_INT_MODE | 929 MASK_AUD_INT_MODE | MASK_AVI_INT_MODE); 930 i2c_wr8(sd, NO_PKT_LIMIT, 0x2c); 931 i2c_wr8(sd, NO_PKT_CLR, 0x53); 932 i2c_wr8(sd, ERR_PK_LIMIT, 0x01); 933 i2c_wr8(sd, NO_PKT_LIMIT2, 0x30); 934 i2c_wr8(sd, NO_GDB_LIMIT, 0x10); 935} 936 937static void tc358743_initial_setup(struct v4l2_subdev *sd) 938{ 939 struct tc358743_state *state = to_state(sd); 940 struct tc358743_platform_data *pdata = &state->pdata; 941 942 /* 943 * IR is not supported by this driver. 944 * CEC is only enabled if needed. 945 */ 946 i2c_wr16_and_or(sd, SYSCTL, ~(MASK_IRRST | MASK_CECRST), 947 (MASK_IRRST | MASK_CECRST)); 948 949 tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST); 950#ifdef CONFIG_VIDEO_TC358743_CEC 951 tc358743_reset(sd, MASK_CECRST); 952#endif 953 tc358743_sleep_mode(sd, false); 954 955 i2c_wr16(sd, FIFOCTL, pdata->fifo_level); 956 957 tc358743_set_ref_clk(sd); 958 959 i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE, 960 pdata->ddc5v_delay & MASK_DDC5V_MODE); 961 i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC); 962 963 tc358743_set_hdmi_phy(sd); 964 tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp); 965 tc358743_set_hdmi_audio(sd); 966 tc358743_set_hdmi_info_frame_mode(sd); 967 968 /* All CE and IT formats are detected as RGB full range in DVI mode */ 969 i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0); 970 971 i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE, 972 MASK_VOUTCOLORMODE_AUTO); 973 i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT); 974} 975 976/* --------------- CEC --------------- */ 977 978#ifdef CONFIG_VIDEO_TC358743_CEC 979static int tc358743_cec_adap_enable(struct cec_adapter *adap, bool enable) 980{ 981 struct tc358743_state *state = adap->priv; 982 struct v4l2_subdev *sd = &state->sd; 983 984 i2c_wr32(sd, CECIMSK, enable ? MASK_CECTIM | MASK_CECRIM : 0); 985 i2c_wr32(sd, CECICLR, MASK_CECTICLR | MASK_CECRICLR); 986 i2c_wr32(sd, CECEN, enable); 987 if (enable) 988 i2c_wr32(sd, CECREN, MASK_CECREN); 989 return 0; 990} 991 992static int tc358743_cec_adap_monitor_all_enable(struct cec_adapter *adap, 993 bool enable) 994{ 995 struct tc358743_state *state = adap->priv; 996 struct v4l2_subdev *sd = &state->sd; 997 u32 reg; 998 999 reg = i2c_rd32(sd, CECRCTL1); 1000 if (enable) 1001 reg |= MASK_CECOTH; 1002 else 1003 reg &= ~MASK_CECOTH; 1004 i2c_wr32(sd, CECRCTL1, reg); 1005 return 0; 1006} 1007 1008static int tc358743_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 1009{ 1010 struct tc358743_state *state = adap->priv; 1011 struct v4l2_subdev *sd = &state->sd; 1012 unsigned int la = 0; 1013 1014 if (log_addr != CEC_LOG_ADDR_INVALID) { 1015 la = i2c_rd32(sd, CECADD); 1016 la |= 1 << log_addr; 1017 } 1018 i2c_wr32(sd, CECADD, la); 1019 return 0; 1020} 1021 1022static int tc358743_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 1023 u32 signal_free_time, struct cec_msg *msg) 1024{ 1025 struct tc358743_state *state = adap->priv; 1026 struct v4l2_subdev *sd = &state->sd; 1027 unsigned int i; 1028 1029 i2c_wr32(sd, CECTCTL, 1030 (cec_msg_is_broadcast(msg) ? MASK_CECBRD : 0) | 1031 (signal_free_time - 1)); 1032 for (i = 0; i < msg->len; i++) 1033 i2c_wr32(sd, CECTBUF1 + i * 4, 1034 msg->msg[i] | ((i == msg->len - 1) ? MASK_CECTEOM : 0)); 1035 i2c_wr32(sd, CECTEN, MASK_CECTEN); 1036 return 0; 1037} 1038 1039static const struct cec_adap_ops tc358743_cec_adap_ops = { 1040 .adap_enable = tc358743_cec_adap_enable, 1041 .adap_log_addr = tc358743_cec_adap_log_addr, 1042 .adap_transmit = tc358743_cec_adap_transmit, 1043 .adap_monitor_all_enable = tc358743_cec_adap_monitor_all_enable, 1044}; 1045 1046static void tc358743_cec_handler(struct v4l2_subdev *sd, u16 intstatus, 1047 bool *handled) 1048{ 1049 struct tc358743_state *state = to_state(sd); 1050 unsigned int cec_rxint, cec_txint; 1051 unsigned int clr = 0; 1052 1053 cec_rxint = i2c_rd32(sd, CECRSTAT); 1054 cec_txint = i2c_rd32(sd, CECTSTAT); 1055 1056 if (intstatus & MASK_CEC_RINT) 1057 clr |= MASK_CECRICLR; 1058 if (intstatus & MASK_CEC_TINT) 1059 clr |= MASK_CECTICLR; 1060 i2c_wr32(sd, CECICLR, clr); 1061 1062 if ((intstatus & MASK_CEC_TINT) && cec_txint) { 1063 if (cec_txint & MASK_CECTIEND) 1064 cec_transmit_attempt_done(state->cec_adap, 1065 CEC_TX_STATUS_OK); 1066 else if (cec_txint & MASK_CECTIAL) 1067 cec_transmit_attempt_done(state->cec_adap, 1068 CEC_TX_STATUS_ARB_LOST); 1069 else if (cec_txint & MASK_CECTIACK) 1070 cec_transmit_attempt_done(state->cec_adap, 1071 CEC_TX_STATUS_NACK); 1072 else if (cec_txint & MASK_CECTIUR) { 1073 /* 1074 * Not sure when this bit is set. Treat 1075 * it as an error for now. 1076 */ 1077 cec_transmit_attempt_done(state->cec_adap, 1078 CEC_TX_STATUS_ERROR); 1079 } 1080 if (handled) 1081 *handled = true; 1082 } 1083 if ((intstatus & MASK_CEC_RINT) && 1084 (cec_rxint & MASK_CECRIEND)) { 1085 struct cec_msg msg = {}; 1086 unsigned int i; 1087 unsigned int v; 1088 1089 v = i2c_rd32(sd, CECRCTR); 1090 msg.len = v & 0x1f; 1091 if (msg.len > CEC_MAX_MSG_SIZE) 1092 msg.len = CEC_MAX_MSG_SIZE; 1093 for (i = 0; i < msg.len; i++) { 1094 v = i2c_rd32(sd, CECRBUF1 + i * 4); 1095 msg.msg[i] = v & 0xff; 1096 } 1097 cec_received_msg(state->cec_adap, &msg); 1098 if (handled) 1099 *handled = true; 1100 } 1101 i2c_wr16(sd, INTSTATUS, 1102 intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)); 1103} 1104 1105#endif 1106 1107/* --------------- IRQ --------------- */ 1108 1109static void tc358743_format_change(struct v4l2_subdev *sd) 1110{ 1111 struct tc358743_state *state = to_state(sd); 1112 struct v4l2_dv_timings timings; 1113 const struct v4l2_event tc358743_ev_fmt = { 1114 .type = V4L2_EVENT_SOURCE_CHANGE, 1115 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 1116 }; 1117 1118 if (tc358743_get_detected_timings(sd, &timings)) { 1119 enable_stream(sd, false); 1120 1121 v4l2_dbg(1, debug, sd, "%s: No signal\n", 1122 __func__); 1123 } else { 1124 if (!v4l2_match_dv_timings(&state->timings, &timings, 0, false)) 1125 enable_stream(sd, false); 1126 1127 if (debug) 1128 v4l2_print_dv_timings(sd->name, 1129 "tc358743_format_change: New format: ", 1130 &timings, false); 1131 } 1132 1133 if (sd->devnode) 1134 v4l2_subdev_notify_event(sd, &tc358743_ev_fmt); 1135} 1136 1137static void tc358743_init_interrupts(struct v4l2_subdev *sd) 1138{ 1139 u16 i; 1140 1141 /* clear interrupt status registers */ 1142 for (i = SYS_INT; i <= KEY_INT; i++) 1143 i2c_wr8(sd, i, 0xff); 1144 1145 i2c_wr16(sd, INTSTATUS, 0xffff); 1146} 1147 1148static void tc358743_enable_interrupts(struct v4l2_subdev *sd, 1149 bool cable_connected) 1150{ 1151 v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__, 1152 cable_connected); 1153 1154 if (cable_connected) { 1155 i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET | 1156 MASK_M_HDMI_DET) & 0xff); 1157 i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG); 1158 i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK | 1159 MASK_M_AF_UNLOCK) & 0xff); 1160 i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END); 1161 i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG); 1162 } else { 1163 i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff); 1164 i2c_wr8(sd, CLK_INTM, 0xff); 1165 i2c_wr8(sd, CBIT_INTM, 0xff); 1166 i2c_wr8(sd, AUDIO_INTM, 0xff); 1167 i2c_wr8(sd, MISC_INTM, 0xff); 1168 } 1169} 1170 1171static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd, 1172 bool *handled) 1173{ 1174 u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM); 1175 u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask; 1176 1177 i2c_wr8(sd, AUDIO_INT, audio_int); 1178 1179 v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int); 1180 1181 tc358743_s_ctrl_audio_sampling_rate(sd); 1182 tc358743_s_ctrl_audio_present(sd); 1183} 1184 1185static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled) 1186{ 1187 v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR)); 1188 1189 i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER); 1190} 1191 1192static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd, 1193 bool *handled) 1194{ 1195 u8 misc_int_mask = i2c_rd8(sd, MISC_INTM); 1196 u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask; 1197 1198 i2c_wr8(sd, MISC_INT, misc_int); 1199 1200 v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int); 1201 1202 if (misc_int & MASK_I_SYNC_CHG) { 1203 /* Reset the HDMI PHY to try to trigger proper lock on the 1204 * incoming video format. Erase BKSV to prevent that old keys 1205 * are used when a new source is connected. */ 1206 if (no_sync(sd) || no_signal(sd)) { 1207 tc358743_reset_phy(sd); 1208 tc358743_erase_bksv(sd); 1209 } 1210 1211 tc358743_format_change(sd); 1212 1213 misc_int &= ~MASK_I_SYNC_CHG; 1214 if (handled) 1215 *handled = true; 1216 } 1217 1218 if (misc_int) { 1219 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n", 1220 __func__, misc_int); 1221 } 1222} 1223 1224static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd, 1225 bool *handled) 1226{ 1227 u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM); 1228 u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask; 1229 1230 i2c_wr8(sd, CBIT_INT, cbit_int); 1231 1232 v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int); 1233 1234 if (cbit_int & MASK_I_CBIT_FS) { 1235 1236 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n", 1237 __func__); 1238 tc358743_s_ctrl_audio_sampling_rate(sd); 1239 1240 cbit_int &= ~MASK_I_CBIT_FS; 1241 if (handled) 1242 *handled = true; 1243 } 1244 1245 if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) { 1246 1247 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n", 1248 __func__); 1249 tc358743_s_ctrl_audio_present(sd); 1250 1251 cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK); 1252 if (handled) 1253 *handled = true; 1254 } 1255 1256 if (cbit_int) { 1257 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n", 1258 __func__, cbit_int); 1259 } 1260} 1261 1262static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled) 1263{ 1264 u8 clk_int_mask = i2c_rd8(sd, CLK_INTM); 1265 u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask; 1266 1267 /* Bit 7 and bit 6 are set even when they are masked */ 1268 i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG); 1269 1270 v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int); 1271 1272 if (clk_int & (MASK_I_IN_DE_CHG)) { 1273 1274 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n", 1275 __func__); 1276 1277 /* If the source switch to a new resolution with the same pixel 1278 * frequency as the existing (e.g. 1080p25 -> 720p50), the 1279 * I_SYNC_CHG interrupt is not always triggered, while the 1280 * I_IN_DE_CHG interrupt seems to work fine. Format change 1281 * notifications are only sent when the signal is stable to 1282 * reduce the number of notifications. */ 1283 if (!no_signal(sd) && !no_sync(sd)) 1284 tc358743_format_change(sd); 1285 1286 clk_int &= ~(MASK_I_IN_DE_CHG); 1287 if (handled) 1288 *handled = true; 1289 } 1290 1291 if (clk_int) { 1292 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n", 1293 __func__, clk_int); 1294 } 1295} 1296 1297static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled) 1298{ 1299 struct tc358743_state *state = to_state(sd); 1300 u8 sys_int_mask = i2c_rd8(sd, SYS_INTM); 1301 u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask; 1302 1303 i2c_wr8(sd, SYS_INT, sys_int); 1304 1305 v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int); 1306 1307 if (sys_int & MASK_I_DDC) { 1308 bool tx_5v = tx_5v_power_present(sd); 1309 1310 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n", 1311 __func__, tx_5v ? "yes" : "no"); 1312 1313 if (tx_5v) { 1314 tc358743_enable_edid(sd); 1315 } else { 1316 tc358743_enable_interrupts(sd, false); 1317 tc358743_disable_edid(sd); 1318 memset(&state->timings, 0, sizeof(state->timings)); 1319 tc358743_erase_bksv(sd); 1320 tc358743_update_controls(sd); 1321 } 1322 1323 sys_int &= ~MASK_I_DDC; 1324 if (handled) 1325 *handled = true; 1326 } 1327 1328 if (sys_int & MASK_I_DVI) { 1329 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n", 1330 __func__); 1331 1332 /* Reset the HDMI PHY to try to trigger proper lock on the 1333 * incoming video format. Erase BKSV to prevent that old keys 1334 * are used when a new source is connected. */ 1335 if (no_sync(sd) || no_signal(sd)) { 1336 tc358743_reset_phy(sd); 1337 tc358743_erase_bksv(sd); 1338 } 1339 1340 sys_int &= ~MASK_I_DVI; 1341 if (handled) 1342 *handled = true; 1343 } 1344 1345 if (sys_int & MASK_I_HDMI) { 1346 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n", 1347 __func__); 1348 1349 /* Register is reset in DVI mode (REF_01, c. 6.6.41) */ 1350 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON); 1351 1352 sys_int &= ~MASK_I_HDMI; 1353 if (handled) 1354 *handled = true; 1355 } 1356 1357 if (sys_int) { 1358 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n", 1359 __func__, sys_int); 1360 } 1361} 1362 1363/* --------------- CORE OPS --------------- */ 1364 1365static int tc358743_log_status(struct v4l2_subdev *sd) 1366{ 1367 struct tc358743_state *state = to_state(sd); 1368 struct v4l2_dv_timings timings; 1369 uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS); 1370 uint16_t sysctl = i2c_rd16(sd, SYSCTL); 1371 u8 vi_status3 = i2c_rd8(sd, VI_STATUS3); 1372 const int deep_color_mode[4] = { 8, 10, 12, 16 }; 1373 static const char * const input_color_space[] = { 1374 "RGB", "YCbCr 601", "opRGB", "YCbCr 709", "NA (4)", 1375 "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601", 1376 "NA(10)", "NA(11)", "NA(12)", "opYCC 601"}; 1377 1378 v4l2_info(sd, "-----Chip status-----\n"); 1379 v4l2_info(sd, "Chip ID: 0x%02x\n", 1380 (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8); 1381 v4l2_info(sd, "Chip revision: 0x%02x\n", 1382 i2c_rd16(sd, CHIPID) & MASK_REVID); 1383 v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n", 1384 !!(sysctl & MASK_IRRST), 1385 !!(sysctl & MASK_CECRST), 1386 !!(sysctl & MASK_CTXRST), 1387 !!(sysctl & MASK_HDMIRST)); 1388 v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off"); 1389 v4l2_info(sd, "Cable detected (+5V power): %s\n", 1390 hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no"); 1391 v4l2_info(sd, "DDC lines enabled: %s\n", 1392 (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ? 1393 "yes" : "no"); 1394 v4l2_info(sd, "Hotplug enabled: %s\n", 1395 (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ? 1396 "yes" : "no"); 1397 v4l2_info(sd, "CEC enabled: %s\n", 1398 (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no"); 1399 v4l2_info(sd, "-----Signal status-----\n"); 1400 v4l2_info(sd, "TMDS signal detected: %s\n", 1401 hdmi_sys_status & MASK_S_TMDS ? "yes" : "no"); 1402 v4l2_info(sd, "Stable sync signal: %s\n", 1403 hdmi_sys_status & MASK_S_SYNC ? "yes" : "no"); 1404 v4l2_info(sd, "PHY PLL locked: %s\n", 1405 hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no"); 1406 v4l2_info(sd, "PHY DE detected: %s\n", 1407 hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no"); 1408 1409 if (tc358743_get_detected_timings(sd, &timings)) { 1410 v4l2_info(sd, "No video detected\n"); 1411 } else { 1412 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings, 1413 true); 1414 } 1415 v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings, 1416 true); 1417 1418 v4l2_info(sd, "-----CSI-TX status-----\n"); 1419 v4l2_info(sd, "Lanes needed: %d\n", 1420 tc358743_num_csi_lanes_needed(sd)); 1421 v4l2_info(sd, "Lanes in use: %d\n", 1422 state->csi_lanes_in_use); 1423 v4l2_info(sd, "Waiting for particular sync signal: %s\n", 1424 (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ? 1425 "yes" : "no"); 1426 v4l2_info(sd, "Transmit mode: %s\n", 1427 (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ? 1428 "yes" : "no"); 1429 v4l2_info(sd, "Receive mode: %s\n", 1430 (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ? 1431 "yes" : "no"); 1432 v4l2_info(sd, "Stopped: %s\n", 1433 (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ? 1434 "yes" : "no"); 1435 v4l2_info(sd, "Color space: %s\n", 1436 state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ? 1437 "YCbCr 422 16-bit" : 1438 state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ? 1439 "RGB 888 24-bit" : "Unsupported"); 1440 1441 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 1442 v4l2_info(sd, "HDCP encrypted content: %s\n", 1443 hdmi_sys_status & MASK_S_HDCP ? "yes" : "no"); 1444 v4l2_info(sd, "Input color space: %s %s range\n", 1445 input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1], 1446 (vi_status3 & MASK_LIMITED) ? "limited" : "full"); 1447 if (!is_hdmi(sd)) 1448 return 0; 1449 v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" : 1450 "off"); 1451 v4l2_info(sd, "Deep color mode: %d-bits per channel\n", 1452 deep_color_mode[(i2c_rd8(sd, VI_STATUS1) & 1453 MASK_S_DEEPCOLOR) >> 2]); 1454 print_infoframes(sd); 1455 1456 return 0; 1457} 1458 1459#ifdef CONFIG_VIDEO_ADV_DEBUG 1460static void tc358743_print_register_map(struct v4l2_subdev *sd) 1461{ 1462 v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n"); 1463 v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n"); 1464 v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n"); 1465 v4l2_info(sd, "0x0400-0x05FF: Reserved\n"); 1466 v4l2_info(sd, "0x0600-0x06FF: CEC Register\n"); 1467 v4l2_info(sd, "0x0700-0x84FF: Reserved\n"); 1468 v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n"); 1469 v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n"); 1470 v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n"); 1471 v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n"); 1472 v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n"); 1473 v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n"); 1474 v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n"); 1475 v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n"); 1476 v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n"); 1477 v4l2_info(sd, "0x9300- : Reserved\n"); 1478} 1479 1480static int tc358743_get_reg_size(u16 address) 1481{ 1482 /* REF_01 p. 66-72 */ 1483 if (address <= 0x00ff) 1484 return 2; 1485 else if ((address >= 0x0100) && (address <= 0x06FF)) 1486 return 4; 1487 else if ((address >= 0x0700) && (address <= 0x84ff)) 1488 return 2; 1489 else 1490 return 1; 1491} 1492 1493static int tc358743_g_register(struct v4l2_subdev *sd, 1494 struct v4l2_dbg_register *reg) 1495{ 1496 if (reg->reg > 0xffff) { 1497 tc358743_print_register_map(sd); 1498 return -EINVAL; 1499 } 1500 1501 reg->size = tc358743_get_reg_size(reg->reg); 1502 1503 reg->val = i2c_rdreg(sd, reg->reg, reg->size); 1504 1505 return 0; 1506} 1507 1508static int tc358743_s_register(struct v4l2_subdev *sd, 1509 const struct v4l2_dbg_register *reg) 1510{ 1511 if (reg->reg > 0xffff) { 1512 tc358743_print_register_map(sd); 1513 return -EINVAL; 1514 } 1515 1516 /* It should not be possible for the user to enable HDCP with a simple 1517 * v4l2-dbg command. 1518 * 1519 * DO NOT REMOVE THIS unless all other issues with HDCP have been 1520 * resolved. 1521 */ 1522 if (reg->reg == HDCP_MODE || 1523 reg->reg == HDCP_REG1 || 1524 reg->reg == HDCP_REG2 || 1525 reg->reg == HDCP_REG3 || 1526 reg->reg == BCAPS) 1527 return 0; 1528 1529 i2c_wrreg(sd, (u16)reg->reg, reg->val, 1530 tc358743_get_reg_size(reg->reg)); 1531 1532 return 0; 1533} 1534#endif 1535 1536static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 1537{ 1538 u16 intstatus = i2c_rd16(sd, INTSTATUS); 1539 1540 v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus); 1541 1542 if (intstatus & MASK_HDMI_INT) { 1543 u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0); 1544 u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1); 1545 1546 if (hdmi_int0 & MASK_I_MISC) 1547 tc358743_hdmi_misc_int_handler(sd, handled); 1548 if (hdmi_int1 & MASK_I_CBIT) 1549 tc358743_hdmi_cbit_int_handler(sd, handled); 1550 if (hdmi_int1 & MASK_I_CLK) 1551 tc358743_hdmi_clk_int_handler(sd, handled); 1552 if (hdmi_int1 & MASK_I_SYS) 1553 tc358743_hdmi_sys_int_handler(sd, handled); 1554 if (hdmi_int1 & MASK_I_AUD) 1555 tc358743_hdmi_audio_int_handler(sd, handled); 1556 1557 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT); 1558 intstatus &= ~MASK_HDMI_INT; 1559 } 1560 1561#ifdef CONFIG_VIDEO_TC358743_CEC 1562 if (intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)) { 1563 tc358743_cec_handler(sd, intstatus, handled); 1564 i2c_wr16(sd, INTSTATUS, 1565 intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)); 1566 intstatus &= ~(MASK_CEC_RINT | MASK_CEC_TINT); 1567 } 1568#endif 1569 1570 if (intstatus & MASK_CSI_INT) { 1571 u32 csi_int = i2c_rd32(sd, CSI_INT); 1572 1573 if (csi_int & MASK_INTER) 1574 tc358743_csi_err_int_handler(sd, handled); 1575 1576 i2c_wr16(sd, INTSTATUS, MASK_CSI_INT); 1577 } 1578 1579 intstatus = i2c_rd16(sd, INTSTATUS); 1580 if (intstatus) { 1581 v4l2_dbg(1, debug, sd, 1582 "%s: Unhandled IntStatus interrupts: 0x%02x\n", 1583 __func__, intstatus); 1584 } 1585 1586 return 0; 1587} 1588 1589static irqreturn_t tc358743_irq_handler(int irq, void *dev_id) 1590{ 1591 struct tc358743_state *state = dev_id; 1592 bool handled = false; 1593 1594 tc358743_isr(&state->sd, 0, &handled); 1595 1596 return handled ? IRQ_HANDLED : IRQ_NONE; 1597} 1598 1599static void tc358743_irq_poll_timer(struct timer_list *t) 1600{ 1601 struct tc358743_state *state = timer_container_of(state, t, timer); 1602 unsigned int msecs; 1603 1604 schedule_work(&state->work_i2c_poll); 1605 /* 1606 * If CEC is present, then we need to poll more frequently, 1607 * otherwise we will miss CEC messages. 1608 */ 1609 msecs = state->cec_adap ? POLL_INTERVAL_CEC_MS : POLL_INTERVAL_MS; 1610 mod_timer(&state->timer, jiffies + msecs_to_jiffies(msecs)); 1611} 1612 1613static void tc358743_work_i2c_poll(struct work_struct *work) 1614{ 1615 struct tc358743_state *state = container_of(work, 1616 struct tc358743_state, work_i2c_poll); 1617 bool handled; 1618 1619 tc358743_isr(&state->sd, 0, &handled); 1620} 1621 1622static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, 1623 struct v4l2_event_subscription *sub) 1624{ 1625 switch (sub->type) { 1626 case V4L2_EVENT_SOURCE_CHANGE: 1627 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 1628 case V4L2_EVENT_CTRL: 1629 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 1630 default: 1631 return -EINVAL; 1632 } 1633} 1634 1635/* --------------- VIDEO OPS --------------- */ 1636 1637static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status) 1638{ 1639 *status = 0; 1640 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 1641 *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0; 1642 1643 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 1644 1645 return 0; 1646} 1647 1648static int tc358743_s_dv_timings(struct v4l2_subdev *sd, unsigned int pad, 1649 struct v4l2_dv_timings *timings) 1650{ 1651 struct tc358743_state *state = to_state(sd); 1652 1653 if (pad != 0) 1654 return -EINVAL; 1655 1656 if (!timings) 1657 return -EINVAL; 1658 1659 if (debug) 1660 v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ", 1661 timings, false); 1662 1663 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { 1664 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1665 return 0; 1666 } 1667 1668 if (!v4l2_valid_dv_timings(timings, 1669 &tc358743_timings_cap, NULL, NULL)) { 1670 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__); 1671 return -ERANGE; 1672 } 1673 1674 state->timings = *timings; 1675 1676 enable_stream(sd, false); 1677 tc358743_set_pll(sd); 1678 tc358743_set_csi(sd); 1679 1680 return 0; 1681} 1682 1683static int tc358743_g_dv_timings(struct v4l2_subdev *sd, unsigned int pad, 1684 struct v4l2_dv_timings *timings) 1685{ 1686 struct tc358743_state *state = to_state(sd); 1687 1688 if (pad != 0) 1689 return -EINVAL; 1690 1691 *timings = state->timings; 1692 1693 return 0; 1694} 1695 1696static int tc358743_enum_dv_timings(struct v4l2_subdev *sd, 1697 struct v4l2_enum_dv_timings *timings) 1698{ 1699 if (timings->pad != 0) 1700 return -EINVAL; 1701 1702 return v4l2_enum_dv_timings_cap(timings, 1703 &tc358743_timings_cap, NULL, NULL); 1704} 1705 1706static int tc358743_query_dv_timings(struct v4l2_subdev *sd, unsigned int pad, 1707 struct v4l2_dv_timings *timings) 1708{ 1709 int ret; 1710 1711 if (pad != 0) 1712 return -EINVAL; 1713 1714 ret = tc358743_get_detected_timings(sd, timings); 1715 if (ret) 1716 return ret; 1717 1718 if (debug) 1719 v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ", 1720 timings, false); 1721 1722 if (!v4l2_valid_dv_timings(timings, 1723 &tc358743_timings_cap, NULL, NULL)) { 1724 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__); 1725 return -ERANGE; 1726 } 1727 1728 return 0; 1729} 1730 1731static int tc358743_dv_timings_cap(struct v4l2_subdev *sd, 1732 struct v4l2_dv_timings_cap *cap) 1733{ 1734 if (cap->pad != 0) 1735 return -EINVAL; 1736 1737 *cap = tc358743_timings_cap; 1738 1739 return 0; 1740} 1741 1742static int tc358743_get_mbus_config(struct v4l2_subdev *sd, 1743 unsigned int pad, 1744 struct v4l2_mbus_config *cfg) 1745{ 1746 struct tc358743_state *state = to_state(sd); 1747 1748 cfg->type = V4L2_MBUS_CSI2_DPHY; 1749 1750 /* Support for non-continuous CSI-2 clock is missing in the driver */ 1751 cfg->bus.mipi_csi2.flags = 0; 1752 cfg->bus.mipi_csi2.num_data_lanes = state->csi_lanes_in_use; 1753 1754 return 0; 1755} 1756 1757static int tc358743_s_stream(struct v4l2_subdev *sd, int enable) 1758{ 1759 enable_stream(sd, enable); 1760 if (!enable) { 1761 /* Put all lanes in LP-11 state (STOPSTATE) */ 1762 tc358743_set_csi(sd); 1763 } 1764 1765 return 0; 1766} 1767 1768/* --------------- PAD OPS --------------- */ 1769 1770static int tc358743_enum_mbus_code(struct v4l2_subdev *sd, 1771 struct v4l2_subdev_state *sd_state, 1772 struct v4l2_subdev_mbus_code_enum *code) 1773{ 1774 switch (code->index) { 1775 case 0: 1776 code->code = MEDIA_BUS_FMT_RGB888_1X24; 1777 break; 1778 case 1: 1779 code->code = MEDIA_BUS_FMT_UYVY8_1X16; 1780 break; 1781 default: 1782 return -EINVAL; 1783 } 1784 return 0; 1785} 1786 1787static u32 tc358743_g_colorspace(u32 code) 1788{ 1789 switch (code) { 1790 case MEDIA_BUS_FMT_RGB888_1X24: 1791 return V4L2_COLORSPACE_SRGB; 1792 case MEDIA_BUS_FMT_UYVY8_1X16: 1793 return V4L2_COLORSPACE_SMPTE170M; 1794 default: 1795 return 0; 1796 } 1797} 1798 1799static int tc358743_get_fmt(struct v4l2_subdev *sd, 1800 struct v4l2_subdev_state *sd_state, 1801 struct v4l2_subdev_format *format) 1802{ 1803 struct tc358743_state *state = to_state(sd); 1804 1805 if (format->pad != 0) 1806 return -EINVAL; 1807 1808 format->format.code = state->mbus_fmt_code; 1809 format->format.width = state->timings.bt.width; 1810 format->format.height = state->timings.bt.height; 1811 format->format.field = V4L2_FIELD_NONE; 1812 1813 format->format.colorspace = tc358743_g_colorspace(format->format.code); 1814 1815 return 0; 1816} 1817 1818static int tc358743_set_fmt(struct v4l2_subdev *sd, 1819 struct v4l2_subdev_state *sd_state, 1820 struct v4l2_subdev_format *format) 1821{ 1822 struct tc358743_state *state = to_state(sd); 1823 1824 u32 code = format->format.code; /* is overwritten by get_fmt */ 1825 int ret = tc358743_get_fmt(sd, sd_state, format); 1826 1827 if (code == MEDIA_BUS_FMT_RGB888_1X24 || 1828 code == MEDIA_BUS_FMT_UYVY8_1X16) 1829 format->format.code = code; 1830 format->format.colorspace = tc358743_g_colorspace(format->format.code); 1831 1832 if (ret) 1833 return ret; 1834 1835 if (format->which == V4L2_SUBDEV_FORMAT_TRY) 1836 return 0; 1837 1838 state->mbus_fmt_code = format->format.code; 1839 1840 enable_stream(sd, false); 1841 tc358743_set_pll(sd); 1842 tc358743_set_csi(sd); 1843 tc358743_set_csi_color_space(sd); 1844 1845 return 0; 1846} 1847 1848static int tc358743_g_edid(struct v4l2_subdev *sd, 1849 struct v4l2_subdev_edid *edid) 1850{ 1851 struct tc358743_state *state = to_state(sd); 1852 1853 memset(edid->reserved, 0, sizeof(edid->reserved)); 1854 1855 if (edid->pad != 0) 1856 return -EINVAL; 1857 1858 if (edid->start_block == 0 && edid->blocks == 0) { 1859 edid->blocks = state->edid_blocks_written; 1860 return 0; 1861 } 1862 1863 if (state->edid_blocks_written == 0) 1864 return -ENODATA; 1865 1866 if (edid->start_block >= state->edid_blocks_written || 1867 edid->blocks == 0) 1868 return -EINVAL; 1869 1870 if (edid->start_block + edid->blocks > state->edid_blocks_written) 1871 edid->blocks = state->edid_blocks_written - edid->start_block; 1872 1873 i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid, 1874 edid->blocks * EDID_BLOCK_SIZE); 1875 1876 return 0; 1877} 1878 1879static int tc358743_s_edid(struct v4l2_subdev *sd, 1880 struct v4l2_subdev_edid *edid) 1881{ 1882 struct tc358743_state *state = to_state(sd); 1883 u16 edid_len = edid->blocks * EDID_BLOCK_SIZE; 1884 u16 pa; 1885 int err; 1886 int i; 1887 1888 v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n", 1889 __func__, edid->pad, edid->start_block, edid->blocks); 1890 1891 memset(edid->reserved, 0, sizeof(edid->reserved)); 1892 1893 if (edid->pad != 0) 1894 return -EINVAL; 1895 1896 if (edid->start_block != 0) 1897 return -EINVAL; 1898 1899 if (edid->blocks > EDID_NUM_BLOCKS_MAX) { 1900 edid->blocks = EDID_NUM_BLOCKS_MAX; 1901 return -E2BIG; 1902 } 1903 pa = cec_get_edid_phys_addr(edid->edid, edid->blocks * 128, NULL); 1904 err = v4l2_phys_addr_validate(pa, &pa, NULL); 1905 if (err) 1906 return err; 1907 1908 cec_phys_addr_invalidate(state->cec_adap); 1909 1910 tc358743_disable_edid(sd); 1911 1912 i2c_wr8(sd, EDID_LEN1, edid_len & 0xff); 1913 i2c_wr8(sd, EDID_LEN2, edid_len >> 8); 1914 1915 if (edid->blocks == 0) { 1916 state->edid_blocks_written = 0; 1917 return 0; 1918 } 1919 1920 for (i = 0; i < edid_len; i += EDID_BLOCK_SIZE) 1921 i2c_wr(sd, EDID_RAM + i, edid->edid + i, EDID_BLOCK_SIZE); 1922 1923 state->edid_blocks_written = edid->blocks; 1924 1925 cec_s_phys_addr(state->cec_adap, pa, false); 1926 1927 if (tx_5v_power_present(sd)) 1928 tc358743_enable_edid(sd); 1929 1930 return 0; 1931} 1932 1933/* -------------------------------------------------------------------------- */ 1934 1935static const struct v4l2_subdev_core_ops tc358743_core_ops = { 1936 .log_status = tc358743_log_status, 1937#ifdef CONFIG_VIDEO_ADV_DEBUG 1938 .g_register = tc358743_g_register, 1939 .s_register = tc358743_s_register, 1940#endif 1941 .interrupt_service_routine = tc358743_isr, 1942 .subscribe_event = tc358743_subscribe_event, 1943 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1944}; 1945 1946static const struct v4l2_subdev_video_ops tc358743_video_ops = { 1947 .g_input_status = tc358743_g_input_status, 1948 .s_stream = tc358743_s_stream, 1949}; 1950 1951static const struct v4l2_subdev_pad_ops tc358743_pad_ops = { 1952 .enum_mbus_code = tc358743_enum_mbus_code, 1953 .set_fmt = tc358743_set_fmt, 1954 .get_fmt = tc358743_get_fmt, 1955 .get_edid = tc358743_g_edid, 1956 .set_edid = tc358743_s_edid, 1957 .s_dv_timings = tc358743_s_dv_timings, 1958 .g_dv_timings = tc358743_g_dv_timings, 1959 .query_dv_timings = tc358743_query_dv_timings, 1960 .enum_dv_timings = tc358743_enum_dv_timings, 1961 .dv_timings_cap = tc358743_dv_timings_cap, 1962 .get_mbus_config = tc358743_get_mbus_config, 1963}; 1964 1965static const struct v4l2_subdev_ops tc358743_ops = { 1966 .core = &tc358743_core_ops, 1967 .video = &tc358743_video_ops, 1968 .pad = &tc358743_pad_ops, 1969}; 1970 1971/* --------------- CUSTOM CTRLS --------------- */ 1972 1973static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = { 1974 .id = TC358743_CID_AUDIO_SAMPLING_RATE, 1975 .name = "Audio sampling rate", 1976 .type = V4L2_CTRL_TYPE_INTEGER, 1977 .min = 0, 1978 .max = 768000, 1979 .step = 1, 1980 .def = 0, 1981 .flags = V4L2_CTRL_FLAG_READ_ONLY, 1982}; 1983 1984static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = { 1985 .id = TC358743_CID_AUDIO_PRESENT, 1986 .name = "Audio present", 1987 .type = V4L2_CTRL_TYPE_BOOLEAN, 1988 .min = 0, 1989 .max = 1, 1990 .step = 1, 1991 .def = 0, 1992 .flags = V4L2_CTRL_FLAG_READ_ONLY, 1993}; 1994 1995/* --------------- PROBE / REMOVE --------------- */ 1996 1997#ifdef CONFIG_OF 1998static void tc358743_gpio_reset(struct tc358743_state *state) 1999{ 2000 usleep_range(5000, 10000); 2001 gpiod_set_value(state->reset_gpio, 1); 2002 usleep_range(1000, 2000); 2003 gpiod_set_value(state->reset_gpio, 0); 2004 msleep(20); 2005} 2006 2007static int tc358743_probe_of(struct tc358743_state *state) 2008{ 2009 struct device *dev = &state->i2c_client->dev; 2010 struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 }; 2011 struct device_node *ep; 2012 struct clk *refclk; 2013 u32 bps_pr_lane; 2014 int ret; 2015 2016 refclk = devm_clk_get(dev, "refclk"); 2017 if (IS_ERR(refclk)) 2018 return dev_err_probe(dev, PTR_ERR(refclk), 2019 "failed to get refclk\n"); 2020 2021 ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); 2022 if (!ep) { 2023 dev_err(dev, "missing endpoint node\n"); 2024 return -EINVAL; 2025 } 2026 2027 ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep), &endpoint); 2028 if (ret) { 2029 dev_err(dev, "failed to parse endpoint\n"); 2030 goto put_node; 2031 } 2032 2033 if (endpoint.bus_type != V4L2_MBUS_CSI2_DPHY || 2034 endpoint.bus.mipi_csi2.num_data_lanes == 0 || 2035 endpoint.nr_of_link_frequencies == 0) { 2036 dev_err(dev, "missing CSI-2 properties in endpoint\n"); 2037 ret = -EINVAL; 2038 goto free_endpoint; 2039 } 2040 2041 if (endpoint.bus.mipi_csi2.num_data_lanes > 4) { 2042 dev_err(dev, "invalid number of lanes\n"); 2043 ret = -EINVAL; 2044 goto free_endpoint; 2045 } 2046 2047 state->bus = endpoint.bus.mipi_csi2; 2048 2049 ret = clk_prepare_enable(refclk); 2050 if (ret) { 2051 dev_err(dev, "Failed! to enable clock\n"); 2052 goto free_endpoint; 2053 } 2054 2055 state->pdata.refclk_hz = clk_get_rate(refclk); 2056 state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS; 2057 state->pdata.enable_hdcp = false; 2058 /* 2059 * Ideally the FIFO trigger level should be set based on the input and 2060 * output data rates, but the calculations required are buried in 2061 * Toshiba's register settings spreadsheet. 2062 * A value of 16 works with a 594Mbps data rate for 720p60 (using 2 2063 * lanes) and 1080p60 (using 4 lanes), but fails when the data rate 2064 * is increased, or a lower pixel clock is used that result in CSI 2065 * reading out faster than the data is arriving. 2066 * 2067 * A value of 374 works with both those modes at 594Mbps, and with most 2068 * modes on 972Mbps. 2069 */ 2070 state->pdata.fifo_level = 374; 2071 /* 2072 * The PLL input clock is obtained by dividing refclk by pll_prd. 2073 * It must be between 6 MHz and 40 MHz, lower frequency is better. 2074 */ 2075 switch (state->pdata.refclk_hz) { 2076 case 26000000: 2077 case 27000000: 2078 case 42000000: 2079 state->pdata.pll_prd = state->pdata.refclk_hz / 6000000; 2080 break; 2081 default: 2082 dev_err(dev, "unsupported refclk rate: %u Hz\n", 2083 state->pdata.refclk_hz); 2084 goto disable_clk; 2085 } 2086 2087 /* 2088 * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps. 2089 * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60. 2090 * 972 Mbps allows 1080P50 UYVY over 2-lane. 2091 */ 2092 bps_pr_lane = 2 * endpoint.link_frequencies[0]; 2093 if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) { 2094 dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane); 2095 ret = -EINVAL; 2096 goto disable_clk; 2097 } 2098 2099 /* The CSI speed per lane is refclk / pll_prd * pll_fbd */ 2100 state->pdata.pll_fbd = bps_pr_lane / 2101 state->pdata.refclk_hz * state->pdata.pll_prd; 2102 2103 /* 2104 * FIXME: These timings are from REF_02 for 594 or 972 Mbps per lane 2105 * (297 MHz or 486 MHz link frequency). 2106 * In principle it should be possible to calculate 2107 * them based on link frequency and resolution. 2108 */ 2109 switch (bps_pr_lane) { 2110 default: 2111 dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane); 2112 fallthrough; 2113 case 594000000U: 2114 state->pdata.lineinitcnt = 0xe80; 2115 state->pdata.lptxtimecnt = 0x003; 2116 /* tclk-preparecnt: 3, tclk-zerocnt: 20 */ 2117 state->pdata.tclk_headercnt = 0x1403; 2118 state->pdata.tclk_trailcnt = 0x00; 2119 /* ths-preparecnt: 3, ths-zerocnt: 1 */ 2120 state->pdata.ths_headercnt = 0x0103; 2121 state->pdata.twakeup = 0x4882; 2122 state->pdata.tclk_postcnt = 0x008; 2123 state->pdata.ths_trailcnt = 0x2; 2124 state->pdata.hstxvregcnt = 0; 2125 break; 2126 case 972000000U: 2127 state->pdata.lineinitcnt = 0x1b58; 2128 state->pdata.lptxtimecnt = 0x007; 2129 /* tclk-preparecnt: 6, tclk-zerocnt: 40 */ 2130 state->pdata.tclk_headercnt = 0x2806; 2131 state->pdata.tclk_trailcnt = 0x00; 2132 /* ths-preparecnt: 6, ths-zerocnt: 8 */ 2133 state->pdata.ths_headercnt = 0x0806; 2134 state->pdata.twakeup = 0x4268; 2135 state->pdata.tclk_postcnt = 0x008; 2136 state->pdata.ths_trailcnt = 0x5; 2137 state->pdata.hstxvregcnt = 0; 2138 break; 2139 } 2140 2141 state->reset_gpio = devm_gpiod_get_optional(dev, "reset", 2142 GPIOD_OUT_LOW); 2143 if (IS_ERR(state->reset_gpio)) { 2144 dev_err(dev, "failed to get reset gpio\n"); 2145 ret = PTR_ERR(state->reset_gpio); 2146 goto disable_clk; 2147 } 2148 2149 if (state->reset_gpio) 2150 tc358743_gpio_reset(state); 2151 2152 ret = 0; 2153 goto free_endpoint; 2154 2155disable_clk: 2156 clk_disable_unprepare(refclk); 2157free_endpoint: 2158 v4l2_fwnode_endpoint_free(&endpoint); 2159put_node: 2160 of_node_put(ep); 2161 return ret; 2162} 2163#else 2164static inline int tc358743_probe_of(struct tc358743_state *state) 2165{ 2166 return -ENODEV; 2167} 2168#endif 2169 2170static int tc358743_probe(struct i2c_client *client) 2171{ 2172 static struct v4l2_dv_timings default_timing = 2173 V4L2_DV_BT_CEA_640X480P59_94; 2174 struct tc358743_state *state; 2175 struct tc358743_platform_data *pdata = client->dev.platform_data; 2176 struct v4l2_subdev *sd; 2177 u16 irq_mask = MASK_HDMI_MSK | MASK_CSI_MSK; 2178 u16 chipid; 2179 int err; 2180 2181 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 2182 return -EIO; 2183 v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n", 2184 client->addr << 1, client->adapter->name); 2185 2186 state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state), 2187 GFP_KERNEL); 2188 if (!state) 2189 return -ENOMEM; 2190 2191 state->i2c_client = client; 2192 2193 /* platform data */ 2194 if (pdata) { 2195 state->pdata = *pdata; 2196 state->bus.flags = 0; 2197 } else { 2198 err = tc358743_probe_of(state); 2199 if (err == -ENODEV) 2200 v4l_err(client, "No platform data!\n"); 2201 if (err) 2202 return err; 2203 } 2204 2205 sd = &state->sd; 2206 v4l2_i2c_subdev_init(sd, client, &tc358743_ops); 2207 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 2208 2209 /* i2c access */ 2210 if (i2c_rd16_err(sd, CHIPID, &chipid) || 2211 (chipid & MASK_CHIPID) != 0) { 2212 v4l2_info(sd, "not a TC358743 on address 0x%x\n", 2213 client->addr << 1); 2214 return -ENODEV; 2215 } 2216 2217 /* control handlers */ 2218 v4l2_ctrl_handler_init(&state->hdl, 3); 2219 2220 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL, 2221 V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0); 2222 2223 /* custom controls */ 2224 state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl, 2225 &tc358743_ctrl_audio_sampling_rate, NULL); 2226 2227 state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl, 2228 &tc358743_ctrl_audio_present, NULL); 2229 2230 sd->ctrl_handler = &state->hdl; 2231 if (state->hdl.error) { 2232 err = state->hdl.error; 2233 goto err_hdl; 2234 } 2235 2236 if (tc358743_update_controls(sd)) { 2237 err = -ENODEV; 2238 goto err_hdl; 2239 } 2240 2241 state->pad.flags = MEDIA_PAD_FL_SOURCE; 2242 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 2243 err = media_entity_pads_init(&sd->entity, 1, &state->pad); 2244 if (err < 0) 2245 goto err_hdl; 2246 2247 state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24; 2248 2249 sd->dev = &client->dev; 2250 2251 mutex_init(&state->confctl_mutex); 2252 2253 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 2254 tc358743_delayed_work_enable_hotplug); 2255 2256#ifdef CONFIG_VIDEO_TC358743_CEC 2257 state->cec_adap = cec_allocate_adapter(&tc358743_cec_adap_ops, 2258 state, dev_name(&client->dev), 2259 CEC_CAP_DEFAULTS | CEC_CAP_MONITOR_ALL, CEC_MAX_LOG_ADDRS); 2260 if (IS_ERR(state->cec_adap)) { 2261 err = PTR_ERR(state->cec_adap); 2262 goto err_hdl; 2263 } 2264 irq_mask |= MASK_CEC_RMSK | MASK_CEC_TMSK; 2265#endif 2266 2267 tc358743_initial_setup(sd); 2268 2269 tc358743_s_dv_timings(sd, 0, &default_timing); 2270 2271 tc358743_set_csi_color_space(sd); 2272 2273 tc358743_init_interrupts(sd); 2274 2275 if (state->i2c_client->irq) { 2276 err = devm_request_threaded_irq(&client->dev, 2277 state->i2c_client->irq, 2278 NULL, tc358743_irq_handler, 2279 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 2280 "tc358743", state); 2281 if (err) 2282 goto err_work_queues; 2283 } else { 2284 INIT_WORK(&state->work_i2c_poll, 2285 tc358743_work_i2c_poll); 2286 timer_setup(&state->timer, tc358743_irq_poll_timer, 0); 2287 state->timer.expires = jiffies + 2288 msecs_to_jiffies(POLL_INTERVAL_MS); 2289 add_timer(&state->timer); 2290 } 2291 2292 err = cec_register_adapter(state->cec_adap, &client->dev); 2293 if (err < 0) { 2294 pr_err("%s: failed to register the cec device\n", __func__); 2295 cec_delete_adapter(state->cec_adap); 2296 state->cec_adap = NULL; 2297 goto err_work_queues; 2298 } 2299 2300 tc358743_enable_interrupts(sd, tx_5v_power_present(sd)); 2301 i2c_wr16(sd, INTMASK, ~irq_mask); 2302 2303 err = v4l2_ctrl_handler_setup(sd->ctrl_handler); 2304 if (err) 2305 goto err_work_queues; 2306 2307 err = v4l2_async_register_subdev(sd); 2308 if (err < 0) 2309 goto err_work_queues; 2310 2311 i2c_wr8(sd, TYP_ACP_SET, packet_type); 2312 i2c_wr8(sd, PK_AUTO_CLR, 0xff); 2313 i2c_wr8(sd, NO_PKT_CLR, MASK_NO_ACP_CLR); 2314 2315 state->debugfs_dir = debugfs_create_dir(sd->name, v4l2_debugfs_root()); 2316 state->infoframes = v4l2_debugfs_if_alloc(state->debugfs_dir, 2317 V4L2_DEBUGFS_IF_AVI | V4L2_DEBUGFS_IF_AUDIO | 2318 V4L2_DEBUGFS_IF_SPD | V4L2_DEBUGFS_IF_HDMI | 2319 V4L2_DEBUGFS_IF_DRM, sd, tc358743_debugfs_if_read); 2320 2321 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 2322 client->addr << 1, client->adapter->name); 2323 2324 return 0; 2325 2326err_work_queues: 2327 cec_unregister_adapter(state->cec_adap); 2328 if (!state->i2c_client->irq) { 2329 timer_delete_sync(&state->timer); 2330 flush_work(&state->work_i2c_poll); 2331 } 2332 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 2333 mutex_destroy(&state->confctl_mutex); 2334err_hdl: 2335 media_entity_cleanup(&sd->entity); 2336 v4l2_ctrl_handler_free(&state->hdl); 2337 return err; 2338} 2339 2340static void tc358743_remove(struct i2c_client *client) 2341{ 2342 struct v4l2_subdev *sd = i2c_get_clientdata(client); 2343 struct tc358743_state *state = to_state(sd); 2344 2345 if (!state->i2c_client->irq) { 2346 timer_delete_sync(&state->timer); 2347 flush_work(&state->work_i2c_poll); 2348 } 2349 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 2350 v4l2_debugfs_if_free(state->infoframes); 2351 debugfs_remove_recursive(state->debugfs_dir); 2352 cec_unregister_adapter(state->cec_adap); 2353 v4l2_async_unregister_subdev(sd); 2354 v4l2_device_unregister_subdev(sd); 2355 mutex_destroy(&state->confctl_mutex); 2356 media_entity_cleanup(&sd->entity); 2357 v4l2_ctrl_handler_free(&state->hdl); 2358} 2359 2360static const struct i2c_device_id tc358743_id[] = { 2361 { "tc358743" }, 2362 {} 2363}; 2364 2365MODULE_DEVICE_TABLE(i2c, tc358743_id); 2366 2367#if IS_ENABLED(CONFIG_OF) 2368static const struct of_device_id tc358743_of_match[] = { 2369 { .compatible = "toshiba,tc358743" }, 2370 {}, 2371}; 2372MODULE_DEVICE_TABLE(of, tc358743_of_match); 2373#endif 2374 2375static struct i2c_driver tc358743_driver = { 2376 .driver = { 2377 .name = "tc358743", 2378 .of_match_table = of_match_ptr(tc358743_of_match), 2379 }, 2380 .probe = tc358743_probe, 2381 .remove = tc358743_remove, 2382 .id_table = tc358743_id, 2383}; 2384 2385module_i2c_driver(tc358743_driver);
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