st-mipid02.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Driver for ST MIPID02 CSI-2 to PARALLEL bridge
  4 *
  5 * Copyright (C) STMicroelectronics SA 2019
  6 * Authors: Mickael Guene <mickael.guene@st.com>
  7 *          for STMicroelectronics.
  8 *
  9 *
 10 */
 11
 12#include <linux/clk.h>
 13#include <linux/delay.h>
 14#include <linux/gpio/consumer.h>
 15#include <linux/i2c.h>
 16#include <linux/module.h>
 17#include <linux/pm_runtime.h>
 18#include <linux/of_graph.h>
 19#include <linux/regulator/consumer.h>
 20#include <media/mipi-csi2.h>
 21#include <media/v4l2-async.h>
 22#include <media/v4l2-cci.h>
 23#include <media/v4l2-ctrls.h>
 24#include <media/v4l2-device.h>
 25#include <media/v4l2-fwnode.h>
 26#include <media/v4l2-subdev.h>
 27
 28#define MIPID02_CLK_LANE_WR_REG1	CCI_REG8(0x01)
 29#define MIPID02_CLK_LANE_REG1		CCI_REG8(0x02)
 30#define MIPID02_CLK_LANE_REG3		CCI_REG8(0x04)
 31#define MIPID02_DATA_LANE0_REG1		CCI_REG8(0x05)
 32#define MIPID02_DATA_LANE0_REG2		CCI_REG8(0x06)
 33#define MIPID02_DATA_LANE1_REG1		CCI_REG8(0x09)
 34#define MIPID02_DATA_LANE1_REG2		CCI_REG8(0x0a)
 35#define MIPID02_MODE_REG1		CCI_REG8(0x14)
 36#define MIPID02_MODE_REG2		CCI_REG8(0x15)
 37#define MIPID02_DATA_ID_RREG		CCI_REG8(0x17)
 38#define MIPID02_DATA_SELECTION_CTRL	CCI_REG8(0x19)
 39#define MIPID02_PIX_WIDTH_CTRL		CCI_REG8(0x1e)
 40#define MIPID02_PIX_WIDTH_CTRL_EMB	CCI_REG8(0x1f)
 41
 42/* Bits definition for MIPID02_CLK_LANE_REG1 */
 43#define CLK_ENABLE					BIT(0)
 44/* Bits definition for MIPID02_CLK_LANE_REG3 */
 45#define CLK_MIPI_CSI					BIT(1)
 46/* Bits definition for MIPID02_DATA_LANE0_REG1 */
 47#define DATA_ENABLE					BIT(0)
 48/* Bits definition for MIPID02_DATA_LANEx_REG2 */
 49#define DATA_MIPI_CSI					BIT(0)
 50/* Bits definition for MIPID02_MODE_REG1 */
 51#define MODE_DATA_SWAP					BIT(2)
 52#define MODE_NO_BYPASS					BIT(6)
 53/* Bits definition for MIPID02_MODE_REG2 */
 54#define MODE_HSYNC_ACTIVE_HIGH				BIT(1)
 55#define MODE_VSYNC_ACTIVE_HIGH				BIT(2)
 56#define MODE_PCLK_SAMPLE_RISING				BIT(3)
 57/* Bits definition for MIPID02_DATA_SELECTION_CTRL */
 58#define SELECTION_MANUAL_DATA				BIT(2)
 59#define SELECTION_MANUAL_WIDTH				BIT(3)
 60
 61static const u32 mipid02_supported_fmt_codes[] = {
 62	MEDIA_BUS_FMT_SBGGR8_1X8, MEDIA_BUS_FMT_SGBRG8_1X8,
 63	MEDIA_BUS_FMT_SGRBG8_1X8, MEDIA_BUS_FMT_SRGGB8_1X8,
 64	MEDIA_BUS_FMT_SBGGR10_1X10, MEDIA_BUS_FMT_SGBRG10_1X10,
 65	MEDIA_BUS_FMT_SGRBG10_1X10, MEDIA_BUS_FMT_SRGGB10_1X10,
 66	MEDIA_BUS_FMT_SBGGR12_1X12, MEDIA_BUS_FMT_SGBRG12_1X12,
 67	MEDIA_BUS_FMT_SGRBG12_1X12, MEDIA_BUS_FMT_SRGGB12_1X12,
 68	MEDIA_BUS_FMT_YUYV8_1X16, MEDIA_BUS_FMT_YVYU8_1X16,
 69	MEDIA_BUS_FMT_UYVY8_1X16, MEDIA_BUS_FMT_VYUY8_1X16,
 70	MEDIA_BUS_FMT_RGB565_1X16, MEDIA_BUS_FMT_BGR888_1X24,
 71	MEDIA_BUS_FMT_Y8_1X8, MEDIA_BUS_FMT_JPEG_1X8
 72};
 73
 74/* regulator supplies */
 75static const char * const mipid02_supply_name[] = {
 76	"VDDE", /* 1.8V digital I/O supply */
 77	"VDDIN", /* 1V8 voltage regulator supply */
 78};
 79
 80#define MIPID02_NUM_SUPPLIES		ARRAY_SIZE(mipid02_supply_name)
 81
 82#define MIPID02_SINK_0			0
 83#define MIPID02_SINK_1			1
 84#define MIPID02_SOURCE			2
 85#define MIPID02_PAD_NB			3
 86
 87struct mipid02_dev {
 88	struct i2c_client *i2c_client;
 89	struct regulator_bulk_data supplies[MIPID02_NUM_SUPPLIES];
 90	struct v4l2_subdev sd;
 91	struct regmap *regmap;
 92	struct media_pad pad[MIPID02_PAD_NB];
 93	struct clk *xclk;
 94	struct gpio_desc *reset_gpio;
 95	/* endpoints info */
 96	struct v4l2_fwnode_endpoint rx;
 97	struct v4l2_fwnode_endpoint tx;
 98	/* remote source */
 99	struct v4l2_async_notifier notifier;
100	struct v4l2_subdev *s_subdev;
101	u16 s_subdev_pad_id;
102	/* registers */
103	struct {
104		u8 clk_lane_reg1;
105		u8 data_lane0_reg1;
106		u8 data_lane1_reg1;
107		u8 mode_reg1;
108		u8 mode_reg2;
109		u8 data_selection_ctrl;
110		u8 data_id_rreg;
111		u8 pix_width_ctrl;
112		u8 pix_width_ctrl_emb;
113	} r;
114};
115
116static int bpp_from_code(__u32 code)
117{
118	switch (code) {
119	case MEDIA_BUS_FMT_SBGGR8_1X8:
120	case MEDIA_BUS_FMT_SGBRG8_1X8:
121	case MEDIA_BUS_FMT_SGRBG8_1X8:
122	case MEDIA_BUS_FMT_SRGGB8_1X8:
123	case MEDIA_BUS_FMT_Y8_1X8:
124		return 8;
125	case MEDIA_BUS_FMT_SBGGR10_1X10:
126	case MEDIA_BUS_FMT_SGBRG10_1X10:
127	case MEDIA_BUS_FMT_SGRBG10_1X10:
128	case MEDIA_BUS_FMT_SRGGB10_1X10:
129		return 10;
130	case MEDIA_BUS_FMT_SBGGR12_1X12:
131	case MEDIA_BUS_FMT_SGBRG12_1X12:
132	case MEDIA_BUS_FMT_SGRBG12_1X12:
133	case MEDIA_BUS_FMT_SRGGB12_1X12:
134		return 12;
135	case MEDIA_BUS_FMT_YUYV8_1X16:
136	case MEDIA_BUS_FMT_YVYU8_1X16:
137	case MEDIA_BUS_FMT_UYVY8_1X16:
138	case MEDIA_BUS_FMT_VYUY8_1X16:
139	case MEDIA_BUS_FMT_RGB565_1X16:
140		return 16;
141	case MEDIA_BUS_FMT_BGR888_1X24:
142		return 24;
143	default:
144		return 0;
145	}
146}
147
148static u8 data_type_from_code(__u32 code)
149{
150	switch (code) {
151	case MEDIA_BUS_FMT_SBGGR8_1X8:
152	case MEDIA_BUS_FMT_SGBRG8_1X8:
153	case MEDIA_BUS_FMT_SGRBG8_1X8:
154	case MEDIA_BUS_FMT_SRGGB8_1X8:
155	case MEDIA_BUS_FMT_Y8_1X8:
156		return MIPI_CSI2_DT_RAW8;
157	case MEDIA_BUS_FMT_SBGGR10_1X10:
158	case MEDIA_BUS_FMT_SGBRG10_1X10:
159	case MEDIA_BUS_FMT_SGRBG10_1X10:
160	case MEDIA_BUS_FMT_SRGGB10_1X10:
161		return MIPI_CSI2_DT_RAW10;
162	case MEDIA_BUS_FMT_SBGGR12_1X12:
163	case MEDIA_BUS_FMT_SGBRG12_1X12:
164	case MEDIA_BUS_FMT_SGRBG12_1X12:
165	case MEDIA_BUS_FMT_SRGGB12_1X12:
166		return MIPI_CSI2_DT_RAW12;
167	case MEDIA_BUS_FMT_YUYV8_1X16:
168	case MEDIA_BUS_FMT_YVYU8_1X16:
169	case MEDIA_BUS_FMT_UYVY8_1X16:
170	case MEDIA_BUS_FMT_VYUY8_1X16:
171		return MIPI_CSI2_DT_YUV422_8B;
172	case MEDIA_BUS_FMT_BGR888_1X24:
173		return MIPI_CSI2_DT_RGB888;
174	case MEDIA_BUS_FMT_RGB565_1X16:
175		return MIPI_CSI2_DT_RGB565;
176	default:
177		return 0;
178	}
179}
180
181static __u32 get_fmt_code(__u32 code)
182{
183	unsigned int i;
184
185	for (i = 0; i < ARRAY_SIZE(mipid02_supported_fmt_codes); i++) {
186		if (code == mipid02_supported_fmt_codes[i])
187			return code;
188	}
189
190	return mipid02_supported_fmt_codes[0];
191}
192
193static __u32 serial_to_parallel_code(__u32 serial)
194{
195	if (serial == MEDIA_BUS_FMT_RGB565_1X16)
196		return MEDIA_BUS_FMT_RGB565_2X8_LE;
197	if (serial == MEDIA_BUS_FMT_YUYV8_1X16)
198		return MEDIA_BUS_FMT_YUYV8_2X8;
199	if (serial == MEDIA_BUS_FMT_YVYU8_1X16)
200		return MEDIA_BUS_FMT_YVYU8_2X8;
201	if (serial == MEDIA_BUS_FMT_UYVY8_1X16)
202		return MEDIA_BUS_FMT_UYVY8_2X8;
203	if (serial == MEDIA_BUS_FMT_VYUY8_1X16)
204		return MEDIA_BUS_FMT_VYUY8_2X8;
205	if (serial == MEDIA_BUS_FMT_BGR888_1X24)
206		return MEDIA_BUS_FMT_BGR888_3X8;
207
208	return serial;
209}
210
211static inline struct mipid02_dev *to_mipid02_dev(struct v4l2_subdev *sd)
212{
213	return container_of(sd, struct mipid02_dev, sd);
214}
215
216static int mipid02_get_regulators(struct mipid02_dev *bridge)
217{
218	unsigned int i;
219
220	for (i = 0; i < MIPID02_NUM_SUPPLIES; i++)
221		bridge->supplies[i].supply = mipid02_supply_name[i];
222
223	return devm_regulator_bulk_get(&bridge->i2c_client->dev,
224				       MIPID02_NUM_SUPPLIES,
225				       bridge->supplies);
226}
227
228static void mipid02_apply_reset(struct mipid02_dev *bridge)
229{
230	gpiod_set_value_cansleep(bridge->reset_gpio, 0);
231	usleep_range(5000, 10000);
232	gpiod_set_value_cansleep(bridge->reset_gpio, 1);
233	usleep_range(5000, 10000);
234	gpiod_set_value_cansleep(bridge->reset_gpio, 0);
235	usleep_range(5000, 10000);
236}
237
238static int mipid02_set_power_on(struct device *dev)
239{
240	struct v4l2_subdev *sd = dev_get_drvdata(dev);
241	struct mipid02_dev *bridge = to_mipid02_dev(sd);
242	struct i2c_client *client = bridge->i2c_client;
243	int ret;
244
245	ret = clk_prepare_enable(bridge->xclk);
246	if (ret) {
247		dev_err(&client->dev, "%s: failed to enable clock\n", __func__);
248		return ret;
249	}
250
251	ret = regulator_bulk_enable(MIPID02_NUM_SUPPLIES,
252				    bridge->supplies);
253	if (ret) {
254		dev_err(&client->dev, "%s: failed to enable regulators\n",
255			    __func__);
256		goto xclk_off;
257	}
258
259	if (bridge->reset_gpio) {
260		dev_dbg(&client->dev, "apply reset");
261		mipid02_apply_reset(bridge);
262	} else {
263		dev_dbg(&client->dev, "don't apply reset");
264		usleep_range(5000, 10000);
265	}
266
267	return 0;
268
269xclk_off:
270	clk_disable_unprepare(bridge->xclk);
271	return ret;
272}
273
274static int mipid02_set_power_off(struct device *dev)
275{
276	struct v4l2_subdev *sd = dev_get_drvdata(dev);
277	struct mipid02_dev *bridge = to_mipid02_dev(sd);
278
279	regulator_bulk_disable(MIPID02_NUM_SUPPLIES, bridge->supplies);
280	clk_disable_unprepare(bridge->xclk);
281
282	return 0;
283}
284
285static int mipid02_detect(struct mipid02_dev *bridge)
286{
287	u64 reg;
288
289	/*
290	 * There is no version registers. Just try to read register
291	 * MIPID02_CLK_LANE_WR_REG1.
292	 */
293	return cci_read(bridge->regmap, MIPID02_CLK_LANE_WR_REG1, &reg, NULL);
294}
295
296/*
297 * We need to know link frequency to setup clk_lane_reg1 timings. Link frequency
298 * will be retrieve from connected device via v4l2_get_link_freq, bit per pixel
299 * and number of lanes.
300 */
301static int mipid02_configure_from_rx_speed(struct mipid02_dev *bridge,
302					   struct v4l2_mbus_framefmt *fmt)
303{
304	struct media_pad *remote =
305		&bridge->s_subdev->entity.pads[bridge->s_subdev_pad_id];
306	struct i2c_client *client = bridge->i2c_client;
307	struct v4l2_fwnode_endpoint *ep = &bridge->rx;
308	u32 bpp = bpp_from_code(fmt->code);
309	/*
310	 * clk_lane_reg1 requires 4 times the unit interval time, and bitrate
311	 * is twice the link frequency, hence ui_4 = 1000000000 * 4 / 2
312	 */
313	u64 ui_4 = 2000000000;
314	s64 link_freq;
315
316	link_freq = v4l2_get_link_freq(remote, bpp,
317				       2 * ep->bus.mipi_csi2.num_data_lanes);
318	if (link_freq < 0) {
319		dev_err(&client->dev, "Failed to get link frequency");
320		return -EINVAL;
321	}
322
323	dev_dbg(&client->dev, "detect link_freq = %lld Hz", link_freq);
324	ui_4 = div64_u64(ui_4, link_freq);
325	bridge->r.clk_lane_reg1 |= ui_4 << 2;
326
327	return 0;
328}
329
330static int mipid02_configure_clk_lane(struct mipid02_dev *bridge)
331{
332	struct i2c_client *client = bridge->i2c_client;
333	struct v4l2_fwnode_endpoint *ep = &bridge->rx;
334	bool *polarities = ep->bus.mipi_csi2.lane_polarities;
335
336	/* midid02 doesn't support clock lane remapping */
337	if (ep->bus.mipi_csi2.clock_lane != 0) {
338		dev_err(&client->dev, "clk lane must be map to lane 0\n");
339		return -EINVAL;
340	}
341	bridge->r.clk_lane_reg1 |= (polarities[0] << 1) | CLK_ENABLE;
342
343	return 0;
344}
345
346static int mipid02_configure_data0_lane(struct mipid02_dev *bridge, int nb,
347					bool are_lanes_swap, bool *polarities)
348{
349	bool are_pin_swap = are_lanes_swap ? polarities[2] : polarities[1];
350
351	if (nb == 1 && are_lanes_swap)
352		return 0;
353
354	/*
355	 * data lane 0 as pin swap polarity reversed compared to clock and
356	 * data lane 1
357	 */
358	if (!are_pin_swap)
359		bridge->r.data_lane0_reg1 = 1 << 1;
360	bridge->r.data_lane0_reg1 |= DATA_ENABLE;
361
362	return 0;
363}
364
365static int mipid02_configure_data1_lane(struct mipid02_dev *bridge, int nb,
366					bool are_lanes_swap, bool *polarities)
367{
368	bool are_pin_swap = are_lanes_swap ? polarities[1] : polarities[2];
369
370	if (nb == 1 && !are_lanes_swap)
371		return 0;
372
373	if (are_pin_swap)
374		bridge->r.data_lane1_reg1 = 1 << 1;
375	bridge->r.data_lane1_reg1 |= DATA_ENABLE;
376
377	return 0;
378}
379
380static int mipid02_configure_from_rx(struct mipid02_dev *bridge,
381				     struct v4l2_mbus_framefmt *fmt)
382{
383	struct v4l2_fwnode_endpoint *ep = &bridge->rx;
384	bool are_lanes_swap = ep->bus.mipi_csi2.data_lanes[0] == 2;
385	bool *polarities = ep->bus.mipi_csi2.lane_polarities;
386	int nb = ep->bus.mipi_csi2.num_data_lanes;
387	int ret;
388
389	ret = mipid02_configure_clk_lane(bridge);
390	if (ret)
391		return ret;
392
393	ret = mipid02_configure_data0_lane(bridge, nb, are_lanes_swap,
394					   polarities);
395	if (ret)
396		return ret;
397
398	ret = mipid02_configure_data1_lane(bridge, nb, are_lanes_swap,
399					   polarities);
400	if (ret)
401		return ret;
402
403	bridge->r.mode_reg1 |= are_lanes_swap ? MODE_DATA_SWAP : 0;
404	bridge->r.mode_reg1 |= (nb - 1) << 1;
405
406	return mipid02_configure_from_rx_speed(bridge, fmt);
407}
408
409static int mipid02_configure_from_tx(struct mipid02_dev *bridge)
410{
411	struct v4l2_fwnode_endpoint *ep = &bridge->tx;
412
413	bridge->r.data_selection_ctrl = SELECTION_MANUAL_WIDTH;
414	bridge->r.pix_width_ctrl = ep->bus.parallel.bus_width;
415	bridge->r.pix_width_ctrl_emb = ep->bus.parallel.bus_width;
416	if (ep->bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
417		bridge->r.mode_reg2 |= MODE_HSYNC_ACTIVE_HIGH;
418	if (ep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
419		bridge->r.mode_reg2 |= MODE_VSYNC_ACTIVE_HIGH;
420	if (ep->bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
421		bridge->r.mode_reg2 |= MODE_PCLK_SAMPLE_RISING;
422
423	return 0;
424}
425
426static int mipid02_configure_from_code(struct mipid02_dev *bridge,
427				       struct v4l2_mbus_framefmt *fmt)
428{
429	u8 data_type;
430
431	bridge->r.data_id_rreg = 0;
432
433	if (fmt->code != MEDIA_BUS_FMT_JPEG_1X8) {
434		bridge->r.data_selection_ctrl |= SELECTION_MANUAL_DATA;
435
436		data_type = data_type_from_code(fmt->code);
437		if (!data_type)
438			return -EINVAL;
439		bridge->r.data_id_rreg = data_type;
440	}
441
442	return 0;
443}
444
445static int mipid02_disable_streams(struct v4l2_subdev *sd,
446				   struct v4l2_subdev_state *state, u32 pad,
447				   u64 streams_mask)
448{
449	struct mipid02_dev *bridge = to_mipid02_dev(sd);
450	struct i2c_client *client = bridge->i2c_client;
451	int ret = -EINVAL;
452
453	if (!bridge->s_subdev)
454		goto error;
455
456	ret = v4l2_subdev_disable_streams(bridge->s_subdev,
457					  bridge->s_subdev_pad_id, BIT(0));
458	if (ret)
459		goto error;
460
461	/* Disable all lanes */
462	cci_write(bridge->regmap, MIPID02_CLK_LANE_REG1, 0, &ret);
463	cci_write(bridge->regmap, MIPID02_DATA_LANE0_REG1, 0, &ret);
464	cci_write(bridge->regmap, MIPID02_DATA_LANE1_REG1, 0, &ret);
465	if (ret)
466		goto error;
467
468	pm_runtime_put_autosuspend(&client->dev);
469
470error:
471	if (ret)
472		dev_err(&client->dev, "failed to stream off %d", ret);
473
474	return ret;
475}
476
477static int mipid02_enable_streams(struct v4l2_subdev *sd,
478				  struct v4l2_subdev_state *state, u32 pad,
479				  u64 streams_mask)
480{
481	struct mipid02_dev *bridge = to_mipid02_dev(sd);
482	struct i2c_client *client = bridge->i2c_client;
483	struct v4l2_mbus_framefmt *fmt;
484	int ret = -EINVAL;
485
486	if (!bridge->s_subdev)
487		return ret;
488
489	memset(&bridge->r, 0, sizeof(bridge->r));
490
491	fmt = v4l2_subdev_state_get_format(state, MIPID02_SINK_0);
492
493	/* build registers content */
494	ret = mipid02_configure_from_rx(bridge, fmt);
495	if (ret)
496		return ret;
497	ret = mipid02_configure_from_tx(bridge);
498	if (ret)
499		return ret;
500	ret = mipid02_configure_from_code(bridge, fmt);
501	if (ret)
502		return ret;
503
504	ret = pm_runtime_resume_and_get(&client->dev);
505	if (ret < 0)
506		return ret;
507
508	/* write mipi registers */
509	cci_write(bridge->regmap, MIPID02_CLK_LANE_REG1,
510		  bridge->r.clk_lane_reg1, &ret);
511	cci_write(bridge->regmap, MIPID02_CLK_LANE_REG3, CLK_MIPI_CSI, &ret);
512	cci_write(bridge->regmap, MIPID02_DATA_LANE0_REG1,
513		  bridge->r.data_lane0_reg1, &ret);
514	cci_write(bridge->regmap, MIPID02_DATA_LANE0_REG2, DATA_MIPI_CSI, &ret);
515	cci_write(bridge->regmap, MIPID02_DATA_LANE1_REG1,
516		  bridge->r.data_lane1_reg1, &ret);
517	cci_write(bridge->regmap, MIPID02_DATA_LANE1_REG2, DATA_MIPI_CSI, &ret);
518	cci_write(bridge->regmap, MIPID02_MODE_REG1,
519		  MODE_NO_BYPASS | bridge->r.mode_reg1, &ret);
520	cci_write(bridge->regmap, MIPID02_MODE_REG2, bridge->r.mode_reg2, &ret);
521	cci_write(bridge->regmap, MIPID02_DATA_ID_RREG, bridge->r.data_id_rreg,
522		  &ret);
523	cci_write(bridge->regmap, MIPID02_DATA_SELECTION_CTRL,
524		  bridge->r.data_selection_ctrl, &ret);
525	cci_write(bridge->regmap, MIPID02_PIX_WIDTH_CTRL,
526		  bridge->r.pix_width_ctrl, &ret);
527	cci_write(bridge->regmap, MIPID02_PIX_WIDTH_CTRL_EMB,
528		  bridge->r.pix_width_ctrl_emb, &ret);
529	if (ret)
530		goto error;
531
532	ret = v4l2_subdev_enable_streams(bridge->s_subdev,
533					 bridge->s_subdev_pad_id, BIT(0));
534	if (ret)
535		goto error;
536
537	return 0;
538
539error:
540	cci_write(bridge->regmap, MIPID02_CLK_LANE_REG1, 0, &ret);
541	cci_write(bridge->regmap, MIPID02_DATA_LANE0_REG1, 0, &ret);
542	cci_write(bridge->regmap, MIPID02_DATA_LANE1_REG1, 0, &ret);
543
544	pm_runtime_put_autosuspend(&client->dev);
545	return ret;
546}
547
548static const struct v4l2_mbus_framefmt default_fmt = {
549	.code = MEDIA_BUS_FMT_SBGGR8_1X8,
550	.field = V4L2_FIELD_NONE,
551	.colorspace = V4L2_COLORSPACE_SRGB,
552	.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT,
553	.quantization = V4L2_QUANTIZATION_FULL_RANGE,
554	.xfer_func = V4L2_XFER_FUNC_DEFAULT,
555	.width = 640,
556	.height = 480,
557};
558
559static int mipid02_init_state(struct v4l2_subdev *sd,
560			      struct v4l2_subdev_state *state)
561{
562	*v4l2_subdev_state_get_format(state, MIPID02_SINK_0) = default_fmt;
563	/* MIPID02_SINK_1 isn't supported yet */
564	*v4l2_subdev_state_get_format(state, MIPID02_SOURCE) = default_fmt;
565
566	return 0;
567}
568
569static int mipid02_enum_mbus_code(struct v4l2_subdev *sd,
570				 struct v4l2_subdev_state *sd_state,
571				 struct v4l2_subdev_mbus_code_enum *code)
572{
573	struct v4l2_mbus_framefmt *sink_fmt;
574	int ret = 0;
575
576	switch (code->pad) {
577	case MIPID02_SINK_0:
578		if (code->index >= ARRAY_SIZE(mipid02_supported_fmt_codes))
579			ret = -EINVAL;
580		else
581			code->code = mipid02_supported_fmt_codes[code->index];
582		break;
583	case MIPID02_SOURCE:
584		if (code->index == 0) {
585			sink_fmt = v4l2_subdev_state_get_format(sd_state,
586								MIPID02_SINK_0);
587			code->code = serial_to_parallel_code(sink_fmt->code);
588		} else {
589			ret = -EINVAL;
590		}
591		break;
592	default:
593		ret = -EINVAL;
594	}
595
596	return ret;
597}
598
599static int mipid02_set_fmt(struct v4l2_subdev *sd,
600			   struct v4l2_subdev_state *sd_state,
601			   struct v4l2_subdev_format *fmt)
602{
603	struct mipid02_dev *bridge = to_mipid02_dev(sd);
604	struct i2c_client *client = bridge->i2c_client;
605	struct v4l2_mbus_framefmt *pad_fmt;
606
607	dev_dbg(&client->dev, "%s for %d", __func__, fmt->pad);
608
609	/* second CSI-2 pad not yet supported */
610	if (fmt->pad == MIPID02_SINK_1)
611		return -EINVAL;
612
613	pad_fmt = v4l2_subdev_state_get_format(sd_state, fmt->pad);
614	fmt->format.code = get_fmt_code(fmt->format.code);
615
616	/* code may need to be converted */
617	if (fmt->pad == MIPID02_SOURCE)
618		fmt->format.code = serial_to_parallel_code(fmt->format.code);
619
620	*pad_fmt = fmt->format;
621
622	/* Propagate the format to the source pad in case of sink pad update */
623	if (fmt->pad == MIPID02_SINK_0) {
624		pad_fmt = v4l2_subdev_state_get_format(sd_state,
625						       MIPID02_SOURCE);
626		*pad_fmt = fmt->format;
627		pad_fmt->code = serial_to_parallel_code(fmt->format.code);
628	}
629
630	return 0;
631}
632
633static const struct v4l2_subdev_video_ops mipid02_video_ops = {
634	.s_stream = v4l2_subdev_s_stream_helper,
635};
636
637static const struct v4l2_subdev_pad_ops mipid02_pad_ops = {
638	.enum_mbus_code = mipid02_enum_mbus_code,
639	.get_fmt = v4l2_subdev_get_fmt,
640	.set_fmt = mipid02_set_fmt,
641	.enable_streams = mipid02_enable_streams,
642	.disable_streams = mipid02_disable_streams,
643};
644
645static const struct v4l2_subdev_ops mipid02_subdev_ops = {
646	.video = &mipid02_video_ops,
647	.pad = &mipid02_pad_ops,
648};
649
650static const struct v4l2_subdev_internal_ops mipid02_subdev_internal_ops = {
651	.init_state = mipid02_init_state,
652};
653
654static const struct media_entity_operations mipid02_subdev_entity_ops = {
655	.link_validate = v4l2_subdev_link_validate,
656};
657
658static int mipid02_async_bound(struct v4l2_async_notifier *notifier,
659			       struct v4l2_subdev *s_subdev,
660			       struct v4l2_async_connection *asd)
661{
662	struct mipid02_dev *bridge = to_mipid02_dev(notifier->sd);
663	struct i2c_client *client = bridge->i2c_client;
664	int source_pad;
665	int ret;
666
667	dev_dbg(&client->dev, "sensor_async_bound call %p", s_subdev);
668
669	source_pad = media_entity_get_fwnode_pad(&s_subdev->entity,
670						 s_subdev->fwnode,
671						 MEDIA_PAD_FL_SOURCE);
672	if (source_pad < 0) {
673		dev_err(&client->dev, "Couldn't find output pad for subdev %s\n",
674			s_subdev->name);
675		return source_pad;
676	}
677
678	ret = media_create_pad_link(&s_subdev->entity, source_pad,
679				    &bridge->sd.entity, 0,
680				    MEDIA_LNK_FL_ENABLED |
681				    MEDIA_LNK_FL_IMMUTABLE);
682	if (ret) {
683		dev_err(&client->dev, "Couldn't create media link %d", ret);
684		return ret;
685	}
686
687	bridge->s_subdev = s_subdev;
688	bridge->s_subdev_pad_id = source_pad;
689
690	return 0;
691}
692
693static void mipid02_async_unbind(struct v4l2_async_notifier *notifier,
694				 struct v4l2_subdev *s_subdev,
695				 struct v4l2_async_connection *asd)
696{
697	struct mipid02_dev *bridge = to_mipid02_dev(notifier->sd);
698
699	bridge->s_subdev = NULL;
700}
701
702static const struct v4l2_async_notifier_operations mipid02_notifier_ops = {
703	.bound		= mipid02_async_bound,
704	.unbind		= mipid02_async_unbind,
705};
706
707static int mipid02_parse_rx_ep(struct mipid02_dev *bridge)
708{
709	struct v4l2_fwnode_endpoint ep = { .bus_type = V4L2_MBUS_CSI2_DPHY };
710	struct i2c_client *client = bridge->i2c_client;
711	struct v4l2_async_connection *asd;
712	struct device_node *ep_node;
713	int ret;
714
715	/* parse rx (endpoint 0) */
716	ep_node = of_graph_get_endpoint_by_regs(bridge->i2c_client->dev.of_node,
717						0, 0);
718	if (!ep_node) {
719		dev_err(&client->dev, "unable to find port0 ep");
720		ret = -EINVAL;
721		goto error;
722	}
723
724	ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), &ep);
725	if (ret) {
726		dev_err(&client->dev, "Could not parse v4l2 endpoint %d\n",
727			ret);
728		goto error_of_node_put;
729	}
730
731	/* do some sanity checks */
732	if (ep.bus.mipi_csi2.num_data_lanes > 2) {
733		dev_err(&client->dev, "max supported data lanes is 2 / got %d",
734			ep.bus.mipi_csi2.num_data_lanes);
735		ret = -EINVAL;
736		goto error_of_node_put;
737	}
738
739	/* register it for later use */
740	bridge->rx = ep;
741
742	/* register async notifier so we get noticed when sensor is connected */
743	v4l2_async_subdev_nf_init(&bridge->notifier, &bridge->sd);
744	asd = v4l2_async_nf_add_fwnode_remote(&bridge->notifier,
745					      of_fwnode_handle(ep_node),
746					      struct v4l2_async_connection);
747	of_node_put(ep_node);
748
749	if (IS_ERR(asd)) {
750		dev_err(&client->dev, "fail to register asd to notifier %pe",
751			asd);
752		return PTR_ERR(asd);
753	}
754	bridge->notifier.ops = &mipid02_notifier_ops;
755
756	ret = v4l2_async_nf_register(&bridge->notifier);
757	if (ret)
758		v4l2_async_nf_cleanup(&bridge->notifier);
759
760	return ret;
761
762error_of_node_put:
763	of_node_put(ep_node);
764error:
765
766	return ret;
767}
768
769static int mipid02_parse_tx_ep(struct mipid02_dev *bridge)
770{
771	struct v4l2_fwnode_endpoint ep = { .bus_type = V4L2_MBUS_PARALLEL };
772	struct i2c_client *client = bridge->i2c_client;
773	struct device_node *ep_node;
774	int ret;
775
776	/* parse tx (endpoint 2) */
777	ep_node = of_graph_get_endpoint_by_regs(bridge->i2c_client->dev.of_node,
778						2, 0);
779	if (!ep_node) {
780		dev_err(&client->dev, "unable to find port1 ep");
781		ret = -EINVAL;
782		goto error;
783	}
784
785	ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), &ep);
786	if (ret) {
787		dev_err(&client->dev, "Could not parse v4l2 endpoint\n");
788		goto error_of_node_put;
789	}
790
791	of_node_put(ep_node);
792	bridge->tx = ep;
793
794	return 0;
795
796error_of_node_put:
797	of_node_put(ep_node);
798error:
799
800	return -EINVAL;
801}
802
803static int mipid02_probe(struct i2c_client *client)
804{
805	struct device *dev = &client->dev;
806	struct mipid02_dev *bridge;
807	u32 clk_freq;
808	int ret;
809
810	bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
811	if (!bridge)
812		return -ENOMEM;
813
814	bridge->i2c_client = client;
815	v4l2_i2c_subdev_init(&bridge->sd, client, &mipid02_subdev_ops);
816
817	/* got and check clock */
818	bridge->xclk = devm_clk_get(dev, "xclk");
819	if (IS_ERR(bridge->xclk)) {
820		dev_err(dev, "failed to get xclk\n");
821		return PTR_ERR(bridge->xclk);
822	}
823
824	clk_freq = clk_get_rate(bridge->xclk);
825	if (clk_freq < 6000000 || clk_freq > 27000000) {
826		dev_err(dev, "xclk freq must be in 6-27 Mhz range. got %d Hz\n",
827			clk_freq);
828		return -EINVAL;
829	}
830
831	bridge->reset_gpio = devm_gpiod_get_optional(dev, "reset",
832						     GPIOD_OUT_HIGH);
833
834	if (IS_ERR(bridge->reset_gpio)) {
835		dev_err(dev, "failed to get reset GPIO\n");
836		return PTR_ERR(bridge->reset_gpio);
837	}
838
839	ret = mipid02_get_regulators(bridge);
840	if (ret) {
841		dev_err(dev, "failed to get regulators %d", ret);
842		return ret;
843	}
844
845	/* Initialise the regmap for further cci access */
846	bridge->regmap = devm_cci_regmap_init_i2c(client, 16);
847	if (IS_ERR(bridge->regmap))
848		return dev_err_probe(dev, PTR_ERR(bridge->regmap),
849				     "failed to get cci regmap\n");
850
851	bridge->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
852	bridge->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
853	bridge->sd.internal_ops = &mipid02_subdev_internal_ops;
854	bridge->sd.entity.ops = &mipid02_subdev_entity_ops;
855	bridge->pad[0].flags = MEDIA_PAD_FL_SINK;
856	bridge->pad[1].flags = MEDIA_PAD_FL_SINK;
857	bridge->pad[2].flags = MEDIA_PAD_FL_SOURCE;
858	ret = media_entity_pads_init(&bridge->sd.entity, MIPID02_PAD_NB,
859				     bridge->pad);
860	if (ret) {
861		dev_err(&client->dev, "pads init failed %d", ret);
862		return ret;
863	}
864
865	ret = v4l2_subdev_init_finalize(&bridge->sd);
866	if (ret < 0) {
867		dev_err(dev, "subdev init error: %d\n", ret);
868		goto entity_cleanup;
869	}
870
871	/* enable clock, power and reset device if available */
872	ret = mipid02_set_power_on(&client->dev);
873	if (ret)
874		goto entity_cleanup;
875
876	ret = mipid02_detect(bridge);
877	if (ret) {
878		dev_err(&client->dev, "failed to detect mipid02 %d", ret);
879		goto power_off;
880	}
881
882	ret = mipid02_parse_tx_ep(bridge);
883	if (ret) {
884		dev_err(&client->dev, "failed to parse tx %d", ret);
885		goto power_off;
886	}
887
888	ret = mipid02_parse_rx_ep(bridge);
889	if (ret) {
890		dev_err(&client->dev, "failed to parse rx %d", ret);
891		goto power_off;
892	}
893
894	/* Enable runtime PM and turn off the device */
895	pm_runtime_set_active(dev);
896	pm_runtime_get_noresume(&client->dev);
897	pm_runtime_enable(dev);
898
899	pm_runtime_set_autosuspend_delay(&client->dev, 1000);
900	pm_runtime_use_autosuspend(&client->dev);
901	pm_runtime_put_autosuspend(&client->dev);
902
903	ret = v4l2_async_register_subdev(&bridge->sd);
904	if (ret < 0) {
905		dev_err(&client->dev, "v4l2_async_register_subdev failed %d",
906			    ret);
907		goto unregister_notifier;
908	}
909
910	dev_info(&client->dev, "mipid02 device probe successfully");
911
912	return 0;
913
914unregister_notifier:
915	v4l2_async_nf_unregister(&bridge->notifier);
916	v4l2_async_nf_cleanup(&bridge->notifier);
917	pm_runtime_disable(&client->dev);
918	pm_runtime_set_suspended(&client->dev);
919power_off:
920	mipid02_set_power_off(&client->dev);
921entity_cleanup:
922	media_entity_cleanup(&bridge->sd.entity);
923
924	return ret;
925}
926
927static void mipid02_remove(struct i2c_client *client)
928{
929	struct v4l2_subdev *sd = i2c_get_clientdata(client);
930	struct mipid02_dev *bridge = to_mipid02_dev(sd);
931
932	v4l2_async_nf_unregister(&bridge->notifier);
933	v4l2_async_nf_cleanup(&bridge->notifier);
934	v4l2_async_unregister_subdev(&bridge->sd);
935
936	pm_runtime_disable(&client->dev);
937	if (!pm_runtime_status_suspended(&client->dev))
938		mipid02_set_power_off(&client->dev);
939	pm_runtime_set_suspended(&client->dev);
940	media_entity_cleanup(&bridge->sd.entity);
941}
942
943static const struct of_device_id mipid02_dt_ids[] = {
944	{ .compatible = "st,st-mipid02" },
945	{ /* sentinel */ }
946};
947MODULE_DEVICE_TABLE(of, mipid02_dt_ids);
948
949static const struct dev_pm_ops mipid02_pm_ops = {
950	RUNTIME_PM_OPS(mipid02_set_power_off, mipid02_set_power_on, NULL)
951};
952
953static struct i2c_driver mipid02_i2c_driver = {
954	.driver = {
955		.name  = "st-mipid02",
956		.of_match_table = mipid02_dt_ids,
957		.pm = pm_ptr(&mipid02_pm_ops),
958	},
959	.probe = mipid02_probe,
960	.remove = mipid02_remove,
961};
962
963module_i2c_driver(mipid02_i2c_driver);
964
965MODULE_AUTHOR("Mickael Guene <mickael.guene@st.com>");
966MODULE_DESCRIPTION("STMicroelectronics MIPID02 CSI-2 bridge driver");
967MODULE_LICENSE("GPL v2");