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saa7115.c
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linux-6.19.14/drivers/media/i2c/saa7115.c
1// SPDX-License-Identifier: GPL-2.0+ 2// saa711x - Philips SAA711x video decoder driver 3// This driver can work with saa7111, saa7111a, saa7113, saa7114, 4// saa7115 and saa7118. 5// 6// Based on saa7114 driver by Maxim Yevtyushkin, which is based on 7// the saa7111 driver by Dave Perks. 8// 9// Copyright (C) 1998 Dave Perks <dperks@ibm.net> 10// Copyright (C) 2002 Maxim Yevtyushkin <max@linuxmedialabs.com> 11// 12// Slight changes for video timing and attachment output by 13// Wolfgang Scherr <scherr@net4you.net> 14// 15// Moved over to the linux >= 2.4.x i2c protocol (1/1/2003) 16// by Ronald Bultje <rbultje@ronald.bitfreak.net> 17// 18// Added saa7115 support by Kevin Thayer <nufan_wfk at yahoo.com> 19// (2/17/2003) 20// 21// VBI support (2004) and cleanups (2005) by Hans Verkuil <hverkuil@kernel.org> 22// 23// Copyright (c) 2005-2006 Mauro Carvalho Chehab <mchehab@kernel.org> 24// SAA7111, SAA7113 and SAA7118 support 25 26#include "saa711x_regs.h" 27 28#include <linux/bitops.h> 29#include <linux/kernel.h> 30#include <linux/module.h> 31#include <linux/slab.h> 32#include <linux/i2c.h> 33#include <linux/videodev2.h> 34#include <media/v4l2-device.h> 35#include <media/v4l2-ctrls.h> 36#include <media/v4l2-mc.h> 37#include <media/i2c/saa7115.h> 38#include <asm/div64.h> 39 40#define VRES_60HZ (480+16) 41 42MODULE_DESCRIPTION("Philips SAA7111/SAA7113/SAA7114/SAA7115/SAA7118 video decoder driver"); 43MODULE_AUTHOR( "Maxim Yevtyushkin, Kevin Thayer, Chris Kennedy, " 44 "Hans Verkuil, Mauro Carvalho Chehab"); 45MODULE_LICENSE("GPL"); 46 47static bool debug; 48module_param(debug, bool, 0644); 49 50MODULE_PARM_DESC(debug, "Debug level (0-1)"); 51 52 53enum saa711x_model { 54 SAA7111A, 55 SAA7111, 56 SAA7113, 57 GM7113C, 58 SAA7114, 59 SAA7115, 60 SAA7118, 61}; 62 63enum saa711x_pads { 64 SAA711X_PAD_IF_INPUT, 65 SAA711X_PAD_VID_OUT, 66 SAA711X_NUM_PADS 67}; 68 69struct saa711x_state { 70 struct v4l2_subdev sd; 71#ifdef CONFIG_MEDIA_CONTROLLER 72 struct media_pad pads[SAA711X_NUM_PADS]; 73#endif 74 struct v4l2_ctrl_handler hdl; 75 76 struct { 77 /* chroma gain control cluster */ 78 struct v4l2_ctrl *agc; 79 struct v4l2_ctrl *gain; 80 }; 81 82 v4l2_std_id std; 83 int input; 84 int output; 85 int enable; 86 int radio; 87 int width; 88 int height; 89 enum saa711x_model ident; 90 u32 audclk_freq; 91 u32 crystal_freq; 92 bool ucgc; 93 u8 cgcdiv; 94 bool apll; 95 bool double_asclk; 96}; 97 98static inline struct saa711x_state *to_state(struct v4l2_subdev *sd) 99{ 100 return container_of(sd, struct saa711x_state, sd); 101} 102 103static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 104{ 105 return &container_of(ctrl->handler, struct saa711x_state, hdl)->sd; 106} 107 108/* ----------------------------------------------------------------------- */ 109 110static inline int saa711x_write(struct v4l2_subdev *sd, u8 reg, u8 value) 111{ 112 struct i2c_client *client = v4l2_get_subdevdata(sd); 113 114 return i2c_smbus_write_byte_data(client, reg, value); 115} 116 117/* Sanity routine to check if a register is present */ 118static int saa711x_has_reg(const int id, const u8 reg) 119{ 120 if (id == SAA7111) 121 return reg < 0x20 && reg != 0x01 && reg != 0x0f && 122 (reg < 0x13 || reg > 0x19) && reg != 0x1d && reg != 0x1e; 123 if (id == SAA7111A) 124 return reg < 0x20 && reg != 0x01 && reg != 0x0f && 125 reg != 0x14 && reg != 0x18 && reg != 0x19 && 126 reg != 0x1d && reg != 0x1e; 127 128 /* common for saa7113/4/5/8 */ 129 if (unlikely((reg >= 0x3b && reg <= 0x3f) || reg == 0x5c || reg == 0x5f || 130 reg == 0xa3 || reg == 0xa7 || reg == 0xab || reg == 0xaf || (reg >= 0xb5 && reg <= 0xb7) || 131 reg == 0xd3 || reg == 0xd7 || reg == 0xdb || reg == 0xdf || (reg >= 0xe5 && reg <= 0xe7) || 132 reg == 0x82 || (reg >= 0x89 && reg <= 0x8e))) 133 return 0; 134 135 switch (id) { 136 case GM7113C: 137 return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && reg < 0x20; 138 case SAA7113: 139 return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && (reg < 0x20 || reg > 0x3f) && 140 reg != 0x5d && reg < 0x63; 141 case SAA7114: 142 return (reg < 0x1a || reg > 0x1e) && (reg < 0x20 || reg > 0x2f) && 143 (reg < 0x63 || reg > 0x7f) && reg != 0x33 && reg != 0x37 && 144 reg != 0x81 && reg < 0xf0; 145 case SAA7115: 146 return (reg < 0x20 || reg > 0x2f) && reg != 0x65 && (reg < 0xfc || reg > 0xfe); 147 case SAA7118: 148 return (reg < 0x1a || reg > 0x1d) && (reg < 0x20 || reg > 0x22) && 149 (reg < 0x26 || reg > 0x28) && reg != 0x33 && reg != 0x37 && 150 (reg < 0x63 || reg > 0x7f) && reg != 0x81 && reg < 0xf0; 151 } 152 return 1; 153} 154 155static int saa711x_writeregs(struct v4l2_subdev *sd, const unsigned char *regs) 156{ 157 struct saa711x_state *state = to_state(sd); 158 unsigned char reg, data; 159 160 while (*regs != 0x00) { 161 reg = *(regs++); 162 data = *(regs++); 163 164 /* According with datasheets, reserved regs should be 165 filled with 0 - seems better not to touch on they */ 166 if (saa711x_has_reg(state->ident, reg)) { 167 if (saa711x_write(sd, reg, data) < 0) 168 return -1; 169 } else { 170 v4l2_dbg(1, debug, sd, "tried to access reserved reg 0x%02x\n", reg); 171 } 172 } 173 return 0; 174} 175 176static inline int saa711x_read(struct v4l2_subdev *sd, u8 reg) 177{ 178 struct i2c_client *client = v4l2_get_subdevdata(sd); 179 180 return i2c_smbus_read_byte_data(client, reg); 181} 182 183/* ----------------------------------------------------------------------- */ 184 185/* SAA7111 initialization table */ 186static const unsigned char saa7111_init[] = { 187 R_01_INC_DELAY, 0x00, /* reserved */ 188 189 /*front end */ 190 R_02_INPUT_CNTL_1, 0xd0, /* FUSE=3, GUDL=2, MODE=0 */ 191 R_03_INPUT_CNTL_2, 0x23, /* HLNRS=0, VBSL=1, WPOFF=0, HOLDG=0, 192 * GAFIX=0, GAI1=256, GAI2=256 */ 193 R_04_INPUT_CNTL_3, 0x00, /* GAI1=256 */ 194 R_05_INPUT_CNTL_4, 0x00, /* GAI2=256 */ 195 196 /* decoder */ 197 R_06_H_SYNC_START, 0xf3, /* HSB at 13(50Hz) / 17(60Hz) 198 * pixels after end of last line */ 199 R_07_H_SYNC_STOP, 0xe8, /* HSS seems to be needed to 200 * work with NTSC, too */ 201 R_08_SYNC_CNTL, 0xc8, /* AUFD=1, FSEL=1, EXFIL=0, 202 * VTRC=1, HPLL=0, VNOI=0 */ 203 R_09_LUMA_CNTL, 0x01, /* BYPS=0, PREF=0, BPSS=0, 204 * VBLB=0, UPTCV=0, APER=1 */ 205 R_0A_LUMA_BRIGHT_CNTL, 0x80, 206 R_0B_LUMA_CONTRAST_CNTL, 0x47, /* 0b - CONT=1.109 */ 207 R_0C_CHROMA_SAT_CNTL, 0x40, 208 R_0D_CHROMA_HUE_CNTL, 0x00, 209 R_0E_CHROMA_CNTL_1, 0x01, /* 0e - CDTO=0, CSTD=0, DCCF=0, 210 * FCTC=0, CHBW=1 */ 211 R_0F_CHROMA_GAIN_CNTL, 0x00, /* reserved */ 212 R_10_CHROMA_CNTL_2, 0x48, /* 10 - OFTS=1, HDEL=0, VRLN=1, YDEL=0 */ 213 R_11_MODE_DELAY_CNTL, 0x1c, /* 11 - GPSW=0, CM99=0, FECO=0, COMPO=1, 214 * OEYC=1, OEHV=1, VIPB=0, COLO=0 */ 215 R_12_RT_SIGNAL_CNTL, 0x00, /* 12 - output control 2 */ 216 R_13_RT_X_PORT_OUT_CNTL, 0x00, /* 13 - output control 3 */ 217 R_14_ANAL_ADC_COMPAT_CNTL, 0x00, 218 R_15_VGATE_START_FID_CHG, 0x00, 219 R_16_VGATE_STOP, 0x00, 220 R_17_MISC_VGATE_CONF_AND_MSB, 0x00, 221 222 0x00, 0x00 223}; 224 225/* 226 * This table has one illegal value, and some values that are not 227 * correct according to the datasheet initialization table. 228 * 229 * If you need a table with legal/default values tell the driver in 230 * i2c_board_info.platform_data, and you will get the gm7113c_init 231 * table instead. 232 */ 233 234/* SAA7113 Init codes */ 235static const unsigned char saa7113_init[] = { 236 R_01_INC_DELAY, 0x08, 237 R_02_INPUT_CNTL_1, 0xc2, 238 R_03_INPUT_CNTL_2, 0x30, 239 R_04_INPUT_CNTL_3, 0x00, 240 R_05_INPUT_CNTL_4, 0x00, 241 R_06_H_SYNC_START, 0x89, /* Illegal value -119, 242 * min. value = -108 (0x94) */ 243 R_07_H_SYNC_STOP, 0x0d, 244 R_08_SYNC_CNTL, 0x88, /* Not datasheet default. 245 * HTC = VTR mode, should be 0x98 */ 246 R_09_LUMA_CNTL, 0x01, 247 R_0A_LUMA_BRIGHT_CNTL, 0x80, 248 R_0B_LUMA_CONTRAST_CNTL, 0x47, 249 R_0C_CHROMA_SAT_CNTL, 0x40, 250 R_0D_CHROMA_HUE_CNTL, 0x00, 251 R_0E_CHROMA_CNTL_1, 0x01, 252 R_0F_CHROMA_GAIN_CNTL, 0x2a, 253 R_10_CHROMA_CNTL_2, 0x08, /* Not datsheet default. 254 * VRLN enabled, should be 0x00 */ 255 R_11_MODE_DELAY_CNTL, 0x0c, 256 R_12_RT_SIGNAL_CNTL, 0x07, /* Not datasheet default, 257 * should be 0x01 */ 258 R_13_RT_X_PORT_OUT_CNTL, 0x00, 259 R_14_ANAL_ADC_COMPAT_CNTL, 0x00, 260 R_15_VGATE_START_FID_CHG, 0x00, 261 R_16_VGATE_STOP, 0x00, 262 R_17_MISC_VGATE_CONF_AND_MSB, 0x00, 263 264 0x00, 0x00 265}; 266 267/* 268 * GM7113C is a clone of the SAA7113 chip 269 * This init table is copied out of the saa7113 datasheet. 270 * In R_08 we enable "Automatic Field Detection" [AUFD], 271 * this is disabled when saa711x_set_v4lstd is called. 272 */ 273static const unsigned char gm7113c_init[] = { 274 R_01_INC_DELAY, 0x08, 275 R_02_INPUT_CNTL_1, 0xc0, 276 R_03_INPUT_CNTL_2, 0x33, 277 R_04_INPUT_CNTL_3, 0x00, 278 R_05_INPUT_CNTL_4, 0x00, 279 R_06_H_SYNC_START, 0xe9, 280 R_07_H_SYNC_STOP, 0x0d, 281 R_08_SYNC_CNTL, 0x98, 282 R_09_LUMA_CNTL, 0x01, 283 R_0A_LUMA_BRIGHT_CNTL, 0x80, 284 R_0B_LUMA_CONTRAST_CNTL, 0x47, 285 R_0C_CHROMA_SAT_CNTL, 0x40, 286 R_0D_CHROMA_HUE_CNTL, 0x00, 287 R_0E_CHROMA_CNTL_1, 0x01, 288 R_0F_CHROMA_GAIN_CNTL, 0x2a, 289 R_10_CHROMA_CNTL_2, 0x00, 290 R_11_MODE_DELAY_CNTL, 0x0c, 291 R_12_RT_SIGNAL_CNTL, 0x01, 292 R_13_RT_X_PORT_OUT_CNTL, 0x00, 293 R_14_ANAL_ADC_COMPAT_CNTL, 0x00, 294 R_15_VGATE_START_FID_CHG, 0x00, 295 R_16_VGATE_STOP, 0x00, 296 R_17_MISC_VGATE_CONF_AND_MSB, 0x00, 297 298 0x00, 0x00 299}; 300 301/* If a value differs from the Hauppauge driver values, then the comment starts with 302 'was 0xXX' to denote the Hauppauge value. Otherwise the value is identical to what the 303 Hauppauge driver sets. */ 304 305/* SAA7114 and SAA7115 initialization table */ 306static const unsigned char saa7115_init_auto_input[] = { 307 /* Front-End Part */ 308 R_01_INC_DELAY, 0x48, /* white peak control disabled */ 309 R_03_INPUT_CNTL_2, 0x20, /* was 0x30. 0x20: long vertical blanking */ 310 R_04_INPUT_CNTL_3, 0x90, /* analog gain set to 0 */ 311 R_05_INPUT_CNTL_4, 0x90, /* analog gain set to 0 */ 312 /* Decoder Part */ 313 R_06_H_SYNC_START, 0xeb, /* horiz sync begin = -21 */ 314 R_07_H_SYNC_STOP, 0xe0, /* horiz sync stop = -17 */ 315 R_09_LUMA_CNTL, 0x53, /* 0x53, was 0x56 for 60hz. luminance control */ 316 R_0A_LUMA_BRIGHT_CNTL, 0x80, /* was 0x88. decoder brightness, 0x80 is itu standard */ 317 R_0B_LUMA_CONTRAST_CNTL, 0x44, /* was 0x48. decoder contrast, 0x44 is itu standard */ 318 R_0C_CHROMA_SAT_CNTL, 0x40, /* was 0x47. decoder saturation, 0x40 is itu standard */ 319 R_0D_CHROMA_HUE_CNTL, 0x00, 320 R_0F_CHROMA_GAIN_CNTL, 0x00, /* use automatic gain */ 321 R_10_CHROMA_CNTL_2, 0x06, /* chroma: active adaptive combfilter */ 322 R_11_MODE_DELAY_CNTL, 0x00, 323 R_12_RT_SIGNAL_CNTL, 0x9d, /* RTS0 output control: VGATE */ 324 R_13_RT_X_PORT_OUT_CNTL, 0x80, /* ITU656 standard mode, RTCO output enable RTCE */ 325 R_14_ANAL_ADC_COMPAT_CNTL, 0x00, 326 R_18_RAW_DATA_GAIN_CNTL, 0x40, /* gain 0x00 = nominal */ 327 R_19_RAW_DATA_OFF_CNTL, 0x80, 328 R_1A_COLOR_KILL_LVL_CNTL, 0x77, /* recommended value */ 329 R_1B_MISC_TVVCRDET, 0x42, /* recommended value */ 330 R_1C_ENHAN_COMB_CTRL1, 0xa9, /* recommended value */ 331 R_1D_ENHAN_COMB_CTRL2, 0x01, /* recommended value */ 332 333 334 R_80_GLOBAL_CNTL_1, 0x0, /* No tasks enabled at init */ 335 336 /* Power Device Control */ 337 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset device */ 338 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* set device programmed, all in operational mode */ 339 0x00, 0x00 340}; 341 342/* Used to reset saa7113, saa7114 and saa7115 */ 343static const unsigned char saa7115_cfg_reset_scaler[] = { 344 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00, /* disable I-port output */ 345 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ 346 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */ 347 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* enable I-port output */ 348 0x00, 0x00 349}; 350 351/* ============== SAA7715 VIDEO templates ============= */ 352 353static const unsigned char saa7115_cfg_60hz_video[] = { 354 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */ 355 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ 356 357 R_15_VGATE_START_FID_CHG, 0x03, 358 R_16_VGATE_STOP, 0x11, 359 R_17_MISC_VGATE_CONF_AND_MSB, 0x9c, 360 361 R_08_SYNC_CNTL, 0x68, /* 0xBO: auto detection, 0x68 = NTSC */ 362 R_0E_CHROMA_CNTL_1, 0x07, /* video autodetection is on */ 363 364 R_5A_V_OFF_FOR_SLICER, 0x06, /* standard 60hz value for ITU656 line counting */ 365 366 /* Task A */ 367 R_90_A_TASK_HANDLING_CNTL, 0x80, 368 R_91_A_X_PORT_FORMATS_AND_CONF, 0x48, 369 R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40, 370 R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84, 371 372 /* hoffset low (input), 0x0002 is minimum */ 373 R_94_A_HORIZ_INPUT_WINDOW_START, 0x01, 374 R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00, 375 376 /* hsize low (input), 0x02d0 = 720 */ 377 R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0, 378 R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02, 379 380 R_98_A_VERT_INPUT_WINDOW_START, 0x05, 381 R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00, 382 383 R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x0c, 384 R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00, 385 386 R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0, 387 R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05, 388 389 R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x0c, 390 R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00, 391 392 /* Task B */ 393 R_C0_B_TASK_HANDLING_CNTL, 0x00, 394 R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08, 395 R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00, 396 R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80, 397 398 /* 0x0002 is minimum */ 399 R_C4_B_HORIZ_INPUT_WINDOW_START, 0x02, 400 R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00, 401 402 /* 0x02d0 = 720 */ 403 R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0, 404 R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02, 405 406 /* vwindow start 0x12 = 18 */ 407 R_C8_B_VERT_INPUT_WINDOW_START, 0x12, 408 R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00, 409 410 /* vwindow length 0xf8 = 248 */ 411 R_CA_B_VERT_INPUT_WINDOW_LENGTH, VRES_60HZ>>1, 412 R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, VRES_60HZ>>9, 413 414 /* hwindow 0x02d0 = 720 */ 415 R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0, 416 R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02, 417 418 R_F0_LFCO_PER_LINE, 0xad, /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */ 419 R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0 */ 420 R_F5_PULSGEN_LINE_LENGTH, 0xad, 421 R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01, 422 423 0x00, 0x00 424}; 425 426static const unsigned char saa7115_cfg_50hz_video[] = { 427 R_80_GLOBAL_CNTL_1, 0x00, 428 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ 429 430 R_15_VGATE_START_FID_CHG, 0x37, /* VGATE start */ 431 R_16_VGATE_STOP, 0x16, 432 R_17_MISC_VGATE_CONF_AND_MSB, 0x99, 433 434 R_08_SYNC_CNTL, 0x28, /* 0x28 = PAL */ 435 R_0E_CHROMA_CNTL_1, 0x07, 436 437 R_5A_V_OFF_FOR_SLICER, 0x03, /* standard 50hz value */ 438 439 /* Task A */ 440 R_90_A_TASK_HANDLING_CNTL, 0x81, 441 R_91_A_X_PORT_FORMATS_AND_CONF, 0x48, 442 R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40, 443 R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84, 444 445 /* This is weird: the datasheet says that you should use 2 as the minimum value, */ 446 /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */ 447 /* hoffset low (input), 0x0002 is minimum */ 448 R_94_A_HORIZ_INPUT_WINDOW_START, 0x00, 449 R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00, 450 451 /* hsize low (input), 0x02d0 = 720 */ 452 R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0, 453 R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02, 454 455 R_98_A_VERT_INPUT_WINDOW_START, 0x03, 456 R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00, 457 458 /* vsize 0x12 = 18 */ 459 R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x12, 460 R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00, 461 462 /* hsize 0x05a0 = 1440 */ 463 R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0, 464 R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05, /* hsize hi (output) */ 465 R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x12, /* vsize low (output), 0x12 = 18 */ 466 R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00, /* vsize hi (output) */ 467 468 /* Task B */ 469 R_C0_B_TASK_HANDLING_CNTL, 0x00, 470 R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08, 471 R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00, 472 R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80, 473 474 /* This is weird: the datasheet says that you should use 2 as the minimum value, */ 475 /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */ 476 /* hoffset low (input), 0x0002 is minimum. See comment above. */ 477 R_C4_B_HORIZ_INPUT_WINDOW_START, 0x00, 478 R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00, 479 480 /* hsize 0x02d0 = 720 */ 481 R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0, 482 R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02, 483 484 /* voffset 0x16 = 22 */ 485 R_C8_B_VERT_INPUT_WINDOW_START, 0x16, 486 R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00, 487 488 /* vsize 0x0120 = 288 */ 489 R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0x20, 490 R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x01, 491 492 /* hsize 0x02d0 = 720 */ 493 R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0, 494 R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02, 495 496 R_F0_LFCO_PER_LINE, 0xb0, /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */ 497 R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0, (was 0x05) */ 498 R_F5_PULSGEN_LINE_LENGTH, 0xb0, 499 R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01, 500 501 0x00, 0x00 502}; 503 504/* ============== SAA7715 VIDEO templates (end) ======= */ 505 506static const unsigned char saa7115_cfg_vbi_on[] = { 507 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */ 508 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ 509 R_80_GLOBAL_CNTL_1, 0x30, /* Activate both tasks */ 510 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */ 511 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */ 512 513 0x00, 0x00 514}; 515 516static const unsigned char saa7115_cfg_vbi_off[] = { 517 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */ 518 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ 519 R_80_GLOBAL_CNTL_1, 0x20, /* Activate only task "B" */ 520 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */ 521 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */ 522 523 0x00, 0x00 524}; 525 526 527static const unsigned char saa7115_init_misc[] = { 528 R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F, 0x01, 529 R_83_X_PORT_I_O_ENA_AND_OUT_CLK, 0x01, 530 R_84_I_PORT_SIGNAL_DEF, 0x20, 531 R_85_I_PORT_SIGNAL_POLAR, 0x21, 532 R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT, 0xc5, 533 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, 534 535 /* Task A */ 536 R_A0_A_HORIZ_PRESCALING, 0x01, 537 R_A1_A_ACCUMULATION_LENGTH, 0x00, 538 R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00, 539 540 /* Configure controls at nominal value*/ 541 R_A4_A_LUMA_BRIGHTNESS_CNTL, 0x80, 542 R_A5_A_LUMA_CONTRAST_CNTL, 0x40, 543 R_A6_A_CHROMA_SATURATION_CNTL, 0x40, 544 545 /* note: 2 x zoom ensures that VBI lines have same length as video lines. */ 546 R_A8_A_HORIZ_LUMA_SCALING_INC, 0x00, 547 R_A9_A_HORIZ_LUMA_SCALING_INC_MSB, 0x02, 548 549 R_AA_A_HORIZ_LUMA_PHASE_OFF, 0x00, 550 551 /* must be horiz lum scaling / 2 */ 552 R_AC_A_HORIZ_CHROMA_SCALING_INC, 0x00, 553 R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB, 0x01, 554 555 /* must be offset luma / 2 */ 556 R_AE_A_HORIZ_CHROMA_PHASE_OFF, 0x00, 557 558 R_B0_A_VERT_LUMA_SCALING_INC, 0x00, 559 R_B1_A_VERT_LUMA_SCALING_INC_MSB, 0x04, 560 561 R_B2_A_VERT_CHROMA_SCALING_INC, 0x00, 562 R_B3_A_VERT_CHROMA_SCALING_INC_MSB, 0x04, 563 564 R_B4_A_VERT_SCALING_MODE_CNTL, 0x01, 565 566 R_B8_A_VERT_CHROMA_PHASE_OFF_00, 0x00, 567 R_B9_A_VERT_CHROMA_PHASE_OFF_01, 0x00, 568 R_BA_A_VERT_CHROMA_PHASE_OFF_10, 0x00, 569 R_BB_A_VERT_CHROMA_PHASE_OFF_11, 0x00, 570 571 R_BC_A_VERT_LUMA_PHASE_OFF_00, 0x00, 572 R_BD_A_VERT_LUMA_PHASE_OFF_01, 0x00, 573 R_BE_A_VERT_LUMA_PHASE_OFF_10, 0x00, 574 R_BF_A_VERT_LUMA_PHASE_OFF_11, 0x00, 575 576 /* Task B */ 577 R_D0_B_HORIZ_PRESCALING, 0x01, 578 R_D1_B_ACCUMULATION_LENGTH, 0x00, 579 R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00, 580 581 /* Configure controls at nominal value*/ 582 R_D4_B_LUMA_BRIGHTNESS_CNTL, 0x80, 583 R_D5_B_LUMA_CONTRAST_CNTL, 0x40, 584 R_D6_B_CHROMA_SATURATION_CNTL, 0x40, 585 586 /* hor lum scaling 0x0400 = 1 */ 587 R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00, 588 R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04, 589 590 R_DA_B_HORIZ_LUMA_PHASE_OFF, 0x00, 591 592 /* must be hor lum scaling / 2 */ 593 R_DC_B_HORIZ_CHROMA_SCALING, 0x00, 594 R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02, 595 596 /* must be offset luma / 2 */ 597 R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA, 0x00, 598 599 R_E0_B_VERT_LUMA_SCALING_INC, 0x00, 600 R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04, 601 602 R_E2_B_VERT_CHROMA_SCALING_INC, 0x00, 603 R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04, 604 605 R_E4_B_VERT_SCALING_MODE_CNTL, 0x01, 606 607 R_E8_B_VERT_CHROMA_PHASE_OFF_00, 0x00, 608 R_E9_B_VERT_CHROMA_PHASE_OFF_01, 0x00, 609 R_EA_B_VERT_CHROMA_PHASE_OFF_10, 0x00, 610 R_EB_B_VERT_CHROMA_PHASE_OFF_11, 0x00, 611 612 R_EC_B_VERT_LUMA_PHASE_OFF_00, 0x00, 613 R_ED_B_VERT_LUMA_PHASE_OFF_01, 0x00, 614 R_EE_B_VERT_LUMA_PHASE_OFF_10, 0x00, 615 R_EF_B_VERT_LUMA_PHASE_OFF_11, 0x00, 616 617 R_F2_NOMINAL_PLL2_DTO, 0x50, /* crystal clock = 24.576 MHz, target = 27MHz */ 618 R_F3_PLL_INCREMENT, 0x46, 619 R_F4_PLL2_STATUS, 0x00, 620 R_F7_PULSE_A_POS_MSB, 0x4b, /* not the recommended settings! */ 621 R_F8_PULSE_B_POS, 0x00, 622 R_F9_PULSE_B_POS_MSB, 0x4b, 623 R_FA_PULSE_C_POS, 0x00, 624 R_FB_PULSE_C_POS_MSB, 0x4b, 625 626 /* PLL2 lock detection settings: 71 lines 50% phase error */ 627 R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES, 0x88, 628 629 /* Turn off VBI */ 630 R_40_SLICER_CNTL_1, 0x20, /* No framing code errors allowed. */ 631 R_41_LCR_BASE, 0xff, 632 R_41_LCR_BASE+1, 0xff, 633 R_41_LCR_BASE+2, 0xff, 634 R_41_LCR_BASE+3, 0xff, 635 R_41_LCR_BASE+4, 0xff, 636 R_41_LCR_BASE+5, 0xff, 637 R_41_LCR_BASE+6, 0xff, 638 R_41_LCR_BASE+7, 0xff, 639 R_41_LCR_BASE+8, 0xff, 640 R_41_LCR_BASE+9, 0xff, 641 R_41_LCR_BASE+10, 0xff, 642 R_41_LCR_BASE+11, 0xff, 643 R_41_LCR_BASE+12, 0xff, 644 R_41_LCR_BASE+13, 0xff, 645 R_41_LCR_BASE+14, 0xff, 646 R_41_LCR_BASE+15, 0xff, 647 R_41_LCR_BASE+16, 0xff, 648 R_41_LCR_BASE+17, 0xff, 649 R_41_LCR_BASE+18, 0xff, 650 R_41_LCR_BASE+19, 0xff, 651 R_41_LCR_BASE+20, 0xff, 652 R_41_LCR_BASE+21, 0xff, 653 R_41_LCR_BASE+22, 0xff, 654 R_58_PROGRAM_FRAMING_CODE, 0x40, 655 R_59_H_OFF_FOR_SLICER, 0x47, 656 R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF, 0x83, 657 R_5D_DID, 0xbd, 658 R_5E_SDID, 0x35, 659 660 R_02_INPUT_CNTL_1, 0xc4, /* input tuner -> input 4, amplifier active */ 661 662 R_80_GLOBAL_CNTL_1, 0x20, /* enable task B */ 663 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, 664 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, 665 0x00, 0x00 666}; 667 668static int saa711x_decode_vps(u8 *dst, u8 *p) 669{ 670 static const u8 biphase_tbl[] = { 671 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, 672 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, 673 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96, 674 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2, 675 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94, 676 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0, 677 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, 678 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, 679 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5, 680 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1, 681 0xc3, 0x4b, 0x43, 0xc3, 0x87, 0x0f, 0x07, 0x87, 682 0x83, 0x0b, 0x03, 0x83, 0xc3, 0x4b, 0x43, 0xc3, 683 0xc1, 0x49, 0x41, 0xc1, 0x85, 0x0d, 0x05, 0x85, 684 0x81, 0x09, 0x01, 0x81, 0xc1, 0x49, 0x41, 0xc1, 685 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5, 686 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1, 687 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4, 688 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0, 689 0xc2, 0x4a, 0x42, 0xc2, 0x86, 0x0e, 0x06, 0x86, 690 0x82, 0x0a, 0x02, 0x82, 0xc2, 0x4a, 0x42, 0xc2, 691 0xc0, 0x48, 0x40, 0xc0, 0x84, 0x0c, 0x04, 0x84, 692 0x80, 0x08, 0x00, 0x80, 0xc0, 0x48, 0x40, 0xc0, 693 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4, 694 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0, 695 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, 696 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, 697 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96, 698 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2, 699 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94, 700 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0, 701 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, 702 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, 703 }; 704 int i; 705 u8 c, err = 0; 706 707 for (i = 0; i < 2 * 13; i += 2) { 708 err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]]; 709 c = (biphase_tbl[p[i + 1]] & 0xf) | ((biphase_tbl[p[i]] & 0xf) << 4); 710 dst[i / 2] = c; 711 } 712 return err & 0xf0; 713} 714 715static int saa711x_decode_wss(u8 *p) 716{ 717 static const int wss_bits[8] = { 718 0, 0, 0, 1, 0, 1, 1, 1 719 }; 720 unsigned char parity; 721 int wss = 0; 722 int i; 723 724 for (i = 0; i < 16; i++) { 725 int b1 = wss_bits[p[i] & 7]; 726 int b2 = wss_bits[(p[i] >> 3) & 7]; 727 728 if (b1 == b2) 729 return -1; 730 wss |= b2 << i; 731 } 732 parity = wss & 15; 733 parity ^= parity >> 2; 734 parity ^= parity >> 1; 735 736 if (!(parity & 1)) 737 return -1; 738 739 return wss; 740} 741 742static int saa711x_s_clock_freq(struct v4l2_subdev *sd, u32 freq) 743{ 744 struct saa711x_state *state = to_state(sd); 745 u32 acpf; 746 u32 acni; 747 u32 hz; 748 u64 f; 749 u8 acc = 0; /* reg 0x3a, audio clock control */ 750 751 /* Checks for chips that don't have audio clock (saa7111, saa7113) */ 752 if (!saa711x_has_reg(state->ident, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD)) 753 return 0; 754 755 v4l2_dbg(1, debug, sd, "set audio clock freq: %d\n", freq); 756 757 /* sanity check */ 758 if (freq < 32000 || freq > 48000) 759 return -EINVAL; 760 761 /* hz is the refresh rate times 100 */ 762 hz = (state->std & V4L2_STD_525_60) ? 5994 : 5000; 763 /* acpf = (256 * freq) / field_frequency == (256 * 100 * freq) / hz */ 764 acpf = (25600 * freq) / hz; 765 /* acni = (256 * freq * 2^23) / crystal_frequency = 766 (freq * 2^(8+23)) / crystal_frequency = 767 (freq << 31) / crystal_frequency */ 768 f = freq; 769 f = f << 31; 770 do_div(f, state->crystal_freq); 771 acni = f; 772 if (state->ucgc) { 773 acpf = acpf * state->cgcdiv / 16; 774 acni = acni * state->cgcdiv / 16; 775 acc = 0x80; 776 if (state->cgcdiv == 3) 777 acc |= 0x40; 778 } 779 if (state->apll) 780 acc |= 0x08; 781 782 if (state->double_asclk) { 783 acpf <<= 1; 784 acni <<= 1; 785 } 786 saa711x_write(sd, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03); 787 saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10 << state->double_asclk); 788 saa711x_write(sd, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc); 789 790 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff); 791 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+1, 792 (acpf >> 8) & 0xff); 793 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+2, 794 (acpf >> 16) & 0x03); 795 796 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC, acni & 0xff); 797 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+1, (acni >> 8) & 0xff); 798 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+2, (acni >> 16) & 0x3f); 799 state->audclk_freq = freq; 800 return 0; 801} 802 803static int saa711x_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 804{ 805 struct v4l2_subdev *sd = to_sd(ctrl); 806 struct saa711x_state *state = to_state(sd); 807 808 switch (ctrl->id) { 809 case V4L2_CID_CHROMA_AGC: 810 /* chroma gain cluster */ 811 if (state->agc->val) 812 state->gain->val = 813 saa711x_read(sd, R_0F_CHROMA_GAIN_CNTL) & 0x7f; 814 break; 815 } 816 return 0; 817} 818 819static int saa711x_s_ctrl(struct v4l2_ctrl *ctrl) 820{ 821 struct v4l2_subdev *sd = to_sd(ctrl); 822 struct saa711x_state *state = to_state(sd); 823 824 switch (ctrl->id) { 825 case V4L2_CID_BRIGHTNESS: 826 saa711x_write(sd, R_0A_LUMA_BRIGHT_CNTL, ctrl->val); 827 break; 828 829 case V4L2_CID_CONTRAST: 830 saa711x_write(sd, R_0B_LUMA_CONTRAST_CNTL, ctrl->val); 831 break; 832 833 case V4L2_CID_SATURATION: 834 saa711x_write(sd, R_0C_CHROMA_SAT_CNTL, ctrl->val); 835 break; 836 837 case V4L2_CID_HUE: 838 saa711x_write(sd, R_0D_CHROMA_HUE_CNTL, ctrl->val); 839 break; 840 841 case V4L2_CID_CHROMA_AGC: 842 /* chroma gain cluster */ 843 if (state->agc->val) 844 saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val); 845 else 846 saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val | 0x80); 847 break; 848 849 default: 850 return -EINVAL; 851 } 852 853 return 0; 854} 855 856static int saa711x_set_size(struct v4l2_subdev *sd, int width, int height) 857{ 858 struct saa711x_state *state = to_state(sd); 859 int HPSC, HFSC; 860 int VSCY; 861 int res; 862 int is_50hz = state->std & V4L2_STD_625_50; 863 int Vsrc = is_50hz ? 576 : 480; 864 865 v4l2_dbg(1, debug, sd, "decoder set size to %ix%i\n", width, height); 866 867 /* FIXME need better bounds checking here */ 868 if ((width < 1) || (width > 1440)) 869 return -EINVAL; 870 if ((height < 1) || (height > Vsrc)) 871 return -EINVAL; 872 873 if (!saa711x_has_reg(state->ident, R_D0_B_HORIZ_PRESCALING)) { 874 /* Decoder only supports 720 columns and 480 or 576 lines */ 875 if (width != 720) 876 return -EINVAL; 877 if (height != Vsrc) 878 return -EINVAL; 879 } 880 881 state->width = width; 882 state->height = height; 883 884 if (!saa711x_has_reg(state->ident, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH)) 885 return 0; 886 887 /* probably have a valid size, let's set it */ 888 /* Set output width/height */ 889 /* width */ 890 891 saa711x_write(sd, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 892 (u8) (width & 0xff)); 893 saa711x_write(sd, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 894 (u8) ((width >> 8) & 0xff)); 895 896 /* Vertical Scaling uses height/2 */ 897 res = height / 2; 898 899 /* On 60Hz, it is using a higher Vertical Output Size */ 900 if (!is_50hz) 901 res += (VRES_60HZ - 480) >> 1; 902 903 /* height */ 904 saa711x_write(sd, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, 905 (u8) (res & 0xff)); 906 saa711x_write(sd, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 907 (u8) ((res >> 8) & 0xff)); 908 909 /* Scaling settings */ 910 /* Hprescaler is floor(inres/outres) */ 911 HPSC = (int)(720 / width); 912 /* 0 is not allowed (div. by zero) */ 913 HPSC = HPSC ? HPSC : 1; 914 HFSC = (int)((1024 * 720) / (HPSC * width)); 915 /* FIXME hardcodes to "Task B" 916 * write H prescaler integer */ 917 saa711x_write(sd, R_D0_B_HORIZ_PRESCALING, 918 (u8) (HPSC & 0x3f)); 919 920 v4l2_dbg(1, debug, sd, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC); 921 /* write H fine-scaling (luminance) */ 922 saa711x_write(sd, R_D8_B_HORIZ_LUMA_SCALING_INC, 923 (u8) (HFSC & 0xff)); 924 saa711x_write(sd, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 925 (u8) ((HFSC >> 8) & 0xff)); 926 /* write H fine-scaling (chrominance) 927 * must be lum/2, so i'll just bitshift :) */ 928 saa711x_write(sd, R_DC_B_HORIZ_CHROMA_SCALING, 929 (u8) ((HFSC >> 1) & 0xff)); 930 saa711x_write(sd, R_DD_B_HORIZ_CHROMA_SCALING_MSB, 931 (u8) ((HFSC >> 9) & 0xff)); 932 933 VSCY = (int)((1024 * Vsrc) / height); 934 v4l2_dbg(1, debug, sd, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY); 935 936 /* Correct Contrast and Luminance */ 937 saa711x_write(sd, R_D5_B_LUMA_CONTRAST_CNTL, 938 (u8) (64 * 1024 / VSCY)); 939 saa711x_write(sd, R_D6_B_CHROMA_SATURATION_CNTL, 940 (u8) (64 * 1024 / VSCY)); 941 942 /* write V fine-scaling (luminance) */ 943 saa711x_write(sd, R_E0_B_VERT_LUMA_SCALING_INC, 944 (u8) (VSCY & 0xff)); 945 saa711x_write(sd, R_E1_B_VERT_LUMA_SCALING_INC_MSB, 946 (u8) ((VSCY >> 8) & 0xff)); 947 /* write V fine-scaling (chrominance) */ 948 saa711x_write(sd, R_E2_B_VERT_CHROMA_SCALING_INC, 949 (u8) (VSCY & 0xff)); 950 saa711x_write(sd, R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 951 (u8) ((VSCY >> 8) & 0xff)); 952 953 saa711x_writeregs(sd, saa7115_cfg_reset_scaler); 954 955 /* Activates task "B" */ 956 saa711x_write(sd, R_80_GLOBAL_CNTL_1, 957 saa711x_read(sd, R_80_GLOBAL_CNTL_1) | 0x20); 958 959 return 0; 960} 961 962static void saa711x_set_v4lstd(struct v4l2_subdev *sd, v4l2_std_id std) 963{ 964 struct saa711x_state *state = to_state(sd); 965 966 /* Prevent unnecessary standard changes. During a standard 967 change the I-Port is temporarily disabled. Any devices 968 reading from that port can get confused. 969 Note that s_std is also used to switch from 970 radio to TV mode, so if a s_std is broadcast to 971 all I2C devices then you do not want to have an unwanted 972 side-effect here. */ 973 if (std == state->std) 974 return; 975 976 state->std = std; 977 978 // This works for NTSC-M, SECAM-L and the 50Hz PAL variants. 979 if (std & V4L2_STD_525_60) { 980 v4l2_dbg(1, debug, sd, "decoder set standard 60 Hz\n"); 981 if (state->ident == GM7113C) { 982 u8 reg = saa711x_read(sd, R_08_SYNC_CNTL); 983 reg &= ~(SAA7113_R_08_FSEL | SAA7113_R_08_AUFD); 984 reg |= SAA7113_R_08_FSEL; 985 saa711x_write(sd, R_08_SYNC_CNTL, reg); 986 } else { 987 saa711x_writeregs(sd, saa7115_cfg_60hz_video); 988 } 989 saa711x_set_size(sd, 720, 480); 990 } else { 991 v4l2_dbg(1, debug, sd, "decoder set standard 50 Hz\n"); 992 if (state->ident == GM7113C) { 993 u8 reg = saa711x_read(sd, R_08_SYNC_CNTL); 994 reg &= ~(SAA7113_R_08_FSEL | SAA7113_R_08_AUFD); 995 saa711x_write(sd, R_08_SYNC_CNTL, reg); 996 } else { 997 saa711x_writeregs(sd, saa7115_cfg_50hz_video); 998 } 999 saa711x_set_size(sd, 720, 576); 1000 } 1001 1002 /* Register 0E - Bits D6-D4 on NO-AUTO mode 1003 (SAA7111 and SAA7113 doesn't have auto mode) 1004 50 Hz / 625 lines 60 Hz / 525 lines 1005 000 PAL BGDHI (4.43Mhz) NTSC M (3.58MHz) 1006 001 NTSC 4.43 (50 Hz) PAL 4.43 (60 Hz) 1007 010 Combination-PAL N (3.58MHz) NTSC 4.43 (60 Hz) 1008 011 NTSC N (3.58MHz) PAL M (3.58MHz) 1009 100 reserved NTSC-Japan (3.58MHz) 1010 */ 1011 if (state->ident <= SAA7113 || 1012 state->ident == GM7113C) { 1013 u8 reg = saa711x_read(sd, R_0E_CHROMA_CNTL_1) & 0x8f; 1014 1015 if (std == V4L2_STD_PAL_M) { 1016 reg |= 0x30; 1017 } else if (std == V4L2_STD_PAL_Nc) { 1018 reg |= 0x20; 1019 } else if (std == V4L2_STD_PAL_60) { 1020 reg |= 0x10; 1021 } else if (std == V4L2_STD_NTSC_M_JP) { 1022 reg |= 0x40; 1023 } else if (std & V4L2_STD_SECAM) { 1024 reg |= 0x50; 1025 } 1026 saa711x_write(sd, R_0E_CHROMA_CNTL_1, reg); 1027 } else { 1028 /* restart task B if needed */ 1029 int taskb = saa711x_read(sd, R_80_GLOBAL_CNTL_1) & 0x10; 1030 1031 if (taskb && state->ident == SAA7114) 1032 saa711x_writeregs(sd, saa7115_cfg_vbi_on); 1033 1034 /* switch audio mode too! */ 1035 saa711x_s_clock_freq(sd, state->audclk_freq); 1036 } 1037} 1038 1039/* setup the sliced VBI lcr registers according to the sliced VBI format */ 1040static void saa711x_set_lcr(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt) 1041{ 1042 struct saa711x_state *state = to_state(sd); 1043 int is_50hz = (state->std & V4L2_STD_625_50); 1044 u8 lcr[24]; 1045 int i, x; 1046 1047#if 1 1048 /* saa7113/7114/7118 VBI support are experimental */ 1049 if (!saa711x_has_reg(state->ident, R_41_LCR_BASE)) 1050 return; 1051 1052#else 1053 /* SAA7113 and SAA7118 also should support VBI - Need testing */ 1054 if (state->ident != SAA7115) 1055 return; 1056#endif 1057 1058 for (i = 0; i <= 23; i++) 1059 lcr[i] = 0xff; 1060 1061 if (fmt == NULL) { 1062 /* raw VBI */ 1063 if (is_50hz) 1064 for (i = 6; i <= 23; i++) 1065 lcr[i] = 0xdd; 1066 else 1067 for (i = 10; i <= 21; i++) 1068 lcr[i] = 0xdd; 1069 } else { 1070 /* sliced VBI */ 1071 /* first clear lines that cannot be captured */ 1072 if (is_50hz) { 1073 for (i = 0; i <= 5; i++) 1074 fmt->service_lines[0][i] = 1075 fmt->service_lines[1][i] = 0; 1076 } 1077 else { 1078 for (i = 0; i <= 9; i++) 1079 fmt->service_lines[0][i] = 1080 fmt->service_lines[1][i] = 0; 1081 for (i = 22; i <= 23; i++) 1082 fmt->service_lines[0][i] = 1083 fmt->service_lines[1][i] = 0; 1084 } 1085 1086 /* Now set the lcr values according to the specified service */ 1087 for (i = 6; i <= 23; i++) { 1088 lcr[i] = 0; 1089 for (x = 0; x <= 1; x++) { 1090 switch (fmt->service_lines[1-x][i]) { 1091 case 0: 1092 lcr[i] |= 0xf << (4 * x); 1093 break; 1094 case V4L2_SLICED_TELETEXT_B: 1095 lcr[i] |= 1 << (4 * x); 1096 break; 1097 case V4L2_SLICED_CAPTION_525: 1098 lcr[i] |= 4 << (4 * x); 1099 break; 1100 case V4L2_SLICED_WSS_625: 1101 lcr[i] |= 5 << (4 * x); 1102 break; 1103 case V4L2_SLICED_VPS: 1104 lcr[i] |= 7 << (4 * x); 1105 break; 1106 } 1107 } 1108 } 1109 } 1110 1111 /* write the lcr registers */ 1112 for (i = 2; i <= 23; i++) { 1113 saa711x_write(sd, i - 2 + R_41_LCR_BASE, lcr[i]); 1114 } 1115 1116 /* enable/disable raw VBI capturing */ 1117 saa711x_writeregs(sd, fmt == NULL ? 1118 saa7115_cfg_vbi_on : 1119 saa7115_cfg_vbi_off); 1120} 1121 1122static int saa711x_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *sliced) 1123{ 1124 static const u16 lcr2vbi[] = { 1125 0, V4L2_SLICED_TELETEXT_B, 0, /* 1 */ 1126 0, V4L2_SLICED_CAPTION_525, /* 4 */ 1127 V4L2_SLICED_WSS_625, 0, /* 5 */ 1128 V4L2_SLICED_VPS, 0, 0, 0, 0, /* 7 */ 1129 0, 0, 0, 0 1130 }; 1131 int i; 1132 1133 memset(sliced->service_lines, 0, sizeof(sliced->service_lines)); 1134 sliced->service_set = 0; 1135 /* done if using raw VBI */ 1136 if (saa711x_read(sd, R_80_GLOBAL_CNTL_1) & 0x10) 1137 return 0; 1138 for (i = 2; i <= 23; i++) { 1139 u8 v = saa711x_read(sd, i - 2 + R_41_LCR_BASE); 1140 1141 sliced->service_lines[0][i] = lcr2vbi[v >> 4]; 1142 sliced->service_lines[1][i] = lcr2vbi[v & 0xf]; 1143 sliced->service_set |= 1144 sliced->service_lines[0][i] | sliced->service_lines[1][i]; 1145 } 1146 return 0; 1147} 1148 1149static int saa711x_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt) 1150{ 1151 saa711x_set_lcr(sd, NULL); 1152 return 0; 1153} 1154 1155static int saa711x_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt) 1156{ 1157 saa711x_set_lcr(sd, fmt); 1158 return 0; 1159} 1160 1161static int saa711x_set_fmt(struct v4l2_subdev *sd, 1162 struct v4l2_subdev_state *sd_state, 1163 struct v4l2_subdev_format *format) 1164{ 1165 struct v4l2_mbus_framefmt *fmt = &format->format; 1166 1167 if (format->pad || fmt->code != MEDIA_BUS_FMT_FIXED) 1168 return -EINVAL; 1169 fmt->field = V4L2_FIELD_INTERLACED; 1170 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; 1171 if (format->which == V4L2_SUBDEV_FORMAT_TRY) 1172 return 0; 1173 return saa711x_set_size(sd, fmt->width, fmt->height); 1174} 1175 1176/* Decode the sliced VBI data stream as created by the saa7115. 1177 The format is described in the saa7115 datasheet in Tables 25 and 26 1178 and in Figure 33. 1179 The current implementation uses SAV/EAV codes and not the ancillary data 1180 headers. The vbi->p pointer points to the R_5E_SDID byte right after the SAV 1181 code. */ 1182static int saa711x_decode_vbi_line(struct v4l2_subdev *sd, struct v4l2_decode_vbi_line *vbi) 1183{ 1184 struct saa711x_state *state = to_state(sd); 1185 static const char vbi_no_data_pattern[] = { 1186 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0 1187 }; 1188 u8 *p = vbi->p; 1189 u32 wss; 1190 int id1, id2; /* the ID1 and ID2 bytes from the internal header */ 1191 1192 vbi->type = 0; /* mark result as a failure */ 1193 id1 = p[2]; 1194 id2 = p[3]; 1195 /* Note: the field bit is inverted for 60 Hz video */ 1196 if (state->std & V4L2_STD_525_60) 1197 id1 ^= 0x40; 1198 1199 /* Skip internal header, p now points to the start of the payload */ 1200 p += 4; 1201 vbi->p = p; 1202 1203 /* calculate field and line number of the VBI packet (1-23) */ 1204 vbi->is_second_field = ((id1 & 0x40) != 0); 1205 vbi->line = (id1 & 0x3f) << 3; 1206 vbi->line |= (id2 & 0x70) >> 4; 1207 1208 /* Obtain data type */ 1209 id2 &= 0xf; 1210 1211 /* If the VBI slicer does not detect any signal it will fill up 1212 the payload buffer with 0xa0 bytes. */ 1213 if (!memcmp(p, vbi_no_data_pattern, sizeof(vbi_no_data_pattern))) 1214 return 0; 1215 1216 /* decode payloads */ 1217 switch (id2) { 1218 case 1: 1219 vbi->type = V4L2_SLICED_TELETEXT_B; 1220 break; 1221 case 4: 1222 if (!parity8(p[0]) || !parity8(p[1])) 1223 return 0; 1224 vbi->type = V4L2_SLICED_CAPTION_525; 1225 break; 1226 case 5: 1227 wss = saa711x_decode_wss(p); 1228 if (wss == -1) 1229 return 0; 1230 p[0] = wss & 0xff; 1231 p[1] = wss >> 8; 1232 vbi->type = V4L2_SLICED_WSS_625; 1233 break; 1234 case 7: 1235 if (saa711x_decode_vps(p, p) != 0) 1236 return 0; 1237 vbi->type = V4L2_SLICED_VPS; 1238 break; 1239 default: 1240 break; 1241 } 1242 return 0; 1243} 1244 1245/* ============ SAA7115 AUDIO settings (end) ============= */ 1246 1247static int saa711x_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt) 1248{ 1249 struct saa711x_state *state = to_state(sd); 1250 int status; 1251 1252 if (state->radio) 1253 return 0; 1254 status = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC); 1255 1256 v4l2_dbg(1, debug, sd, "status: 0x%02x\n", status); 1257 vt->signal = ((status & (1 << 6)) == 0) ? 0xffff : 0x0; 1258 return 0; 1259} 1260 1261static int saa711x_s_std(struct v4l2_subdev *sd, v4l2_std_id std) 1262{ 1263 struct saa711x_state *state = to_state(sd); 1264 1265 state->radio = 0; 1266 saa711x_set_v4lstd(sd, std); 1267 return 0; 1268} 1269 1270static int saa711x_s_radio(struct v4l2_subdev *sd) 1271{ 1272 struct saa711x_state *state = to_state(sd); 1273 1274 state->radio = 1; 1275 return 0; 1276} 1277 1278static int saa711x_s_routing(struct v4l2_subdev *sd, 1279 u32 input, u32 output, u32 config) 1280{ 1281 struct saa711x_state *state = to_state(sd); 1282 u8 mask = (state->ident <= SAA7111A) ? 0xf8 : 0xf0; 1283 1284 v4l2_dbg(1, debug, sd, "decoder set input %d output %d\n", 1285 input, output); 1286 1287 /* saa7111/3 does not have these inputs */ 1288 if ((state->ident <= SAA7113 || 1289 state->ident == GM7113C) && 1290 (input == SAA7115_COMPOSITE4 || 1291 input == SAA7115_COMPOSITE5)) { 1292 return -EINVAL; 1293 } 1294 if (input > SAA7115_SVIDEO3) 1295 return -EINVAL; 1296 if (state->input == input && state->output == output) 1297 return 0; 1298 v4l2_dbg(1, debug, sd, "now setting %s input %s output\n", 1299 (input >= SAA7115_SVIDEO0) ? "S-Video" : "Composite", 1300 (output == SAA7115_IPORT_ON) ? "iport on" : "iport off"); 1301 state->input = input; 1302 1303 /* saa7111 has slightly different input numbering */ 1304 if (state->ident <= SAA7111A) { 1305 if (input >= SAA7115_COMPOSITE4) 1306 input -= 2; 1307 /* saa7111 specific */ 1308 saa711x_write(sd, R_10_CHROMA_CNTL_2, 1309 (saa711x_read(sd, R_10_CHROMA_CNTL_2) & 0x3f) | 1310 ((output & 0xc0) ^ 0x40)); 1311 saa711x_write(sd, R_13_RT_X_PORT_OUT_CNTL, 1312 (saa711x_read(sd, R_13_RT_X_PORT_OUT_CNTL) & 0xf0) | 1313 ((output & 2) ? 0x0a : 0)); 1314 } 1315 1316 /* select mode */ 1317 saa711x_write(sd, R_02_INPUT_CNTL_1, 1318 (saa711x_read(sd, R_02_INPUT_CNTL_1) & mask) | 1319 input); 1320 1321 /* bypass chrominance trap for S-Video modes */ 1322 saa711x_write(sd, R_09_LUMA_CNTL, 1323 (saa711x_read(sd, R_09_LUMA_CNTL) & 0x7f) | 1324 (state->input >= SAA7115_SVIDEO0 ? 0x80 : 0x0)); 1325 1326 state->output = output; 1327 if (state->ident == SAA7114 || 1328 state->ident == SAA7115) { 1329 saa711x_write(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK, 1330 (saa711x_read(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK) & 0xfe) | 1331 (state->output & 0x01)); 1332 } 1333 if (state->ident > SAA7111A) { 1334 if (config & SAA7115_IDQ_IS_DEFAULT) 1335 saa711x_write(sd, R_85_I_PORT_SIGNAL_POLAR, 0x20); 1336 else 1337 saa711x_write(sd, R_85_I_PORT_SIGNAL_POLAR, 0x21); 1338 } 1339 return 0; 1340} 1341 1342static int saa711x_s_gpio(struct v4l2_subdev *sd, u32 val) 1343{ 1344 struct saa711x_state *state = to_state(sd); 1345 1346 if (state->ident > SAA7111A) 1347 return -EINVAL; 1348 saa711x_write(sd, 0x11, (saa711x_read(sd, 0x11) & 0x7f) | 1349 (val ? 0x80 : 0)); 1350 return 0; 1351} 1352 1353static int saa711x_s_stream(struct v4l2_subdev *sd, int enable) 1354{ 1355 struct saa711x_state *state = to_state(sd); 1356 1357 v4l2_dbg(1, debug, sd, "%s output\n", 1358 enable ? "enable" : "disable"); 1359 1360 if (state->enable == enable) 1361 return 0; 1362 state->enable = enable; 1363 if (!saa711x_has_reg(state->ident, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED)) 1364 return 0; 1365 saa711x_write(sd, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, state->enable); 1366 return 0; 1367} 1368 1369static int saa711x_s_crystal_freq(struct v4l2_subdev *sd, u32 freq, u32 flags) 1370{ 1371 struct saa711x_state *state = to_state(sd); 1372 1373 if (freq != SAA7115_FREQ_32_11_MHZ && freq != SAA7115_FREQ_24_576_MHZ) 1374 return -EINVAL; 1375 state->crystal_freq = freq; 1376 state->double_asclk = flags & SAA7115_FREQ_FL_DOUBLE_ASCLK; 1377 state->cgcdiv = (flags & SAA7115_FREQ_FL_CGCDIV) ? 3 : 4; 1378 state->ucgc = flags & SAA7115_FREQ_FL_UCGC; 1379 state->apll = flags & SAA7115_FREQ_FL_APLL; 1380 saa711x_s_clock_freq(sd, state->audclk_freq); 1381 return 0; 1382} 1383 1384static int saa711x_reset(struct v4l2_subdev *sd, u32 val) 1385{ 1386 v4l2_dbg(1, debug, sd, "decoder RESET\n"); 1387 saa711x_writeregs(sd, saa7115_cfg_reset_scaler); 1388 return 0; 1389} 1390 1391static int saa711x_g_vbi_data(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_data *data) 1392{ 1393 /* Note: the internal field ID is inverted for NTSC, 1394 so data->field 0 maps to the saa7115 even field, 1395 whereas for PAL it maps to the saa7115 odd field. */ 1396 switch (data->id) { 1397 case V4L2_SLICED_WSS_625: 1398 if (saa711x_read(sd, 0x6b) & 0xc0) 1399 return -EIO; 1400 data->data[0] = saa711x_read(sd, 0x6c); 1401 data->data[1] = saa711x_read(sd, 0x6d); 1402 return 0; 1403 case V4L2_SLICED_CAPTION_525: 1404 if (data->field == 0) { 1405 /* CC */ 1406 if (saa711x_read(sd, 0x66) & 0x30) 1407 return -EIO; 1408 data->data[0] = saa711x_read(sd, 0x69); 1409 data->data[1] = saa711x_read(sd, 0x6a); 1410 return 0; 1411 } 1412 /* XDS */ 1413 if (saa711x_read(sd, 0x66) & 0xc0) 1414 return -EIO; 1415 data->data[0] = saa711x_read(sd, 0x67); 1416 data->data[1] = saa711x_read(sd, 0x68); 1417 return 0; 1418 default: 1419 return -EINVAL; 1420 } 1421} 1422 1423static int saa711x_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 1424{ 1425 struct saa711x_state *state = to_state(sd); 1426 int reg1f, reg1e; 1427 1428 /* 1429 * The V4L2 core already initializes std with all supported 1430 * Standards. All driver needs to do is to mask it, to remove 1431 * standards that don't apply from the mask 1432 */ 1433 1434 reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC); 1435 1436 if (state->ident == SAA7115) { 1437 reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC); 1438 1439 v4l2_dbg(1, debug, sd, "Status byte 1 (0x1e)=0x%02x\n", reg1e); 1440 1441 switch (reg1e & 0x03) { 1442 case 1: 1443 *std &= V4L2_STD_NTSC; 1444 break; 1445 case 2: 1446 /* 1447 * V4L2_STD_PAL just cover the european PAL standards. 1448 * This is wrong, as the device could also be using an 1449 * other PAL standard. 1450 */ 1451 *std &= V4L2_STD_PAL | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | 1452 V4L2_STD_PAL_M | V4L2_STD_PAL_60; 1453 break; 1454 case 3: 1455 *std &= V4L2_STD_SECAM; 1456 break; 1457 default: 1458 *std = V4L2_STD_UNKNOWN; 1459 /* Can't detect anything */ 1460 break; 1461 } 1462 } 1463 1464 v4l2_dbg(1, debug, sd, "Status byte 2 (0x1f)=0x%02x\n", reg1f); 1465 1466 /* horizontal/vertical not locked */ 1467 if (reg1f & 0x40) { 1468 *std = V4L2_STD_UNKNOWN; 1469 goto ret; 1470 } 1471 1472 if (reg1f & 0x20) 1473 *std &= V4L2_STD_525_60; 1474 else 1475 *std &= V4L2_STD_625_50; 1476 1477ret: 1478 v4l2_dbg(1, debug, sd, "detected std mask = %08Lx\n", *std); 1479 1480 return 0; 1481} 1482 1483static int saa711x_g_input_status(struct v4l2_subdev *sd, u32 *status) 1484{ 1485 struct saa711x_state *state = to_state(sd); 1486 int reg1e = 0x80; 1487 int reg1f; 1488 1489 *status = V4L2_IN_ST_NO_SIGNAL; 1490 if (state->ident == SAA7115) 1491 reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC); 1492 reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC); 1493 if ((reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80) 1494 *status = 0; 1495 return 0; 1496} 1497 1498#ifdef CONFIG_VIDEO_ADV_DEBUG 1499static int saa711x_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) 1500{ 1501 reg->val = saa711x_read(sd, reg->reg & 0xff); 1502 reg->size = 1; 1503 return 0; 1504} 1505 1506static int saa711x_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) 1507{ 1508 saa711x_write(sd, reg->reg & 0xff, reg->val & 0xff); 1509 return 0; 1510} 1511#endif 1512 1513static int saa711x_log_status(struct v4l2_subdev *sd) 1514{ 1515 struct saa711x_state *state = to_state(sd); 1516 int reg1e, reg1f; 1517 int signalOk; 1518 int vcr; 1519 1520 v4l2_info(sd, "Audio frequency: %d Hz\n", state->audclk_freq); 1521 if (state->ident != SAA7115) { 1522 /* status for the saa7114 */ 1523 reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC); 1524 signalOk = (reg1f & 0xc1) == 0x81; 1525 v4l2_info(sd, "Video signal: %s\n", signalOk ? "ok" : "bad"); 1526 v4l2_info(sd, "Frequency: %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz"); 1527 return 0; 1528 } 1529 1530 /* status for the saa7115 */ 1531 reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC); 1532 reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC); 1533 1534 signalOk = (reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80; 1535 vcr = !(reg1f & 0x10); 1536 1537 if (state->input >= 6) 1538 v4l2_info(sd, "Input: S-Video %d\n", state->input - 6); 1539 else 1540 v4l2_info(sd, "Input: Composite %d\n", state->input); 1541 v4l2_info(sd, "Video signal: %s\n", signalOk ? (vcr ? "VCR" : "broadcast/DVD") : "bad"); 1542 v4l2_info(sd, "Frequency: %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz"); 1543 1544 switch (reg1e & 0x03) { 1545 case 1: 1546 v4l2_info(sd, "Detected format: NTSC\n"); 1547 break; 1548 case 2: 1549 v4l2_info(sd, "Detected format: PAL\n"); 1550 break; 1551 case 3: 1552 v4l2_info(sd, "Detected format: SECAM\n"); 1553 break; 1554 default: 1555 v4l2_info(sd, "Detected format: BW/No color\n"); 1556 break; 1557 } 1558 v4l2_info(sd, "Width, Height: %d, %d\n", state->width, state->height); 1559 v4l2_ctrl_handler_log_status(&state->hdl, sd->name); 1560 return 0; 1561} 1562 1563/* ----------------------------------------------------------------------- */ 1564 1565static const struct v4l2_ctrl_ops saa711x_ctrl_ops = { 1566 .s_ctrl = saa711x_s_ctrl, 1567 .g_volatile_ctrl = saa711x_g_volatile_ctrl, 1568}; 1569 1570static const struct v4l2_subdev_core_ops saa711x_core_ops = { 1571 .log_status = saa711x_log_status, 1572 .reset = saa711x_reset, 1573 .s_gpio = saa711x_s_gpio, 1574#ifdef CONFIG_VIDEO_ADV_DEBUG 1575 .g_register = saa711x_g_register, 1576 .s_register = saa711x_s_register, 1577#endif 1578}; 1579 1580static const struct v4l2_subdev_tuner_ops saa711x_tuner_ops = { 1581 .s_radio = saa711x_s_radio, 1582 .g_tuner = saa711x_g_tuner, 1583}; 1584 1585static const struct v4l2_subdev_audio_ops saa711x_audio_ops = { 1586 .s_clock_freq = saa711x_s_clock_freq, 1587}; 1588 1589static const struct v4l2_subdev_video_ops saa711x_video_ops = { 1590 .s_std = saa711x_s_std, 1591 .s_routing = saa711x_s_routing, 1592 .s_crystal_freq = saa711x_s_crystal_freq, 1593 .s_stream = saa711x_s_stream, 1594 .querystd = saa711x_querystd, 1595 .g_input_status = saa711x_g_input_status, 1596}; 1597 1598static const struct v4l2_subdev_vbi_ops saa711x_vbi_ops = { 1599 .g_vbi_data = saa711x_g_vbi_data, 1600 .decode_vbi_line = saa711x_decode_vbi_line, 1601 .g_sliced_fmt = saa711x_g_sliced_fmt, 1602 .s_sliced_fmt = saa711x_s_sliced_fmt, 1603 .s_raw_fmt = saa711x_s_raw_fmt, 1604}; 1605 1606static const struct v4l2_subdev_pad_ops saa711x_pad_ops = { 1607 .set_fmt = saa711x_set_fmt, 1608}; 1609 1610static const struct v4l2_subdev_ops saa711x_ops = { 1611 .core = &saa711x_core_ops, 1612 .tuner = &saa711x_tuner_ops, 1613 .audio = &saa711x_audio_ops, 1614 .video = &saa711x_video_ops, 1615 .vbi = &saa711x_vbi_ops, 1616 .pad = &saa711x_pad_ops, 1617}; 1618 1619#define CHIP_VER_SIZE 16 1620 1621/* ----------------------------------------------------------------------- */ 1622 1623static void saa711x_write_platform_data(struct saa711x_state *state, 1624 struct saa7115_platform_data *data) 1625{ 1626 struct v4l2_subdev *sd = &state->sd; 1627 u8 work; 1628 1629 if (state->ident != GM7113C && 1630 state->ident != SAA7113) 1631 return; 1632 1633 if (data->saa7113_r08_htc) { 1634 work = saa711x_read(sd, R_08_SYNC_CNTL); 1635 work &= ~SAA7113_R_08_HTC_MASK; 1636 work |= ((*data->saa7113_r08_htc) << SAA7113_R_08_HTC_OFFSET); 1637 saa711x_write(sd, R_08_SYNC_CNTL, work); 1638 } 1639 1640 if (data->saa7113_r10_vrln) { 1641 work = saa711x_read(sd, R_10_CHROMA_CNTL_2); 1642 work &= ~SAA7113_R_10_VRLN_MASK; 1643 if (*data->saa7113_r10_vrln) 1644 work |= (1 << SAA7113_R_10_VRLN_OFFSET); 1645 saa711x_write(sd, R_10_CHROMA_CNTL_2, work); 1646 } 1647 1648 if (data->saa7113_r10_ofts) { 1649 work = saa711x_read(sd, R_10_CHROMA_CNTL_2); 1650 work &= ~SAA7113_R_10_OFTS_MASK; 1651 work |= (*data->saa7113_r10_ofts << SAA7113_R_10_OFTS_OFFSET); 1652 saa711x_write(sd, R_10_CHROMA_CNTL_2, work); 1653 } 1654 1655 if (data->saa7113_r12_rts0) { 1656 work = saa711x_read(sd, R_12_RT_SIGNAL_CNTL); 1657 work &= ~SAA7113_R_12_RTS0_MASK; 1658 work |= (*data->saa7113_r12_rts0 << SAA7113_R_12_RTS0_OFFSET); 1659 1660 /* According to the datasheet, 1661 * SAA7113_RTS_DOT_IN should only be used on RTS1 */ 1662 WARN_ON(*data->saa7113_r12_rts0 == SAA7113_RTS_DOT_IN); 1663 saa711x_write(sd, R_12_RT_SIGNAL_CNTL, work); 1664 } 1665 1666 if (data->saa7113_r12_rts1) { 1667 work = saa711x_read(sd, R_12_RT_SIGNAL_CNTL); 1668 work &= ~SAA7113_R_12_RTS1_MASK; 1669 work |= (*data->saa7113_r12_rts1 << SAA7113_R_12_RTS1_OFFSET); 1670 saa711x_write(sd, R_12_RT_SIGNAL_CNTL, work); 1671 } 1672 1673 if (data->saa7113_r13_adlsb) { 1674 work = saa711x_read(sd, R_13_RT_X_PORT_OUT_CNTL); 1675 work &= ~SAA7113_R_13_ADLSB_MASK; 1676 if (*data->saa7113_r13_adlsb) 1677 work |= (1 << SAA7113_R_13_ADLSB_OFFSET); 1678 saa711x_write(sd, R_13_RT_X_PORT_OUT_CNTL, work); 1679 } 1680} 1681 1682/** 1683 * saa711x_detect_chip - Detects the saa711x (or clone) variant 1684 * @client: I2C client structure. 1685 * @id: I2C device ID structure. 1686 * @name: Name of the device to be filled. 1687 * 1688 * Detects the Philips/NXP saa711x chip, or some clone of it. 1689 * if 'id' is NULL or id->driver_data is equal to 1, it auto-probes 1690 * the analog demod. 1691 * If the tuner is not found, it returns -ENODEV. 1692 * If auto-detection is disabled and the tuner doesn't match what it was 1693 * required, it returns -EINVAL and fills 'name'. 1694 * If the chip is found, it returns the chip ID and fills 'name'. 1695 */ 1696static int saa711x_detect_chip(struct i2c_client *client, 1697 const struct i2c_device_id *id, 1698 char *name) 1699{ 1700 char chip_ver[CHIP_VER_SIZE]; 1701 char chip_id; 1702 int i; 1703 int autodetect; 1704 1705 autodetect = !id || id->driver_data == 1; 1706 1707 /* Read the chip version register */ 1708 for (i = 0; i < CHIP_VER_SIZE; i++) { 1709 i2c_smbus_write_byte_data(client, 0, i); 1710 chip_ver[i] = i2c_smbus_read_byte_data(client, 0); 1711 name[i] = (chip_ver[i] & 0x0f) + '0'; 1712 if (name[i] > '9') 1713 name[i] += 'a' - '9' - 1; 1714 } 1715 name[i] = '\0'; 1716 1717 /* Check if it is a Philips/NXP chip */ 1718 if (!memcmp(name + 1, "f711", 4)) { 1719 chip_id = name[5]; 1720 snprintf(name, CHIP_VER_SIZE, "saa711%c", chip_id); 1721 1722 if (!autodetect && strcmp(name, id->name)) 1723 return -EINVAL; 1724 1725 switch (chip_id) { 1726 case '1': 1727 if (chip_ver[0] & 0xf0) { 1728 snprintf(name, CHIP_VER_SIZE, "saa711%ca", chip_id); 1729 v4l_info(client, "saa7111a variant found\n"); 1730 return SAA7111A; 1731 } 1732 return SAA7111; 1733 case '3': 1734 return SAA7113; 1735 case '4': 1736 return SAA7114; 1737 case '5': 1738 return SAA7115; 1739 case '8': 1740 return SAA7118; 1741 default: 1742 v4l2_info(client, 1743 "WARNING: Philips/NXP chip unknown - Falling back to saa7111\n"); 1744 return SAA7111; 1745 } 1746 } 1747 1748 /* Check if it is a gm7113c */ 1749 if (!memcmp(name, "0000", 4)) { 1750 chip_id = 0; 1751 for (i = 0; i < 4; i++) { 1752 chip_id = chip_id << 1; 1753 chip_id |= (chip_ver[i] & 0x80) ? 1 : 0; 1754 } 1755 1756 /* 1757 * Note: From the datasheet, only versions 1 and 2 1758 * exists. However, tests on a device labeled as: 1759 * "GM7113C 1145" returned "10" on all 16 chip 1760 * version (reg 0x00) reads. So, we need to also 1761 * accept at least version 0. For now, let's just 1762 * assume that a device that returns "0000" for 1763 * the lower nibble is a gm7113c. 1764 */ 1765 1766 strscpy(name, "gm7113c", CHIP_VER_SIZE); 1767 1768 if (!autodetect && strcmp(name, id->name)) 1769 return -EINVAL; 1770 1771 v4l_dbg(1, debug, client, 1772 "It seems to be a %s chip (%*ph) @ 0x%x.\n", 1773 name, 16, chip_ver, client->addr << 1); 1774 1775 return GM7113C; 1776 } 1777 1778 /* Check if it is a CJC7113 */ 1779 if (!memcmp(name, "1111111111111111", CHIP_VER_SIZE)) { 1780 strscpy(name, "cjc7113", CHIP_VER_SIZE); 1781 1782 if (!autodetect && strcmp(name, id->name)) 1783 return -EINVAL; 1784 1785 v4l_dbg(1, debug, client, 1786 "It seems to be a %s chip (%*ph) @ 0x%x.\n", 1787 name, 16, chip_ver, client->addr << 1); 1788 1789 /* CJC7113 seems to be SAA7113-compatible */ 1790 return SAA7113; 1791 } 1792 1793 /* Chip was not discovered. Return its ID and don't bind */ 1794 v4l_dbg(1, debug, client, "chip %*ph @ 0x%x is unknown.\n", 1795 16, chip_ver, client->addr << 1); 1796 return -ENODEV; 1797} 1798 1799static int saa711x_probe(struct i2c_client *client) 1800{ 1801 const struct i2c_device_id *id = i2c_client_get_device_id(client); 1802 struct saa711x_state *state; 1803 struct v4l2_subdev *sd; 1804 struct v4l2_ctrl_handler *hdl; 1805 struct saa7115_platform_data *pdata; 1806 int ident; 1807 char name[CHIP_VER_SIZE + 1]; 1808#if defined(CONFIG_MEDIA_CONTROLLER) 1809 int ret; 1810#endif 1811 1812 /* Check if the adapter supports the needed features */ 1813 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1814 return -EIO; 1815 1816 ident = saa711x_detect_chip(client, id, name); 1817 if (ident == -EINVAL) { 1818 /* Chip exists, but doesn't match */ 1819 v4l_warn(client, "found %s while %s was expected\n", 1820 name, id->name); 1821 return -ENODEV; 1822 } 1823 if (ident < 0) 1824 return ident; 1825 1826 strscpy(client->name, name, sizeof(client->name)); 1827 1828 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 1829 if (state == NULL) 1830 return -ENOMEM; 1831 sd = &state->sd; 1832 v4l2_i2c_subdev_init(sd, client, &saa711x_ops); 1833 1834#if defined(CONFIG_MEDIA_CONTROLLER) 1835 state->pads[SAA711X_PAD_IF_INPUT].flags = MEDIA_PAD_FL_SINK; 1836 state->pads[SAA711X_PAD_IF_INPUT].sig_type = PAD_SIGNAL_ANALOG; 1837 state->pads[SAA711X_PAD_VID_OUT].flags = MEDIA_PAD_FL_SOURCE; 1838 state->pads[SAA711X_PAD_VID_OUT].sig_type = PAD_SIGNAL_DV; 1839 1840 sd->entity.function = MEDIA_ENT_F_ATV_DECODER; 1841 1842 ret = media_entity_pads_init(&sd->entity, SAA711X_NUM_PADS, 1843 state->pads); 1844 if (ret < 0) 1845 return ret; 1846#endif 1847 1848 v4l_info(client, "%s found @ 0x%x (%s)\n", name, 1849 client->addr << 1, client->adapter->name); 1850 hdl = &state->hdl; 1851 v4l2_ctrl_handler_init(hdl, 6); 1852 /* add in ascending ID order */ 1853 v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops, 1854 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128); 1855 v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops, 1856 V4L2_CID_CONTRAST, 0, 127, 1, 64); 1857 v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops, 1858 V4L2_CID_SATURATION, 0, 127, 1, 64); 1859 v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops, 1860 V4L2_CID_HUE, -128, 127, 1, 0); 1861 state->agc = v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops, 1862 V4L2_CID_CHROMA_AGC, 0, 1, 1, 1); 1863 state->gain = v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops, 1864 V4L2_CID_CHROMA_GAIN, 0, 127, 1, 40); 1865 sd->ctrl_handler = hdl; 1866 if (hdl->error) { 1867 int err = hdl->error; 1868 1869 v4l2_ctrl_handler_free(hdl); 1870 return err; 1871 } 1872 v4l2_ctrl_auto_cluster(2, &state->agc, 0, true); 1873 1874 state->input = -1; 1875 state->output = SAA7115_IPORT_ON; 1876 state->enable = 1; 1877 state->radio = 0; 1878 state->ident = ident; 1879 1880 state->audclk_freq = 48000; 1881 1882 v4l2_dbg(1, debug, sd, "writing init values\n"); 1883 1884 /* init to 60hz/48khz */ 1885 state->crystal_freq = SAA7115_FREQ_24_576_MHZ; 1886 pdata = client->dev.platform_data; 1887 switch (state->ident) { 1888 case SAA7111: 1889 case SAA7111A: 1890 saa711x_writeregs(sd, saa7111_init); 1891 break; 1892 case GM7113C: 1893 saa711x_writeregs(sd, gm7113c_init); 1894 break; 1895 case SAA7113: 1896 if (pdata && pdata->saa7113_force_gm7113c_init) 1897 saa711x_writeregs(sd, gm7113c_init); 1898 else 1899 saa711x_writeregs(sd, saa7113_init); 1900 break; 1901 default: 1902 state->crystal_freq = SAA7115_FREQ_32_11_MHZ; 1903 saa711x_writeregs(sd, saa7115_init_auto_input); 1904 } 1905 if (state->ident > SAA7111A && state->ident != GM7113C) 1906 saa711x_writeregs(sd, saa7115_init_misc); 1907 1908 if (pdata) 1909 saa711x_write_platform_data(state, pdata); 1910 1911 saa711x_set_v4lstd(sd, V4L2_STD_NTSC); 1912 v4l2_ctrl_handler_setup(hdl); 1913 1914 v4l2_dbg(1, debug, sd, "status: (1E) 0x%02x, (1F) 0x%02x\n", 1915 saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC), 1916 saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC)); 1917 return 0; 1918} 1919 1920/* ----------------------------------------------------------------------- */ 1921 1922static void saa711x_remove(struct i2c_client *client) 1923{ 1924 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1925 1926 v4l2_device_unregister_subdev(sd); 1927 v4l2_ctrl_handler_free(sd->ctrl_handler); 1928} 1929 1930static const struct i2c_device_id saa711x_id[] = { 1931 { "saa7115_auto", 1 }, /* autodetect */ 1932 { "saa7111", 0 }, 1933 { "saa7113", 0 }, 1934 { "saa7114", 0 }, 1935 { "saa7115", 0 }, 1936 { "saa7118", 0 }, 1937 { "gm7113c", 0 }, 1938 { } 1939}; 1940MODULE_DEVICE_TABLE(i2c, saa711x_id); 1941 1942static struct i2c_driver saa711x_driver = { 1943 .driver = { 1944 .name = "saa7115", 1945 }, 1946 .probe = saa711x_probe, 1947 .remove = saa711x_remove, 1948 .id_table = saa711x_id, 1949}; 1950 1951module_i2c_driver(saa711x_driver);
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