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ov9734.c
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linux-6.19.14/drivers/media/i2c/ov9734.c
1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2020 Intel Corporation. 3 4#include <linux/acpi.h> 5#include <linux/clk.h> 6#include <linux/delay.h> 7#include <linux/i2c.h> 8#include <linux/module.h> 9#include <linux/pm_runtime.h> 10#include <linux/unaligned.h> 11 12#include <media/v4l2-ctrls.h> 13#include <media/v4l2-device.h> 14#include <media/v4l2-fwnode.h> 15 16#define OV9734_LINK_FREQ_180MHZ 180000000ULL 17#define OV9734_SCLK 36000000LL 18#define OV9734_MCLK 19200000 19/* ov9734 only support 1-lane mipi output */ 20#define OV9734_DATA_LANES 1 21#define OV9734_RGB_DEPTH 10 22 23#define OV9734_REG_CHIP_ID 0x300a 24#define OV9734_CHIP_ID 0x9734 25 26#define OV9734_REG_MODE_SELECT 0x0100 27#define OV9734_MODE_STANDBY 0x00 28#define OV9734_MODE_STREAMING 0x01 29 30/* vertical-timings from sensor */ 31#define OV9734_REG_VTS 0x380e 32#define OV9734_VTS_30FPS 0x0322 33#define OV9734_VTS_30FPS_MIN 0x0322 34#define OV9734_VTS_MAX 0x7fff 35 36/* horizontal-timings from sensor */ 37#define OV9734_REG_HTS 0x380c 38 39/* Exposure controls from sensor */ 40#define OV9734_REG_EXPOSURE 0x3500 41#define OV9734_EXPOSURE_MIN 4 42#define OV9734_EXPOSURE_MAX_MARGIN 4 43#define OV9734_EXPOSURE_STEP 1 44 45/* Analog gain controls from sensor */ 46#define OV9734_REG_ANALOG_GAIN 0x350a 47#define OV9734_ANAL_GAIN_MIN 16 48#define OV9734_ANAL_GAIN_MAX 248 49#define OV9734_ANAL_GAIN_STEP 1 50 51/* Digital gain controls from sensor */ 52#define OV9734_REG_MWB_R_GAIN 0x5180 53#define OV9734_REG_MWB_G_GAIN 0x5182 54#define OV9734_REG_MWB_B_GAIN 0x5184 55#define OV9734_DGTL_GAIN_MIN 256 56#define OV9734_DGTL_GAIN_MAX 1023 57#define OV9734_DGTL_GAIN_STEP 1 58#define OV9734_DGTL_GAIN_DEFAULT 256 59 60/* Test Pattern Control */ 61#define OV9734_REG_TEST_PATTERN 0x5080 62#define OV9734_TEST_PATTERN_ENABLE BIT(7) 63#define OV9734_TEST_PATTERN_BAR_SHIFT 2 64 65/* Group Access */ 66#define OV9734_REG_GROUP_ACCESS 0x3208 67#define OV9734_GROUP_HOLD_START 0x0 68#define OV9734_GROUP_HOLD_END 0x10 69#define OV9734_GROUP_HOLD_LAUNCH 0xa0 70 71enum { 72 OV9734_LINK_FREQ_180MHZ_INDEX, 73}; 74 75struct ov9734_reg { 76 u16 address; 77 u8 val; 78}; 79 80struct ov9734_reg_list { 81 u32 num_of_regs; 82 const struct ov9734_reg *regs; 83}; 84 85struct ov9734_link_freq_config { 86 const struct ov9734_reg_list reg_list; 87}; 88 89struct ov9734_mode { 90 /* Frame width in pixels */ 91 u32 width; 92 93 /* Frame height in pixels */ 94 u32 height; 95 96 /* Horizontal timining size */ 97 u32 hts; 98 99 /* Default vertical timining size */ 100 u32 vts_def; 101 102 /* Min vertical timining size */ 103 u32 vts_min; 104 105 /* Link frequency needed for this resolution */ 106 u32 link_freq_index; 107 108 /* Sensor register settings for this resolution */ 109 const struct ov9734_reg_list reg_list; 110}; 111 112static const struct ov9734_reg mipi_data_rate_360mbps[] = { 113 {0x3030, 0x19}, 114 {0x3080, 0x02}, 115 {0x3081, 0x4b}, 116 {0x3082, 0x04}, 117 {0x3083, 0x00}, 118 {0x3084, 0x02}, 119 {0x3085, 0x01}, 120 {0x3086, 0x01}, 121 {0x3089, 0x01}, 122 {0x308a, 0x00}, 123 {0x301e, 0x15}, 124 {0x3103, 0x01}, 125}; 126 127static const struct ov9734_reg mode_1296x734_regs[] = { 128 {0x3001, 0x00}, 129 {0x3002, 0x00}, 130 {0x3007, 0x00}, 131 {0x3010, 0x00}, 132 {0x3011, 0x08}, 133 {0x3014, 0x22}, 134 {0x3600, 0x55}, 135 {0x3601, 0x02}, 136 {0x3605, 0x22}, 137 {0x3611, 0xe7}, 138 {0x3654, 0x10}, 139 {0x3655, 0x77}, 140 {0x3656, 0x77}, 141 {0x3657, 0x07}, 142 {0x3658, 0x22}, 143 {0x3659, 0x22}, 144 {0x365a, 0x02}, 145 {0x3784, 0x05}, 146 {0x3785, 0x55}, 147 {0x37c0, 0x07}, 148 {0x3800, 0x00}, 149 {0x3801, 0x04}, 150 {0x3802, 0x00}, 151 {0x3803, 0x04}, 152 {0x3804, 0x05}, 153 {0x3805, 0x0b}, 154 {0x3806, 0x02}, 155 {0x3807, 0xdb}, 156 {0x3808, 0x05}, 157 {0x3809, 0x00}, 158 {0x380a, 0x02}, 159 {0x380b, 0xd0}, 160 {0x380c, 0x05}, 161 {0x380d, 0xc6}, 162 {0x380e, 0x03}, 163 {0x380f, 0x22}, 164 {0x3810, 0x00}, 165 {0x3811, 0x04}, 166 {0x3812, 0x00}, 167 {0x3813, 0x04}, 168 {0x3816, 0x00}, 169 {0x3817, 0x00}, 170 {0x3818, 0x00}, 171 {0x3819, 0x04}, 172 {0x3820, 0x18}, 173 {0x3821, 0x00}, 174 {0x382c, 0x06}, 175 {0x3500, 0x00}, 176 {0x3501, 0x31}, 177 {0x3502, 0x00}, 178 {0x3503, 0x03}, 179 {0x3504, 0x00}, 180 {0x3505, 0x00}, 181 {0x3509, 0x10}, 182 {0x350a, 0x00}, 183 {0x350b, 0x40}, 184 {0x3d00, 0x00}, 185 {0x3d01, 0x00}, 186 {0x3d02, 0x00}, 187 {0x3d03, 0x00}, 188 {0x3d04, 0x00}, 189 {0x3d05, 0x00}, 190 {0x3d06, 0x00}, 191 {0x3d07, 0x00}, 192 {0x3d08, 0x00}, 193 {0x3d09, 0x00}, 194 {0x3d0a, 0x00}, 195 {0x3d0b, 0x00}, 196 {0x3d0c, 0x00}, 197 {0x3d0d, 0x00}, 198 {0x3d0e, 0x00}, 199 {0x3d0f, 0x00}, 200 {0x3d80, 0x00}, 201 {0x3d81, 0x00}, 202 {0x3d82, 0x38}, 203 {0x3d83, 0xa4}, 204 {0x3d84, 0x00}, 205 {0x3d85, 0x00}, 206 {0x3d86, 0x1f}, 207 {0x3d87, 0x03}, 208 {0x3d8b, 0x00}, 209 {0x3d8f, 0x00}, 210 {0x4001, 0xe0}, 211 {0x4009, 0x0b}, 212 {0x4300, 0x03}, 213 {0x4301, 0xff}, 214 {0x4304, 0x00}, 215 {0x4305, 0x00}, 216 {0x4309, 0x00}, 217 {0x4600, 0x00}, 218 {0x4601, 0x80}, 219 {0x4800, 0x00}, 220 {0x4805, 0x00}, 221 {0x4821, 0x50}, 222 {0x4823, 0x50}, 223 {0x4837, 0x2d}, 224 {0x4a00, 0x00}, 225 {0x4f00, 0x80}, 226 {0x4f01, 0x10}, 227 {0x4f02, 0x00}, 228 {0x4f03, 0x00}, 229 {0x4f04, 0x00}, 230 {0x4f05, 0x00}, 231 {0x4f06, 0x00}, 232 {0x4f07, 0x00}, 233 {0x4f08, 0x00}, 234 {0x4f09, 0x00}, 235 {0x5000, 0x2f}, 236 {0x500c, 0x00}, 237 {0x500d, 0x00}, 238 {0x500e, 0x00}, 239 {0x500f, 0x00}, 240 {0x5010, 0x00}, 241 {0x5011, 0x00}, 242 {0x5012, 0x00}, 243 {0x5013, 0x00}, 244 {0x5014, 0x00}, 245 {0x5015, 0x00}, 246 {0x5016, 0x00}, 247 {0x5017, 0x00}, 248 {0x5080, 0x00}, 249 {0x5180, 0x01}, 250 {0x5181, 0x00}, 251 {0x5182, 0x01}, 252 {0x5183, 0x00}, 253 {0x5184, 0x01}, 254 {0x5185, 0x00}, 255 {0x5708, 0x06}, 256 {0x380f, 0x2a}, 257 {0x5780, 0x3e}, 258 {0x5781, 0x0f}, 259 {0x5782, 0x44}, 260 {0x5783, 0x02}, 261 {0x5784, 0x01}, 262 {0x5785, 0x01}, 263 {0x5786, 0x00}, 264 {0x5787, 0x04}, 265 {0x5788, 0x02}, 266 {0x5789, 0x0f}, 267 {0x578a, 0xfd}, 268 {0x578b, 0xf5}, 269 {0x578c, 0xf5}, 270 {0x578d, 0x03}, 271 {0x578e, 0x08}, 272 {0x578f, 0x0c}, 273 {0x5790, 0x08}, 274 {0x5791, 0x04}, 275 {0x5792, 0x00}, 276 {0x5793, 0x52}, 277 {0x5794, 0xa3}, 278 {0x5000, 0x3f}, 279 {0x3801, 0x00}, 280 {0x3803, 0x00}, 281 {0x3805, 0x0f}, 282 {0x3807, 0xdf}, 283 {0x3809, 0x10}, 284 {0x380b, 0xde}, 285 {0x3811, 0x00}, 286 {0x3813, 0x01}, 287}; 288 289static const char * const ov9734_test_pattern_menu[] = { 290 "Disabled", 291 "Standard Color Bar", 292 "Top-Bottom Darker Color Bar", 293 "Right-Left Darker Color Bar", 294 "Bottom-Top Darker Color Bar", 295}; 296 297static const s64 link_freq_menu_items[] = { 298 OV9734_LINK_FREQ_180MHZ, 299}; 300 301static const struct ov9734_link_freq_config link_freq_configs[] = { 302 [OV9734_LINK_FREQ_180MHZ_INDEX] = { 303 .reg_list = { 304 .num_of_regs = ARRAY_SIZE(mipi_data_rate_360mbps), 305 .regs = mipi_data_rate_360mbps, 306 } 307 }, 308}; 309 310static const struct ov9734_mode supported_modes[] = { 311 { 312 .width = 1296, 313 .height = 734, 314 .hts = 0x5c6, 315 .vts_def = OV9734_VTS_30FPS, 316 .vts_min = OV9734_VTS_30FPS_MIN, 317 .reg_list = { 318 .num_of_regs = ARRAY_SIZE(mode_1296x734_regs), 319 .regs = mode_1296x734_regs, 320 }, 321 .link_freq_index = OV9734_LINK_FREQ_180MHZ_INDEX, 322 }, 323}; 324 325struct ov9734 { 326 struct device *dev; 327 struct clk *clk; 328 329 struct v4l2_subdev sd; 330 struct media_pad pad; 331 struct v4l2_ctrl_handler ctrl_handler; 332 333 /* V4L2 Controls */ 334 struct v4l2_ctrl *link_freq; 335 struct v4l2_ctrl *pixel_rate; 336 struct v4l2_ctrl *vblank; 337 struct v4l2_ctrl *hblank; 338 struct v4l2_ctrl *exposure; 339 340 /* Current mode */ 341 const struct ov9734_mode *cur_mode; 342 343 /* To serialize asynchronous callbacks */ 344 struct mutex mutex; 345}; 346 347static inline struct ov9734 *to_ov9734(struct v4l2_subdev *subdev) 348{ 349 return container_of(subdev, struct ov9734, sd); 350} 351 352static u64 to_pixel_rate(u32 f_index) 353{ 354 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV9734_DATA_LANES; 355 356 do_div(pixel_rate, OV9734_RGB_DEPTH); 357 358 return pixel_rate; 359} 360 361static u64 to_pixels_per_line(u32 hts, u32 f_index) 362{ 363 u64 ppl = hts * to_pixel_rate(f_index); 364 365 do_div(ppl, OV9734_SCLK); 366 367 return ppl; 368} 369 370static int ov9734_read_reg(struct ov9734 *ov9734, u16 reg, u16 len, u32 *val) 371{ 372 struct i2c_client *client = v4l2_get_subdevdata(&ov9734->sd); 373 struct i2c_msg msgs[2]; 374 u8 addr_buf[2]; 375 u8 data_buf[4] = {0}; 376 int ret; 377 378 if (len > sizeof(data_buf)) 379 return -EINVAL; 380 381 put_unaligned_be16(reg, addr_buf); 382 msgs[0].addr = client->addr; 383 msgs[0].flags = 0; 384 msgs[0].len = sizeof(addr_buf); 385 msgs[0].buf = addr_buf; 386 msgs[1].addr = client->addr; 387 msgs[1].flags = I2C_M_RD; 388 msgs[1].len = len; 389 msgs[1].buf = &data_buf[sizeof(data_buf) - len]; 390 391 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 392 if (ret != ARRAY_SIZE(msgs)) 393 return ret < 0 ? ret : -EIO; 394 395 *val = get_unaligned_be32(data_buf); 396 397 return 0; 398} 399 400static int ov9734_write_reg(struct ov9734 *ov9734, u16 reg, u16 len, u32 val) 401{ 402 struct i2c_client *client = v4l2_get_subdevdata(&ov9734->sd); 403 u8 buf[6]; 404 int ret = 0; 405 406 if (len > 4) 407 return -EINVAL; 408 409 put_unaligned_be16(reg, buf); 410 put_unaligned_be32(val << 8 * (4 - len), buf + 2); 411 412 ret = i2c_master_send(client, buf, len + 2); 413 if (ret != len + 2) 414 return ret < 0 ? ret : -EIO; 415 416 return 0; 417} 418 419static int ov9734_write_reg_list(struct ov9734 *ov9734, 420 const struct ov9734_reg_list *r_list) 421{ 422 unsigned int i; 423 int ret; 424 425 for (i = 0; i < r_list->num_of_regs; i++) { 426 ret = ov9734_write_reg(ov9734, r_list->regs[i].address, 1, 427 r_list->regs[i].val); 428 if (ret) { 429 dev_err_ratelimited(ov9734->dev, 430 "write reg 0x%4.4x return err = %d", 431 r_list->regs[i].address, ret); 432 return ret; 433 } 434 } 435 436 return 0; 437} 438 439static int ov9734_update_digital_gain(struct ov9734 *ov9734, u32 d_gain) 440{ 441 int ret; 442 443 ret = ov9734_write_reg(ov9734, OV9734_REG_GROUP_ACCESS, 1, 444 OV9734_GROUP_HOLD_START); 445 if (ret) 446 return ret; 447 448 ret = ov9734_write_reg(ov9734, OV9734_REG_MWB_R_GAIN, 2, d_gain); 449 if (ret) 450 return ret; 451 452 ret = ov9734_write_reg(ov9734, OV9734_REG_MWB_G_GAIN, 2, d_gain); 453 if (ret) 454 return ret; 455 456 ret = ov9734_write_reg(ov9734, OV9734_REG_MWB_B_GAIN, 2, d_gain); 457 if (ret) 458 return ret; 459 460 ret = ov9734_write_reg(ov9734, OV9734_REG_GROUP_ACCESS, 1, 461 OV9734_GROUP_HOLD_END); 462 if (ret) 463 return ret; 464 465 ret = ov9734_write_reg(ov9734, OV9734_REG_GROUP_ACCESS, 1, 466 OV9734_GROUP_HOLD_LAUNCH); 467 return ret; 468} 469 470static int ov9734_test_pattern(struct ov9734 *ov9734, u32 pattern) 471{ 472 if (pattern) 473 pattern = (pattern - 1) << OV9734_TEST_PATTERN_BAR_SHIFT | 474 OV9734_TEST_PATTERN_ENABLE; 475 476 return ov9734_write_reg(ov9734, OV9734_REG_TEST_PATTERN, 1, pattern); 477} 478 479static int ov9734_set_ctrl(struct v4l2_ctrl *ctrl) 480{ 481 struct ov9734 *ov9734 = container_of(ctrl->handler, 482 struct ov9734, ctrl_handler); 483 s64 exposure_max; 484 int ret = 0; 485 486 /* Propagate change of current control to all related controls */ 487 if (ctrl->id == V4L2_CID_VBLANK) { 488 /* Update max exposure while meeting expected vblanking */ 489 exposure_max = ov9734->cur_mode->height + ctrl->val - 490 OV9734_EXPOSURE_MAX_MARGIN; 491 __v4l2_ctrl_modify_range(ov9734->exposure, 492 ov9734->exposure->minimum, 493 exposure_max, ov9734->exposure->step, 494 exposure_max); 495 } 496 497 /* V4L2 controls values will be applied only when power is already up */ 498 if (!pm_runtime_get_if_in_use(ov9734->dev)) 499 return 0; 500 501 switch (ctrl->id) { 502 case V4L2_CID_ANALOGUE_GAIN: 503 ret = ov9734_write_reg(ov9734, OV9734_REG_ANALOG_GAIN, 504 2, ctrl->val); 505 break; 506 507 case V4L2_CID_DIGITAL_GAIN: 508 ret = ov9734_update_digital_gain(ov9734, ctrl->val); 509 break; 510 511 case V4L2_CID_EXPOSURE: 512 /* 4 least significant bits of expsoure are fractional part */ 513 ret = ov9734_write_reg(ov9734, OV9734_REG_EXPOSURE, 514 3, ctrl->val << 4); 515 break; 516 517 case V4L2_CID_VBLANK: 518 ret = ov9734_write_reg(ov9734, OV9734_REG_VTS, 2, 519 ov9734->cur_mode->height + ctrl->val); 520 break; 521 522 case V4L2_CID_TEST_PATTERN: 523 ret = ov9734_test_pattern(ov9734, ctrl->val); 524 break; 525 526 default: 527 ret = -EINVAL; 528 break; 529 } 530 531 pm_runtime_put(ov9734->dev); 532 533 return ret; 534} 535 536static const struct v4l2_ctrl_ops ov9734_ctrl_ops = { 537 .s_ctrl = ov9734_set_ctrl, 538}; 539 540static int ov9734_init_controls(struct ov9734 *ov9734) 541{ 542 struct v4l2_ctrl_handler *ctrl_hdlr; 543 const struct ov9734_mode *cur_mode; 544 s64 exposure_max, h_blank, pixel_rate; 545 u32 vblank_min, vblank_max, vblank_default; 546 int ret, size; 547 548 ctrl_hdlr = &ov9734->ctrl_handler; 549 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8); 550 if (ret) 551 return ret; 552 553 ctrl_hdlr->lock = &ov9734->mutex; 554 cur_mode = ov9734->cur_mode; 555 size = ARRAY_SIZE(link_freq_menu_items); 556 ov9734->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov9734_ctrl_ops, 557 V4L2_CID_LINK_FREQ, 558 size - 1, 0, 559 link_freq_menu_items); 560 if (ov9734->link_freq) 561 ov9734->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 562 563 pixel_rate = to_pixel_rate(OV9734_LINK_FREQ_180MHZ_INDEX); 564 ov9734->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov9734_ctrl_ops, 565 V4L2_CID_PIXEL_RATE, 0, 566 pixel_rate, 1, pixel_rate); 567 vblank_min = cur_mode->vts_min - cur_mode->height; 568 vblank_max = OV9734_VTS_MAX - cur_mode->height; 569 vblank_default = cur_mode->vts_def - cur_mode->height; 570 ov9734->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov9734_ctrl_ops, 571 V4L2_CID_VBLANK, vblank_min, 572 vblank_max, 1, vblank_default); 573 h_blank = to_pixels_per_line(cur_mode->hts, cur_mode->link_freq_index); 574 h_blank -= cur_mode->width; 575 ov9734->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov9734_ctrl_ops, 576 V4L2_CID_HBLANK, h_blank, h_blank, 1, 577 h_blank); 578 if (ov9734->hblank) 579 ov9734->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 580 581 v4l2_ctrl_new_std(ctrl_hdlr, &ov9734_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 582 OV9734_ANAL_GAIN_MIN, OV9734_ANAL_GAIN_MAX, 583 OV9734_ANAL_GAIN_STEP, OV9734_ANAL_GAIN_MIN); 584 v4l2_ctrl_new_std(ctrl_hdlr, &ov9734_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 585 OV9734_DGTL_GAIN_MIN, OV9734_DGTL_GAIN_MAX, 586 OV9734_DGTL_GAIN_STEP, OV9734_DGTL_GAIN_DEFAULT); 587 exposure_max = ov9734->cur_mode->vts_def - OV9734_EXPOSURE_MAX_MARGIN; 588 ov9734->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov9734_ctrl_ops, 589 V4L2_CID_EXPOSURE, 590 OV9734_EXPOSURE_MIN, exposure_max, 591 OV9734_EXPOSURE_STEP, 592 exposure_max); 593 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov9734_ctrl_ops, 594 V4L2_CID_TEST_PATTERN, 595 ARRAY_SIZE(ov9734_test_pattern_menu) - 1, 596 0, 0, ov9734_test_pattern_menu); 597 if (ctrl_hdlr->error) 598 return ctrl_hdlr->error; 599 600 ov9734->sd.ctrl_handler = ctrl_hdlr; 601 602 return 0; 603} 604 605static void ov9734_update_pad_format(const struct ov9734_mode *mode, 606 struct v4l2_mbus_framefmt *fmt) 607{ 608 fmt->width = mode->width; 609 fmt->height = mode->height; 610 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; 611 fmt->field = V4L2_FIELD_NONE; 612} 613 614static int ov9734_start_streaming(struct ov9734 *ov9734) 615{ 616 const struct ov9734_reg_list *reg_list; 617 int link_freq_index, ret; 618 619 link_freq_index = ov9734->cur_mode->link_freq_index; 620 reg_list = &link_freq_configs[link_freq_index].reg_list; 621 ret = ov9734_write_reg_list(ov9734, reg_list); 622 if (ret) { 623 dev_err(ov9734->dev, "failed to set plls"); 624 return ret; 625 } 626 627 reg_list = &ov9734->cur_mode->reg_list; 628 ret = ov9734_write_reg_list(ov9734, reg_list); 629 if (ret) { 630 dev_err(ov9734->dev, "failed to set mode"); 631 return ret; 632 } 633 634 ret = __v4l2_ctrl_handler_setup(ov9734->sd.ctrl_handler); 635 if (ret) 636 return ret; 637 638 ret = ov9734_write_reg(ov9734, OV9734_REG_MODE_SELECT, 639 1, OV9734_MODE_STREAMING); 640 if (ret) 641 dev_err(ov9734->dev, "failed to start stream"); 642 643 return ret; 644} 645 646static void ov9734_stop_streaming(struct ov9734 *ov9734) 647{ 648 if (ov9734_write_reg(ov9734, OV9734_REG_MODE_SELECT, 649 1, OV9734_MODE_STANDBY)) 650 dev_err(ov9734->dev, "failed to stop stream"); 651} 652 653static int ov9734_set_stream(struct v4l2_subdev *sd, int enable) 654{ 655 struct ov9734 *ov9734 = to_ov9734(sd); 656 int ret = 0; 657 658 mutex_lock(&ov9734->mutex); 659 660 if (enable) { 661 ret = pm_runtime_resume_and_get(ov9734->dev); 662 if (ret < 0) { 663 mutex_unlock(&ov9734->mutex); 664 return ret; 665 } 666 667 ret = ov9734_start_streaming(ov9734); 668 if (ret) { 669 enable = 0; 670 ov9734_stop_streaming(ov9734); 671 pm_runtime_put(ov9734->dev); 672 } 673 } else { 674 ov9734_stop_streaming(ov9734); 675 pm_runtime_put(ov9734->dev); 676 } 677 678 mutex_unlock(&ov9734->mutex); 679 680 return ret; 681} 682 683static int ov9734_set_format(struct v4l2_subdev *sd, 684 struct v4l2_subdev_state *sd_state, 685 struct v4l2_subdev_format *fmt) 686{ 687 struct ov9734 *ov9734 = to_ov9734(sd); 688 const struct ov9734_mode *mode; 689 s32 vblank_def, h_blank; 690 691 mode = v4l2_find_nearest_size(supported_modes, 692 ARRAY_SIZE(supported_modes), width, 693 height, fmt->format.width, 694 fmt->format.height); 695 696 mutex_lock(&ov9734->mutex); 697 ov9734_update_pad_format(mode, &fmt->format); 698 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 699 *v4l2_subdev_state_get_format(sd_state, fmt->pad) = fmt->format; 700 } else { 701 ov9734->cur_mode = mode; 702 __v4l2_ctrl_s_ctrl(ov9734->link_freq, mode->link_freq_index); 703 __v4l2_ctrl_s_ctrl_int64(ov9734->pixel_rate, 704 to_pixel_rate(mode->link_freq_index)); 705 706 /* Update limits and set FPS to default */ 707 vblank_def = mode->vts_def - mode->height; 708 __v4l2_ctrl_modify_range(ov9734->vblank, 709 mode->vts_min - mode->height, 710 OV9734_VTS_MAX - mode->height, 1, 711 vblank_def); 712 __v4l2_ctrl_s_ctrl(ov9734->vblank, vblank_def); 713 h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) - 714 mode->width; 715 __v4l2_ctrl_modify_range(ov9734->hblank, h_blank, h_blank, 1, 716 h_blank); 717 } 718 719 mutex_unlock(&ov9734->mutex); 720 721 return 0; 722} 723 724static int ov9734_get_format(struct v4l2_subdev *sd, 725 struct v4l2_subdev_state *sd_state, 726 struct v4l2_subdev_format *fmt) 727{ 728 struct ov9734 *ov9734 = to_ov9734(sd); 729 730 mutex_lock(&ov9734->mutex); 731 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 732 fmt->format = *v4l2_subdev_state_get_format(sd_state, 733 fmt->pad); 734 else 735 ov9734_update_pad_format(ov9734->cur_mode, &fmt->format); 736 737 mutex_unlock(&ov9734->mutex); 738 739 return 0; 740} 741 742static int ov9734_enum_mbus_code(struct v4l2_subdev *sd, 743 struct v4l2_subdev_state *sd_state, 744 struct v4l2_subdev_mbus_code_enum *code) 745{ 746 if (code->index > 0) 747 return -EINVAL; 748 749 code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 750 751 return 0; 752} 753 754static int ov9734_enum_frame_size(struct v4l2_subdev *sd, 755 struct v4l2_subdev_state *sd_state, 756 struct v4l2_subdev_frame_size_enum *fse) 757{ 758 if (fse->index >= ARRAY_SIZE(supported_modes)) 759 return -EINVAL; 760 761 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 762 return -EINVAL; 763 764 fse->min_width = supported_modes[fse->index].width; 765 fse->max_width = fse->min_width; 766 fse->min_height = supported_modes[fse->index].height; 767 fse->max_height = fse->min_height; 768 769 return 0; 770} 771 772static int ov9734_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 773{ 774 struct ov9734 *ov9734 = to_ov9734(sd); 775 776 mutex_lock(&ov9734->mutex); 777 ov9734_update_pad_format(&supported_modes[0], 778 v4l2_subdev_state_get_format(fh->state, 0)); 779 mutex_unlock(&ov9734->mutex); 780 781 return 0; 782} 783 784static const struct v4l2_subdev_video_ops ov9734_video_ops = { 785 .s_stream = ov9734_set_stream, 786}; 787 788static const struct v4l2_subdev_pad_ops ov9734_pad_ops = { 789 .set_fmt = ov9734_set_format, 790 .get_fmt = ov9734_get_format, 791 .enum_mbus_code = ov9734_enum_mbus_code, 792 .enum_frame_size = ov9734_enum_frame_size, 793}; 794 795static const struct v4l2_subdev_ops ov9734_subdev_ops = { 796 .video = &ov9734_video_ops, 797 .pad = &ov9734_pad_ops, 798}; 799 800static const struct media_entity_operations ov9734_subdev_entity_ops = { 801 .link_validate = v4l2_subdev_link_validate, 802}; 803 804static const struct v4l2_subdev_internal_ops ov9734_internal_ops = { 805 .open = ov9734_open, 806}; 807 808static int ov9734_identify_module(struct ov9734 *ov9734) 809{ 810 int ret; 811 u32 val; 812 813 ret = ov9734_read_reg(ov9734, OV9734_REG_CHIP_ID, 2, &val); 814 if (ret) 815 return ret; 816 817 if (val != OV9734_CHIP_ID) { 818 dev_err(ov9734->dev, "chip id mismatch: %x!=%x", 819 OV9734_CHIP_ID, val); 820 return -ENXIO; 821 } 822 823 return 0; 824} 825 826static int ov9734_check_hwcfg(struct device *dev) 827{ 828 struct fwnode_handle *ep; 829 struct fwnode_handle *fwnode = dev_fwnode(dev); 830 struct v4l2_fwnode_endpoint bus_cfg = { 831 .bus_type = V4L2_MBUS_CSI2_DPHY 832 }; 833 int ret; 834 unsigned int i, j; 835 836 if (!fwnode) 837 return -ENXIO; 838 839 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 840 if (!ep) 841 return -ENXIO; 842 843 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 844 fwnode_handle_put(ep); 845 if (ret) 846 return ret; 847 848 if (!bus_cfg.nr_of_link_frequencies) { 849 dev_err(dev, "no link frequencies defined"); 850 ret = -EINVAL; 851 goto check_hwcfg_error; 852 } 853 854 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { 855 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { 856 if (link_freq_menu_items[i] == 857 bus_cfg.link_frequencies[j]) 858 break; 859 } 860 861 if (j == bus_cfg.nr_of_link_frequencies) { 862 dev_err(dev, "no link frequency %lld supported", 863 link_freq_menu_items[i]); 864 ret = -EINVAL; 865 goto check_hwcfg_error; 866 } 867 } 868 869check_hwcfg_error: 870 v4l2_fwnode_endpoint_free(&bus_cfg); 871 872 return ret; 873} 874 875static void ov9734_remove(struct i2c_client *client) 876{ 877 struct v4l2_subdev *sd = i2c_get_clientdata(client); 878 struct ov9734 *ov9734 = to_ov9734(sd); 879 880 v4l2_async_unregister_subdev(sd); 881 media_entity_cleanup(&sd->entity); 882 v4l2_ctrl_handler_free(sd->ctrl_handler); 883 pm_runtime_disable(ov9734->dev); 884 pm_runtime_set_suspended(ov9734->dev); 885 mutex_destroy(&ov9734->mutex); 886} 887 888static int ov9734_probe(struct i2c_client *client) 889{ 890 struct ov9734 *ov9734; 891 unsigned long freq; 892 int ret; 893 894 ret = ov9734_check_hwcfg(&client->dev); 895 if (ret) { 896 dev_err(&client->dev, "failed to check HW configuration: %d", 897 ret); 898 return ret; 899 } 900 901 ov9734 = devm_kzalloc(&client->dev, sizeof(*ov9734), GFP_KERNEL); 902 if (!ov9734) 903 return -ENOMEM; 904 905 ov9734->dev = &client->dev; 906 907 ov9734->clk = devm_v4l2_sensor_clk_get(ov9734->dev, NULL); 908 if (IS_ERR(ov9734->clk)) 909 return dev_err_probe(ov9734->dev, PTR_ERR(ov9734->clk), 910 "failed to get clock\n"); 911 912 freq = clk_get_rate(ov9734->clk); 913 if (freq != OV9734_MCLK) 914 return dev_err_probe(ov9734->dev, -EINVAL, 915 "external clock %lu is not supported", 916 freq); 917 918 v4l2_i2c_subdev_init(&ov9734->sd, client, &ov9734_subdev_ops); 919 ret = ov9734_identify_module(ov9734); 920 if (ret) { 921 dev_err(ov9734->dev, "failed to find sensor: %d", ret); 922 return ret; 923 } 924 925 mutex_init(&ov9734->mutex); 926 ov9734->cur_mode = &supported_modes[0]; 927 ret = ov9734_init_controls(ov9734); 928 if (ret) { 929 dev_err(ov9734->dev, "failed to init controls: %d", ret); 930 goto probe_error_v4l2_ctrl_handler_free; 931 } 932 933 ov9734->sd.internal_ops = &ov9734_internal_ops; 934 ov9734->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 935 ov9734->sd.entity.ops = &ov9734_subdev_entity_ops; 936 ov9734->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 937 ov9734->pad.flags = MEDIA_PAD_FL_SOURCE; 938 ret = media_entity_pads_init(&ov9734->sd.entity, 1, &ov9734->pad); 939 if (ret) { 940 dev_err(ov9734->dev, "failed to init entity pads: %d", ret); 941 goto probe_error_v4l2_ctrl_handler_free; 942 } 943 944 /* 945 * Device is already turned on by i2c-core with ACPI domain PM. 946 * Enable runtime PM and turn off the device. 947 */ 948 pm_runtime_set_active(ov9734->dev); 949 pm_runtime_enable(ov9734->dev); 950 pm_runtime_idle(ov9734->dev); 951 952 ret = v4l2_async_register_subdev_sensor(&ov9734->sd); 953 if (ret < 0) { 954 dev_err(ov9734->dev, "failed to register V4L2 subdev: %d", 955 ret); 956 goto probe_error_media_entity_cleanup_pm; 957 } 958 959 return 0; 960 961probe_error_media_entity_cleanup_pm: 962 pm_runtime_disable(ov9734->dev); 963 pm_runtime_set_suspended(ov9734->dev); 964 media_entity_cleanup(&ov9734->sd.entity); 965 966probe_error_v4l2_ctrl_handler_free: 967 v4l2_ctrl_handler_free(ov9734->sd.ctrl_handler); 968 mutex_destroy(&ov9734->mutex); 969 970 return ret; 971} 972 973static const struct acpi_device_id ov9734_acpi_ids[] = { 974 { "OVTI9734", }, 975 {} 976}; 977 978MODULE_DEVICE_TABLE(acpi, ov9734_acpi_ids); 979 980static struct i2c_driver ov9734_i2c_driver = { 981 .driver = { 982 .name = "ov9734", 983 .acpi_match_table = ov9734_acpi_ids, 984 }, 985 .probe = ov9734_probe, 986 .remove = ov9734_remove, 987}; 988 989module_i2c_driver(ov9734_i2c_driver); 990 991MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>"); 992MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>"); 993MODULE_DESCRIPTION("OmniVision OV9734 sensor driver"); 994MODULE_LICENSE("GPL v2");
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