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ov8858.c
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linux-6.19.14/drivers/media/i2c/ov8858.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2023 Jacopo Mondi <jacopo.mondi@ideasonboard.com> 4 * Copyright (C) 2022 Nicholas Roth <nicholas@rothemail.net> 5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd. 6 */ 7 8#include <linux/unaligned.h> 9 10#include <linux/clk.h> 11#include <linux/delay.h> 12#include <linux/device.h> 13#include <linux/gpio/consumer.h> 14#include <linux/i2c.h> 15#include <linux/module.h> 16#include <linux/of.h> 17#include <linux/pm_runtime.h> 18#include <linux/property.h> 19#include <linux/regulator/consumer.h> 20#include <linux/slab.h> 21 22#include <media/media-entity.h> 23#include <media/v4l2-async.h> 24#include <media/v4l2-common.h> 25#include <media/v4l2-ctrls.h> 26#include <media/v4l2-device.h> 27#include <media/v4l2-fwnode.h> 28#include <media/v4l2-mediabus.h> 29#include <media/v4l2-subdev.h> 30 31#define OV8858_LINK_FREQ 360000000U 32#define OV8858_XVCLK_FREQ 24000000 33 34#define OV8858_REG_SIZE_SHIFT 16 35#define OV8858_REG_ADDR_MASK 0xffff 36#define OV8858_REG_8BIT(n) ((1U << OV8858_REG_SIZE_SHIFT) | (n)) 37#define OV8858_REG_16BIT(n) ((2U << OV8858_REG_SIZE_SHIFT) | (n)) 38#define OV8858_REG_24BIT(n) ((3U << OV8858_REG_SIZE_SHIFT) | (n)) 39 40#define OV8858_REG_SC_CTRL0100 OV8858_REG_8BIT(0x0100) 41#define OV8858_MODE_SW_STANDBY 0x0 42#define OV8858_MODE_STREAMING 0x1 43 44#define OV8858_REG_CHIP_ID OV8858_REG_24BIT(0x300a) 45#define OV8858_CHIP_ID 0x008858 46 47#define OV8858_REG_SUB_ID OV8858_REG_8BIT(0x302a) 48#define OV8858_R1A 0xb0 49#define OV8858_R2A 0xb2 50 51#define OV8858_REG_LONG_EXPO OV8858_REG_24BIT(0x3500) 52#define OV8858_EXPOSURE_MIN 4 53#define OV8858_EXPOSURE_STEP 1 54#define OV8858_EXPOSURE_MARGIN 4 55 56#define OV8858_REG_LONG_GAIN OV8858_REG_16BIT(0x3508) 57#define OV8858_LONG_GAIN_MIN 0x0 58#define OV8858_LONG_GAIN_MAX 0x7ff 59#define OV8858_LONG_GAIN_STEP 1 60#define OV8858_LONG_GAIN_DEFAULT 0x80 61 62#define OV8858_REG_LONG_DIGIGAIN OV8858_REG_16BIT(0x350a) 63#define OV8858_LONG_DIGIGAIN_H_MASK 0x3fc0 64#define OV8858_LONG_DIGIGAIN_L_MASK 0x3f 65#define OV8858_LONG_DIGIGAIN_H_SHIFT 2 66#define OV8858_LONG_DIGIGAIN_MIN 0x0 67#define OV8858_LONG_DIGIGAIN_MAX 0x3fff 68#define OV8858_LONG_DIGIGAIN_STEP 1 69#define OV8858_LONG_DIGIGAIN_DEFAULT 0x200 70 71#define OV8858_REG_VTS OV8858_REG_16BIT(0x380e) 72#define OV8858_VTS_MAX 0x7fff 73 74#define OV8858_REG_TEST_PATTERN OV8858_REG_8BIT(0x5e00) 75#define OV8858_TEST_PATTERN_ENABLE 0x80 76#define OV8858_TEST_PATTERN_DISABLE 0x0 77 78#define REG_NULL 0xffff 79 80static const char * const ov8858_supply_names[] = { 81 "avdd", /* Analog power */ 82 "dovdd", /* Digital I/O power */ 83 "dvdd", /* Digital core power */ 84}; 85 86struct regval { 87 u16 addr; 88 u8 val; 89}; 90 91struct regval_modes { 92 const struct regval *mode_2lanes; 93 const struct regval *mode_4lanes; 94}; 95 96struct ov8858_mode { 97 u32 width; 98 u32 height; 99 u32 hts_def; 100 u32 vts_def; 101 u32 exp_def; 102 const struct regval_modes reg_modes; 103}; 104 105struct ov8858 { 106 struct clk *xvclk; 107 struct gpio_desc *reset_gpio; 108 struct gpio_desc *pwdn_gpio; 109 struct regulator_bulk_data supplies[ARRAY_SIZE(ov8858_supply_names)]; 110 111 struct v4l2_subdev subdev; 112 struct media_pad pad; 113 114 struct v4l2_ctrl_handler ctrl_handler; 115 struct v4l2_ctrl *exposure; 116 struct v4l2_ctrl *hblank; 117 struct v4l2_ctrl *vblank; 118 119 const struct regval *global_regs; 120 121 unsigned int num_lanes; 122}; 123 124static inline struct ov8858 *sd_to_ov8858(struct v4l2_subdev *sd) 125{ 126 return container_of(sd, struct ov8858, subdev); 127} 128 129static const struct regval ov8858_global_regs_r1a[] = { 130 {0x0100, 0x00}, 131 {0x0100, 0x00}, 132 {0x0100, 0x00}, 133 {0x0100, 0x00}, 134 {0x0302, 0x1e}, 135 {0x0303, 0x00}, 136 {0x0304, 0x03}, 137 {0x030e, 0x00}, 138 {0x030f, 0x09}, 139 {0x0312, 0x01}, 140 {0x031e, 0x0c}, 141 {0x3600, 0x00}, 142 {0x3601, 0x00}, 143 {0x3602, 0x00}, 144 {0x3603, 0x00}, 145 {0x3604, 0x22}, 146 {0x3605, 0x30}, 147 {0x3606, 0x00}, 148 {0x3607, 0x20}, 149 {0x3608, 0x11}, 150 {0x3609, 0x28}, 151 {0x360a, 0x00}, 152 {0x360b, 0x06}, 153 {0x360c, 0xdc}, 154 {0x360d, 0x40}, 155 {0x360e, 0x0c}, 156 {0x360f, 0x20}, 157 {0x3610, 0x07}, 158 {0x3611, 0x20}, 159 {0x3612, 0x88}, 160 {0x3613, 0x80}, 161 {0x3614, 0x58}, 162 {0x3615, 0x00}, 163 {0x3616, 0x4a}, 164 {0x3617, 0xb0}, 165 {0x3618, 0x56}, 166 {0x3619, 0x70}, 167 {0x361a, 0x99}, 168 {0x361b, 0x00}, 169 {0x361c, 0x07}, 170 {0x361d, 0x00}, 171 {0x361e, 0x00}, 172 {0x361f, 0x00}, 173 {0x3638, 0xff}, 174 {0x3633, 0x0c}, 175 {0x3634, 0x0c}, 176 {0x3635, 0x0c}, 177 {0x3636, 0x0c}, 178 {0x3645, 0x13}, 179 {0x3646, 0x83}, 180 {0x364a, 0x07}, 181 {0x3015, 0x01}, 182 {0x3018, 0x32}, 183 {0x3020, 0x93}, 184 {0x3022, 0x01}, 185 {0x3031, 0x0a}, 186 {0x3034, 0x00}, 187 {0x3106, 0x01}, 188 {0x3305, 0xf1}, 189 {0x3308, 0x00}, 190 {0x3309, 0x28}, 191 {0x330a, 0x00}, 192 {0x330b, 0x20}, 193 {0x330c, 0x00}, 194 {0x330d, 0x00}, 195 {0x330e, 0x00}, 196 {0x330f, 0x40}, 197 {0x3307, 0x04}, 198 {0x3500, 0x00}, 199 {0x3501, 0x4d}, 200 {0x3502, 0x40}, 201 {0x3503, 0x00}, 202 {0x3505, 0x80}, 203 {0x3508, 0x04}, 204 {0x3509, 0x00}, 205 {0x350c, 0x00}, 206 {0x350d, 0x80}, 207 {0x3510, 0x00}, 208 {0x3511, 0x02}, 209 {0x3512, 0x00}, 210 {0x3700, 0x18}, 211 {0x3701, 0x0c}, 212 {0x3702, 0x28}, 213 {0x3703, 0x19}, 214 {0x3704, 0x14}, 215 {0x3705, 0x00}, 216 {0x3706, 0x35}, 217 {0x3707, 0x04}, 218 {0x3708, 0x24}, 219 {0x3709, 0x33}, 220 {0x370a, 0x00}, 221 {0x370b, 0xb5}, 222 {0x370c, 0x04}, 223 {0x3718, 0x12}, 224 {0x3719, 0x31}, 225 {0x3712, 0x42}, 226 {0x3714, 0x24}, 227 {0x371e, 0x19}, 228 {0x371f, 0x40}, 229 {0x3720, 0x05}, 230 {0x3721, 0x05}, 231 {0x3724, 0x06}, 232 {0x3725, 0x01}, 233 {0x3726, 0x06}, 234 {0x3728, 0x05}, 235 {0x3729, 0x02}, 236 {0x372a, 0x03}, 237 {0x372b, 0x53}, 238 {0x372c, 0xa3}, 239 {0x372d, 0x53}, 240 {0x372e, 0x06}, 241 {0x372f, 0x10}, 242 {0x3730, 0x01}, 243 {0x3731, 0x06}, 244 {0x3732, 0x14}, 245 {0x3733, 0x10}, 246 {0x3734, 0x40}, 247 {0x3736, 0x20}, 248 {0x373a, 0x05}, 249 {0x373b, 0x06}, 250 {0x373c, 0x0a}, 251 {0x373e, 0x03}, 252 {0x3755, 0x10}, 253 {0x3758, 0x00}, 254 {0x3759, 0x4c}, 255 {0x375a, 0x06}, 256 {0x375b, 0x13}, 257 {0x375c, 0x20}, 258 {0x375d, 0x02}, 259 {0x375e, 0x00}, 260 {0x375f, 0x14}, 261 {0x3768, 0x22}, 262 {0x3769, 0x44}, 263 {0x376a, 0x44}, 264 {0x3761, 0x00}, 265 {0x3762, 0x00}, 266 {0x3763, 0x00}, 267 {0x3766, 0xff}, 268 {0x376b, 0x00}, 269 {0x3772, 0x23}, 270 {0x3773, 0x02}, 271 {0x3774, 0x16}, 272 {0x3775, 0x12}, 273 {0x3776, 0x04}, 274 {0x3777, 0x00}, 275 {0x3778, 0x1b}, 276 {0x37a0, 0x44}, 277 {0x37a1, 0x3d}, 278 {0x37a2, 0x3d}, 279 {0x37a3, 0x00}, 280 {0x37a4, 0x00}, 281 {0x37a5, 0x00}, 282 {0x37a6, 0x00}, 283 {0x37a7, 0x44}, 284 {0x37a8, 0x4c}, 285 {0x37a9, 0x4c}, 286 {0x3760, 0x00}, 287 {0x376f, 0x01}, 288 {0x37aa, 0x44}, 289 {0x37ab, 0x2e}, 290 {0x37ac, 0x2e}, 291 {0x37ad, 0x33}, 292 {0x37ae, 0x0d}, 293 {0x37af, 0x0d}, 294 {0x37b0, 0x00}, 295 {0x37b1, 0x00}, 296 {0x37b2, 0x00}, 297 {0x37b3, 0x42}, 298 {0x37b4, 0x42}, 299 {0x37b5, 0x33}, 300 {0x37b6, 0x00}, 301 {0x37b7, 0x00}, 302 {0x37b8, 0x00}, 303 {0x37b9, 0xff}, 304 {0x3800, 0x00}, 305 {0x3801, 0x0c}, 306 {0x3802, 0x00}, 307 {0x3803, 0x0c}, 308 {0x3804, 0x0c}, 309 {0x3805, 0xd3}, 310 {0x3806, 0x09}, 311 {0x3807, 0xa3}, 312 {0x3808, 0x06}, 313 {0x3809, 0x60}, 314 {0x380a, 0x04}, 315 {0x380b, 0xc8}, 316 {0x380c, 0x07}, 317 {0x380d, 0x88}, 318 {0x380e, 0x04}, 319 {0x380f, 0xdc}, 320 {0x3810, 0x00}, 321 {0x3811, 0x04}, 322 {0x3813, 0x02}, 323 {0x3814, 0x03}, 324 {0x3815, 0x01}, 325 {0x3820, 0x00}, 326 {0x3821, 0x67}, 327 {0x382a, 0x03}, 328 {0x382b, 0x01}, 329 {0x3830, 0x08}, 330 {0x3836, 0x02}, 331 {0x3837, 0x18}, 332 {0x3841, 0xff}, 333 {0x3846, 0x48}, 334 {0x3d85, 0x14}, 335 {0x3f08, 0x08}, 336 {0x3f0a, 0x80}, 337 {0x4000, 0xf1}, 338 {0x4001, 0x10}, 339 {0x4005, 0x10}, 340 {0x4002, 0x27}, 341 {0x4009, 0x81}, 342 {0x400b, 0x0c}, 343 {0x401b, 0x00}, 344 {0x401d, 0x00}, 345 {0x4020, 0x00}, 346 {0x4021, 0x04}, 347 {0x4022, 0x04}, 348 {0x4023, 0xb9}, 349 {0x4024, 0x05}, 350 {0x4025, 0x2a}, 351 {0x4026, 0x05}, 352 {0x4027, 0x2b}, 353 {0x4028, 0x00}, 354 {0x4029, 0x02}, 355 {0x402a, 0x04}, 356 {0x402b, 0x04}, 357 {0x402c, 0x02}, 358 {0x402d, 0x02}, 359 {0x402e, 0x08}, 360 {0x402f, 0x02}, 361 {0x401f, 0x00}, 362 {0x4034, 0x3f}, 363 {0x403d, 0x04}, 364 {0x4300, 0xff}, 365 {0x4301, 0x00}, 366 {0x4302, 0x0f}, 367 {0x4316, 0x00}, 368 {0x4500, 0x38}, 369 {0x4503, 0x18}, 370 {0x4600, 0x00}, 371 {0x4601, 0xcb}, 372 {0x481f, 0x32}, 373 {0x4837, 0x16}, 374 {0x4850, 0x10}, 375 {0x4851, 0x32}, 376 {0x4b00, 0x2a}, 377 {0x4b0d, 0x00}, 378 {0x4d00, 0x04}, 379 {0x4d01, 0x18}, 380 {0x4d02, 0xc3}, 381 {0x4d03, 0xff}, 382 {0x4d04, 0xff}, 383 {0x4d05, 0xff}, 384 {0x5000, 0x7e}, 385 {0x5001, 0x01}, 386 {0x5002, 0x08}, 387 {0x5003, 0x20}, 388 {0x5046, 0x12}, 389 {0x5901, 0x00}, 390 {0x5e00, 0x00}, 391 {0x5e01, 0x41}, 392 {0x382d, 0x7f}, 393 {0x4825, 0x3a}, 394 {0x4826, 0x40}, 395 {0x4808, 0x25}, 396 {REG_NULL, 0x00}, 397}; 398 399static const struct regval ov8858_global_regs_r2a_2lane[] = { 400 /* 401 * MIPI=720Mbps, SysClk=144Mhz,Dac Clock=360Mhz. 402 * v00_01_00 (05/29/2014) : initial setting 403 * AM19 : 3617 <- 0xC0 404 * AM20 : change FWC_6K_EN to be default 0x3618=0x5a 405 */ 406 {0x0103, 0x01}, /* software reset */ 407 {0x0100, 0x00}, /* software standby */ 408 {0x0302, 0x1e}, /* pll1_multi */ 409 {0x0303, 0x00}, /* pll1_divm */ 410 {0x0304, 0x03}, /* pll1_div_mipi */ 411 {0x030e, 0x02}, /* pll2_rdiv */ 412 {0x030f, 0x04}, /* pll2_divsp */ 413 {0x0312, 0x03}, /* pll2_pre_div0, pll2_r_divdac */ 414 {0x031e, 0x0c}, /* pll1_no_lat */ 415 {0x3600, 0x00}, 416 {0x3601, 0x00}, 417 {0x3602, 0x00}, 418 {0x3603, 0x00}, 419 {0x3604, 0x22}, 420 {0x3605, 0x20}, 421 {0x3606, 0x00}, 422 {0x3607, 0x20}, 423 {0x3608, 0x11}, 424 {0x3609, 0x28}, 425 {0x360a, 0x00}, 426 {0x360b, 0x05}, 427 {0x360c, 0xd4}, 428 {0x360d, 0x40}, 429 {0x360e, 0x0c}, 430 {0x360f, 0x20}, 431 {0x3610, 0x07}, 432 {0x3611, 0x20}, 433 {0x3612, 0x88}, 434 {0x3613, 0x80}, 435 {0x3614, 0x58}, 436 {0x3615, 0x00}, 437 {0x3616, 0x4a}, 438 {0x3617, 0x90}, 439 {0x3618, 0x5a}, 440 {0x3619, 0x70}, 441 {0x361a, 0x99}, 442 {0x361b, 0x0a}, 443 {0x361c, 0x07}, 444 {0x361d, 0x00}, 445 {0x361e, 0x00}, 446 {0x361f, 0x00}, 447 {0x3638, 0xff}, 448 {0x3633, 0x0f}, 449 {0x3634, 0x0f}, 450 {0x3635, 0x0f}, 451 {0x3636, 0x12}, 452 {0x3645, 0x13}, 453 {0x3646, 0x83}, 454 {0x364a, 0x07}, 455 {0x3015, 0x00}, 456 {0x3018, 0x32}, /* MIPI 2 lane */ 457 {0x3020, 0x93}, /* Clock switch output normal, pclk_div =/1 */ 458 {0x3022, 0x01}, /* pd_mipi enable when rst_sync */ 459 {0x3031, 0x0a}, /* MIPI 10-bit mode */ 460 {0x3034, 0x00}, 461 {0x3106, 0x01}, /* sclk_div, sclk_pre_div */ 462 {0x3305, 0xf1}, 463 {0x3308, 0x00}, 464 {0x3309, 0x28}, 465 {0x330a, 0x00}, 466 {0x330b, 0x20}, 467 {0x330c, 0x00}, 468 {0x330d, 0x00}, 469 {0x330e, 0x00}, 470 {0x330f, 0x40}, 471 {0x3307, 0x04}, 472 {0x3500, 0x00}, /* exposure H */ 473 {0x3501, 0x4d}, /* exposure M */ 474 {0x3502, 0x40}, /* exposure L */ 475 {0x3503, 0x80}, /* gain delay ?, exposure delay 1 frame, real gain */ 476 {0x3505, 0x80}, /* gain option */ 477 {0x3508, 0x02}, /* gain H */ 478 {0x3509, 0x00}, /* gain L */ 479 {0x350c, 0x00}, /* short gain H */ 480 {0x350d, 0x80}, /* short gain L */ 481 {0x3510, 0x00}, /* short exposure H */ 482 {0x3511, 0x02}, /* short exposure M */ 483 {0x3512, 0x00}, /* short exposure L */ 484 {0x3700, 0x18}, 485 {0x3701, 0x0c}, 486 {0x3702, 0x28}, 487 {0x3703, 0x19}, 488 {0x3704, 0x14}, 489 {0x3705, 0x00}, 490 {0x3706, 0x82}, 491 {0x3707, 0x04}, 492 {0x3708, 0x24}, 493 {0x3709, 0x33}, 494 {0x370a, 0x01}, 495 {0x370b, 0x82}, 496 {0x370c, 0x04}, 497 {0x3718, 0x12}, 498 {0x3719, 0x31}, 499 {0x3712, 0x42}, 500 {0x3714, 0x24}, 501 {0x371e, 0x19}, 502 {0x371f, 0x40}, 503 {0x3720, 0x05}, 504 {0x3721, 0x05}, 505 {0x3724, 0x06}, 506 {0x3725, 0x01}, 507 {0x3726, 0x06}, 508 {0x3728, 0x05}, 509 {0x3729, 0x02}, 510 {0x372a, 0x03}, 511 {0x372b, 0x53}, 512 {0x372c, 0xa3}, 513 {0x372d, 0x53}, 514 {0x372e, 0x06}, 515 {0x372f, 0x10}, 516 {0x3730, 0x01}, 517 {0x3731, 0x06}, 518 {0x3732, 0x14}, 519 {0x3733, 0x10}, 520 {0x3734, 0x40}, 521 {0x3736, 0x20}, 522 {0x373a, 0x05}, 523 {0x373b, 0x06}, 524 {0x373c, 0x0a}, 525 {0x373e, 0x03}, 526 {0x3750, 0x0a}, 527 {0x3751, 0x0e}, 528 {0x3755, 0x10}, 529 {0x3758, 0x00}, 530 {0x3759, 0x4c}, 531 {0x375a, 0x06}, 532 {0x375b, 0x13}, 533 {0x375c, 0x20}, 534 {0x375d, 0x02}, 535 {0x375e, 0x00}, 536 {0x375f, 0x14}, 537 {0x3768, 0x22}, 538 {0x3769, 0x44}, 539 {0x376a, 0x44}, 540 {0x3761, 0x00}, 541 {0x3762, 0x00}, 542 {0x3763, 0x00}, 543 {0x3766, 0xff}, 544 {0x376b, 0x00}, 545 {0x3772, 0x23}, 546 {0x3773, 0x02}, 547 {0x3774, 0x16}, 548 {0x3775, 0x12}, 549 {0x3776, 0x04}, 550 {0x3777, 0x00}, 551 {0x3778, 0x17}, 552 {0x37a0, 0x44}, 553 {0x37a1, 0x3d}, 554 {0x37a2, 0x3d}, 555 {0x37a3, 0x00}, 556 {0x37a4, 0x00}, 557 {0x37a5, 0x00}, 558 {0x37a6, 0x00}, 559 {0x37a7, 0x44}, 560 {0x37a8, 0x4c}, 561 {0x37a9, 0x4c}, 562 {0x3760, 0x00}, 563 {0x376f, 0x01}, 564 {0x37aa, 0x44}, 565 {0x37ab, 0x2e}, 566 {0x37ac, 0x2e}, 567 {0x37ad, 0x33}, 568 {0x37ae, 0x0d}, 569 {0x37af, 0x0d}, 570 {0x37b0, 0x00}, 571 {0x37b1, 0x00}, 572 {0x37b2, 0x00}, 573 {0x37b3, 0x42}, 574 {0x37b4, 0x42}, 575 {0x37b5, 0x31}, 576 {0x37b6, 0x00}, 577 {0x37b7, 0x00}, 578 {0x37b8, 0x00}, 579 {0x37b9, 0xff}, 580 {0x3800, 0x00}, /* x start H */ 581 {0x3801, 0x0c}, /* x start L */ 582 {0x3802, 0x00}, /* y start H */ 583 {0x3803, 0x0c}, /* y start L */ 584 {0x3804, 0x0c}, /* x end H */ 585 {0x3805, 0xd3}, /* x end L */ 586 {0x3806, 0x09}, /* y end H */ 587 {0x3807, 0xa3}, /* y end L */ 588 {0x3808, 0x06}, /* x output size H */ 589 {0x3809, 0x60}, /* x output size L */ 590 {0x380a, 0x04}, /* y output size H */ 591 {0x380b, 0xc8}, /* y output size L */ 592 {0x380c, 0x07}, /* HTS H */ 593 {0x380d, 0x88}, /* HTS L */ 594 {0x380e, 0x04}, /* VTS H */ 595 {0x380f, 0xdc}, /* VTS L */ 596 {0x3810, 0x00}, /* ISP x win H */ 597 {0x3811, 0x04}, /* ISP x win L */ 598 {0x3813, 0x02}, /* ISP y win L */ 599 {0x3814, 0x03}, /* x odd inc */ 600 {0x3815, 0x01}, /* x even inc */ 601 {0x3820, 0x00}, /* vflip off */ 602 {0x3821, 0x67}, /* mirror on, bin on */ 603 {0x382a, 0x03}, /* y odd inc */ 604 {0x382b, 0x01}, /* y even inc */ 605 {0x3830, 0x08}, 606 {0x3836, 0x02}, 607 {0x3837, 0x18}, 608 {0x3841, 0xff}, /* window auto size enable */ 609 {0x3846, 0x48}, 610 {0x3d85, 0x16}, /* OTP power up load data enable with BIST */ 611 {0x3d8c, 0x73}, /* OTP setting start High */ 612 {0x3d8d, 0xde}, /* OTP setting start Low */ 613 {0x3f08, 0x08}, 614 {0x3f0a, 0x00}, 615 {0x4000, 0xf1}, /* out_range_trig, format_chg_trig */ 616 {0x4001, 0x10}, /* total 128 black column */ 617 {0x4005, 0x10}, /* BLC target L */ 618 {0x4002, 0x27}, /* value used to limit BLC offset */ 619 {0x4009, 0x81}, /* final BLC offset limitation enable */ 620 {0x400b, 0x0c}, /* DCBLC on, DCBLC manual mode on */ 621 {0x401b, 0x00}, /* zero line R coefficient */ 622 {0x401d, 0x00}, /* zoro line T coefficient */ 623 {0x4020, 0x00}, /* Anchor left start H */ 624 {0x4021, 0x04}, /* Anchor left start L */ 625 {0x4022, 0x06}, /* Anchor left end H */ 626 {0x4023, 0x00}, /* Anchor left end L */ 627 {0x4024, 0x0f}, /* Anchor right start H */ 628 {0x4025, 0x2a}, /* Anchor right start L */ 629 {0x4026, 0x0f}, /* Anchor right end H */ 630 {0x4027, 0x2b}, /* Anchor right end L */ 631 {0x4028, 0x00}, /* top zero line start */ 632 {0x4029, 0x02}, /* top zero line number */ 633 {0x402a, 0x04}, /* top black line start */ 634 {0x402b, 0x04}, /* top black line number */ 635 {0x402c, 0x00}, /* bottom zero line start */ 636 {0x402d, 0x02}, /* bottom zoro line number */ 637 {0x402e, 0x04}, /* bottom black line start */ 638 {0x402f, 0x04}, /* bottom black line number */ 639 {0x401f, 0x00}, /* interpolation x/y disable, Anchor one disable */ 640 {0x4034, 0x3f}, 641 {0x403d, 0x04}, /* md_precision_en */ 642 {0x4300, 0xff}, /* clip max H */ 643 {0x4301, 0x00}, /* clip min H */ 644 {0x4302, 0x0f}, /* clip min L, clip max L */ 645 {0x4316, 0x00}, 646 {0x4500, 0x58}, 647 {0x4503, 0x18}, 648 {0x4600, 0x00}, 649 {0x4601, 0xcb}, 650 {0x481f, 0x32}, /* clk prepare min */ 651 {0x4837, 0x16}, /* global timing */ 652 {0x4850, 0x10}, /* lane 1 = 1, lane 0 = 0 */ 653 {0x4851, 0x32}, /* lane 3 = 3, lane 2 = 2 */ 654 {0x4b00, 0x2a}, 655 {0x4b0d, 0x00}, 656 {0x4d00, 0x04}, /* temperature sensor */ 657 {0x4d01, 0x18}, 658 {0x4d02, 0xc3}, 659 {0x4d03, 0xff}, 660 {0x4d04, 0xff}, 661 {0x4d05, 0xff}, /* temperature sensor */ 662 {0x5000, 0xfe}, /* lenc on, slave/master AWB gain/statistics enable */ 663 {0x5001, 0x01}, /* BLC on */ 664 {0x5002, 0x08}, /* H scale off, WBMATCH off, OTP_DPC */ 665 {0x5003, 0x20}, /* DPC_DBC buffer control enable, WB */ 666 {0x501e, 0x93}, /* enable digital gain */ 667 {0x5046, 0x12}, 668 {0x5780, 0x3e}, /* DPC */ 669 {0x5781, 0x0f}, 670 {0x5782, 0x44}, 671 {0x5783, 0x02}, 672 {0x5784, 0x01}, 673 {0x5785, 0x00}, 674 {0x5786, 0x00}, 675 {0x5787, 0x04}, 676 {0x5788, 0x02}, 677 {0x5789, 0x0f}, 678 {0x578a, 0xfd}, 679 {0x578b, 0xf5}, 680 {0x578c, 0xf5}, 681 {0x578d, 0x03}, 682 {0x578e, 0x08}, 683 {0x578f, 0x0c}, 684 {0x5790, 0x08}, 685 {0x5791, 0x04}, 686 {0x5792, 0x00}, 687 {0x5793, 0x52}, 688 {0x5794, 0xa3}, /* DPC */ 689 {0x5871, 0x0d}, /* Lenc */ 690 {0x5870, 0x18}, 691 {0x586e, 0x10}, 692 {0x586f, 0x08}, 693 {0x58f7, 0x01}, 694 {0x58f8, 0x3d}, /* Lenc */ 695 {0x5901, 0x00}, /* H skip off, V skip off */ 696 {0x5b00, 0x02}, /* OTP DPC start address */ 697 {0x5b01, 0x10}, /* OTP DPC start address */ 698 {0x5b02, 0x03}, /* OTP DPC end address */ 699 {0x5b03, 0xcf}, /* OTP DPC end address */ 700 {0x5b05, 0x6c}, /* recover method = 2b11, */ 701 {0x5e00, 0x00}, /* use 0x3ff to test pattern off */ 702 {0x5e01, 0x41}, /* window cut enable */ 703 {0x382d, 0x7f}, 704 {0x4825, 0x3a}, /* lpx_p_min */ 705 {0x4826, 0x40}, /* hs_prepare_min */ 706 {0x4808, 0x25}, /* wake up delay in 1/1024 s */ 707 {0x3763, 0x18}, 708 {0x3768, 0xcc}, 709 {0x470b, 0x28}, 710 {0x4202, 0x00}, 711 {0x400d, 0x10}, /* BLC offset trigger L */ 712 {0x4040, 0x04}, /* BLC gain th2 */ 713 {0x403e, 0x04}, /* BLC gain th1 */ 714 {0x4041, 0xc6}, /* BLC */ 715 {0x3007, 0x80}, 716 {0x400a, 0x01}, 717 {REG_NULL, 0x00}, 718}; 719 720/* 721 * Xclk 24Mhz 722 * max_framerate 30fps 723 * mipi_datarate per lane 720Mbps 724 */ 725static const struct regval ov8858_1632x1224_regs_2lane[] = { 726 /* 727 * MIPI=720Mbps, SysClk=144Mhz,Dac Clock=360Mhz. 728 * v00_01_00 (05/29/2014) : initial setting 729 * AM19 : 3617 <- 0xC0 730 * AM20 : change FWC_6K_EN to be default 0x3618=0x5a 731 */ 732 {0x0100, 0x00}, 733 {0x3501, 0x4d}, /* exposure M */ 734 {0x3502, 0x40}, /* exposure L */ 735 {0x3778, 0x17}, 736 {0x3808, 0x06}, /* x output size H */ 737 {0x3809, 0x60}, /* x output size L */ 738 {0x380a, 0x04}, /* y output size H */ 739 {0x380b, 0xc8}, /* y output size L */ 740 {0x380c, 0x07}, /* HTS H */ 741 {0x380d, 0x88}, /* HTS L */ 742 {0x380e, 0x04}, /* VTS H */ 743 {0x380f, 0xdc}, /* VTS L */ 744 {0x3814, 0x03}, /* x odd inc */ 745 {0x3821, 0x67}, /* mirror on, bin on */ 746 {0x382a, 0x03}, /* y odd inc */ 747 {0x3830, 0x08}, 748 {0x3836, 0x02}, 749 {0x3f0a, 0x00}, 750 {0x4001, 0x10}, /* total 128 black column */ 751 {0x4022, 0x06}, /* Anchor left end H */ 752 {0x4023, 0x00}, /* Anchor left end L */ 753 {0x4025, 0x2a}, /* Anchor right start L */ 754 {0x4027, 0x2b}, /* Anchor right end L */ 755 {0x402b, 0x04}, /* top black line number */ 756 {0x402f, 0x04}, /* bottom black line number */ 757 {0x4500, 0x58}, 758 {0x4600, 0x00}, 759 {0x4601, 0xcb}, 760 {0x382d, 0x7f}, 761 {0x0100, 0x01}, 762 {REG_NULL, 0x00}, 763}; 764 765/* 766 * Xclk 24Mhz 767 * max_framerate 15fps 768 * mipi_datarate per lane 720Mbps 769 */ 770static const struct regval ov8858_3264x2448_regs_2lane[] = { 771 {0x0100, 0x00}, 772 {0x3501, 0x9a}, /* exposure M */ 773 {0x3502, 0x20}, /* exposure L */ 774 {0x3778, 0x1a}, 775 {0x3808, 0x0c}, /* x output size H */ 776 {0x3809, 0xc0}, /* x output size L */ 777 {0x380a, 0x09}, /* y output size H */ 778 {0x380b, 0x90}, /* y output size L */ 779 {0x380c, 0x07}, /* HTS H */ 780 {0x380d, 0x94}, /* HTS L */ 781 {0x380e, 0x09}, /* VTS H */ 782 {0x380f, 0xaa}, /* VTS L */ 783 {0x3814, 0x01}, /* x odd inc */ 784 {0x3821, 0x46}, /* mirror on, bin off */ 785 {0x382a, 0x01}, /* y odd inc */ 786 {0x3830, 0x06}, 787 {0x3836, 0x01}, 788 {0x3f0a, 0x00}, 789 {0x4001, 0x00}, /* total 256 black column */ 790 {0x4022, 0x0c}, /* Anchor left end H */ 791 {0x4023, 0x60}, /* Anchor left end L */ 792 {0x4025, 0x36}, /* Anchor right start L */ 793 {0x4027, 0x37}, /* Anchor right end L */ 794 {0x402b, 0x08}, /* top black line number */ 795 {0x402f, 0x08}, /* bottom black line number */ 796 {0x4500, 0x58}, 797 {0x4600, 0x01}, 798 {0x4601, 0x97}, 799 {0x382d, 0xff}, 800 {REG_NULL, 0x00}, 801}; 802 803static const struct regval ov8858_global_regs_r2a_4lane[] = { 804 /* 805 * MIPI=720Mbps, SysClk=144Mhz,Dac Clock=360Mhz. 806 * v00_01_00 (05/29/2014) : initial setting 807 * AM19 : 3617 <- 0xC0 808 * AM20 : change FWC_6K_EN to be default 0x3618=0x5a 809 */ 810 {0x0103, 0x01}, /* software reset for OVTATool only */ 811 {0x0103, 0x01}, /* software reset */ 812 {0x0100, 0x00}, /* software standby */ 813 {0x0302, 0x1e}, /* pll1_multi */ 814 {0x0303, 0x00}, /* pll1_divm */ 815 {0x0304, 0x03}, /* pll1_div_mipi */ 816 {0x030e, 0x00}, /* pll2_rdiv */ 817 {0x030f, 0x04}, /* pll2_divsp */ 818 {0x0312, 0x01}, /* pll2_pre_div0, pll2_r_divdac */ 819 {0x031e, 0x0c}, /* pll1_no_lat */ 820 {0x3600, 0x00}, 821 {0x3601, 0x00}, 822 {0x3602, 0x00}, 823 {0x3603, 0x00}, 824 {0x3604, 0x22}, 825 {0x3605, 0x20}, 826 {0x3606, 0x00}, 827 {0x3607, 0x20}, 828 {0x3608, 0x11}, 829 {0x3609, 0x28}, 830 {0x360a, 0x00}, 831 {0x360b, 0x05}, 832 {0x360c, 0xd4}, 833 {0x360d, 0x40}, 834 {0x360e, 0x0c}, 835 {0x360f, 0x20}, 836 {0x3610, 0x07}, 837 {0x3611, 0x20}, 838 {0x3612, 0x88}, 839 {0x3613, 0x80}, 840 {0x3614, 0x58}, 841 {0x3615, 0x00}, 842 {0x3616, 0x4a}, 843 {0x3617, 0x90}, 844 {0x3618, 0x5a}, 845 {0x3619, 0x70}, 846 {0x361a, 0x99}, 847 {0x361b, 0x0a}, 848 {0x361c, 0x07}, 849 {0x361d, 0x00}, 850 {0x361e, 0x00}, 851 {0x361f, 0x00}, 852 {0x3638, 0xff}, 853 {0x3633, 0x0f}, 854 {0x3634, 0x0f}, 855 {0x3635, 0x0f}, 856 {0x3636, 0x12}, 857 {0x3645, 0x13}, 858 {0x3646, 0x83}, 859 {0x364a, 0x07}, 860 {0x3015, 0x01}, 861 {0x3018, 0x72}, /* MIPI 4 lane */ 862 {0x3020, 0x93}, /* Clock switch output normal, pclk_div =/1 */ 863 {0x3022, 0x01}, /* pd_mipi enable when rst_sync */ 864 {0x3031, 0x0a}, /* MIPI 10-bit mode */ 865 {0x3034, 0x00}, 866 {0x3106, 0x01}, /* sclk_div, sclk_pre_div */ 867 {0x3305, 0xf1}, 868 {0x3308, 0x00}, 869 {0x3309, 0x28}, 870 {0x330a, 0x00}, 871 {0x330b, 0x20}, 872 {0x330c, 0x00}, 873 {0x330d, 0x00}, 874 {0x330e, 0x00}, 875 {0x330f, 0x40}, 876 {0x3307, 0x04}, 877 {0x3500, 0x00}, /* exposure H */ 878 {0x3501, 0x4d}, /* exposure M */ 879 {0x3502, 0x40}, /* exposure L */ 880 {0x3503, 0x80}, /* gain delay ?, exposure delay 1 frame, real gain */ 881 {0x3505, 0x80}, /* gain option */ 882 {0x3508, 0x02}, /* gain H */ 883 {0x3509, 0x00}, /* gain L */ 884 {0x350c, 0x00}, /* short gain H */ 885 {0x350d, 0x80}, /* short gain L */ 886 {0x3510, 0x00}, /* short exposure H */ 887 {0x3511, 0x02}, /* short exposure M */ 888 {0x3512, 0x00}, /* short exposure L */ 889 {0x3700, 0x30}, 890 {0x3701, 0x18}, 891 {0x3702, 0x50}, 892 {0x3703, 0x32}, 893 {0x3704, 0x28}, 894 {0x3705, 0x00}, 895 {0x3706, 0x82}, 896 {0x3707, 0x08}, 897 {0x3708, 0x48}, 898 {0x3709, 0x66}, 899 {0x370a, 0x01}, 900 {0x370b, 0x82}, 901 {0x370c, 0x07}, 902 {0x3718, 0x14}, 903 {0x3719, 0x31}, 904 {0x3712, 0x44}, 905 {0x3714, 0x24}, 906 {0x371e, 0x31}, 907 {0x371f, 0x7f}, 908 {0x3720, 0x0a}, 909 {0x3721, 0x0a}, 910 {0x3724, 0x0c}, 911 {0x3725, 0x02}, 912 {0x3726, 0x0c}, 913 {0x3728, 0x0a}, 914 {0x3729, 0x03}, 915 {0x372a, 0x06}, 916 {0x372b, 0xa6}, 917 {0x372c, 0xa6}, 918 {0x372d, 0xa6}, 919 {0x372e, 0x0c}, 920 {0x372f, 0x20}, 921 {0x3730, 0x02}, 922 {0x3731, 0x0c}, 923 {0x3732, 0x28}, 924 {0x3733, 0x10}, 925 {0x3734, 0x40}, 926 {0x3736, 0x30}, 927 {0x373a, 0x0a}, 928 {0x373b, 0x0b}, 929 {0x373c, 0x14}, 930 {0x373e, 0x06}, 931 {0x3750, 0x0a}, 932 {0x3751, 0x0e}, 933 {0x3755, 0x10}, 934 {0x3758, 0x00}, 935 {0x3759, 0x4c}, 936 {0x375a, 0x0c}, 937 {0x375b, 0x26}, 938 {0x375c, 0x20}, 939 {0x375d, 0x04}, 940 {0x375e, 0x00}, 941 {0x375f, 0x28}, 942 {0x3768, 0x22}, 943 {0x3769, 0x44}, 944 {0x376a, 0x44}, 945 {0x3761, 0x00}, 946 {0x3762, 0x00}, 947 {0x3763, 0x00}, 948 {0x3766, 0xff}, 949 {0x376b, 0x00}, 950 {0x3772, 0x46}, 951 {0x3773, 0x04}, 952 {0x3774, 0x2c}, 953 {0x3775, 0x13}, 954 {0x3776, 0x08}, 955 {0x3777, 0x00}, 956 {0x3778, 0x17}, 957 {0x37a0, 0x88}, 958 {0x37a1, 0x7a}, 959 {0x37a2, 0x7a}, 960 {0x37a3, 0x00}, 961 {0x37a4, 0x00}, 962 {0x37a5, 0x00}, 963 {0x37a6, 0x00}, 964 {0x37a7, 0x88}, 965 {0x37a8, 0x98}, 966 {0x37a9, 0x98}, 967 {0x3760, 0x00}, 968 {0x376f, 0x01}, 969 {0x37aa, 0x88}, 970 {0x37ab, 0x5c}, 971 {0x37ac, 0x5c}, 972 {0x37ad, 0x55}, 973 {0x37ae, 0x19}, 974 {0x37af, 0x19}, 975 {0x37b0, 0x00}, 976 {0x37b1, 0x00}, 977 {0x37b2, 0x00}, 978 {0x37b3, 0x84}, 979 {0x37b4, 0x84}, 980 {0x37b5, 0x60}, 981 {0x37b6, 0x00}, 982 {0x37b7, 0x00}, 983 {0x37b8, 0x00}, 984 {0x37b9, 0xff}, 985 {0x3800, 0x00}, /* x start H */ 986 {0x3801, 0x0c}, /* x start L */ 987 {0x3802, 0x00}, /* y start H */ 988 {0x3803, 0x0c}, /* y start L */ 989 {0x3804, 0x0c}, /* x end H */ 990 {0x3805, 0xd3}, /* x end L */ 991 {0x3806, 0x09}, /* y end H */ 992 {0x3807, 0xa3}, /* y end L */ 993 {0x3808, 0x06}, /* x output size H */ 994 {0x3809, 0x60}, /* x output size L */ 995 {0x380a, 0x04}, /* y output size H */ 996 {0x380b, 0xc8}, /* y output size L */ 997 {0x380c, 0x07}, /* HTS H */ 998 {0x380d, 0x88}, /* HTS L */ 999 {0x380e, 0x04}, /* VTS H */ 1000 {0x380f, 0xdc}, /* VTS L */ 1001 {0x3810, 0x00}, /* ISP x win H */ 1002 {0x3811, 0x04}, /* ISP x win L */ 1003 {0x3813, 0x02}, /* ISP y win L */ 1004 {0x3814, 0x03}, /* x odd inc */ 1005 {0x3815, 0x01}, /* x even inc */ 1006 {0x3820, 0x00}, /* vflip off */ 1007 {0x3821, 0x67}, /* mirror on, bin o */ 1008 {0x382a, 0x03}, /* y odd inc */ 1009 {0x382b, 0x01}, /* y even inc */ 1010 {0x3830, 0x08}, 1011 {0x3836, 0x02}, 1012 {0x3837, 0x18}, 1013 {0x3841, 0xff}, /* window auto size enable */ 1014 {0x3846, 0x48}, 1015 {0x3d85, 0x16}, /* OTP power up load data/setting enable */ 1016 {0x3d8c, 0x73}, /* OTP setting start High */ 1017 {0x3d8d, 0xde}, /* OTP setting start Low */ 1018 {0x3f08, 0x10}, 1019 {0x3f0a, 0x00}, 1020 {0x4000, 0xf1}, /* out_range/format_chg/gain/exp_chg trig enable */ 1021 {0x4001, 0x10}, /* total 128 black column */ 1022 {0x4005, 0x10}, /* BLC target L */ 1023 {0x4002, 0x27}, /* value used to limit BLC offset */ 1024 {0x4009, 0x81}, /* final BLC offset limitation enable */ 1025 {0x400b, 0x0c}, /* DCBLC on, DCBLC manual mode on */ 1026 {0x401b, 0x00}, /* zero line R coefficient */ 1027 {0x401d, 0x00}, /* zoro line T coefficient */ 1028 {0x4020, 0x00}, /* Anchor left start H */ 1029 {0x4021, 0x04}, /* Anchor left start L */ 1030 {0x4022, 0x06}, /* Anchor left end H */ 1031 {0x4023, 0x00}, /* Anchor left end L */ 1032 {0x4024, 0x0f}, /* Anchor right start H */ 1033 {0x4025, 0x2a}, /* Anchor right start L */ 1034 {0x4026, 0x0f}, /* Anchor right end H */ 1035 {0x4027, 0x2b}, /* Anchor right end L */ 1036 {0x4028, 0x00}, /* top zero line start */ 1037 {0x4029, 0x02}, /* top zero line number */ 1038 {0x402a, 0x04}, /* top black line start */ 1039 {0x402b, 0x04}, /* top black line number */ 1040 {0x402c, 0x00}, /* bottom zero line start */ 1041 {0x402d, 0x02}, /* bottom zoro line number */ 1042 {0x402e, 0x04}, /* bottom black line start */ 1043 {0x402f, 0x04}, /* bottom black line number */ 1044 {0x401f, 0x00}, /* interpolation x/y disable, Anchor one disable */ 1045 {0x4034, 0x3f}, 1046 {0x403d, 0x04}, /* md_precision_en */ 1047 {0x4300, 0xff}, /* clip max H */ 1048 {0x4301, 0x00}, /* clip min H */ 1049 {0x4302, 0x0f}, /* clip min L, clip max L */ 1050 {0x4316, 0x00}, 1051 {0x4500, 0x58}, 1052 {0x4503, 0x18}, 1053 {0x4600, 0x00}, 1054 {0x4601, 0xcb}, 1055 {0x481f, 0x32}, /* clk prepare min */ 1056 {0x4837, 0x16}, /* global timing */ 1057 {0x4850, 0x10}, /* lane 1 = 1, lane 0 = 0 */ 1058 {0x4851, 0x32}, /* lane 3 = 3, lane 2 = 2 */ 1059 {0x4b00, 0x2a}, 1060 {0x4b0d, 0x00}, 1061 {0x4d00, 0x04}, /* temperature sensor */ 1062 {0x4d01, 0x18}, 1063 {0x4d02, 0xc3}, 1064 {0x4d03, 0xff}, 1065 {0x4d04, 0xff}, 1066 {0x4d05, 0xff}, /* temperature sensor */ 1067 {0x5000, 0xfe}, /* lenc on, slave/master AWB gain/statistics enable */ 1068 {0x5001, 0x01}, /* BLC on */ 1069 {0x5002, 0x08}, /* WBMATCH sensor's gain, H scale/WBMATCH/OTP_DPC off */ 1070 {0x5003, 0x20}, /* DPC_DBC buffer control enable, WB */ 1071 {0x501e, 0x93}, /* enable digital gain */ 1072 {0x5046, 0x12}, 1073 {0x5780, 0x3e}, /* DPC */ 1074 {0x5781, 0x0f}, 1075 {0x5782, 0x44}, 1076 {0x5783, 0x02}, 1077 {0x5784, 0x01}, 1078 {0x5785, 0x00}, 1079 {0x5786, 0x00}, 1080 {0x5787, 0x04}, 1081 {0x5788, 0x02}, 1082 {0x5789, 0x0f}, 1083 {0x578a, 0xfd}, 1084 {0x578b, 0xf5}, 1085 {0x578c, 0xf5}, 1086 {0x578d, 0x03}, 1087 {0x578e, 0x08}, 1088 {0x578f, 0x0c}, 1089 {0x5790, 0x08}, 1090 {0x5791, 0x04}, 1091 {0x5792, 0x00}, 1092 {0x5793, 0x52}, 1093 {0x5794, 0xa3}, /* DPC */ 1094 {0x5871, 0x0d}, /* Lenc */ 1095 {0x5870, 0x18}, 1096 {0x586e, 0x10}, 1097 {0x586f, 0x08}, 1098 {0x58f7, 0x01}, 1099 {0x58f8, 0x3d}, /* Lenc */ 1100 {0x5901, 0x00}, /* H skip off, V skip off */ 1101 {0x5b00, 0x02}, /* OTP DPC start address */ 1102 {0x5b01, 0x10}, /* OTP DPC start address */ 1103 {0x5b02, 0x03}, /* OTP DPC end address */ 1104 {0x5b03, 0xcf}, /* OTP DPC end address */ 1105 {0x5b05, 0x6c}, /* recover method = 2b11 */ 1106 {0x5e00, 0x00}, /* use 0x3ff to test pattern off */ 1107 {0x5e01, 0x41}, /* window cut enable */ 1108 {0x382d, 0x7f}, 1109 {0x4825, 0x3a}, /* lpx_p_min */ 1110 {0x4826, 0x40}, /* hs_prepare_min */ 1111 {0x4808, 0x25}, /* wake up delay in 1/1024 s */ 1112 {0x3763, 0x18}, 1113 {0x3768, 0xcc}, 1114 {0x470b, 0x28}, 1115 {0x4202, 0x00}, 1116 {0x400d, 0x10}, /* BLC offset trigger L */ 1117 {0x4040, 0x04}, /* BLC gain th2 */ 1118 {0x403e, 0x04}, /* BLC gain th1 */ 1119 {0x4041, 0xc6}, /* BLC */ 1120 {0x3007, 0x80}, 1121 {0x400a, 0x01}, 1122 {REG_NULL, 0x00}, 1123}; 1124 1125/* 1126 * Xclk 24Mhz 1127 * max_framerate 60fps 1128 * mipi_datarate per lane 720Mbps 1129 */ 1130static const struct regval ov8858_1632x1224_regs_4lane[] = { 1131 {0x0100, 0x00}, 1132 {0x3501, 0x4d}, /* exposure M */ 1133 {0x3502, 0x40}, /* exposure L */ 1134 {0x3808, 0x06}, /* x output size H */ 1135 {0x3809, 0x60}, /* x output size L */ 1136 {0x380a, 0x04}, /* y output size H */ 1137 {0x380b, 0xc8}, /* y output size L */ 1138 {0x380c, 0x07}, /* HTS H */ 1139 {0x380d, 0x88}, /* HTS L */ 1140 {0x380e, 0x04}, /* VTS H */ 1141 {0x380f, 0xdc}, /* VTS L */ 1142 {0x3814, 0x03}, /* x odd inc */ 1143 {0x3821, 0x67}, /* mirror on, bin on */ 1144 {0x382a, 0x03}, /* y odd inc */ 1145 {0x3830, 0x08}, 1146 {0x3836, 0x02}, 1147 {0x3f0a, 0x00}, 1148 {0x4001, 0x10}, /* total 128 black column */ 1149 {0x4022, 0x06}, /* Anchor left end H */ 1150 {0x4023, 0x00}, /* Anchor left end L */ 1151 {0x4025, 0x2a}, /* Anchor right start L */ 1152 {0x4027, 0x2b}, /* Anchor right end L */ 1153 {0x402b, 0x04}, /* top black line number */ 1154 {0x402f, 0x04}, /* bottom black line number */ 1155 {0x4500, 0x58}, 1156 {0x4600, 0x00}, 1157 {0x4601, 0xcb}, 1158 {0x382d, 0x7f}, 1159 {0x0100, 0x01}, 1160 {REG_NULL, 0x00}, 1161}; 1162 1163/* 1164 * Xclk 24Mhz 1165 * max_framerate 30fps 1166 * mipi_datarate per lane 720Mbps 1167 */ 1168static const struct regval ov8858_3264x2448_regs_4lane[] = { 1169 {0x0100, 0x00}, 1170 {0x3501, 0x9a}, /* exposure M */ 1171 {0x3502, 0x20}, /* exposure L */ 1172 {0x3808, 0x0c}, /* x output size H */ 1173 {0x3809, 0xc0}, /* x output size L */ 1174 {0x380a, 0x09}, /* y output size H */ 1175 {0x380b, 0x90}, /* y output size L */ 1176 {0x380c, 0x07}, /* HTS H */ 1177 {0x380d, 0x94}, /* HTS L */ 1178 {0x380e, 0x09}, /* VTS H */ 1179 {0x380f, 0xaa}, /* VTS L */ 1180 {0x3814, 0x01}, /* x odd inc */ 1181 {0x3821, 0x46}, /* mirror on, bin off */ 1182 {0x382a, 0x01}, /* y odd inc */ 1183 {0x3830, 0x06}, 1184 {0x3836, 0x01}, 1185 {0x3f0a, 0x00}, 1186 {0x4001, 0x00}, /* total 256 black column */ 1187 {0x4022, 0x0c}, /* Anchor left end H */ 1188 {0x4023, 0x60}, /* Anchor left end L */ 1189 {0x4025, 0x36}, /* Anchor right start L */ 1190 {0x4027, 0x37}, /* Anchor right end L */ 1191 {0x402b, 0x08}, /* top black line number */ 1192 {0x402f, 0x08}, /* interpolation x/y disable, Anchor one disable */ 1193 {0x4500, 0x58}, 1194 {0x4600, 0x01}, 1195 {0x4601, 0x97}, 1196 {0x382d, 0xff}, 1197 {REG_NULL, 0x00}, 1198}; 1199 1200static const struct ov8858_mode ov8858_modes[] = { 1201 { 1202 .width = 3264, 1203 .height = 2448, 1204 .exp_def = 2464, 1205 .hts_def = 1940 * 2, 1206 .vts_def = 2472, 1207 .reg_modes = { 1208 .mode_2lanes = ov8858_3264x2448_regs_2lane, 1209 .mode_4lanes = ov8858_3264x2448_regs_4lane, 1210 }, 1211 }, 1212 { 1213 .width = 1632, 1214 .height = 1224, 1215 .exp_def = 1232, 1216 .hts_def = 1928 * 2, 1217 .vts_def = 1244, 1218 .reg_modes = { 1219 .mode_2lanes = ov8858_1632x1224_regs_2lane, 1220 .mode_4lanes = ov8858_1632x1224_regs_4lane, 1221 }, 1222 }, 1223}; 1224 1225static const s64 link_freq_menu_items[] = { 1226 OV8858_LINK_FREQ 1227}; 1228 1229static const char * const ov8858_test_pattern_menu[] = { 1230 "Disabled", 1231 "Vertical Color Bar Type 1", 1232 "Vertical Color Bar Type 2", 1233 "Vertical Color Bar Type 3", 1234 "Vertical Color Bar Type 4" 1235}; 1236 1237/* ---------------------------------------------------------------------------- 1238 * HW access 1239 */ 1240 1241static int ov8858_write(struct ov8858 *ov8858, u32 reg, u32 val, int *err) 1242{ 1243 struct i2c_client *client = v4l2_get_subdevdata(&ov8858->subdev); 1244 unsigned int len = (reg >> OV8858_REG_SIZE_SHIFT) & 3; 1245 u16 addr = reg & OV8858_REG_ADDR_MASK; 1246 u8 buf[6]; 1247 int ret; 1248 1249 if (err && *err) 1250 return *err; 1251 1252 put_unaligned_be16(addr, buf); 1253 put_unaligned_be32(val << (8 * (4 - len)), buf + 2); 1254 1255 ret = i2c_master_send(client, buf, len + 2); 1256 if (ret != len + 2) { 1257 ret = ret < 0 ? ret : -EIO; 1258 if (err) 1259 *err = ret; 1260 1261 dev_err(&client->dev, 1262 "Failed to write reg %u: %d\n", addr, ret); 1263 return ret; 1264 } 1265 1266 return 0; 1267} 1268 1269static int ov8858_write_array(struct ov8858 *ov8858, const struct regval *regs) 1270{ 1271 unsigned int i; 1272 int ret = 0; 1273 1274 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; ++i) { 1275 ov8858_write(ov8858, OV8858_REG_8BIT(regs[i].addr), 1276 regs[i].val, &ret); 1277 } 1278 1279 return ret; 1280} 1281 1282static int ov8858_read(struct ov8858 *ov8858, u32 reg, u32 *val) 1283{ 1284 struct i2c_client *client = v4l2_get_subdevdata(&ov8858->subdev); 1285 __be16 reg_addr_be = cpu_to_be16(reg & OV8858_REG_ADDR_MASK); 1286 unsigned int len = (reg >> OV8858_REG_SIZE_SHIFT) & 3; 1287 struct i2c_msg msgs[2]; 1288 __be32 data_be = 0; 1289 u8 *data_be_p; 1290 int ret; 1291 1292 data_be_p = (u8 *)&data_be; 1293 1294 /* Write register address */ 1295 msgs[0].addr = client->addr; 1296 msgs[0].flags = 0; 1297 msgs[0].len = 2; 1298 msgs[0].buf = (u8 *)®_addr_be; 1299 1300 /* Read data from register */ 1301 msgs[1].addr = client->addr; 1302 msgs[1].flags = I2C_M_RD; 1303 msgs[1].len = len; 1304 msgs[1].buf = &data_be_p[4 - len]; 1305 1306 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 1307 if (ret != ARRAY_SIZE(msgs)) { 1308 ret = ret < 0 ? ret : -EIO; 1309 dev_err(&client->dev, 1310 "Failed to read reg %u: %d\n", reg, ret); 1311 return ret; 1312 } 1313 1314 *val = be32_to_cpu(data_be); 1315 1316 return 0; 1317} 1318 1319/* ---------------------------------------------------------------------------- 1320 * Streaming 1321 */ 1322 1323static int ov8858_start_stream(struct ov8858 *ov8858, 1324 struct v4l2_subdev_state *state) 1325{ 1326 struct v4l2_mbus_framefmt *format; 1327 const struct ov8858_mode *mode; 1328 const struct regval *reg_list; 1329 int ret; 1330 1331 ret = ov8858_write_array(ov8858, ov8858->global_regs); 1332 if (ret) 1333 return ret; 1334 1335 format = v4l2_subdev_state_get_format(state, 0); 1336 mode = v4l2_find_nearest_size(ov8858_modes, ARRAY_SIZE(ov8858_modes), 1337 width, height, format->width, 1338 format->height); 1339 1340 reg_list = ov8858->num_lanes == 4 1341 ? mode->reg_modes.mode_4lanes 1342 : mode->reg_modes.mode_2lanes; 1343 1344 ret = ov8858_write_array(ov8858, reg_list); 1345 if (ret) 1346 return ret; 1347 1348 /* 200 usec max to let PLL stabilize. */ 1349 fsleep(200); 1350 1351 ret = __v4l2_ctrl_handler_setup(&ov8858->ctrl_handler); 1352 if (ret) 1353 return ret; 1354 1355 ret = ov8858_write(ov8858, OV8858_REG_SC_CTRL0100, 1356 OV8858_MODE_STREAMING, NULL); 1357 if (ret) 1358 return ret; 1359 1360 /* t5 (fixed) = 10msec before entering streaming state */ 1361 fsleep(10000); 1362 1363 return 0; 1364} 1365 1366static int ov8858_stop_stream(struct ov8858 *ov8858) 1367{ 1368 return ov8858_write(ov8858, OV8858_REG_SC_CTRL0100, 1369 OV8858_MODE_SW_STANDBY, NULL); 1370} 1371 1372static int ov8858_s_stream(struct v4l2_subdev *sd, int on) 1373{ 1374 struct i2c_client *client = v4l2_get_subdevdata(sd); 1375 struct ov8858 *ov8858 = sd_to_ov8858(sd); 1376 struct v4l2_subdev_state *state; 1377 int ret = 0; 1378 1379 state = v4l2_subdev_lock_and_get_active_state(sd); 1380 1381 if (on) { 1382 ret = pm_runtime_resume_and_get(&client->dev); 1383 if (ret < 0) 1384 goto unlock_and_return; 1385 1386 ret = ov8858_start_stream(ov8858, state); 1387 if (ret) { 1388 dev_err(&client->dev, "Failed to start streaming\n"); 1389 pm_runtime_put_sync(&client->dev); 1390 goto unlock_and_return; 1391 } 1392 } else { 1393 ov8858_stop_stream(ov8858); 1394 pm_runtime_put_autosuspend(&client->dev); 1395 } 1396 1397unlock_and_return: 1398 v4l2_subdev_unlock_state(state); 1399 1400 return ret; 1401} 1402 1403static const struct v4l2_subdev_video_ops ov8858_video_ops = { 1404 .s_stream = ov8858_s_stream, 1405}; 1406 1407/* ---------------------------------------------------------------------------- 1408 * Pad ops 1409 */ 1410 1411static int ov8858_set_fmt(struct v4l2_subdev *sd, 1412 struct v4l2_subdev_state *state, 1413 struct v4l2_subdev_format *fmt) 1414{ 1415 struct ov8858 *ov8858 = sd_to_ov8858(sd); 1416 const struct ov8858_mode *mode; 1417 s64 h_blank, vblank_def; 1418 1419 mode = v4l2_find_nearest_size(ov8858_modes, ARRAY_SIZE(ov8858_modes), 1420 width, height, fmt->format.width, 1421 fmt->format.height); 1422 1423 fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10; 1424 fmt->format.width = mode->width; 1425 fmt->format.height = mode->height; 1426 fmt->format.field = V4L2_FIELD_NONE; 1427 1428 /* Store the format in the current subdev state. */ 1429 *v4l2_subdev_state_get_format(state, 0) = fmt->format; 1430 1431 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 1432 return 0; 1433 1434 /* Adjust control limits when a new mode is applied. */ 1435 h_blank = mode->hts_def - mode->width; 1436 __v4l2_ctrl_modify_range(ov8858->hblank, h_blank, h_blank, 1, 1437 h_blank); 1438 1439 vblank_def = mode->vts_def - mode->height; 1440 __v4l2_ctrl_modify_range(ov8858->vblank, vblank_def, 1441 OV8858_VTS_MAX - mode->height, 1, 1442 vblank_def); 1443 1444 return 0; 1445} 1446 1447static int ov8858_enum_frame_sizes(struct v4l2_subdev *sd, 1448 struct v4l2_subdev_state *state, 1449 struct v4l2_subdev_frame_size_enum *fse) 1450{ 1451 if (fse->index >= ARRAY_SIZE(ov8858_modes)) 1452 return -EINVAL; 1453 1454 if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10) 1455 return -EINVAL; 1456 1457 fse->min_width = ov8858_modes[fse->index].width; 1458 fse->max_width = ov8858_modes[fse->index].width; 1459 fse->max_height = ov8858_modes[fse->index].height; 1460 fse->min_height = ov8858_modes[fse->index].height; 1461 1462 return 0; 1463} 1464 1465static int ov8858_enum_mbus_code(struct v4l2_subdev *sd, 1466 struct v4l2_subdev_state *state, 1467 struct v4l2_subdev_mbus_code_enum *code) 1468{ 1469 if (code->index != 0) 1470 return -EINVAL; 1471 1472 code->code = MEDIA_BUS_FMT_SBGGR10_1X10; 1473 1474 return 0; 1475} 1476 1477static int ov8858_init_state(struct v4l2_subdev *sd, 1478 struct v4l2_subdev_state *sd_state) 1479{ 1480 const struct ov8858_mode *def_mode = &ov8858_modes[0]; 1481 struct v4l2_subdev_format fmt = { 1482 .which = V4L2_SUBDEV_FORMAT_TRY, 1483 .format = { 1484 .width = def_mode->width, 1485 .height = def_mode->height, 1486 }, 1487 }; 1488 1489 ov8858_set_fmt(sd, sd_state, &fmt); 1490 1491 return 0; 1492} 1493 1494static const struct v4l2_subdev_pad_ops ov8858_pad_ops = { 1495 .enum_mbus_code = ov8858_enum_mbus_code, 1496 .enum_frame_size = ov8858_enum_frame_sizes, 1497 .get_fmt = v4l2_subdev_get_fmt, 1498 .set_fmt = ov8858_set_fmt, 1499}; 1500 1501static const struct v4l2_subdev_ops ov8858_subdev_ops = { 1502 .video = &ov8858_video_ops, 1503 .pad = &ov8858_pad_ops, 1504}; 1505 1506static const struct v4l2_subdev_internal_ops ov8858_internal_ops = { 1507 .init_state = ov8858_init_state, 1508}; 1509 1510/* ---------------------------------------------------------------------------- 1511 * Controls handling 1512 */ 1513 1514static int ov8858_enable_test_pattern(struct ov8858 *ov8858, u32 pattern) 1515{ 1516 u32 val; 1517 1518 if (pattern) 1519 val = (pattern - 1) | OV8858_TEST_PATTERN_ENABLE; 1520 else 1521 val = OV8858_TEST_PATTERN_DISABLE; 1522 1523 return ov8858_write(ov8858, OV8858_REG_TEST_PATTERN, val, NULL); 1524} 1525 1526static int ov8858_set_ctrl(struct v4l2_ctrl *ctrl) 1527{ 1528 struct ov8858 *ov8858 = container_of(ctrl->handler, 1529 struct ov8858, ctrl_handler); 1530 1531 struct i2c_client *client = v4l2_get_subdevdata(&ov8858->subdev); 1532 struct v4l2_mbus_framefmt *format; 1533 struct v4l2_subdev_state *state; 1534 u16 digi_gain; 1535 s64 max_exp; 1536 int ret; 1537 1538 /* 1539 * The control handler and the subdev state use the same mutex and the 1540 * mutex is guaranteed to be locked: 1541 * - by the core when s_ctrl is called int the VIDIOC_S_CTRL call path 1542 * - by the driver when s_ctrl is called in the s_stream(1) call path 1543 */ 1544 state = v4l2_subdev_get_locked_active_state(&ov8858->subdev); 1545 format = v4l2_subdev_state_get_format(state, 0); 1546 1547 /* Propagate change of current control to all related controls */ 1548 switch (ctrl->id) { 1549 case V4L2_CID_VBLANK: 1550 /* Update max exposure while meeting expected vblanking */ 1551 max_exp = format->height + ctrl->val - OV8858_EXPOSURE_MARGIN; 1552 __v4l2_ctrl_modify_range(ov8858->exposure, 1553 ov8858->exposure->minimum, max_exp, 1554 ov8858->exposure->step, 1555 ov8858->exposure->default_value); 1556 break; 1557 } 1558 1559 if (!pm_runtime_get_if_in_use(&client->dev)) 1560 return 0; 1561 1562 switch (ctrl->id) { 1563 case V4L2_CID_EXPOSURE: 1564 /* 4 least significant bits of exposure are fractional part */ 1565 ret = ov8858_write(ov8858, OV8858_REG_LONG_EXPO, 1566 ctrl->val << 4, NULL); 1567 break; 1568 case V4L2_CID_ANALOGUE_GAIN: 1569 ret = ov8858_write(ov8858, OV8858_REG_LONG_GAIN, 1570 ctrl->val, NULL); 1571 break; 1572 case V4L2_CID_DIGITAL_GAIN: 1573 /* 1574 * Digital gain is assembled as: 1575 * 0x350a[7:0] = dgain[13:6] 1576 * 0x350b[5:0] = dgain[5:0] 1577 * Reassemble the control value to write it in one go. 1578 */ 1579 digi_gain = (ctrl->val & OV8858_LONG_DIGIGAIN_L_MASK) 1580 | ((ctrl->val & OV8858_LONG_DIGIGAIN_H_MASK) << 1581 OV8858_LONG_DIGIGAIN_H_SHIFT); 1582 ret = ov8858_write(ov8858, OV8858_REG_LONG_DIGIGAIN, 1583 digi_gain, NULL); 1584 break; 1585 case V4L2_CID_VBLANK: 1586 ret = ov8858_write(ov8858, OV8858_REG_VTS, 1587 ctrl->val + format->height, NULL); 1588 break; 1589 case V4L2_CID_TEST_PATTERN: 1590 ret = ov8858_enable_test_pattern(ov8858, ctrl->val); 1591 break; 1592 default: 1593 ret = -EINVAL; 1594 dev_warn(&client->dev, "%s Unhandled id: 0x%x\n", 1595 __func__, ctrl->id); 1596 break; 1597 } 1598 1599 pm_runtime_put(&client->dev); 1600 1601 return ret; 1602} 1603 1604static const struct v4l2_ctrl_ops ov8858_ctrl_ops = { 1605 .s_ctrl = ov8858_set_ctrl, 1606}; 1607 1608/* ---------------------------------------------------------------------------- 1609 * Power Management 1610 */ 1611 1612static int ov8858_power_on(struct ov8858 *ov8858) 1613{ 1614 struct i2c_client *client = v4l2_get_subdevdata(&ov8858->subdev); 1615 struct device *dev = &client->dev; 1616 unsigned long delay_us; 1617 int ret; 1618 1619 if (clk_get_rate(ov8858->xvclk) != OV8858_XVCLK_FREQ) 1620 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n"); 1621 1622 ret = clk_prepare_enable(ov8858->xvclk); 1623 if (ret < 0) { 1624 dev_err(dev, "Failed to enable xvclk\n"); 1625 return ret; 1626 } 1627 1628 ret = regulator_bulk_enable(ARRAY_SIZE(ov8858_supply_names), 1629 ov8858->supplies); 1630 if (ret < 0) { 1631 dev_err(dev, "Failed to enable regulators\n"); 1632 goto disable_clk; 1633 } 1634 1635 /* 1636 * The chip manual only suggests 8192 cycles prior to first SCCB 1637 * transaction, but a double sleep between the release of gpios 1638 * helps with sporadic failures observed at probe time. 1639 */ 1640 delay_us = DIV_ROUND_UP(8192, OV8858_XVCLK_FREQ / 1000 / 1000); 1641 1642 gpiod_set_value_cansleep(ov8858->reset_gpio, 0); 1643 fsleep(delay_us); 1644 gpiod_set_value_cansleep(ov8858->pwdn_gpio, 0); 1645 fsleep(delay_us); 1646 1647 return 0; 1648 1649disable_clk: 1650 clk_disable_unprepare(ov8858->xvclk); 1651 1652 return ret; 1653} 1654 1655static void ov8858_power_off(struct ov8858 *ov8858) 1656{ 1657 gpiod_set_value_cansleep(ov8858->pwdn_gpio, 1); 1658 clk_disable_unprepare(ov8858->xvclk); 1659 gpiod_set_value_cansleep(ov8858->reset_gpio, 1); 1660 1661 regulator_bulk_disable(ARRAY_SIZE(ov8858_supply_names), 1662 ov8858->supplies); 1663} 1664 1665static int ov8858_runtime_resume(struct device *dev) 1666{ 1667 struct i2c_client *client = to_i2c_client(dev); 1668 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1669 struct ov8858 *ov8858 = sd_to_ov8858(sd); 1670 1671 return ov8858_power_on(ov8858); 1672} 1673 1674static int ov8858_runtime_suspend(struct device *dev) 1675{ 1676 struct i2c_client *client = to_i2c_client(dev); 1677 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1678 struct ov8858 *ov8858 = sd_to_ov8858(sd); 1679 1680 ov8858_power_off(ov8858); 1681 1682 return 0; 1683} 1684 1685static const struct dev_pm_ops ov8858_pm_ops = { 1686 SET_RUNTIME_PM_OPS(ov8858_runtime_suspend, 1687 ov8858_runtime_resume, NULL) 1688}; 1689 1690/* ---------------------------------------------------------------------------- 1691 * Probe and initialization 1692 */ 1693 1694static int ov8858_init_ctrls(struct ov8858 *ov8858) 1695{ 1696 struct i2c_client *client = v4l2_get_subdevdata(&ov8858->subdev); 1697 struct v4l2_ctrl_handler *handler = &ov8858->ctrl_handler; 1698 const struct ov8858_mode *mode = &ov8858_modes[0]; 1699 struct v4l2_fwnode_device_properties props; 1700 s64 exposure_max, vblank_def; 1701 unsigned int pixel_rate; 1702 struct v4l2_ctrl *ctrl; 1703 u32 h_blank; 1704 int ret; 1705 1706 ret = v4l2_ctrl_handler_init(handler, 10); 1707 if (ret) 1708 return ret; 1709 1710 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ, 1711 0, 0, link_freq_menu_items); 1712 if (ctrl) 1713 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1714 1715 /* pixel rate = link frequency * 2 * lanes / bpp */ 1716 pixel_rate = OV8858_LINK_FREQ * 2 * ov8858->num_lanes / 10; 1717 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 1718 0, pixel_rate, 1, pixel_rate); 1719 1720 h_blank = mode->hts_def - mode->width; 1721 ov8858->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK, 1722 h_blank, h_blank, 1, h_blank); 1723 if (ov8858->hblank) 1724 ov8858->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1725 1726 vblank_def = mode->vts_def - mode->height; 1727 ov8858->vblank = v4l2_ctrl_new_std(handler, &ov8858_ctrl_ops, 1728 V4L2_CID_VBLANK, vblank_def, 1729 OV8858_VTS_MAX - mode->height, 1730 1, vblank_def); 1731 1732 exposure_max = mode->vts_def - OV8858_EXPOSURE_MARGIN; 1733 ov8858->exposure = v4l2_ctrl_new_std(handler, &ov8858_ctrl_ops, 1734 V4L2_CID_EXPOSURE, 1735 OV8858_EXPOSURE_MIN, 1736 exposure_max, OV8858_EXPOSURE_STEP, 1737 mode->exp_def); 1738 1739 v4l2_ctrl_new_std(handler, &ov8858_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 1740 OV8858_LONG_GAIN_MIN, OV8858_LONG_GAIN_MAX, 1741 OV8858_LONG_GAIN_STEP, OV8858_LONG_GAIN_DEFAULT); 1742 1743 v4l2_ctrl_new_std(handler, &ov8858_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 1744 OV8858_LONG_DIGIGAIN_MIN, OV8858_LONG_DIGIGAIN_MAX, 1745 OV8858_LONG_DIGIGAIN_STEP, 1746 OV8858_LONG_DIGIGAIN_DEFAULT); 1747 1748 v4l2_ctrl_new_std_menu_items(handler, &ov8858_ctrl_ops, 1749 V4L2_CID_TEST_PATTERN, 1750 ARRAY_SIZE(ov8858_test_pattern_menu) - 1, 1751 0, 0, ov8858_test_pattern_menu); 1752 1753 if (handler->error) { 1754 ret = handler->error; 1755 goto err_free_handler; 1756 } 1757 1758 ret = v4l2_fwnode_device_parse(&client->dev, &props); 1759 if (ret) 1760 goto err_free_handler; 1761 1762 ret = v4l2_ctrl_new_fwnode_properties(handler, &ov8858_ctrl_ops, 1763 &props); 1764 if (ret) 1765 goto err_free_handler; 1766 1767 ov8858->subdev.ctrl_handler = handler; 1768 1769 return 0; 1770 1771err_free_handler: 1772 dev_err(&client->dev, "Failed to init controls: %d\n", ret); 1773 v4l2_ctrl_handler_free(handler); 1774 1775 return ret; 1776} 1777 1778static int ov8858_check_sensor_id(struct ov8858 *ov8858) 1779{ 1780 struct i2c_client *client = v4l2_get_subdevdata(&ov8858->subdev); 1781 u32 id = 0; 1782 int ret; 1783 1784 ret = ov8858_read(ov8858, OV8858_REG_CHIP_ID, &id); 1785 if (ret) 1786 return ret; 1787 1788 if (id != OV8858_CHIP_ID) { 1789 dev_err(&client->dev, "Unexpected sensor id 0x%x\n", id); 1790 return -ENODEV; 1791 } 1792 1793 ret = ov8858_read(ov8858, OV8858_REG_SUB_ID, &id); 1794 if (ret) 1795 return ret; 1796 1797 dev_info(&client->dev, "Detected OV8858 sensor, revision 0x%x\n", id); 1798 1799 if (id == OV8858_R2A) { 1800 /* R2A supports 2 and 4 lanes modes. */ 1801 ov8858->global_regs = ov8858->num_lanes == 4 1802 ? ov8858_global_regs_r2a_4lane 1803 : ov8858_global_regs_r2a_2lane; 1804 } else if (ov8858->num_lanes == 2) { 1805 /* 1806 * R1A only supports 2 lanes mode and it's only partially 1807 * supported. 1808 */ 1809 ov8858->global_regs = ov8858_global_regs_r1a; 1810 dev_warn(&client->dev, "R1A may not work well!\n"); 1811 } else { 1812 dev_err(&client->dev, 1813 "Unsupported number of data lanes for R1A revision.\n"); 1814 return -EINVAL; 1815 } 1816 1817 return 0; 1818} 1819 1820static int ov8858_configure_regulators(struct ov8858 *ov8858) 1821{ 1822 struct i2c_client *client = v4l2_get_subdevdata(&ov8858->subdev); 1823 unsigned int i; 1824 1825 for (i = 0; i < ARRAY_SIZE(ov8858_supply_names); i++) 1826 ov8858->supplies[i].supply = ov8858_supply_names[i]; 1827 1828 return devm_regulator_bulk_get(&client->dev, 1829 ARRAY_SIZE(ov8858_supply_names), 1830 ov8858->supplies); 1831} 1832 1833static int ov8858_parse_of(struct ov8858 *ov8858) 1834{ 1835 struct v4l2_fwnode_endpoint vep = { .bus_type = V4L2_MBUS_CSI2_DPHY }; 1836 struct i2c_client *client = v4l2_get_subdevdata(&ov8858->subdev); 1837 struct device *dev = &client->dev; 1838 struct fwnode_handle *endpoint; 1839 int ret; 1840 1841 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL); 1842 if (!endpoint) { 1843 dev_err(dev, "Failed to get endpoint\n"); 1844 return -EINVAL; 1845 } 1846 1847 ret = v4l2_fwnode_endpoint_parse(endpoint, &vep); 1848 fwnode_handle_put(endpoint); 1849 if (ret) { 1850 dev_err(dev, "Failed to parse endpoint: %d\n", ret); 1851 return ret; 1852 } 1853 1854 ov8858->num_lanes = vep.bus.mipi_csi2.num_data_lanes; 1855 switch (ov8858->num_lanes) { 1856 case 4: 1857 case 2: 1858 break; 1859 default: 1860 dev_err(dev, "Unsupported number of data lanes %u\n", 1861 ov8858->num_lanes); 1862 return -EINVAL; 1863 } 1864 1865 return 0; 1866} 1867 1868static int ov8858_probe(struct i2c_client *client) 1869{ 1870 struct device *dev = &client->dev; 1871 struct v4l2_subdev *sd; 1872 struct ov8858 *ov8858; 1873 int ret; 1874 1875 ov8858 = devm_kzalloc(dev, sizeof(*ov8858), GFP_KERNEL); 1876 if (!ov8858) 1877 return -ENOMEM; 1878 1879 ov8858->xvclk = devm_v4l2_sensor_clk_get(dev, "xvclk"); 1880 if (IS_ERR(ov8858->xvclk)) 1881 return dev_err_probe(dev, PTR_ERR(ov8858->xvclk), 1882 "Failed to get xvclk\n"); 1883 1884 ov8858->reset_gpio = devm_gpiod_get_optional(dev, "reset", 1885 GPIOD_OUT_HIGH); 1886 if (IS_ERR(ov8858->reset_gpio)) 1887 return dev_err_probe(dev, PTR_ERR(ov8858->reset_gpio), 1888 "Failed to get reset gpio\n"); 1889 1890 ov8858->pwdn_gpio = devm_gpiod_get_optional(dev, "powerdown", 1891 GPIOD_OUT_HIGH); 1892 if (IS_ERR(ov8858->pwdn_gpio)) 1893 return dev_err_probe(dev, PTR_ERR(ov8858->pwdn_gpio), 1894 "Failed to get powerdown gpio\n"); 1895 1896 v4l2_i2c_subdev_init(&ov8858->subdev, client, &ov8858_subdev_ops); 1897 ov8858->subdev.internal_ops = &ov8858_internal_ops; 1898 1899 ret = ov8858_configure_regulators(ov8858); 1900 if (ret) 1901 return dev_err_probe(dev, ret, "Failed to get regulators\n"); 1902 1903 ret = ov8858_parse_of(ov8858); 1904 if (ret) 1905 return ret; 1906 1907 ret = ov8858_init_ctrls(ov8858); 1908 if (ret) 1909 return ret; 1910 1911 sd = &ov8858->subdev; 1912 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1913 ov8858->pad.flags = MEDIA_PAD_FL_SOURCE; 1914 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; 1915 ret = media_entity_pads_init(&sd->entity, 1, &ov8858->pad); 1916 if (ret < 0) 1917 goto err_free_handler; 1918 1919 sd->state_lock = ov8858->ctrl_handler.lock; 1920 ret = v4l2_subdev_init_finalize(sd); 1921 if (ret < 0) { 1922 dev_err(&client->dev, "Subdev initialization error %d\n", ret); 1923 goto err_clean_entity; 1924 } 1925 1926 ret = ov8858_power_on(ov8858); 1927 if (ret) 1928 goto err_clean_entity; 1929 1930 pm_runtime_set_active(dev); 1931 pm_runtime_get_noresume(dev); 1932 pm_runtime_enable(dev); 1933 1934 ret = ov8858_check_sensor_id(ov8858); 1935 if (ret) 1936 goto err_power_off; 1937 1938 pm_runtime_set_autosuspend_delay(dev, 1000); 1939 pm_runtime_use_autosuspend(dev); 1940 1941 ret = v4l2_async_register_subdev_sensor(sd); 1942 if (ret) { 1943 dev_err(dev, "v4l2 async register subdev failed\n"); 1944 goto err_power_off; 1945 } 1946 1947 pm_runtime_put_autosuspend(dev); 1948 1949 return 0; 1950 1951err_power_off: 1952 pm_runtime_disable(dev); 1953 pm_runtime_put_noidle(dev); 1954 ov8858_power_off(ov8858); 1955err_clean_entity: 1956 media_entity_cleanup(&sd->entity); 1957err_free_handler: 1958 v4l2_ctrl_handler_free(&ov8858->ctrl_handler); 1959 1960 return ret; 1961} 1962 1963static void ov8858_remove(struct i2c_client *client) 1964{ 1965 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1966 struct ov8858 *ov8858 = sd_to_ov8858(sd); 1967 1968 v4l2_async_unregister_subdev(sd); 1969 media_entity_cleanup(&sd->entity); 1970 v4l2_ctrl_handler_free(&ov8858->ctrl_handler); 1971 1972 pm_runtime_disable(&client->dev); 1973 if (!pm_runtime_status_suspended(&client->dev)) 1974 ov8858_power_off(ov8858); 1975 pm_runtime_set_suspended(&client->dev); 1976} 1977 1978static const struct of_device_id ov8858_of_match[] = { 1979 { .compatible = "ovti,ov8858" }, 1980 { /* sentinel */ }, 1981}; 1982MODULE_DEVICE_TABLE(of, ov8858_of_match); 1983 1984static struct i2c_driver ov8858_i2c_driver = { 1985 .driver = { 1986 .name = "ov8858", 1987 .pm = &ov8858_pm_ops, 1988 .of_match_table = ov8858_of_match, 1989 }, 1990 .probe = ov8858_probe, 1991 .remove = ov8858_remove, 1992}; 1993 1994module_i2c_driver(ov8858_i2c_driver); 1995 1996MODULE_DESCRIPTION("OmniVision OV8858 sensor driver"); 1997MODULE_LICENSE("GPL");
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