ov7251.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Driver for the OV7251 camera sensor.
   4 *
   5 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
   6 * Copyright (c) 2017-2018, Linaro Ltd.
   7 */
   8
   9#include <linux/bitops.h>
  10#include <linux/clk.h>
  11#include <linux/delay.h>
  12#include <linux/device.h>
  13#include <linux/gpio/consumer.h>
  14#include <linux/i2c.h>
  15#include <linux/init.h>
  16#include <linux/module.h>
  17#include <linux/mod_devicetable.h>
  18#include <linux/pm_runtime.h>
  19#include <linux/regulator/consumer.h>
  20#include <linux/slab.h>
  21#include <linux/types.h>
  22#include <media/v4l2-ctrls.h>
  23#include <media/v4l2-fwnode.h>
  24#include <media/v4l2-subdev.h>
  25
  26#define OV7251_SC_MODE_SELECT		0x0100
  27#define OV7251_SC_MODE_SELECT_SW_STANDBY	0x0
  28#define OV7251_SC_MODE_SELECT_STREAMING		0x1
  29
  30#define OV7251_CHIP_ID_HIGH		0x300a
  31#define OV7251_CHIP_ID_HIGH_BYTE	0x77
  32#define OV7251_CHIP_ID_LOW		0x300b
  33#define OV7251_CHIP_ID_LOW_BYTE		0x50
  34#define OV7251_SC_GP_IO_IN1		0x3029
  35#define OV7251_AEC_EXPO_0		0x3500
  36#define OV7251_AEC_EXPO_1		0x3501
  37#define OV7251_AEC_EXPO_2		0x3502
  38#define OV7251_AEC_AGC_ADJ_0		0x350a
  39#define OV7251_AEC_AGC_ADJ_1		0x350b
  40#define OV7251_TIMING_FORMAT1		0x3820
  41#define OV7251_TIMING_FORMAT1_VFLIP	BIT(2)
  42#define OV7251_TIMING_FORMAT2		0x3821
  43#define OV7251_TIMING_FORMAT2_MIRROR	BIT(2)
  44#define OV7251_PRE_ISP_00		0x5e00
  45#define OV7251_PRE_ISP_00_TEST_PATTERN	BIT(7)
  46#define OV7251_PLL1_PRE_DIV_REG		0x30b4
  47#define OV7251_PLL1_MULT_REG		0x30b3
  48#define OV7251_PLL1_DIVIDER_REG		0x30b1
  49#define OV7251_PLL1_PIX_DIV_REG		0x30b0
  50#define OV7251_PLL1_MIPI_DIV_REG	0x30b5
  51#define OV7251_PLL2_PRE_DIV_REG		0x3098
  52#define OV7251_PLL2_MULT_REG		0x3099
  53#define OV7251_PLL2_DIVIDER_REG		0x309d
  54#define OV7251_PLL2_SYS_DIV_REG		0x309a
  55#define OV7251_PLL2_ADC_DIV_REG		0x309b
  56
  57#define OV7251_NATIVE_WIDTH		656
  58#define OV7251_NATIVE_HEIGHT		496
  59#define OV7251_ACTIVE_START_LEFT	4
  60#define OV7251_ACTIVE_START_TOP		4
  61#define OV7251_ACTIVE_WIDTH		648
  62#define OV7251_ACTIVE_HEIGHT		488
  63
  64#define OV7251_FIXED_PPL		928
  65#define OV7251_TIMING_VTS_REG		0x380e
  66#define OV7251_TIMING_MIN_VTS		1
  67#define OV7251_TIMING_MAX_VTS		0xffff
  68#define OV7251_INTEGRATION_MARGIN	20
  69
  70struct reg_value {
  71	u16 reg;
  72	u8 val;
  73};
  74
  75struct ov7251_mode_info {
  76	u32 width;
  77	u32 height;
  78	u32 vts;
  79	const struct reg_value *data;
  80	u32 data_size;
  81	u32 pixel_clock;
  82	u32 link_freq;
  83	u16 exposure_max;
  84	u16 exposure_def;
  85	struct v4l2_fract timeperframe;
  86};
  87
  88struct ov7251_pll1_cfg {
  89	unsigned int pre_div;
  90	unsigned int mult;
  91	unsigned int div;
  92	unsigned int pix_div;
  93	unsigned int mipi_div;
  94};
  95
  96struct ov7251_pll2_cfg {
  97	unsigned int pre_div;
  98	unsigned int mult;
  99	unsigned int div;
 100	unsigned int sys_div;
 101	unsigned int adc_div;
 102};
 103
 104/*
 105 * Rubbish ordering, but only PLL1 needs to have a separate configuration per
 106 * link frequency and the array member needs to be last.
 107 */
 108struct ov7251_pll_cfgs {
 109	const struct ov7251_pll2_cfg *pll2;
 110	const struct ov7251_pll1_cfg *pll1[];
 111};
 112
 113enum xclk_rate {
 114	OV7251_19_2_MHZ,
 115	OV7251_24_MHZ,
 116	OV7251_NUM_SUPPORTED_RATES
 117};
 118
 119enum supported_link_freqs {
 120	OV7251_LINK_FREQ_240_MHZ,
 121	OV7251_LINK_FREQ_319_2_MHZ,
 122	OV7251_NUM_SUPPORTED_LINK_FREQS
 123};
 124
 125struct ov7251 {
 126	struct i2c_client *i2c_client;
 127	struct device *dev;
 128	struct v4l2_subdev sd;
 129	struct media_pad pad;
 130	struct v4l2_fwnode_endpoint ep;
 131	struct v4l2_mbus_framefmt fmt;
 132	struct v4l2_rect crop;
 133	struct clk *xclk;
 134	u32 xclk_freq;
 135
 136	struct regulator *io_regulator;
 137	struct regulator *core_regulator;
 138	struct regulator *analog_regulator;
 139
 140	const struct ov7251_pll_cfgs *pll_cfgs;
 141	enum supported_link_freqs link_freq_idx;
 142	const struct ov7251_mode_info *current_mode;
 143
 144	struct v4l2_ctrl_handler ctrls;
 145	struct v4l2_ctrl *pixel_clock;
 146	struct v4l2_ctrl *link_freq;
 147	struct v4l2_ctrl *exposure;
 148	struct v4l2_ctrl *gain;
 149	struct v4l2_ctrl *hblank;
 150	struct v4l2_ctrl *vblank;
 151
 152	/* Cached register values */
 153	u8 aec_pk_manual;
 154	u8 pre_isp_00;
 155	u8 timing_format1;
 156	u8 timing_format2;
 157
 158	struct mutex lock; /* lock to protect power state, ctrls and mode */
 159	bool power_on;
 160
 161	struct gpio_desc *enable_gpio;
 162};
 163
 164static inline struct ov7251 *to_ov7251(struct v4l2_subdev *sd)
 165{
 166	return container_of(sd, struct ov7251, sd);
 167}
 168
 169static const struct ov7251_pll1_cfg ov7251_pll1_cfg_19_2_mhz_240_mhz = {
 170	.pre_div = 0x03,
 171	.mult = 0x4b,
 172	.div = 0x01,
 173	.pix_div = 0x0a,
 174	.mipi_div = 0x05,
 175};
 176
 177static const struct ov7251_pll1_cfg ov7251_pll1_cfg_19_2_mhz_319_2_mhz = {
 178	.pre_div = 0x01,
 179	.mult = 0x85,
 180	.div = 0x04,
 181	.pix_div = 0x0a,
 182	.mipi_div = 0x05,
 183};
 184
 185static const struct ov7251_pll1_cfg ov7251_pll1_cfg_24_mhz_240_mhz = {
 186	.pre_div = 0x03,
 187	.mult = 0x64,
 188	.div = 0x01,
 189	.pix_div = 0x0a,
 190	.mipi_div = 0x05,
 191};
 192
 193static const struct ov7251_pll1_cfg ov7251_pll1_cfg_24_mhz_319_2_mhz = {
 194	.pre_div = 0x05,
 195	.mult = 0x85,
 196	.div = 0x02,
 197	.pix_div = 0x0a,
 198	.mipi_div = 0x05,
 199};
 200
 201static const struct ov7251_pll2_cfg ov7251_pll2_cfg_19_2_mhz = {
 202	.pre_div = 0x04,
 203	.mult = 0x32,
 204	.div = 0x00,
 205	.sys_div = 0x05,
 206	.adc_div = 0x04,
 207};
 208
 209static const struct ov7251_pll2_cfg ov7251_pll2_cfg_24_mhz = {
 210	.pre_div = 0x04,
 211	.mult = 0x28,
 212	.div = 0x00,
 213	.sys_div = 0x05,
 214	.adc_div = 0x04,
 215};
 216
 217static const struct ov7251_pll_cfgs ov7251_pll_cfgs_19_2_mhz = {
 218	.pll2 = &ov7251_pll2_cfg_19_2_mhz,
 219	.pll1 = {
 220		[OV7251_LINK_FREQ_240_MHZ] = &ov7251_pll1_cfg_19_2_mhz_240_mhz,
 221		[OV7251_LINK_FREQ_319_2_MHZ] = &ov7251_pll1_cfg_19_2_mhz_319_2_mhz,
 222	},
 223};
 224
 225static const struct ov7251_pll_cfgs ov7251_pll_cfgs_24_mhz = {
 226	.pll2 = &ov7251_pll2_cfg_24_mhz,
 227	.pll1 = {
 228		[OV7251_LINK_FREQ_240_MHZ] = &ov7251_pll1_cfg_24_mhz_240_mhz,
 229		[OV7251_LINK_FREQ_319_2_MHZ] = &ov7251_pll1_cfg_24_mhz_319_2_mhz,
 230	},
 231};
 232
 233static const struct ov7251_pll_cfgs *ov7251_pll_cfgs[] = {
 234	[OV7251_19_2_MHZ] = &ov7251_pll_cfgs_19_2_mhz,
 235	[OV7251_24_MHZ] = &ov7251_pll_cfgs_24_mhz,
 236};
 237
 238static const struct reg_value ov7251_global_init_setting[] = {
 239	{ 0x0103, 0x01 },
 240	{ 0x303b, 0x02 },
 241};
 242
 243static const struct reg_value ov7251_setting_vga_30fps[] = {
 244	{ 0x3005, 0x00 },
 245	{ 0x3012, 0xc0 },
 246	{ 0x3013, 0xd2 },
 247	{ 0x3014, 0x04 },
 248	{ 0x3016, 0xf0 },
 249	{ 0x3017, 0xf0 },
 250	{ 0x3018, 0xf0 },
 251	{ 0x301a, 0xf0 },
 252	{ 0x301b, 0xf0 },
 253	{ 0x301c, 0xf0 },
 254	{ 0x3023, 0x05 },
 255	{ 0x3037, 0xf0 },
 256	{ 0x3106, 0xda },
 257	{ 0x3503, 0x07 },
 258	{ 0x3509, 0x10 },
 259	{ 0x3600, 0x1c },
 260	{ 0x3602, 0x62 },
 261	{ 0x3620, 0xb7 },
 262	{ 0x3622, 0x04 },
 263	{ 0x3626, 0x21 },
 264	{ 0x3627, 0x30 },
 265	{ 0x3630, 0x44 },
 266	{ 0x3631, 0x35 },
 267	{ 0x3634, 0x60 },
 268	{ 0x3636, 0x00 },
 269	{ 0x3662, 0x01 },
 270	{ 0x3663, 0x70 },
 271	{ 0x3664, 0x50 },
 272	{ 0x3666, 0x0a },
 273	{ 0x3669, 0x1a },
 274	{ 0x366a, 0x00 },
 275	{ 0x366b, 0x50 },
 276	{ 0x3673, 0x01 },
 277	{ 0x3674, 0xff },
 278	{ 0x3675, 0x03 },
 279	{ 0x3705, 0xc1 },
 280	{ 0x3709, 0x40 },
 281	{ 0x373c, 0x08 },
 282	{ 0x3742, 0x00 },
 283	{ 0x3757, 0xb3 },
 284	{ 0x3788, 0x00 },
 285	{ 0x37a8, 0x01 },
 286	{ 0x37a9, 0xc0 },
 287	{ 0x3800, 0x00 },
 288	{ 0x3801, 0x04 },
 289	{ 0x3802, 0x00 },
 290	{ 0x3803, 0x04 },
 291	{ 0x3804, 0x02 },
 292	{ 0x3805, 0x8b },
 293	{ 0x3806, 0x01 },
 294	{ 0x3807, 0xeb },
 295	{ 0x3808, 0x02 }, /* width high */
 296	{ 0x3809, 0x80 }, /* width low */
 297	{ 0x380a, 0x01 }, /* height high */
 298	{ 0x380b, 0xe0 }, /* height low */
 299	{ 0x380c, 0x03 }, /* total horiz timing high */
 300	{ 0x380d, 0xa0 }, /* total horiz timing low */
 301	{ 0x380e, 0x06 }, /* total vertical timing high */
 302	{ 0x380f, 0xbc }, /* total vertical timing low */
 303	{ 0x3810, 0x00 },
 304	{ 0x3811, 0x04 },
 305	{ 0x3812, 0x00 },
 306	{ 0x3813, 0x05 },
 307	{ 0x3814, 0x11 },
 308	{ 0x3815, 0x11 },
 309	{ 0x3820, 0x40 },
 310	{ 0x3821, 0x00 },
 311	{ 0x382f, 0x0e },
 312	{ 0x3832, 0x00 },
 313	{ 0x3833, 0x05 },
 314	{ 0x3834, 0x00 },
 315	{ 0x3835, 0x0c },
 316	{ 0x3837, 0x00 },
 317	{ 0x3b80, 0x00 },
 318	{ 0x3b81, 0xa5 },
 319	{ 0x3b82, 0x10 },
 320	{ 0x3b83, 0x00 },
 321	{ 0x3b84, 0x08 },
 322	{ 0x3b85, 0x00 },
 323	{ 0x3b86, 0x01 },
 324	{ 0x3b87, 0x00 },
 325	{ 0x3b88, 0x00 },
 326	{ 0x3b89, 0x00 },
 327	{ 0x3b8a, 0x00 },
 328	{ 0x3b8b, 0x05 },
 329	{ 0x3b8c, 0x00 },
 330	{ 0x3b8d, 0x00 },
 331	{ 0x3b8e, 0x00 },
 332	{ 0x3b8f, 0x1a },
 333	{ 0x3b94, 0x05 },
 334	{ 0x3b95, 0xf2 },
 335	{ 0x3b96, 0x40 },
 336	{ 0x3c00, 0x89 },
 337	{ 0x3c01, 0x63 },
 338	{ 0x3c02, 0x01 },
 339	{ 0x3c03, 0x00 },
 340	{ 0x3c04, 0x00 },
 341	{ 0x3c05, 0x03 },
 342	{ 0x3c06, 0x00 },
 343	{ 0x3c07, 0x06 },
 344	{ 0x3c0c, 0x01 },
 345	{ 0x3c0d, 0xd0 },
 346	{ 0x3c0e, 0x02 },
 347	{ 0x3c0f, 0x0a },
 348	{ 0x4001, 0x42 },
 349	{ 0x4004, 0x04 },
 350	{ 0x4005, 0x00 },
 351	{ 0x404e, 0x01 },
 352	{ 0x4300, 0xff },
 353	{ 0x4301, 0x00 },
 354	{ 0x4315, 0x00 },
 355	{ 0x4501, 0x48 },
 356	{ 0x4600, 0x00 },
 357	{ 0x4601, 0x4e },
 358	{ 0x4801, 0x0f },
 359	{ 0x4806, 0x0f },
 360	{ 0x4819, 0xaa },
 361	{ 0x4823, 0x3e },
 362	{ 0x4837, 0x19 },
 363	{ 0x4a0d, 0x00 },
 364	{ 0x4a47, 0x7f },
 365	{ 0x4a49, 0xf0 },
 366	{ 0x4a4b, 0x30 },
 367	{ 0x5000, 0x85 },
 368	{ 0x5001, 0x80 },
 369};
 370
 371static const struct reg_value ov7251_setting_vga_60fps[] = {
 372	{ 0x3005, 0x00 },
 373	{ 0x3012, 0xc0 },
 374	{ 0x3013, 0xd2 },
 375	{ 0x3014, 0x04 },
 376	{ 0x3016, 0x10 },
 377	{ 0x3017, 0x00 },
 378	{ 0x3018, 0x00 },
 379	{ 0x301a, 0x00 },
 380	{ 0x301b, 0x00 },
 381	{ 0x301c, 0x00 },
 382	{ 0x3023, 0x05 },
 383	{ 0x3037, 0xf0 },
 384	{ 0x3106, 0xda },
 385	{ 0x3503, 0x07 },
 386	{ 0x3509, 0x10 },
 387	{ 0x3600, 0x1c },
 388	{ 0x3602, 0x62 },
 389	{ 0x3620, 0xb7 },
 390	{ 0x3622, 0x04 },
 391	{ 0x3626, 0x21 },
 392	{ 0x3627, 0x30 },
 393	{ 0x3630, 0x44 },
 394	{ 0x3631, 0x35 },
 395	{ 0x3634, 0x60 },
 396	{ 0x3636, 0x00 },
 397	{ 0x3662, 0x01 },
 398	{ 0x3663, 0x70 },
 399	{ 0x3664, 0x50 },
 400	{ 0x3666, 0x0a },
 401	{ 0x3669, 0x1a },
 402	{ 0x366a, 0x00 },
 403	{ 0x366b, 0x50 },
 404	{ 0x3673, 0x01 },
 405	{ 0x3674, 0xff },
 406	{ 0x3675, 0x03 },
 407	{ 0x3705, 0xc1 },
 408	{ 0x3709, 0x40 },
 409	{ 0x373c, 0x08 },
 410	{ 0x3742, 0x00 },
 411	{ 0x3757, 0xb3 },
 412	{ 0x3788, 0x00 },
 413	{ 0x37a8, 0x01 },
 414	{ 0x37a9, 0xc0 },
 415	{ 0x3800, 0x00 },
 416	{ 0x3801, 0x04 },
 417	{ 0x3802, 0x00 },
 418	{ 0x3803, 0x04 },
 419	{ 0x3804, 0x02 },
 420	{ 0x3805, 0x8b },
 421	{ 0x3806, 0x01 },
 422	{ 0x3807, 0xeb },
 423	{ 0x3808, 0x02 }, /* width high */
 424	{ 0x3809, 0x80 }, /* width low */
 425	{ 0x380a, 0x01 }, /* height high */
 426	{ 0x380b, 0xe0 }, /* height low */
 427	{ 0x380c, 0x03 }, /* total horiz timing high */
 428	{ 0x380d, 0xa0 }, /* total horiz timing low */
 429	{ 0x380e, 0x03 }, /* total vertical timing high */
 430	{ 0x380f, 0x5c }, /* total vertical timing low */
 431	{ 0x3810, 0x00 },
 432	{ 0x3811, 0x04 },
 433	{ 0x3812, 0x00 },
 434	{ 0x3813, 0x05 },
 435	{ 0x3814, 0x11 },
 436	{ 0x3815, 0x11 },
 437	{ 0x3820, 0x40 },
 438	{ 0x3821, 0x00 },
 439	{ 0x382f, 0x0e },
 440	{ 0x3832, 0x00 },
 441	{ 0x3833, 0x05 },
 442	{ 0x3834, 0x00 },
 443	{ 0x3835, 0x0c },
 444	{ 0x3837, 0x00 },
 445	{ 0x3b80, 0x00 },
 446	{ 0x3b81, 0xa5 },
 447	{ 0x3b82, 0x10 },
 448	{ 0x3b83, 0x00 },
 449	{ 0x3b84, 0x08 },
 450	{ 0x3b85, 0x00 },
 451	{ 0x3b86, 0x01 },
 452	{ 0x3b87, 0x00 },
 453	{ 0x3b88, 0x00 },
 454	{ 0x3b89, 0x00 },
 455	{ 0x3b8a, 0x00 },
 456	{ 0x3b8b, 0x05 },
 457	{ 0x3b8c, 0x00 },
 458	{ 0x3b8d, 0x00 },
 459	{ 0x3b8e, 0x00 },
 460	{ 0x3b8f, 0x1a },
 461	{ 0x3b94, 0x05 },
 462	{ 0x3b95, 0xf2 },
 463	{ 0x3b96, 0x40 },
 464	{ 0x3c00, 0x89 },
 465	{ 0x3c01, 0x63 },
 466	{ 0x3c02, 0x01 },
 467	{ 0x3c03, 0x00 },
 468	{ 0x3c04, 0x00 },
 469	{ 0x3c05, 0x03 },
 470	{ 0x3c06, 0x00 },
 471	{ 0x3c07, 0x06 },
 472	{ 0x3c0c, 0x01 },
 473	{ 0x3c0d, 0xd0 },
 474	{ 0x3c0e, 0x02 },
 475	{ 0x3c0f, 0x0a },
 476	{ 0x4001, 0x42 },
 477	{ 0x4004, 0x04 },
 478	{ 0x4005, 0x00 },
 479	{ 0x404e, 0x01 },
 480	{ 0x4300, 0xff },
 481	{ 0x4301, 0x00 },
 482	{ 0x4315, 0x00 },
 483	{ 0x4501, 0x48 },
 484	{ 0x4600, 0x00 },
 485	{ 0x4601, 0x4e },
 486	{ 0x4801, 0x0f },
 487	{ 0x4806, 0x0f },
 488	{ 0x4819, 0xaa },
 489	{ 0x4823, 0x3e },
 490	{ 0x4837, 0x19 },
 491	{ 0x4a0d, 0x00 },
 492	{ 0x4a47, 0x7f },
 493	{ 0x4a49, 0xf0 },
 494	{ 0x4a4b, 0x30 },
 495	{ 0x5000, 0x85 },
 496	{ 0x5001, 0x80 },
 497};
 498
 499static const struct reg_value ov7251_setting_vga_90fps[] = {
 500	{ 0x3005, 0x00 },
 501	{ 0x3012, 0xc0 },
 502	{ 0x3013, 0xd2 },
 503	{ 0x3014, 0x04 },
 504	{ 0x3016, 0x10 },
 505	{ 0x3017, 0x00 },
 506	{ 0x3018, 0x00 },
 507	{ 0x301a, 0x00 },
 508	{ 0x301b, 0x00 },
 509	{ 0x301c, 0x00 },
 510	{ 0x3023, 0x05 },
 511	{ 0x3037, 0xf0 },
 512	{ 0x3106, 0xda },
 513	{ 0x3503, 0x07 },
 514	{ 0x3509, 0x10 },
 515	{ 0x3600, 0x1c },
 516	{ 0x3602, 0x62 },
 517	{ 0x3620, 0xb7 },
 518	{ 0x3622, 0x04 },
 519	{ 0x3626, 0x21 },
 520	{ 0x3627, 0x30 },
 521	{ 0x3630, 0x44 },
 522	{ 0x3631, 0x35 },
 523	{ 0x3634, 0x60 },
 524	{ 0x3636, 0x00 },
 525	{ 0x3662, 0x01 },
 526	{ 0x3663, 0x70 },
 527	{ 0x3664, 0x50 },
 528	{ 0x3666, 0x0a },
 529	{ 0x3669, 0x1a },
 530	{ 0x366a, 0x00 },
 531	{ 0x366b, 0x50 },
 532	{ 0x3673, 0x01 },
 533	{ 0x3674, 0xff },
 534	{ 0x3675, 0x03 },
 535	{ 0x3705, 0xc1 },
 536	{ 0x3709, 0x40 },
 537	{ 0x373c, 0x08 },
 538	{ 0x3742, 0x00 },
 539	{ 0x3757, 0xb3 },
 540	{ 0x3788, 0x00 },
 541	{ 0x37a8, 0x01 },
 542	{ 0x37a9, 0xc0 },
 543	{ 0x3800, 0x00 },
 544	{ 0x3801, 0x04 },
 545	{ 0x3802, 0x00 },
 546	{ 0x3803, 0x04 },
 547	{ 0x3804, 0x02 },
 548	{ 0x3805, 0x8b },
 549	{ 0x3806, 0x01 },
 550	{ 0x3807, 0xeb },
 551	{ 0x3808, 0x02 }, /* width high */
 552	{ 0x3809, 0x80 }, /* width low */
 553	{ 0x380a, 0x01 }, /* height high */
 554	{ 0x380b, 0xe0 }, /* height low */
 555	{ 0x380c, 0x03 }, /* total horiz timing high */
 556	{ 0x380d, 0xa0 }, /* total horiz timing low */
 557	{ 0x380e, 0x02 }, /* total vertical timing high */
 558	{ 0x380f, 0x3c }, /* total vertical timing low */
 559	{ 0x3810, 0x00 },
 560	{ 0x3811, 0x04 },
 561	{ 0x3812, 0x00 },
 562	{ 0x3813, 0x05 },
 563	{ 0x3814, 0x11 },
 564	{ 0x3815, 0x11 },
 565	{ 0x3820, 0x40 },
 566	{ 0x3821, 0x00 },
 567	{ 0x382f, 0x0e },
 568	{ 0x3832, 0x00 },
 569	{ 0x3833, 0x05 },
 570	{ 0x3834, 0x00 },
 571	{ 0x3835, 0x0c },
 572	{ 0x3837, 0x00 },
 573	{ 0x3b80, 0x00 },
 574	{ 0x3b81, 0xa5 },
 575	{ 0x3b82, 0x10 },
 576	{ 0x3b83, 0x00 },
 577	{ 0x3b84, 0x08 },
 578	{ 0x3b85, 0x00 },
 579	{ 0x3b86, 0x01 },
 580	{ 0x3b87, 0x00 },
 581	{ 0x3b88, 0x00 },
 582	{ 0x3b89, 0x00 },
 583	{ 0x3b8a, 0x00 },
 584	{ 0x3b8b, 0x05 },
 585	{ 0x3b8c, 0x00 },
 586	{ 0x3b8d, 0x00 },
 587	{ 0x3b8e, 0x00 },
 588	{ 0x3b8f, 0x1a },
 589	{ 0x3b94, 0x05 },
 590	{ 0x3b95, 0xf2 },
 591	{ 0x3b96, 0x40 },
 592	{ 0x3c00, 0x89 },
 593	{ 0x3c01, 0x63 },
 594	{ 0x3c02, 0x01 },
 595	{ 0x3c03, 0x00 },
 596	{ 0x3c04, 0x00 },
 597	{ 0x3c05, 0x03 },
 598	{ 0x3c06, 0x00 },
 599	{ 0x3c07, 0x06 },
 600	{ 0x3c0c, 0x01 },
 601	{ 0x3c0d, 0xd0 },
 602	{ 0x3c0e, 0x02 },
 603	{ 0x3c0f, 0x0a },
 604	{ 0x4001, 0x42 },
 605	{ 0x4004, 0x04 },
 606	{ 0x4005, 0x00 },
 607	{ 0x404e, 0x01 },
 608	{ 0x4300, 0xff },
 609	{ 0x4301, 0x00 },
 610	{ 0x4315, 0x00 },
 611	{ 0x4501, 0x48 },
 612	{ 0x4600, 0x00 },
 613	{ 0x4601, 0x4e },
 614	{ 0x4801, 0x0f },
 615	{ 0x4806, 0x0f },
 616	{ 0x4819, 0xaa },
 617	{ 0x4823, 0x3e },
 618	{ 0x4837, 0x19 },
 619	{ 0x4a0d, 0x00 },
 620	{ 0x4a47, 0x7f },
 621	{ 0x4a49, 0xf0 },
 622	{ 0x4a4b, 0x30 },
 623	{ 0x5000, 0x85 },
 624	{ 0x5001, 0x80 },
 625};
 626
 627static const unsigned long supported_xclk_rates[] = {
 628	[OV7251_19_2_MHZ] = 19200000,
 629	[OV7251_24_MHZ] = 24000000,
 630};
 631
 632static const s64 link_freq[] = {
 633	[OV7251_LINK_FREQ_240_MHZ] = 240000000,
 634	[OV7251_LINK_FREQ_319_2_MHZ] = 319200000,
 635};
 636
 637static const s64 pixel_rates[] = {
 638	[OV7251_LINK_FREQ_240_MHZ] = 48000000,
 639	[OV7251_LINK_FREQ_319_2_MHZ] = 63840000,
 640};
 641
 642static const struct ov7251_mode_info ov7251_mode_info_data[] = {
 643	{
 644		.width = 640,
 645		.height = 480,
 646		.vts = 1724,
 647		.data = ov7251_setting_vga_30fps,
 648		.data_size = ARRAY_SIZE(ov7251_setting_vga_30fps),
 649		.exposure_max = 1704,
 650		.exposure_def = 504,
 651		.timeperframe = {
 652			.numerator = 100,
 653			.denominator = 3000
 654		}
 655	},
 656	{
 657		.width = 640,
 658		.height = 480,
 659		.vts = 860,
 660		.data = ov7251_setting_vga_60fps,
 661		.data_size = ARRAY_SIZE(ov7251_setting_vga_60fps),
 662		.exposure_max = 840,
 663		.exposure_def = 504,
 664		.timeperframe = {
 665			.numerator = 100,
 666			.denominator = 6014
 667		}
 668	},
 669	{
 670		.width = 640,
 671		.height = 480,
 672		.vts = 572,
 673		.data = ov7251_setting_vga_90fps,
 674		.data_size = ARRAY_SIZE(ov7251_setting_vga_90fps),
 675		.exposure_max = 552,
 676		.exposure_def = 504,
 677		.timeperframe = {
 678			.numerator = 100,
 679			.denominator = 9043
 680		}
 681	},
 682};
 683
 684static int ov7251_regulators_enable(struct ov7251 *ov7251)
 685{
 686	int ret;
 687
 688	/* OV7251 power up sequence requires core regulator
 689	 * to be enabled not earlier than io regulator
 690	 */
 691
 692	ret = regulator_enable(ov7251->io_regulator);
 693	if (ret < 0) {
 694		dev_err(ov7251->dev, "set io voltage failed\n");
 695		return ret;
 696	}
 697
 698	ret = regulator_enable(ov7251->analog_regulator);
 699	if (ret) {
 700		dev_err(ov7251->dev, "set analog voltage failed\n");
 701		goto err_disable_io;
 702	}
 703
 704	ret = regulator_enable(ov7251->core_regulator);
 705	if (ret) {
 706		dev_err(ov7251->dev, "set core voltage failed\n");
 707		goto err_disable_analog;
 708	}
 709
 710	return 0;
 711
 712err_disable_analog:
 713	regulator_disable(ov7251->analog_regulator);
 714
 715err_disable_io:
 716	regulator_disable(ov7251->io_regulator);
 717
 718	return ret;
 719}
 720
 721static void ov7251_regulators_disable(struct ov7251 *ov7251)
 722{
 723	int ret;
 724
 725	ret = regulator_disable(ov7251->core_regulator);
 726	if (ret < 0)
 727		dev_err(ov7251->dev, "core regulator disable failed\n");
 728
 729	ret = regulator_disable(ov7251->analog_regulator);
 730	if (ret < 0)
 731		dev_err(ov7251->dev, "analog regulator disable failed\n");
 732
 733	ret = regulator_disable(ov7251->io_regulator);
 734	if (ret < 0)
 735		dev_err(ov7251->dev, "io regulator disable failed\n");
 736}
 737
 738static int ov7251_write_reg(struct ov7251 *ov7251, u16 reg, u8 val)
 739{
 740	u8 regbuf[3];
 741	int ret;
 742
 743	regbuf[0] = reg >> 8;
 744	regbuf[1] = reg & 0xff;
 745	regbuf[2] = val;
 746
 747	ret = i2c_master_send(ov7251->i2c_client, regbuf, 3);
 748	if (ret < 0) {
 749		dev_err(ov7251->dev, "%s: write reg error %d: reg=%x, val=%x\n",
 750			__func__, ret, reg, val);
 751		return ret;
 752	}
 753
 754	return 0;
 755}
 756
 757static int ov7251_write_seq_regs(struct ov7251 *ov7251, u16 reg, u8 *val,
 758				 u8 num)
 759{
 760	u8 regbuf[5];
 761	u8 nregbuf = sizeof(reg) + num * sizeof(*val);
 762	int ret = 0;
 763
 764	if (nregbuf > sizeof(regbuf))
 765		return -EINVAL;
 766
 767	regbuf[0] = reg >> 8;
 768	regbuf[1] = reg & 0xff;
 769
 770	memcpy(regbuf + 2, val, num);
 771
 772	ret = i2c_master_send(ov7251->i2c_client, regbuf, nregbuf);
 773	if (ret < 0) {
 774		dev_err(ov7251->dev,
 775			"%s: write seq regs error %d: first reg=%x\n",
 776			__func__, ret, reg);
 777		return ret;
 778	}
 779
 780	return 0;
 781}
 782
 783static int ov7251_read_reg(struct ov7251 *ov7251, u16 reg, u8 *val)
 784{
 785	u8 regbuf[2];
 786	int ret;
 787
 788	regbuf[0] = reg >> 8;
 789	regbuf[1] = reg & 0xff;
 790
 791	ret = i2c_master_send(ov7251->i2c_client, regbuf, 2);
 792	if (ret < 0) {
 793		dev_err(ov7251->dev, "%s: write reg error %d: reg=%x\n",
 794			__func__, ret, reg);
 795		return ret;
 796	}
 797
 798	ret = i2c_master_recv(ov7251->i2c_client, val, 1);
 799	if (ret < 0) {
 800		dev_err(ov7251->dev, "%s: read reg error %d: reg=%x\n",
 801			__func__, ret, reg);
 802		return ret;
 803	}
 804
 805	return 0;
 806}
 807
 808static int ov7251_pll_configure(struct ov7251 *ov7251)
 809{
 810	const struct ov7251_pll_cfgs *configs;
 811	int ret;
 812
 813	configs = ov7251->pll_cfgs;
 814
 815	ret = ov7251_write_reg(ov7251, OV7251_PLL1_PRE_DIV_REG,
 816			       configs->pll1[ov7251->link_freq_idx]->pre_div);
 817	if (ret < 0)
 818		return ret;
 819
 820	ret = ov7251_write_reg(ov7251, OV7251_PLL1_MULT_REG,
 821			       configs->pll1[ov7251->link_freq_idx]->mult);
 822	if (ret < 0)
 823		return ret;
 824	ret = ov7251_write_reg(ov7251, OV7251_PLL1_DIVIDER_REG,
 825			       configs->pll1[ov7251->link_freq_idx]->div);
 826	if (ret < 0)
 827		return ret;
 828
 829	ret = ov7251_write_reg(ov7251, OV7251_PLL1_PIX_DIV_REG,
 830			       configs->pll1[ov7251->link_freq_idx]->pix_div);
 831	if (ret < 0)
 832		return ret;
 833
 834	ret = ov7251_write_reg(ov7251, OV7251_PLL1_MIPI_DIV_REG,
 835			       configs->pll1[ov7251->link_freq_idx]->mipi_div);
 836	if (ret < 0)
 837		return ret;
 838
 839	ret = ov7251_write_reg(ov7251, OV7251_PLL2_PRE_DIV_REG,
 840			       configs->pll2->pre_div);
 841	if (ret < 0)
 842		return ret;
 843
 844	ret = ov7251_write_reg(ov7251, OV7251_PLL2_MULT_REG,
 845			       configs->pll2->mult);
 846	if (ret < 0)
 847		return ret;
 848
 849	ret = ov7251_write_reg(ov7251, OV7251_PLL2_DIVIDER_REG,
 850			       configs->pll2->div);
 851	if (ret < 0)
 852		return ret;
 853
 854	ret = ov7251_write_reg(ov7251, OV7251_PLL2_SYS_DIV_REG,
 855			       configs->pll2->sys_div);
 856	if (ret < 0)
 857		return ret;
 858
 859	ret = ov7251_write_reg(ov7251, OV7251_PLL2_ADC_DIV_REG,
 860			       configs->pll2->adc_div);
 861
 862	return ret;
 863}
 864
 865static int ov7251_set_exposure(struct ov7251 *ov7251, s32 exposure)
 866{
 867	u16 reg;
 868	u8 val[3];
 869
 870	reg = OV7251_AEC_EXPO_0;
 871	val[0] = (exposure & 0xf000) >> 12; /* goes to OV7251_AEC_EXPO_0 */
 872	val[1] = (exposure & 0x0ff0) >> 4;  /* goes to OV7251_AEC_EXPO_1 */
 873	val[2] = (exposure & 0x000f) << 4;  /* goes to OV7251_AEC_EXPO_2 */
 874
 875	return ov7251_write_seq_regs(ov7251, reg, val, 3);
 876}
 877
 878static int ov7251_set_gain(struct ov7251 *ov7251, s32 gain)
 879{
 880	u16 reg;
 881	u8 val[2];
 882
 883	reg = OV7251_AEC_AGC_ADJ_0;
 884	val[0] = (gain & 0x0300) >> 8; /* goes to OV7251_AEC_AGC_ADJ_0 */
 885	val[1] = gain & 0xff;          /* goes to OV7251_AEC_AGC_ADJ_1 */
 886
 887	return ov7251_write_seq_regs(ov7251, reg, val, 2);
 888}
 889
 890static int ov7251_set_register_array(struct ov7251 *ov7251,
 891				     const struct reg_value *settings,
 892				     unsigned int num_settings)
 893{
 894	unsigned int i;
 895	int ret;
 896
 897	for (i = 0; i < num_settings; ++i, ++settings) {
 898		ret = ov7251_write_reg(ov7251, settings->reg, settings->val);
 899		if (ret < 0)
 900			return ret;
 901	}
 902
 903	return 0;
 904}
 905
 906static int ov7251_set_power_on(struct device *dev)
 907{
 908	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
 909	struct v4l2_subdev *sd = i2c_get_clientdata(client);
 910	struct ov7251 *ov7251 = to_ov7251(sd);
 911	int ret;
 912	u32 wait_us;
 913
 914	ret = ov7251_regulators_enable(ov7251);
 915	if (ret < 0)
 916		return ret;
 917
 918	ret = clk_prepare_enable(ov7251->xclk);
 919	if (ret < 0) {
 920		dev_err(ov7251->dev, "clk prepare enable failed\n");
 921		ov7251_regulators_disable(ov7251);
 922		return ret;
 923	}
 924
 925	usleep_range(1000, 1100);
 926
 927	gpiod_set_value_cansleep(ov7251->enable_gpio, 1);
 928
 929	/* wait at least 65536 external clock cycles */
 930	wait_us = DIV_ROUND_UP(65536 * 1000,
 931			       DIV_ROUND_UP(ov7251->xclk_freq, 1000));
 932	usleep_range(wait_us, wait_us + 1000);
 933
 934	ret = ov7251_set_register_array(ov7251,
 935					ov7251_global_init_setting,
 936					ARRAY_SIZE(ov7251_global_init_setting));
 937	if (ret < 0) {
 938		dev_err(ov7251->dev, "error during global init\n");
 939		gpiod_set_value_cansleep(ov7251->enable_gpio, 0);
 940		clk_disable_unprepare(ov7251->xclk);
 941		ov7251_regulators_disable(ov7251);
 942		return ret;
 943	}
 944
 945	return ret;
 946}
 947
 948static int ov7251_set_power_off(struct device *dev)
 949{
 950	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
 951	struct v4l2_subdev *sd = i2c_get_clientdata(client);
 952	struct ov7251 *ov7251 = to_ov7251(sd);
 953
 954	clk_disable_unprepare(ov7251->xclk);
 955	gpiod_set_value_cansleep(ov7251->enable_gpio, 0);
 956	ov7251_regulators_disable(ov7251);
 957
 958	return 0;
 959}
 960
 961static int ov7251_set_hflip(struct ov7251 *ov7251, s32 value)
 962{
 963	u8 val = ov7251->timing_format2;
 964	int ret;
 965
 966	if (value)
 967		val |= OV7251_TIMING_FORMAT2_MIRROR;
 968	else
 969		val &= ~OV7251_TIMING_FORMAT2_MIRROR;
 970
 971	ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT2, val);
 972	if (!ret)
 973		ov7251->timing_format2 = val;
 974
 975	return ret;
 976}
 977
 978static int ov7251_set_vflip(struct ov7251 *ov7251, s32 value)
 979{
 980	u8 val = ov7251->timing_format1;
 981	int ret;
 982
 983	if (value)
 984		val |= OV7251_TIMING_FORMAT1_VFLIP;
 985	else
 986		val &= ~OV7251_TIMING_FORMAT1_VFLIP;
 987
 988	ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT1, val);
 989	if (!ret)
 990		ov7251->timing_format1 = val;
 991
 992	return ret;
 993}
 994
 995static int ov7251_set_test_pattern(struct ov7251 *ov7251, s32 value)
 996{
 997	u8 val = ov7251->pre_isp_00;
 998	int ret;
 999
1000	if (value)
1001		val |= OV7251_PRE_ISP_00_TEST_PATTERN;
1002	else
1003		val &= ~OV7251_PRE_ISP_00_TEST_PATTERN;
1004
1005	ret = ov7251_write_reg(ov7251, OV7251_PRE_ISP_00, val);
1006	if (!ret)
1007		ov7251->pre_isp_00 = val;
1008
1009	return ret;
1010}
1011
1012static const char * const ov7251_test_pattern_menu[] = {
1013	"Disabled",
1014	"Vertical Pattern Bars",
1015};
1016
1017static int ov7251_vts_configure(struct ov7251 *ov7251, s32 vblank)
1018{
1019	u8 vts[2];
1020
1021	vts[0] = ((ov7251->current_mode->height + vblank) & 0xff00) >> 8;
1022	vts[1] = ((ov7251->current_mode->height + vblank) & 0x00ff);
1023
1024	return ov7251_write_seq_regs(ov7251, OV7251_TIMING_VTS_REG, vts, 2);
1025}
1026
1027static int ov7251_s_ctrl(struct v4l2_ctrl *ctrl)
1028{
1029	struct ov7251 *ov7251 = container_of(ctrl->handler,
1030					     struct ov7251, ctrls);
1031	int ret;
1032
1033	/* If VBLANK is altered we need to update exposure to compensate */
1034	if (ctrl->id == V4L2_CID_VBLANK) {
1035		int exposure_max;
1036
1037		exposure_max = ov7251->current_mode->height + ctrl->val -
1038			       OV7251_INTEGRATION_MARGIN;
1039		__v4l2_ctrl_modify_range(ov7251->exposure,
1040					 ov7251->exposure->minimum,
1041					 exposure_max,
1042					 ov7251->exposure->step,
1043					 min(ov7251->exposure->val,
1044					     exposure_max));
1045	}
1046
1047	/* v4l2_ctrl_lock() locks our mutex */
1048
1049	if (!pm_runtime_get_if_in_use(ov7251->dev))
1050		return 0;
1051
1052	switch (ctrl->id) {
1053	case V4L2_CID_EXPOSURE:
1054		ret = ov7251_set_exposure(ov7251, ctrl->val);
1055		break;
1056	case V4L2_CID_GAIN:
1057		ret = ov7251_set_gain(ov7251, ctrl->val);
1058		break;
1059	case V4L2_CID_TEST_PATTERN:
1060		ret = ov7251_set_test_pattern(ov7251, ctrl->val);
1061		break;
1062	case V4L2_CID_HFLIP:
1063		ret = ov7251_set_hflip(ov7251, ctrl->val);
1064		break;
1065	case V4L2_CID_VFLIP:
1066		ret = ov7251_set_vflip(ov7251, ctrl->val);
1067		break;
1068	case V4L2_CID_VBLANK:
1069		ret = ov7251_vts_configure(ov7251, ctrl->val);
1070		break;
1071	default:
1072		ret = -EINVAL;
1073		break;
1074	}
1075
1076	pm_runtime_put(ov7251->dev);
1077
1078	return ret;
1079}
1080
1081static const struct v4l2_ctrl_ops ov7251_ctrl_ops = {
1082	.s_ctrl = ov7251_s_ctrl,
1083};
1084
1085static int ov7251_enum_mbus_code(struct v4l2_subdev *sd,
1086				 struct v4l2_subdev_state *sd_state,
1087				 struct v4l2_subdev_mbus_code_enum *code)
1088{
1089	if (code->index > 0)
1090		return -EINVAL;
1091
1092	code->code = MEDIA_BUS_FMT_Y10_1X10;
1093
1094	return 0;
1095}
1096
1097static int ov7251_enum_frame_size(struct v4l2_subdev *subdev,
1098				  struct v4l2_subdev_state *sd_state,
1099				  struct v4l2_subdev_frame_size_enum *fse)
1100{
1101	if (fse->code != MEDIA_BUS_FMT_Y10_1X10)
1102		return -EINVAL;
1103
1104	if (fse->index >= ARRAY_SIZE(ov7251_mode_info_data))
1105		return -EINVAL;
1106
1107	fse->min_width = ov7251_mode_info_data[fse->index].width;
1108	fse->max_width = ov7251_mode_info_data[fse->index].width;
1109	fse->min_height = ov7251_mode_info_data[fse->index].height;
1110	fse->max_height = ov7251_mode_info_data[fse->index].height;
1111
1112	return 0;
1113}
1114
1115static int ov7251_enum_frame_ival(struct v4l2_subdev *subdev,
1116				  struct v4l2_subdev_state *sd_state,
1117				  struct v4l2_subdev_frame_interval_enum *fie)
1118{
1119	unsigned int index = fie->index;
1120	unsigned int i;
1121
1122	for (i = 0; i < ARRAY_SIZE(ov7251_mode_info_data); i++) {
1123		if (fie->width != ov7251_mode_info_data[i].width ||
1124		    fie->height != ov7251_mode_info_data[i].height)
1125			continue;
1126
1127		if (index-- == 0) {
1128			fie->interval = ov7251_mode_info_data[i].timeperframe;
1129			return 0;
1130		}
1131	}
1132
1133	return -EINVAL;
1134}
1135
1136static struct v4l2_mbus_framefmt *
1137__ov7251_get_pad_format(struct ov7251 *ov7251,
1138			struct v4l2_subdev_state *sd_state,
1139			unsigned int pad,
1140			enum v4l2_subdev_format_whence which)
1141{
1142	switch (which) {
1143	case V4L2_SUBDEV_FORMAT_TRY:
1144		return v4l2_subdev_state_get_format(sd_state, pad);
1145	case V4L2_SUBDEV_FORMAT_ACTIVE:
1146		return &ov7251->fmt;
1147	default:
1148		return NULL;
1149	}
1150}
1151
1152static int ov7251_get_format(struct v4l2_subdev *sd,
1153			     struct v4l2_subdev_state *sd_state,
1154			     struct v4l2_subdev_format *format)
1155{
1156	struct ov7251 *ov7251 = to_ov7251(sd);
1157
1158	mutex_lock(&ov7251->lock);
1159	format->format = *__ov7251_get_pad_format(ov7251, sd_state,
1160						  format->pad,
1161						  format->which);
1162	mutex_unlock(&ov7251->lock);
1163
1164	return 0;
1165}
1166
1167static struct v4l2_rect *
1168__ov7251_get_pad_crop(struct ov7251 *ov7251,
1169		      struct v4l2_subdev_state *sd_state,
1170		      unsigned int pad, enum v4l2_subdev_format_whence which)
1171{
1172	switch (which) {
1173	case V4L2_SUBDEV_FORMAT_TRY:
1174		return v4l2_subdev_state_get_crop(sd_state, pad);
1175	case V4L2_SUBDEV_FORMAT_ACTIVE:
1176		return &ov7251->crop;
1177	default:
1178		return NULL;
1179	}
1180}
1181
1182static inline u32 avg_fps(const struct v4l2_fract *t)
1183{
1184	return (t->denominator + (t->numerator >> 1)) / t->numerator;
1185}
1186
1187static const struct ov7251_mode_info *
1188ov7251_find_mode_by_ival(struct ov7251 *ov7251, struct v4l2_fract *timeperframe)
1189{
1190	const struct ov7251_mode_info *mode = ov7251->current_mode;
1191	unsigned int fps_req = avg_fps(timeperframe);
1192	unsigned int max_dist_match = (unsigned int) -1;
1193	unsigned int i, n = 0;
1194
1195	for (i = 0; i < ARRAY_SIZE(ov7251_mode_info_data); i++) {
1196		unsigned int dist;
1197		unsigned int fps_tmp;
1198
1199		if (mode->width != ov7251_mode_info_data[i].width ||
1200		    mode->height != ov7251_mode_info_data[i].height)
1201			continue;
1202
1203		fps_tmp = avg_fps(&ov7251_mode_info_data[i].timeperframe);
1204
1205		dist = abs(fps_req - fps_tmp);
1206
1207		if (dist < max_dist_match) {
1208			n = i;
1209			max_dist_match = dist;
1210		}
1211	}
1212
1213	return &ov7251_mode_info_data[n];
1214}
1215
1216static int ov7251_set_format(struct v4l2_subdev *sd,
1217			     struct v4l2_subdev_state *sd_state,
1218			     struct v4l2_subdev_format *format)
1219{
1220	struct ov7251 *ov7251 = to_ov7251(sd);
1221	struct v4l2_mbus_framefmt *__format;
1222	int vblank_max, vblank_def;
1223	struct v4l2_rect *__crop;
1224	const struct ov7251_mode_info *new_mode;
1225	int ret = 0;
1226
1227	mutex_lock(&ov7251->lock);
1228
1229	__crop = __ov7251_get_pad_crop(ov7251, sd_state, format->pad,
1230				       format->which);
1231
1232	new_mode = v4l2_find_nearest_size(ov7251_mode_info_data,
1233				ARRAY_SIZE(ov7251_mode_info_data),
1234				width, height,
1235				format->format.width, format->format.height);
1236
1237	__crop->width = new_mode->width;
1238	__crop->height = new_mode->height;
1239
1240	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
1241		ret = __v4l2_ctrl_modify_range(ov7251->exposure,
1242					       1, new_mode->exposure_max,
1243					       1, new_mode->exposure_def);
1244		if (ret < 0)
1245			goto exit;
1246
1247		ret = __v4l2_ctrl_s_ctrl(ov7251->exposure,
1248					 new_mode->exposure_def);
1249		if (ret < 0)
1250			goto exit;
1251
1252		ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16);
1253		if (ret < 0)
1254			goto exit;
1255
1256		vblank_max = OV7251_TIMING_MAX_VTS - new_mode->height;
1257		vblank_def = new_mode->vts - new_mode->height;
1258		ret = __v4l2_ctrl_modify_range(ov7251->vblank,
1259					       OV7251_TIMING_MIN_VTS,
1260					       vblank_max, 1, vblank_def);
1261		if (ret < 0)
1262			goto exit;
1263
1264		ov7251->current_mode = new_mode;
1265	}
1266
1267	__format = __ov7251_get_pad_format(ov7251, sd_state, format->pad,
1268					   format->which);
1269	__format->width = __crop->width;
1270	__format->height = __crop->height;
1271	__format->code = MEDIA_BUS_FMT_Y10_1X10;
1272	__format->field = V4L2_FIELD_NONE;
1273	__format->colorspace = V4L2_COLORSPACE_SRGB;
1274	__format->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(__format->colorspace);
1275	__format->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,
1276				__format->colorspace, __format->ycbcr_enc);
1277	__format->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(__format->colorspace);
1278
1279	format->format = *__format;
1280
1281exit:
1282	mutex_unlock(&ov7251->lock);
1283
1284	return ret;
1285}
1286
1287static int ov7251_init_state(struct v4l2_subdev *subdev,
1288			     struct v4l2_subdev_state *sd_state)
1289{
1290	struct v4l2_subdev_format fmt = {
1291		.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY
1292		: V4L2_SUBDEV_FORMAT_ACTIVE,
1293		.format = {
1294			.width = 640,
1295			.height = 480
1296		}
1297	};
1298
1299	ov7251_set_format(subdev, sd_state, &fmt);
1300
1301	return 0;
1302}
1303
1304static int ov7251_get_selection(struct v4l2_subdev *sd,
1305				struct v4l2_subdev_state *sd_state,
1306				struct v4l2_subdev_selection *sel)
1307{
1308	struct ov7251 *ov7251 = to_ov7251(sd);
1309
1310	switch (sel->target) {
1311	case V4L2_SEL_TGT_CROP_DEFAULT:
1312	case V4L2_SEL_TGT_CROP:
1313	mutex_lock(&ov7251->lock);
1314		sel->r = *__ov7251_get_pad_crop(ov7251, sd_state, sel->pad,
1315						sel->which);
1316		mutex_unlock(&ov7251->lock);
1317		break;
1318	case V4L2_SEL_TGT_NATIVE_SIZE:
1319		sel->r.top = 0;
1320		sel->r.left = 0;
1321		sel->r.width = OV7251_NATIVE_WIDTH;
1322		sel->r.height = OV7251_NATIVE_HEIGHT;
1323		break;
1324	case V4L2_SEL_TGT_CROP_BOUNDS:
1325		sel->r.top = OV7251_ACTIVE_START_TOP;
1326		sel->r.left = OV7251_ACTIVE_START_LEFT;
1327		sel->r.width = OV7251_ACTIVE_WIDTH;
1328		sel->r.height = OV7251_ACTIVE_HEIGHT;
1329		break;
1330	default:
1331		return -EINVAL;
1332	}
1333
1334	return 0;
1335}
1336
1337static int ov7251_s_stream(struct v4l2_subdev *subdev, int enable)
1338{
1339	struct ov7251 *ov7251 = to_ov7251(subdev);
1340	int ret;
1341
1342	mutex_lock(&ov7251->lock);
1343
1344	if (enable) {
1345		ret = pm_runtime_resume_and_get(ov7251->dev);
1346		if (ret) {
1347			mutex_unlock(&ov7251->lock);
1348			return ret;
1349		}
1350
1351		ret = ov7251_pll_configure(ov7251);
1352		if (ret) {
1353			dev_err(ov7251->dev, "error configuring PLLs\n");
1354			goto err_power_down;
1355		}
1356
1357		ret = ov7251_set_register_array(ov7251,
1358					ov7251->current_mode->data,
1359					ov7251->current_mode->data_size);
1360		if (ret < 0) {
1361			dev_err(ov7251->dev, "could not set mode %dx%d\n",
1362				ov7251->current_mode->width,
1363				ov7251->current_mode->height);
1364			goto err_power_down;
1365		}
1366		ret = __v4l2_ctrl_handler_setup(&ov7251->ctrls);
1367		if (ret < 0) {
1368			dev_err(ov7251->dev, "could not sync v4l2 controls\n");
1369			goto err_power_down;
1370		}
1371		ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT,
1372				       OV7251_SC_MODE_SELECT_STREAMING);
1373		if (ret)
1374			goto err_power_down;
1375	} else {
1376		ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT,
1377				       OV7251_SC_MODE_SELECT_SW_STANDBY);
1378		pm_runtime_put(ov7251->dev);
1379	}
1380
1381	mutex_unlock(&ov7251->lock);
1382	return ret;
1383
1384err_power_down:
1385	pm_runtime_put(ov7251->dev);
1386	mutex_unlock(&ov7251->lock);
1387	return ret;
1388}
1389
1390static int ov7251_get_frame_interval(struct v4l2_subdev *subdev,
1391				     struct v4l2_subdev_state *sd_state,
1392				     struct v4l2_subdev_frame_interval *fi)
1393{
1394	struct ov7251 *ov7251 = to_ov7251(subdev);
1395
1396	/*
1397	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
1398	 * subdev active state API.
1399	 */
1400	if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1401		return -EINVAL;
1402
1403	mutex_lock(&ov7251->lock);
1404	fi->interval = ov7251->current_mode->timeperframe;
1405	mutex_unlock(&ov7251->lock);
1406
1407	return 0;
1408}
1409
1410static int ov7251_set_frame_interval(struct v4l2_subdev *subdev,
1411				     struct v4l2_subdev_state *sd_state,
1412				     struct v4l2_subdev_frame_interval *fi)
1413{
1414	struct ov7251 *ov7251 = to_ov7251(subdev);
1415	const struct ov7251_mode_info *new_mode;
1416	int ret = 0;
1417
1418	/*
1419	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
1420	 * subdev active state API.
1421	 */
1422	if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1423		return -EINVAL;
1424
1425	mutex_lock(&ov7251->lock);
1426	new_mode = ov7251_find_mode_by_ival(ov7251, &fi->interval);
1427
1428	if (new_mode != ov7251->current_mode) {
1429		ret = __v4l2_ctrl_modify_range(ov7251->exposure,
1430					       1, new_mode->exposure_max,
1431					       1, new_mode->exposure_def);
1432		if (ret < 0)
1433			goto exit;
1434
1435		ret = __v4l2_ctrl_s_ctrl(ov7251->exposure,
1436					 new_mode->exposure_def);
1437		if (ret < 0)
1438			goto exit;
1439
1440		ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16);
1441		if (ret < 0)
1442			goto exit;
1443
1444		ov7251->current_mode = new_mode;
1445	}
1446
1447	fi->interval = ov7251->current_mode->timeperframe;
1448
1449exit:
1450	mutex_unlock(&ov7251->lock);
1451
1452	return ret;
1453}
1454
1455static const struct v4l2_subdev_video_ops ov7251_video_ops = {
1456	.s_stream = ov7251_s_stream,
1457};
1458
1459static const struct v4l2_subdev_pad_ops ov7251_subdev_pad_ops = {
1460	.enum_mbus_code = ov7251_enum_mbus_code,
1461	.enum_frame_size = ov7251_enum_frame_size,
1462	.enum_frame_interval = ov7251_enum_frame_ival,
1463	.get_fmt = ov7251_get_format,
1464	.set_fmt = ov7251_set_format,
1465	.get_selection = ov7251_get_selection,
1466	.get_frame_interval = ov7251_get_frame_interval,
1467	.set_frame_interval = ov7251_set_frame_interval,
1468};
1469
1470static const struct v4l2_subdev_ops ov7251_subdev_ops = {
1471	.video = &ov7251_video_ops,
1472	.pad = &ov7251_subdev_pad_ops,
1473};
1474
1475static const struct v4l2_subdev_internal_ops ov7251_internal_ops = {
1476	.init_state = ov7251_init_state,
1477};
1478
1479static int ov7251_check_hwcfg(struct ov7251 *ov7251)
1480{
1481	struct fwnode_handle *fwnode = dev_fwnode(ov7251->dev);
1482	struct v4l2_fwnode_endpoint bus_cfg = {
1483		.bus_type = V4L2_MBUS_CSI2_DPHY,
1484	};
1485	struct fwnode_handle *endpoint;
1486	unsigned int i, j;
1487	int ret;
1488
1489	/*
1490	 * Sometimes the fwnode graph is initialized by the bridge driver
1491	 * Bridge drivers doing this may also add GPIO mappings, wait for this.
1492	 */
1493	endpoint = fwnode_graph_get_next_endpoint(fwnode, NULL);
1494	if (!endpoint)
1495		return dev_err_probe(ov7251->dev, -EPROBE_DEFER,
1496				     "waiting for fwnode graph endpoint\n");
1497
1498	ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg);
1499	fwnode_handle_put(endpoint);
1500	if (ret)
1501		return dev_err_probe(ov7251->dev, ret,
1502				     "parsing endpoint node failed\n");
1503
1504	if (!bus_cfg.nr_of_link_frequencies) {
1505		ret = dev_err_probe(ov7251->dev, -EINVAL,
1506				    "no link frequencies defined\n");
1507		goto out_free_bus_cfg;
1508	}
1509
1510	for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) {
1511		for (j = 0; j < ARRAY_SIZE(link_freq); j++)
1512			if (bus_cfg.link_frequencies[i] == link_freq[j])
1513				break;
1514
1515		if (j < ARRAY_SIZE(link_freq))
1516			break;
1517	}
1518
1519	if (i == bus_cfg.nr_of_link_frequencies) {
1520		ret = dev_err_probe(ov7251->dev, -EINVAL,
1521				    "no supported link freq found\n");
1522		goto out_free_bus_cfg;
1523	}
1524
1525	ov7251->link_freq_idx = i;
1526
1527out_free_bus_cfg:
1528	v4l2_fwnode_endpoint_free(&bus_cfg);
1529
1530	return ret;
1531}
1532
1533static int ov7251_detect_chip(struct ov7251 *ov7251)
1534{
1535	u8 chip_id_high, chip_id_low, chip_rev;
1536	int ret;
1537
1538	ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_HIGH, &chip_id_high);
1539	if (ret < 0 || chip_id_high != OV7251_CHIP_ID_HIGH_BYTE)
1540		return dev_err_probe(ov7251->dev, -ENODEV,
1541				     "could not read ID high\n");
1542
1543	ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_LOW, &chip_id_low);
1544	if (ret < 0 || chip_id_low != OV7251_CHIP_ID_LOW_BYTE)
1545		return dev_err_probe(ov7251->dev, -ENODEV,
1546				     "could not read ID low\n");
1547
1548	ret = ov7251_read_reg(ov7251, OV7251_SC_GP_IO_IN1, &chip_rev);
1549	if (ret < 0)
1550		return dev_err_probe(ov7251->dev, -ENODEV,
1551				     "could not read revision\n");
1552	chip_rev >>= 4;
1553
1554	dev_info(ov7251->dev,
1555		 "OV7251 revision %x (%s) detected at address 0x%02x\n",
1556		 chip_rev,
1557		 chip_rev == 0x4 ? "1A / 1B" :
1558		 chip_rev == 0x5 ? "1C / 1D" :
1559		 chip_rev == 0x6 ? "1E" :
1560		 chip_rev == 0x7 ? "1F" : "unknown",
1561		 ov7251->i2c_client->addr);
1562
1563	return 0;
1564}
1565
1566static int ov7251_init_ctrls(struct ov7251 *ov7251)
1567{
1568	int vblank_max, vblank_def;
1569	s64 pixel_rate;
1570	int hblank;
1571
1572	v4l2_ctrl_handler_init(&ov7251->ctrls, 7);
1573	ov7251->ctrls.lock = &ov7251->lock;
1574
1575	v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1576			  V4L2_CID_HFLIP, 0, 1, 1, 0);
1577	v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1578			  V4L2_CID_VFLIP, 0, 1, 1, 0);
1579	ov7251->exposure = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1580					     V4L2_CID_EXPOSURE, 1, 32, 1, 32);
1581	ov7251->gain = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1582					 V4L2_CID_GAIN, 16, 1023, 1, 16);
1583	v4l2_ctrl_new_std_menu_items(&ov7251->ctrls, &ov7251_ctrl_ops,
1584				     V4L2_CID_TEST_PATTERN,
1585				     ARRAY_SIZE(ov7251_test_pattern_menu) - 1,
1586				     0, 0, ov7251_test_pattern_menu);
1587
1588	pixel_rate = pixel_rates[ov7251->link_freq_idx];
1589	ov7251->pixel_clock = v4l2_ctrl_new_std(&ov7251->ctrls,
1590						&ov7251_ctrl_ops,
1591						V4L2_CID_PIXEL_RATE,
1592						pixel_rate, INT_MAX,
1593						pixel_rate, pixel_rate);
1594	ov7251->link_freq = v4l2_ctrl_new_int_menu(&ov7251->ctrls,
1595						   &ov7251_ctrl_ops,
1596						   V4L2_CID_LINK_FREQ,
1597						   ARRAY_SIZE(link_freq) - 1,
1598						   ov7251->link_freq_idx,
1599						   link_freq);
1600	if (ov7251->link_freq)
1601		ov7251->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1602	if (ov7251->pixel_clock)
1603		ov7251->pixel_clock->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1604
1605	hblank = OV7251_FIXED_PPL - ov7251->current_mode->width;
1606	ov7251->hblank = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1607					   V4L2_CID_HBLANK, hblank, hblank, 1,
1608					   hblank);
1609	if (ov7251->hblank)
1610		ov7251->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1611
1612	vblank_max = OV7251_TIMING_MAX_VTS - ov7251->current_mode->height;
1613	vblank_def = ov7251->current_mode->vts - ov7251->current_mode->height;
1614	ov7251->vblank = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1615					   V4L2_CID_VBLANK,
1616					   OV7251_TIMING_MIN_VTS, vblank_max, 1,
1617					   vblank_def);
1618
1619	ov7251->sd.ctrl_handler = &ov7251->ctrls;
1620
1621	if (ov7251->ctrls.error) {
1622		v4l2_ctrl_handler_free(&ov7251->ctrls);
1623		return ov7251->ctrls.error;
1624	}
1625
1626	return 0;
1627}
1628
1629static int ov7251_probe(struct i2c_client *client)
1630{
1631	struct device *dev = &client->dev;
1632	struct ov7251 *ov7251;
1633	int ret;
1634	int i;
1635
1636	ov7251 = devm_kzalloc(dev, sizeof(struct ov7251), GFP_KERNEL);
1637	if (!ov7251)
1638		return -ENOMEM;
1639
1640	ov7251->i2c_client = client;
1641	ov7251->dev = dev;
1642
1643	ret = ov7251_check_hwcfg(ov7251);
1644	if (ret)
1645		return ret;
1646
1647	/* get system clock (xclk) */
1648	ov7251->xclk = devm_v4l2_sensor_clk_get(dev, NULL);
1649	if (IS_ERR(ov7251->xclk))
1650		return dev_err_probe(dev, PTR_ERR(ov7251->xclk),
1651				     "could not get xclk");
1652
1653	ov7251->xclk_freq = clk_get_rate(ov7251->xclk);
1654
1655	for (i = 0; i < ARRAY_SIZE(supported_xclk_rates); i++)
1656		if (ov7251->xclk_freq == supported_xclk_rates[i])
1657			break;
1658
1659	if (i == ARRAY_SIZE(supported_xclk_rates))
1660		return dev_err_probe(dev, -EINVAL,
1661				     "clock rate %u Hz is unsupported\n",
1662				     ov7251->xclk_freq);
1663
1664	ov7251->pll_cfgs = ov7251_pll_cfgs[i];
1665
1666	ov7251->io_regulator = devm_regulator_get(dev, "vdddo");
1667	if (IS_ERR(ov7251->io_regulator)) {
1668		dev_err(dev, "cannot get io regulator\n");
1669		return PTR_ERR(ov7251->io_regulator);
1670	}
1671
1672	ov7251->core_regulator = devm_regulator_get(dev, "vddd");
1673	if (IS_ERR(ov7251->core_regulator)) {
1674		dev_err(dev, "cannot get core regulator\n");
1675		return PTR_ERR(ov7251->core_regulator);
1676	}
1677
1678	ov7251->analog_regulator = devm_regulator_get(dev, "vdda");
1679	if (IS_ERR(ov7251->analog_regulator)) {
1680		dev_err(dev, "cannot get analog regulator\n");
1681		return PTR_ERR(ov7251->analog_regulator);
1682	}
1683
1684	ov7251->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
1685	if (IS_ERR(ov7251->enable_gpio)) {
1686		dev_err(dev, "cannot get enable gpio\n");
1687		return PTR_ERR(ov7251->enable_gpio);
1688	}
1689
1690	mutex_init(&ov7251->lock);
1691
1692	ov7251->current_mode = &ov7251_mode_info_data[0];
1693	ret = ov7251_init_ctrls(ov7251);
1694	if (ret) {
1695		dev_err_probe(dev, ret, "error during v4l2 ctrl init\n");
1696		goto destroy_mutex;
1697	}
1698
1699	v4l2_i2c_subdev_init(&ov7251->sd, client, &ov7251_subdev_ops);
1700	ov7251->sd.internal_ops = &ov7251_internal_ops;
1701	ov7251->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1702	ov7251->pad.flags = MEDIA_PAD_FL_SOURCE;
1703	ov7251->sd.dev = &client->dev;
1704	ov7251->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1705
1706	ret = media_entity_pads_init(&ov7251->sd.entity, 1, &ov7251->pad);
1707	if (ret < 0) {
1708		dev_err(dev, "could not register media entity\n");
1709		goto free_ctrl;
1710	}
1711
1712	ret = ov7251_set_power_on(ov7251->dev);
1713	if (ret)
1714		goto free_entity;
1715
1716	ret = ov7251_detect_chip(ov7251);
1717	if (ret)
1718		goto power_down;
1719
1720	pm_runtime_set_active(&client->dev);
1721	pm_runtime_get_noresume(&client->dev);
1722	pm_runtime_enable(&client->dev);
1723
1724	ret = ov7251_read_reg(ov7251, OV7251_PRE_ISP_00,
1725			      &ov7251->pre_isp_00);
1726	if (ret < 0) {
1727		dev_err(dev, "could not read test pattern value\n");
1728		ret = -ENODEV;
1729		goto err_pm_runtime;
1730	}
1731
1732	ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT1,
1733			      &ov7251->timing_format1);
1734	if (ret < 0) {
1735		dev_err(dev, "could not read vflip value\n");
1736		ret = -ENODEV;
1737		goto err_pm_runtime;
1738	}
1739
1740	ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT2,
1741			      &ov7251->timing_format2);
1742	if (ret < 0) {
1743		dev_err(dev, "could not read hflip value\n");
1744		ret = -ENODEV;
1745		goto err_pm_runtime;
1746	}
1747
1748	pm_runtime_set_autosuspend_delay(&client->dev, 1000);
1749	pm_runtime_use_autosuspend(&client->dev);
1750	pm_runtime_put_autosuspend(&client->dev);
1751
1752	ret = v4l2_async_register_subdev(&ov7251->sd);
1753	if (ret < 0) {
1754		dev_err(dev, "could not register v4l2 device\n");
1755		goto free_entity;
1756	}
1757
1758	ov7251_init_state(&ov7251->sd, NULL);
1759
1760	return 0;
1761
1762err_pm_runtime:
1763	pm_runtime_disable(ov7251->dev);
1764	pm_runtime_put_noidle(ov7251->dev);
1765power_down:
1766	ov7251_set_power_off(ov7251->dev);
1767free_entity:
1768	media_entity_cleanup(&ov7251->sd.entity);
1769free_ctrl:
1770	v4l2_ctrl_handler_free(&ov7251->ctrls);
1771destroy_mutex:
1772	mutex_destroy(&ov7251->lock);
1773
1774	return ret;
1775}
1776
1777static void ov7251_remove(struct i2c_client *client)
1778{
1779	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1780	struct ov7251 *ov7251 = to_ov7251(sd);
1781
1782	v4l2_async_unregister_subdev(&ov7251->sd);
1783	media_entity_cleanup(&ov7251->sd.entity);
1784	v4l2_ctrl_handler_free(&ov7251->ctrls);
1785	mutex_destroy(&ov7251->lock);
1786
1787	pm_runtime_disable(ov7251->dev);
1788	if (!pm_runtime_status_suspended(ov7251->dev))
1789		ov7251_set_power_off(ov7251->dev);
1790	pm_runtime_set_suspended(ov7251->dev);
1791}
1792
1793static const struct dev_pm_ops ov7251_pm_ops = {
1794	SET_RUNTIME_PM_OPS(ov7251_set_power_off, ov7251_set_power_on, NULL)
1795};
1796
1797static const struct of_device_id ov7251_of_match[] = {
1798	{ .compatible = "ovti,ov7251" },
1799	{ /* sentinel */ }
1800};
1801MODULE_DEVICE_TABLE(of, ov7251_of_match);
1802
1803static const struct acpi_device_id ov7251_acpi_match[] = {
1804	{ "INT347E" },
1805	{ }
1806};
1807MODULE_DEVICE_TABLE(acpi, ov7251_acpi_match);
1808
1809static struct i2c_driver ov7251_i2c_driver = {
1810	.driver = {
1811		.of_match_table = ov7251_of_match,
1812		.acpi_match_table = ov7251_acpi_match,
1813		.name  = "ov7251",
1814		.pm = &ov7251_pm_ops,
1815	},
1816	.probe = ov7251_probe,
1817	.remove = ov7251_remove,
1818};
1819
1820module_i2c_driver(ov7251_i2c_driver);
1821
1822MODULE_DESCRIPTION("Omnivision OV7251 Camera Driver");
1823MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
1824MODULE_LICENSE("GPL v2");