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ov5675.c
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linux-6.19.14/drivers/media/i2c/ov5675.c
1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2019 Intel Corporation. 3 4#include <linux/acpi.h> 5#include <linux/clk.h> 6#include <linux/delay.h> 7#include <linux/gpio/consumer.h> 8#include <linux/i2c.h> 9#include <linux/mod_devicetable.h> 10#include <linux/module.h> 11#include <linux/pm_runtime.h> 12#include <linux/regulator/consumer.h> 13#include <linux/unaligned.h> 14 15#include <media/v4l2-ctrls.h> 16#include <media/v4l2-device.h> 17#include <media/v4l2-fwnode.h> 18 19#define OV5675_REG_VALUE_08BIT 1 20#define OV5675_REG_VALUE_16BIT 2 21#define OV5675_REG_VALUE_24BIT 3 22 23#define OV5675_LINK_FREQ_450MHZ 450000000ULL 24#define OV5675_SCLK 90000000LL 25#define OV5675_XVCLK_19_2 19200000 26#define OV5675_DATA_LANES 2 27#define OV5675_RGB_DEPTH 10 28 29#define OV5675_REG_CHIP_ID 0x300a 30#define OV5675_CHIP_ID 0x5675 31 32#define OV5675_REG_MODE_SELECT 0x0100 33#define OV5675_MODE_STANDBY 0x00 34#define OV5675_MODE_STREAMING 0x01 35 36/* vertical-timings from sensor */ 37#define OV5675_REG_VTS 0x380e 38#define OV5675_VTS_30FPS 0x07e4 39#define OV5675_VTS_30FPS_MIN 0x07e4 40#define OV5675_VTS_MAX 0x7fff 41 42/* horizontal-timings from sensor */ 43#define OV5675_REG_HTS 0x380c 44 45/* Exposure controls from sensor */ 46#define OV5675_REG_EXPOSURE 0x3500 47#define OV5675_EXPOSURE_MIN 4 48#define OV5675_EXPOSURE_MAX_MARGIN 4 49#define OV5675_EXPOSURE_STEP 1 50 51/* Analog gain controls from sensor */ 52#define OV5675_REG_ANALOG_GAIN 0x3508 53#define OV5675_ANAL_GAIN_MIN 128 54#define OV5675_ANAL_GAIN_MAX 2047 55#define OV5675_ANAL_GAIN_STEP 1 56 57/* Digital gain controls from sensor */ 58#define OV5675_REG_DIGITAL_GAIN 0x350a 59#define OV5675_REG_MWB_R_GAIN 0x5019 60#define OV5675_REG_MWB_G_GAIN 0x501b 61#define OV5675_REG_MWB_B_GAIN 0x501d 62#define OV5675_DGTL_GAIN_MIN 1024 63#define OV5675_DGTL_GAIN_MAX 4095 64#define OV5675_DGTL_GAIN_STEP 1 65#define OV5675_DGTL_GAIN_DEFAULT 1024 66 67/* Group Access */ 68#define OV5675_REG_GROUP_ACCESS 0x3208 69#define OV5675_GROUP_HOLD_START 0x0 70#define OV5675_GROUP_HOLD_END 0x10 71#define OV5675_GROUP_HOLD_LAUNCH 0xa0 72 73/* Test Pattern Control */ 74#define OV5675_REG_TEST_PATTERN 0x4503 75#define OV5675_TEST_PATTERN_ENABLE BIT(7) 76#define OV5675_TEST_PATTERN_BAR_SHIFT 2 77 78/* Flip Mirror Controls from sensor */ 79#define OV5675_REG_FORMAT1 0x3820 80#define OV5675_REG_FORMAT2 0x373d 81 82#define to_ov5675(_sd) container_of(_sd, struct ov5675, sd) 83 84static const char * const ov5675_supply_names[] = { 85 "avdd", /* Analog power */ 86 "dovdd", /* Digital I/O power */ 87 "dvdd", /* Digital core power */ 88}; 89 90#define OV5675_NUM_SUPPLIES ARRAY_SIZE(ov5675_supply_names) 91 92enum { 93 OV5675_LINK_FREQ_900MBPS, 94}; 95 96struct ov5675_reg { 97 u16 address; 98 u8 val; 99}; 100 101struct ov5675_reg_list { 102 u32 num_of_regs; 103 const struct ov5675_reg *regs; 104}; 105 106struct ov5675_link_freq_config { 107 const struct ov5675_reg_list reg_list; 108}; 109 110struct ov5675_mode { 111 /* Frame width in pixels */ 112 u32 width; 113 114 /* Frame height in pixels */ 115 u32 height; 116 117 /* Horizontal timining size */ 118 u32 hts; 119 120 /* Default vertical timining size */ 121 u32 vts_def; 122 123 /* Min vertical timining size */ 124 u32 vts_min; 125 126 /* Link frequency needed for this resolution */ 127 u32 link_freq_index; 128 129 /* Sensor register settings for this resolution */ 130 const struct ov5675_reg_list reg_list; 131}; 132 133static const struct ov5675_reg mipi_data_rate_900mbps[] = { 134 {0x0103, 0x01}, 135 {0x0100, 0x00}, 136 {0x0300, 0x04}, 137 {0x0302, 0x8d}, 138 {0x0303, 0x00}, 139 {0x030d, 0x26}, 140}; 141 142static const struct ov5675_reg mode_2592x1944_regs[] = { 143 {0x3002, 0x21}, 144 {0x3107, 0x23}, 145 {0x3501, 0x20}, 146 {0x3503, 0x0c}, 147 {0x3508, 0x03}, 148 {0x3509, 0x00}, 149 {0x3600, 0x66}, 150 {0x3602, 0x30}, 151 {0x3610, 0xa5}, 152 {0x3612, 0x93}, 153 {0x3620, 0x80}, 154 {0x3642, 0x0e}, 155 {0x3661, 0x00}, 156 {0x3662, 0x10}, 157 {0x3664, 0xf3}, 158 {0x3665, 0x9e}, 159 {0x3667, 0xa5}, 160 {0x366e, 0x55}, 161 {0x366f, 0x55}, 162 {0x3670, 0x11}, 163 {0x3671, 0x11}, 164 {0x3672, 0x11}, 165 {0x3673, 0x11}, 166 {0x3714, 0x24}, 167 {0x371a, 0x3e}, 168 {0x3733, 0x10}, 169 {0x3734, 0x00}, 170 {0x373d, 0x24}, 171 {0x3764, 0x20}, 172 {0x3765, 0x20}, 173 {0x3766, 0x12}, 174 {0x37a1, 0x14}, 175 {0x37a8, 0x1c}, 176 {0x37ab, 0x0f}, 177 {0x37c2, 0x04}, 178 {0x37cb, 0x00}, 179 {0x37cc, 0x00}, 180 {0x37cd, 0x00}, 181 {0x37ce, 0x00}, 182 {0x37d8, 0x02}, 183 {0x37d9, 0x08}, 184 {0x37dc, 0x04}, 185 {0x3800, 0x00}, 186 {0x3801, 0x00}, 187 {0x3802, 0x00}, 188 {0x3803, 0x04}, 189 {0x3804, 0x0a}, 190 {0x3805, 0x3f}, 191 {0x3806, 0x07}, 192 {0x3807, 0xb3}, 193 {0x3808, 0x0a}, 194 {0x3809, 0x20}, 195 {0x380a, 0x07}, 196 {0x380b, 0x98}, 197 {0x380c, 0x02}, 198 {0x380d, 0xee}, 199 {0x380e, 0x07}, 200 {0x380f, 0xe4}, 201 {0x3811, 0x10}, 202 {0x3813, 0x0d}, 203 {0x3814, 0x01}, 204 {0x3815, 0x01}, 205 {0x3816, 0x01}, 206 {0x3817, 0x01}, 207 {0x381e, 0x02}, 208 {0x3820, 0x88}, 209 {0x3821, 0x01}, 210 {0x3832, 0x04}, 211 {0x3c80, 0x01}, 212 {0x3c82, 0x00}, 213 {0x3c83, 0xc8}, 214 {0x3c8c, 0x0f}, 215 {0x3c8d, 0xa0}, 216 {0x3c90, 0x07}, 217 {0x3c91, 0x00}, 218 {0x3c92, 0x00}, 219 {0x3c93, 0x00}, 220 {0x3c94, 0xd0}, 221 {0x3c95, 0x50}, 222 {0x3c96, 0x35}, 223 {0x3c97, 0x00}, 224 {0x4001, 0xe0}, 225 {0x4008, 0x02}, 226 {0x4009, 0x0d}, 227 {0x400f, 0x80}, 228 {0x4013, 0x02}, 229 {0x4040, 0x00}, 230 {0x4041, 0x07}, 231 {0x404c, 0x50}, 232 {0x404e, 0x20}, 233 {0x4500, 0x06}, 234 {0x4503, 0x00}, 235 {0x450a, 0x04}, 236 {0x4809, 0x04}, 237 {0x480c, 0x12}, 238 {0x4819, 0x70}, 239 {0x4825, 0x32}, 240 {0x4826, 0x32}, 241 {0x482a, 0x06}, 242 {0x4833, 0x08}, 243 {0x4837, 0x0d}, 244 {0x5000, 0x77}, 245 {0x5b00, 0x01}, 246 {0x5b01, 0x10}, 247 {0x5b02, 0x01}, 248 {0x5b03, 0xdb}, 249 {0x5b05, 0x6c}, 250 {0x5e10, 0xfc}, 251 {0x3500, 0x00}, 252 {0x3501, 0x3E}, 253 {0x3502, 0x60}, 254 {0x3503, 0x08}, 255 {0x3508, 0x04}, 256 {0x3509, 0x00}, 257 {0x3832, 0x48}, 258 {0x5780, 0x3e}, 259 {0x5781, 0x0f}, 260 {0x5782, 0x44}, 261 {0x5783, 0x02}, 262 {0x5784, 0x01}, 263 {0x5785, 0x01}, 264 {0x5786, 0x00}, 265 {0x5787, 0x04}, 266 {0x5788, 0x02}, 267 {0x5789, 0x0f}, 268 {0x578a, 0xfd}, 269 {0x578b, 0xf5}, 270 {0x578c, 0xf5}, 271 {0x578d, 0x03}, 272 {0x578e, 0x08}, 273 {0x578f, 0x0c}, 274 {0x5790, 0x08}, 275 {0x5791, 0x06}, 276 {0x5792, 0x00}, 277 {0x5793, 0x52}, 278 {0x5794, 0xa3}, 279 {0x4003, 0x40}, 280 {0x3107, 0x01}, 281 {0x3c80, 0x08}, 282 {0x3c83, 0xb1}, 283 {0x3c8c, 0x10}, 284 {0x3c8d, 0x00}, 285 {0x3c90, 0x00}, 286 {0x3c94, 0x00}, 287 {0x3c95, 0x00}, 288 {0x3c96, 0x00}, 289 {0x37cb, 0x09}, 290 {0x37cc, 0x15}, 291 {0x37cd, 0x1f}, 292 {0x37ce, 0x1f}, 293}; 294 295static const struct ov5675_reg mode_1296x972_regs[] = { 296 {0x3002, 0x21}, 297 {0x3107, 0x23}, 298 {0x3501, 0x20}, 299 {0x3503, 0x0c}, 300 {0x3508, 0x03}, 301 {0x3509, 0x00}, 302 {0x3600, 0x66}, 303 {0x3602, 0x30}, 304 {0x3610, 0xa5}, 305 {0x3612, 0x93}, 306 {0x3620, 0x80}, 307 {0x3642, 0x0e}, 308 {0x3661, 0x00}, 309 {0x3662, 0x08}, 310 {0x3664, 0xf3}, 311 {0x3665, 0x9e}, 312 {0x3667, 0xa5}, 313 {0x366e, 0x55}, 314 {0x366f, 0x55}, 315 {0x3670, 0x11}, 316 {0x3671, 0x11}, 317 {0x3672, 0x11}, 318 {0x3673, 0x11}, 319 {0x3714, 0x28}, 320 {0x371a, 0x3e}, 321 {0x3733, 0x10}, 322 {0x3734, 0x00}, 323 {0x373d, 0x24}, 324 {0x3764, 0x20}, 325 {0x3765, 0x20}, 326 {0x3766, 0x12}, 327 {0x37a1, 0x14}, 328 {0x37a8, 0x1c}, 329 {0x37ab, 0x0f}, 330 {0x37c2, 0x14}, 331 {0x37cb, 0x00}, 332 {0x37cc, 0x00}, 333 {0x37cd, 0x00}, 334 {0x37ce, 0x00}, 335 {0x37d8, 0x02}, 336 {0x37d9, 0x04}, 337 {0x37dc, 0x04}, 338 {0x3800, 0x00}, 339 {0x3801, 0x00}, 340 {0x3802, 0x00}, 341 {0x3803, 0x00}, 342 {0x3804, 0x0a}, 343 {0x3805, 0x3f}, 344 {0x3806, 0x07}, 345 {0x3807, 0xb7}, 346 {0x3808, 0x05}, 347 {0x3809, 0x10}, 348 {0x380a, 0x03}, 349 {0x380b, 0xcc}, 350 {0x380c, 0x02}, 351 {0x380d, 0xee}, 352 {0x380e, 0x07}, 353 {0x380f, 0xd0}, 354 {0x3811, 0x08}, 355 {0x3813, 0x0d}, 356 {0x3814, 0x03}, 357 {0x3815, 0x01}, 358 {0x3816, 0x03}, 359 {0x3817, 0x01}, 360 {0x381e, 0x02}, 361 {0x3820, 0x8b}, 362 {0x3821, 0x01}, 363 {0x3832, 0x04}, 364 {0x3c80, 0x01}, 365 {0x3c82, 0x00}, 366 {0x3c83, 0xc8}, 367 {0x3c8c, 0x0f}, 368 {0x3c8d, 0xa0}, 369 {0x3c90, 0x07}, 370 {0x3c91, 0x00}, 371 {0x3c92, 0x00}, 372 {0x3c93, 0x00}, 373 {0x3c94, 0xd0}, 374 {0x3c95, 0x50}, 375 {0x3c96, 0x35}, 376 {0x3c97, 0x00}, 377 {0x4001, 0xe0}, 378 {0x4008, 0x00}, 379 {0x4009, 0x07}, 380 {0x400f, 0x80}, 381 {0x4013, 0x02}, 382 {0x4040, 0x00}, 383 {0x4041, 0x03}, 384 {0x404c, 0x50}, 385 {0x404e, 0x20}, 386 {0x4500, 0x06}, 387 {0x4503, 0x00}, 388 {0x450a, 0x04}, 389 {0x4809, 0x04}, 390 {0x480c, 0x12}, 391 {0x4819, 0x70}, 392 {0x4825, 0x32}, 393 {0x4826, 0x32}, 394 {0x482a, 0x06}, 395 {0x4833, 0x08}, 396 {0x4837, 0x0d}, 397 {0x5000, 0x77}, 398 {0x5b00, 0x01}, 399 {0x5b01, 0x10}, 400 {0x5b02, 0x01}, 401 {0x5b03, 0xdb}, 402 {0x5b05, 0x6c}, 403 {0x5e10, 0xfc}, 404 {0x3500, 0x00}, 405 {0x3501, 0x1F}, 406 {0x3502, 0x20}, 407 {0x3503, 0x08}, 408 {0x3508, 0x04}, 409 {0x3509, 0x00}, 410 {0x3832, 0x48}, 411 {0x5780, 0x3e}, 412 {0x5781, 0x0f}, 413 {0x5782, 0x44}, 414 {0x5783, 0x02}, 415 {0x5784, 0x01}, 416 {0x5785, 0x01}, 417 {0x5786, 0x00}, 418 {0x5787, 0x04}, 419 {0x5788, 0x02}, 420 {0x5789, 0x0f}, 421 {0x578a, 0xfd}, 422 {0x578b, 0xf5}, 423 {0x578c, 0xf5}, 424 {0x578d, 0x03}, 425 {0x578e, 0x08}, 426 {0x578f, 0x0c}, 427 {0x5790, 0x08}, 428 {0x5791, 0x06}, 429 {0x5792, 0x00}, 430 {0x5793, 0x52}, 431 {0x5794, 0xa3}, 432 {0x4003, 0x40}, 433 {0x3107, 0x01}, 434 {0x3c80, 0x08}, 435 {0x3c83, 0xb1}, 436 {0x3c8c, 0x10}, 437 {0x3c8d, 0x00}, 438 {0x3c90, 0x00}, 439 {0x3c94, 0x00}, 440 {0x3c95, 0x00}, 441 {0x3c96, 0x00}, 442 {0x37cb, 0x09}, 443 {0x37cc, 0x15}, 444 {0x37cd, 0x1f}, 445 {0x37ce, 0x1f}, 446}; 447 448static const char * const ov5675_test_pattern_menu[] = { 449 "Disabled", 450 "Standard Color Bar", 451 "Top-Bottom Darker Color Bar", 452 "Right-Left Darker Color Bar", 453 "Bottom-Top Darker Color Bar" 454}; 455 456static const s64 link_freq_menu_items[] = { 457 OV5675_LINK_FREQ_450MHZ, 458}; 459 460static const struct ov5675_link_freq_config link_freq_configs[] = { 461 [OV5675_LINK_FREQ_900MBPS] = { 462 .reg_list = { 463 .num_of_regs = ARRAY_SIZE(mipi_data_rate_900mbps), 464 .regs = mipi_data_rate_900mbps, 465 } 466 } 467}; 468 469static const struct ov5675_mode supported_modes[] = { 470 { 471 .width = 2592, 472 .height = 1944, 473 .hts = 1500, 474 .vts_def = OV5675_VTS_30FPS, 475 .vts_min = OV5675_VTS_30FPS_MIN, 476 .reg_list = { 477 .num_of_regs = ARRAY_SIZE(mode_2592x1944_regs), 478 .regs = mode_2592x1944_regs, 479 }, 480 .link_freq_index = OV5675_LINK_FREQ_900MBPS, 481 }, 482 { 483 .width = 1296, 484 .height = 972, 485 .hts = 1500, 486 .vts_def = OV5675_VTS_30FPS, 487 .vts_min = OV5675_VTS_30FPS_MIN, 488 .reg_list = { 489 .num_of_regs = ARRAY_SIZE(mode_1296x972_regs), 490 .regs = mode_1296x972_regs, 491 }, 492 .link_freq_index = OV5675_LINK_FREQ_900MBPS, 493 } 494}; 495 496struct ov5675 { 497 struct device *dev; 498 499 struct v4l2_subdev sd; 500 struct media_pad pad; 501 struct v4l2_ctrl_handler ctrl_handler; 502 struct clk *xvclk; 503 struct gpio_desc *reset_gpio; 504 struct regulator_bulk_data supplies[OV5675_NUM_SUPPLIES]; 505 506 /* V4L2 Controls */ 507 struct v4l2_ctrl *link_freq; 508 struct v4l2_ctrl *pixel_rate; 509 struct v4l2_ctrl *vblank; 510 struct v4l2_ctrl *hblank; 511 struct v4l2_ctrl *exposure; 512 513 /* Current mode */ 514 const struct ov5675_mode *cur_mode; 515 516 /* To serialize asynchronous callbacks */ 517 struct mutex mutex; 518 519 /* True if the device has been identified */ 520 bool identified; 521}; 522 523static u64 to_pixel_rate(u32 f_index) 524{ 525 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV5675_DATA_LANES; 526 527 do_div(pixel_rate, OV5675_RGB_DEPTH); 528 529 return pixel_rate; 530} 531 532static u64 to_pixels_per_line(u32 hts, u32 f_index) 533{ 534 u64 ppl = hts * to_pixel_rate(f_index); 535 536 do_div(ppl, OV5675_SCLK); 537 538 return ppl; 539} 540 541static int ov5675_read_reg(struct ov5675 *ov5675, u16 reg, u16 len, u32 *val) 542{ 543 struct i2c_client *client = v4l2_get_subdevdata(&ov5675->sd); 544 struct i2c_msg msgs[2]; 545 u8 addr_buf[2]; 546 u8 data_buf[4] = {0}; 547 int ret; 548 549 if (len > 4) 550 return -EINVAL; 551 552 put_unaligned_be16(reg, addr_buf); 553 msgs[0].addr = client->addr; 554 msgs[0].flags = 0; 555 msgs[0].len = sizeof(addr_buf); 556 msgs[0].buf = addr_buf; 557 msgs[1].addr = client->addr; 558 msgs[1].flags = I2C_M_RD; 559 msgs[1].len = len; 560 msgs[1].buf = &data_buf[4 - len]; 561 562 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 563 if (ret != ARRAY_SIZE(msgs)) 564 return -EIO; 565 566 *val = get_unaligned_be32(data_buf); 567 568 return 0; 569} 570 571static int ov5675_write_reg(struct ov5675 *ov5675, u16 reg, u16 len, u32 val) 572{ 573 struct i2c_client *client = v4l2_get_subdevdata(&ov5675->sd); 574 u8 buf[6]; 575 576 if (len > 4) 577 return -EINVAL; 578 579 put_unaligned_be16(reg, buf); 580 put_unaligned_be32(val << 8 * (4 - len), buf + 2); 581 if (i2c_master_send(client, buf, len + 2) != len + 2) 582 return -EIO; 583 584 return 0; 585} 586 587static int ov5675_write_reg_list(struct ov5675 *ov5675, 588 const struct ov5675_reg_list *r_list) 589{ 590 unsigned int i; 591 int ret; 592 593 for (i = 0; i < r_list->num_of_regs; i++) { 594 ret = ov5675_write_reg(ov5675, r_list->regs[i].address, 1, 595 r_list->regs[i].val); 596 if (ret) { 597 dev_err_ratelimited(ov5675->dev, 598 "failed to write reg 0x%4.4x. error = %d", 599 r_list->regs[i].address, ret); 600 return ret; 601 } 602 } 603 604 return 0; 605} 606 607static int ov5675_update_digital_gain(struct ov5675 *ov5675, u32 d_gain) 608{ 609 int ret; 610 611 ret = ov5675_write_reg(ov5675, OV5675_REG_GROUP_ACCESS, 612 OV5675_REG_VALUE_08BIT, 613 OV5675_GROUP_HOLD_START); 614 if (ret) 615 return ret; 616 617 ret = ov5675_write_reg(ov5675, OV5675_REG_MWB_R_GAIN, 618 OV5675_REG_VALUE_16BIT, d_gain); 619 if (ret) 620 return ret; 621 622 ret = ov5675_write_reg(ov5675, OV5675_REG_MWB_G_GAIN, 623 OV5675_REG_VALUE_16BIT, d_gain); 624 if (ret) 625 return ret; 626 627 ret = ov5675_write_reg(ov5675, OV5675_REG_MWB_B_GAIN, 628 OV5675_REG_VALUE_16BIT, d_gain); 629 if (ret) 630 return ret; 631 632 ret = ov5675_write_reg(ov5675, OV5675_REG_GROUP_ACCESS, 633 OV5675_REG_VALUE_08BIT, 634 OV5675_GROUP_HOLD_END); 635 if (ret) 636 return ret; 637 638 ret = ov5675_write_reg(ov5675, OV5675_REG_GROUP_ACCESS, 639 OV5675_REG_VALUE_08BIT, 640 OV5675_GROUP_HOLD_LAUNCH); 641 return ret; 642} 643 644static int ov5675_test_pattern(struct ov5675 *ov5675, u32 pattern) 645{ 646 if (pattern) 647 pattern = (pattern - 1) << OV5675_TEST_PATTERN_BAR_SHIFT | 648 OV5675_TEST_PATTERN_ENABLE; 649 650 return ov5675_write_reg(ov5675, OV5675_REG_TEST_PATTERN, 651 OV5675_REG_VALUE_08BIT, pattern); 652} 653 654/* 655 * OV5675 supports keeping the pixel order by mirror and flip function 656 * The Bayer order isn't affected by the flip controls 657 */ 658static int ov5675_set_ctrl_hflip(struct ov5675 *ov5675, u32 ctrl_val) 659{ 660 int ret; 661 u32 val; 662 663 ret = ov5675_read_reg(ov5675, OV5675_REG_FORMAT1, 664 OV5675_REG_VALUE_08BIT, &val); 665 if (ret) 666 return ret; 667 668 return ov5675_write_reg(ov5675, OV5675_REG_FORMAT1, 669 OV5675_REG_VALUE_08BIT, 670 ctrl_val ? val & ~BIT(3) : val | BIT(3)); 671} 672 673static int ov5675_set_ctrl_vflip(struct ov5675 *ov5675, u8 ctrl_val) 674{ 675 int ret; 676 u32 val; 677 678 ret = ov5675_read_reg(ov5675, OV5675_REG_FORMAT1, 679 OV5675_REG_VALUE_08BIT, &val); 680 if (ret) 681 return ret; 682 683 ret = ov5675_write_reg(ov5675, OV5675_REG_FORMAT1, 684 OV5675_REG_VALUE_08BIT, 685 ctrl_val ? val | BIT(4) | BIT(5) : val & ~BIT(4) & ~BIT(5)); 686 687 if (ret) 688 return ret; 689 690 ret = ov5675_read_reg(ov5675, OV5675_REG_FORMAT2, 691 OV5675_REG_VALUE_08BIT, &val); 692 693 if (ret) 694 return ret; 695 696 return ov5675_write_reg(ov5675, OV5675_REG_FORMAT2, 697 OV5675_REG_VALUE_08BIT, 698 ctrl_val ? val | BIT(1) : val & ~BIT(1)); 699} 700 701static int ov5675_set_ctrl(struct v4l2_ctrl *ctrl) 702{ 703 struct ov5675 *ov5675 = container_of(ctrl->handler, 704 struct ov5675, ctrl_handler); 705 s64 exposure_max; 706 int ret = 0; 707 708 /* Propagate change of current control to all related controls */ 709 if (ctrl->id == V4L2_CID_VBLANK) { 710 /* Update max exposure while meeting expected vblanking */ 711 exposure_max = ov5675->cur_mode->height + ctrl->val - 712 OV5675_EXPOSURE_MAX_MARGIN; 713 __v4l2_ctrl_modify_range(ov5675->exposure, 714 ov5675->exposure->minimum, 715 exposure_max, ov5675->exposure->step, 716 exposure_max); 717 } 718 719 /* V4L2 controls values will be applied only when power is already up */ 720 if (!pm_runtime_get_if_in_use(ov5675->dev)) 721 return 0; 722 723 switch (ctrl->id) { 724 case V4L2_CID_ANALOGUE_GAIN: 725 ret = ov5675_write_reg(ov5675, OV5675_REG_ANALOG_GAIN, 726 OV5675_REG_VALUE_16BIT, ctrl->val); 727 break; 728 729 case V4L2_CID_DIGITAL_GAIN: 730 ret = ov5675_update_digital_gain(ov5675, ctrl->val); 731 break; 732 733 case V4L2_CID_EXPOSURE: 734 /* 4 least significant bits of expsoure are fractional part 735 * val = val << 4 736 * for ov5675, the unit of exposure is different from other 737 * OmniVision sensors, its exposure value is twice of the 738 * register value, the exposure should be divided by 2 before 739 * set register, e.g. val << 3. 740 */ 741 ret = ov5675_write_reg(ov5675, OV5675_REG_EXPOSURE, 742 OV5675_REG_VALUE_24BIT, ctrl->val << 3); 743 break; 744 745 case V4L2_CID_VBLANK: 746 ret = ov5675_write_reg(ov5675, OV5675_REG_VTS, 747 OV5675_REG_VALUE_16BIT, 748 ov5675->cur_mode->height + ctrl->val + 749 10); 750 break; 751 752 case V4L2_CID_TEST_PATTERN: 753 ret = ov5675_test_pattern(ov5675, ctrl->val); 754 break; 755 756 case V4L2_CID_HFLIP: 757 ov5675_set_ctrl_hflip(ov5675, ctrl->val); 758 break; 759 760 case V4L2_CID_VFLIP: 761 ov5675_set_ctrl_vflip(ov5675, ctrl->val); 762 break; 763 764 default: 765 ret = -EINVAL; 766 break; 767 } 768 769 pm_runtime_put(ov5675->dev); 770 771 return ret; 772} 773 774static const struct v4l2_ctrl_ops ov5675_ctrl_ops = { 775 .s_ctrl = ov5675_set_ctrl, 776}; 777 778static int ov5675_init_controls(struct ov5675 *ov5675) 779{ 780 struct v4l2_fwnode_device_properties props; 781 struct v4l2_ctrl_handler *ctrl_hdlr; 782 s64 exposure_max, h_blank; 783 int ret; 784 785 ctrl_hdlr = &ov5675->ctrl_handler; 786 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10); 787 if (ret) 788 return ret; 789 790 ctrl_hdlr->lock = &ov5675->mutex; 791 ov5675->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov5675_ctrl_ops, 792 V4L2_CID_LINK_FREQ, 793 ARRAY_SIZE(link_freq_menu_items) - 1, 794 0, link_freq_menu_items); 795 if (ov5675->link_freq) 796 ov5675->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 797 798 ov5675->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops, 799 V4L2_CID_PIXEL_RATE, 0, 800 to_pixel_rate(OV5675_LINK_FREQ_900MBPS), 801 1, 802 to_pixel_rate(OV5675_LINK_FREQ_900MBPS)); 803 ov5675->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops, 804 V4L2_CID_VBLANK, 805 ov5675->cur_mode->vts_min - ov5675->cur_mode->height, 806 OV5675_VTS_MAX - ov5675->cur_mode->height, 1, 807 ov5675->cur_mode->vts_def - ov5675->cur_mode->height); 808 h_blank = to_pixels_per_line(ov5675->cur_mode->hts, 809 ov5675->cur_mode->link_freq_index) - ov5675->cur_mode->width; 810 ov5675->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops, 811 V4L2_CID_HBLANK, h_blank, h_blank, 1, 812 h_blank); 813 if (ov5675->hblank) 814 ov5675->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 815 816 v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 817 OV5675_ANAL_GAIN_MIN, OV5675_ANAL_GAIN_MAX, 818 OV5675_ANAL_GAIN_STEP, OV5675_ANAL_GAIN_MIN); 819 v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 820 OV5675_DGTL_GAIN_MIN, OV5675_DGTL_GAIN_MAX, 821 OV5675_DGTL_GAIN_STEP, OV5675_DGTL_GAIN_DEFAULT); 822 exposure_max = (ov5675->cur_mode->vts_def - OV5675_EXPOSURE_MAX_MARGIN); 823 ov5675->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops, 824 V4L2_CID_EXPOSURE, 825 OV5675_EXPOSURE_MIN, exposure_max, 826 OV5675_EXPOSURE_STEP, 827 exposure_max); 828 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov5675_ctrl_ops, 829 V4L2_CID_TEST_PATTERN, 830 ARRAY_SIZE(ov5675_test_pattern_menu) - 1, 831 0, 0, ov5675_test_pattern_menu); 832 v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops, 833 V4L2_CID_HFLIP, 0, 1, 1, 0); 834 v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops, 835 V4L2_CID_VFLIP, 0, 1, 1, 0); 836 837 if (ctrl_hdlr->error) { 838 v4l2_ctrl_handler_free(ctrl_hdlr); 839 return ctrl_hdlr->error; 840 } 841 842 ret = v4l2_fwnode_device_parse(ov5675->dev, &props); 843 if (ret) 844 goto error; 845 846 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov5675_ctrl_ops, 847 &props); 848 if (ret) 849 goto error; 850 851 ov5675->sd.ctrl_handler = ctrl_hdlr; 852 853 return 0; 854 855error: 856 v4l2_ctrl_handler_free(ctrl_hdlr); 857 858 return ret; 859} 860 861static void ov5675_update_pad_format(const struct ov5675_mode *mode, 862 struct v4l2_mbus_framefmt *fmt) 863{ 864 fmt->width = mode->width; 865 fmt->height = mode->height; 866 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; 867 fmt->field = V4L2_FIELD_NONE; 868} 869 870static int ov5675_identify_module(struct ov5675 *ov5675) 871{ 872 int ret; 873 u32 val; 874 875 if (ov5675->identified) 876 return 0; 877 878 ret = ov5675_read_reg(ov5675, OV5675_REG_CHIP_ID, 879 OV5675_REG_VALUE_24BIT, &val); 880 if (ret) 881 return ret; 882 883 if (val != OV5675_CHIP_ID) { 884 dev_err(ov5675->dev, "chip id mismatch: %x!=%x", 885 OV5675_CHIP_ID, val); 886 return -ENXIO; 887 } 888 889 ov5675->identified = true; 890 891 return 0; 892} 893 894static int ov5675_start_streaming(struct ov5675 *ov5675) 895{ 896 const struct ov5675_reg_list *reg_list; 897 int link_freq_index, ret; 898 899 ret = ov5675_identify_module(ov5675); 900 if (ret) 901 return ret; 902 903 link_freq_index = ov5675->cur_mode->link_freq_index; 904 reg_list = &link_freq_configs[link_freq_index].reg_list; 905 ret = ov5675_write_reg_list(ov5675, reg_list); 906 if (ret) { 907 dev_err(ov5675->dev, "failed to set plls"); 908 return ret; 909 } 910 911 reg_list = &ov5675->cur_mode->reg_list; 912 ret = ov5675_write_reg_list(ov5675, reg_list); 913 if (ret) { 914 dev_err(ov5675->dev, "failed to set mode"); 915 return ret; 916 } 917 918 ret = __v4l2_ctrl_handler_setup(ov5675->sd.ctrl_handler); 919 if (ret) 920 return ret; 921 922 ret = ov5675_write_reg(ov5675, OV5675_REG_MODE_SELECT, 923 OV5675_REG_VALUE_08BIT, OV5675_MODE_STREAMING); 924 if (ret) { 925 dev_err(ov5675->dev, "failed to set stream"); 926 return ret; 927 } 928 929 return 0; 930} 931 932static void ov5675_stop_streaming(struct ov5675 *ov5675) 933{ 934 if (ov5675_write_reg(ov5675, OV5675_REG_MODE_SELECT, 935 OV5675_REG_VALUE_08BIT, OV5675_MODE_STANDBY)) 936 dev_err(ov5675->dev, "failed to set stream"); 937} 938 939static int ov5675_set_stream(struct v4l2_subdev *sd, int enable) 940{ 941 struct ov5675 *ov5675 = to_ov5675(sd); 942 int ret = 0; 943 944 mutex_lock(&ov5675->mutex); 945 if (enable) { 946 ret = pm_runtime_resume_and_get(ov5675->dev); 947 if (ret < 0) { 948 mutex_unlock(&ov5675->mutex); 949 return ret; 950 } 951 952 ret = ov5675_start_streaming(ov5675); 953 if (ret) { 954 enable = 0; 955 ov5675_stop_streaming(ov5675); 956 pm_runtime_put(ov5675->dev); 957 } 958 } else { 959 ov5675_stop_streaming(ov5675); 960 pm_runtime_put(ov5675->dev); 961 } 962 963 mutex_unlock(&ov5675->mutex); 964 965 return ret; 966} 967 968static int ov5675_power_off(struct device *dev) 969{ 970 struct v4l2_subdev *sd = dev_get_drvdata(dev); 971 struct ov5675 *ov5675 = to_ov5675(sd); 972 973 usleep_range(90, 100); 974 975 clk_disable_unprepare(ov5675->xvclk); 976 gpiod_set_value_cansleep(ov5675->reset_gpio, 1); 977 regulator_bulk_disable(OV5675_NUM_SUPPLIES, ov5675->supplies); 978 979 return 0; 980} 981 982static int ov5675_power_on(struct device *dev) 983{ 984 struct v4l2_subdev *sd = dev_get_drvdata(dev); 985 struct ov5675 *ov5675 = to_ov5675(sd); 986 int ret; 987 988 ret = clk_prepare_enable(ov5675->xvclk); 989 if (ret < 0) { 990 dev_err(dev, "failed to enable xvclk: %d\n", ret); 991 return ret; 992 } 993 994 gpiod_set_value_cansleep(ov5675->reset_gpio, 1); 995 996 ret = regulator_bulk_enable(OV5675_NUM_SUPPLIES, ov5675->supplies); 997 if (ret) { 998 clk_disable_unprepare(ov5675->xvclk); 999 return ret; 1000 } 1001 1002 /* Reset pulse should be at least 2ms and reset gpio released only once 1003 * regulators are stable. 1004 */ 1005 usleep_range(2000, 2200); 1006 1007 gpiod_set_value_cansleep(ov5675->reset_gpio, 0); 1008 1009 /* Worst case quiesence gap is 1.365 milliseconds @ 6MHz XVCLK 1010 * Add an additional threshold grace period to ensure reset 1011 * completion before initiating our first I2C transaction. 1012 */ 1013 usleep_range(1500, 1600); 1014 1015 return 0; 1016} 1017 1018static int ov5675_set_format(struct v4l2_subdev *sd, 1019 struct v4l2_subdev_state *sd_state, 1020 struct v4l2_subdev_format *fmt) 1021{ 1022 struct ov5675 *ov5675 = to_ov5675(sd); 1023 const struct ov5675_mode *mode; 1024 s32 vblank_def, h_blank; 1025 1026 mode = v4l2_find_nearest_size(supported_modes, 1027 ARRAY_SIZE(supported_modes), width, 1028 height, fmt->format.width, 1029 fmt->format.height); 1030 1031 mutex_lock(&ov5675->mutex); 1032 ov5675_update_pad_format(mode, &fmt->format); 1033 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1034 *v4l2_subdev_state_get_format(sd_state, fmt->pad) = fmt->format; 1035 } else { 1036 ov5675->cur_mode = mode; 1037 __v4l2_ctrl_s_ctrl(ov5675->link_freq, mode->link_freq_index); 1038 __v4l2_ctrl_s_ctrl_int64(ov5675->pixel_rate, 1039 to_pixel_rate(mode->link_freq_index)); 1040 1041 /* Update limits and set FPS to default */ 1042 vblank_def = mode->vts_def - mode->height; 1043 __v4l2_ctrl_modify_range(ov5675->vblank, 1044 mode->vts_min - mode->height, 1045 OV5675_VTS_MAX - mode->height, 1, 1046 vblank_def); 1047 __v4l2_ctrl_s_ctrl(ov5675->vblank, vblank_def); 1048 h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) - 1049 mode->width; 1050 __v4l2_ctrl_modify_range(ov5675->hblank, h_blank, h_blank, 1, 1051 h_blank); 1052 } 1053 1054 mutex_unlock(&ov5675->mutex); 1055 1056 return 0; 1057} 1058 1059static int ov5675_get_format(struct v4l2_subdev *sd, 1060 struct v4l2_subdev_state *sd_state, 1061 struct v4l2_subdev_format *fmt) 1062{ 1063 struct ov5675 *ov5675 = to_ov5675(sd); 1064 1065 mutex_lock(&ov5675->mutex); 1066 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 1067 fmt->format = *v4l2_subdev_state_get_format(sd_state, 1068 fmt->pad); 1069 else 1070 ov5675_update_pad_format(ov5675->cur_mode, &fmt->format); 1071 1072 mutex_unlock(&ov5675->mutex); 1073 1074 return 0; 1075} 1076 1077static int ov5675_get_selection(struct v4l2_subdev *sd, 1078 struct v4l2_subdev_state *state, 1079 struct v4l2_subdev_selection *sel) 1080{ 1081 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) 1082 return -EINVAL; 1083 1084 switch (sel->target) { 1085 case V4L2_SEL_TGT_CROP_BOUNDS: 1086 sel->r.top = 0; 1087 sel->r.left = 0; 1088 sel->r.width = 2624; 1089 sel->r.height = 2000; 1090 return 0; 1091 case V4L2_SEL_TGT_CROP: 1092 case V4L2_SEL_TGT_CROP_DEFAULT: 1093 sel->r.top = 16; 1094 sel->r.left = 16; 1095 sel->r.width = 2592; 1096 sel->r.height = 1944; 1097 return 0; 1098 } 1099 return -EINVAL; 1100} 1101 1102static int ov5675_enum_mbus_code(struct v4l2_subdev *sd, 1103 struct v4l2_subdev_state *sd_state, 1104 struct v4l2_subdev_mbus_code_enum *code) 1105{ 1106 if (code->index > 0) 1107 return -EINVAL; 1108 1109 code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 1110 1111 return 0; 1112} 1113 1114static int ov5675_enum_frame_size(struct v4l2_subdev *sd, 1115 struct v4l2_subdev_state *sd_state, 1116 struct v4l2_subdev_frame_size_enum *fse) 1117{ 1118 if (fse->index >= ARRAY_SIZE(supported_modes)) 1119 return -EINVAL; 1120 1121 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 1122 return -EINVAL; 1123 1124 fse->min_width = supported_modes[fse->index].width; 1125 fse->max_width = fse->min_width; 1126 fse->min_height = supported_modes[fse->index].height; 1127 fse->max_height = fse->min_height; 1128 1129 return 0; 1130} 1131 1132static int ov5675_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 1133{ 1134 struct ov5675 *ov5675 = to_ov5675(sd); 1135 1136 mutex_lock(&ov5675->mutex); 1137 ov5675_update_pad_format(&supported_modes[0], 1138 v4l2_subdev_state_get_format(fh->state, 0)); 1139 mutex_unlock(&ov5675->mutex); 1140 1141 return 0; 1142} 1143 1144static const struct v4l2_subdev_video_ops ov5675_video_ops = { 1145 .s_stream = ov5675_set_stream, 1146}; 1147 1148static const struct v4l2_subdev_pad_ops ov5675_pad_ops = { 1149 .set_fmt = ov5675_set_format, 1150 .get_fmt = ov5675_get_format, 1151 .get_selection = ov5675_get_selection, 1152 .enum_mbus_code = ov5675_enum_mbus_code, 1153 .enum_frame_size = ov5675_enum_frame_size, 1154}; 1155 1156static const struct v4l2_subdev_ops ov5675_subdev_ops = { 1157 .video = &ov5675_video_ops, 1158 .pad = &ov5675_pad_ops, 1159}; 1160 1161static const struct media_entity_operations ov5675_subdev_entity_ops = { 1162 .link_validate = v4l2_subdev_link_validate, 1163}; 1164 1165static const struct v4l2_subdev_internal_ops ov5675_internal_ops = { 1166 .open = ov5675_open, 1167}; 1168 1169static int ov5675_get_hwcfg(struct ov5675 *ov5675) 1170{ 1171 struct device *dev = ov5675->dev; 1172 struct fwnode_handle *ep; 1173 struct fwnode_handle *fwnode = dev_fwnode(dev); 1174 struct v4l2_fwnode_endpoint bus_cfg = { 1175 .bus_type = V4L2_MBUS_CSI2_DPHY 1176 }; 1177 u32 xvclk_rate; 1178 int ret; 1179 unsigned int i, j; 1180 1181 if (!fwnode) 1182 return -ENXIO; 1183 1184 ov5675->xvclk = devm_v4l2_sensor_clk_get(dev, NULL); 1185 if (IS_ERR(ov5675->xvclk)) 1186 return dev_err_probe(dev, PTR_ERR(ov5675->xvclk), 1187 "failed to get xvclk: %pe\n", 1188 ov5675->xvclk); 1189 1190 xvclk_rate = clk_get_rate(ov5675->xvclk); 1191 if (xvclk_rate != OV5675_XVCLK_19_2) { 1192 dev_err(dev, "external clock rate %u is unsupported", 1193 xvclk_rate); 1194 return -EINVAL; 1195 } 1196 1197 ov5675->reset_gpio = devm_gpiod_get_optional(dev, "reset", 1198 GPIOD_OUT_HIGH); 1199 if (IS_ERR(ov5675->reset_gpio)) { 1200 ret = PTR_ERR(ov5675->reset_gpio); 1201 dev_err(dev, "failed to get reset-gpios: %d\n", ret); 1202 return ret; 1203 } 1204 1205 for (i = 0; i < OV5675_NUM_SUPPLIES; i++) 1206 ov5675->supplies[i].supply = ov5675_supply_names[i]; 1207 1208 ret = devm_regulator_bulk_get(dev, OV5675_NUM_SUPPLIES, 1209 ov5675->supplies); 1210 if (ret) 1211 return ret; 1212 1213 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 1214 if (!ep) 1215 return -ENXIO; 1216 1217 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 1218 fwnode_handle_put(ep); 1219 if (ret) 1220 return ret; 1221 1222 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV5675_DATA_LANES) { 1223 dev_err(dev, "number of CSI2 data lanes %d is not supported", 1224 bus_cfg.bus.mipi_csi2.num_data_lanes); 1225 ret = -EINVAL; 1226 goto check_hwcfg_error; 1227 } 1228 1229 if (!bus_cfg.nr_of_link_frequencies) { 1230 dev_err(dev, "no link frequencies defined"); 1231 ret = -EINVAL; 1232 goto check_hwcfg_error; 1233 } 1234 1235 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { 1236 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { 1237 if (link_freq_menu_items[i] == 1238 bus_cfg.link_frequencies[j]) 1239 break; 1240 } 1241 1242 if (j == bus_cfg.nr_of_link_frequencies) { 1243 dev_err(dev, "no link frequency %lld supported", 1244 link_freq_menu_items[i]); 1245 ret = -EINVAL; 1246 goto check_hwcfg_error; 1247 } 1248 } 1249 1250check_hwcfg_error: 1251 v4l2_fwnode_endpoint_free(&bus_cfg); 1252 1253 return ret; 1254} 1255 1256static void ov5675_remove(struct i2c_client *client) 1257{ 1258 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1259 struct ov5675 *ov5675 = to_ov5675(sd); 1260 1261 v4l2_async_unregister_subdev(sd); 1262 media_entity_cleanup(&sd->entity); 1263 v4l2_ctrl_handler_free(sd->ctrl_handler); 1264 pm_runtime_disable(ov5675->dev); 1265 mutex_destroy(&ov5675->mutex); 1266 1267 if (!pm_runtime_status_suspended(ov5675->dev)) 1268 ov5675_power_off(ov5675->dev); 1269 pm_runtime_set_suspended(ov5675->dev); 1270} 1271 1272static int ov5675_probe(struct i2c_client *client) 1273{ 1274 struct ov5675 *ov5675; 1275 bool full_power; 1276 int ret; 1277 1278 ov5675 = devm_kzalloc(&client->dev, sizeof(*ov5675), GFP_KERNEL); 1279 if (!ov5675) 1280 return -ENOMEM; 1281 1282 ov5675->dev = &client->dev; 1283 1284 ret = ov5675_get_hwcfg(ov5675); 1285 if (ret) 1286 return ret; 1287 1288 v4l2_i2c_subdev_init(&ov5675->sd, client, &ov5675_subdev_ops); 1289 1290 ret = ov5675_power_on(ov5675->dev); 1291 if (ret) { 1292 dev_err(ov5675->dev, "failed to power on: %d\n", ret); 1293 return ret; 1294 } 1295 1296 full_power = acpi_dev_state_d0(ov5675->dev); 1297 if (full_power) { 1298 ret = ov5675_identify_module(ov5675); 1299 if (ret) { 1300 dev_err(ov5675->dev, "failed to find sensor: %d", ret); 1301 goto probe_power_off; 1302 } 1303 } 1304 1305 mutex_init(&ov5675->mutex); 1306 ov5675->cur_mode = &supported_modes[0]; 1307 ret = ov5675_init_controls(ov5675); 1308 if (ret) { 1309 dev_err(ov5675->dev, "failed to init controls: %d", ret); 1310 goto probe_error_v4l2_ctrl_handler_free; 1311 } 1312 1313 ov5675->sd.internal_ops = &ov5675_internal_ops; 1314 ov5675->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1315 ov5675->sd.entity.ops = &ov5675_subdev_entity_ops; 1316 ov5675->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1317 ov5675->pad.flags = MEDIA_PAD_FL_SOURCE; 1318 ret = media_entity_pads_init(&ov5675->sd.entity, 1, &ov5675->pad); 1319 if (ret) { 1320 dev_err(ov5675->dev, "failed to init entity pads: %d", ret); 1321 goto probe_error_v4l2_ctrl_handler_free; 1322 } 1323 1324 ret = v4l2_async_register_subdev_sensor(&ov5675->sd); 1325 if (ret < 0) { 1326 dev_err(ov5675->dev, "failed to register V4L2 subdev: %d", 1327 ret); 1328 goto probe_error_media_entity_cleanup; 1329 } 1330 1331 /* Set the device's state to active if it's in D0 state. */ 1332 if (full_power) 1333 pm_runtime_set_active(ov5675->dev); 1334 pm_runtime_enable(ov5675->dev); 1335 pm_runtime_idle(ov5675->dev); 1336 1337 return 0; 1338 1339probe_error_media_entity_cleanup: 1340 media_entity_cleanup(&ov5675->sd.entity); 1341 1342probe_error_v4l2_ctrl_handler_free: 1343 v4l2_ctrl_handler_free(ov5675->sd.ctrl_handler); 1344 mutex_destroy(&ov5675->mutex); 1345probe_power_off: 1346 ov5675_power_off(ov5675->dev); 1347 1348 return ret; 1349} 1350 1351static const struct dev_pm_ops ov5675_pm_ops = { 1352 SET_RUNTIME_PM_OPS(ov5675_power_off, ov5675_power_on, NULL) 1353}; 1354 1355#ifdef CONFIG_ACPI 1356static const struct acpi_device_id ov5675_acpi_ids[] = { 1357 {"OVTI5675"}, 1358 {} 1359}; 1360 1361MODULE_DEVICE_TABLE(acpi, ov5675_acpi_ids); 1362#endif 1363 1364static const struct of_device_id ov5675_of_match[] = { 1365 { .compatible = "ovti,ov5675", }, 1366 { /* sentinel */ }, 1367}; 1368MODULE_DEVICE_TABLE(of, ov5675_of_match); 1369 1370static struct i2c_driver ov5675_i2c_driver = { 1371 .driver = { 1372 .name = "ov5675", 1373 .pm = &ov5675_pm_ops, 1374 .acpi_match_table = ACPI_PTR(ov5675_acpi_ids), 1375 .of_match_table = ov5675_of_match, 1376 }, 1377 .probe = ov5675_probe, 1378 .remove = ov5675_remove, 1379 .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE, 1380}; 1381 1382module_i2c_driver(ov5675_i2c_driver); 1383 1384MODULE_AUTHOR("Shawn Tu"); 1385MODULE_DESCRIPTION("OmniVision OV5675 sensor driver"); 1386MODULE_LICENSE("GPL v2");
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