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ov2740.c
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linux-6.19.14/drivers/media/i2c/ov2740.c
1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2020 Intel Corporation. 3 4#include <linux/acpi.h> 5#include <linux/clk.h> 6#include <linux/delay.h> 7#include <linux/gpio/consumer.h> 8#include <linux/i2c.h> 9#include <linux/module.h> 10#include <linux/nvmem-provider.h> 11#include <linux/pm_runtime.h> 12#include <linux/regmap.h> 13#include <linux/regulator/consumer.h> 14#include <linux/unaligned.h> 15#include <media/v4l2-ctrls.h> 16#include <media/v4l2-device.h> 17#include <media/v4l2-fwnode.h> 18 19#define OV2740_LINK_FREQ_360MHZ 360000000ULL 20#define OV2740_LINK_FREQ_180MHZ 180000000ULL 21#define OV2740_SCLK 72000000LL 22#define OV2740_MCLK 19200000 23#define OV2740_DATA_LANES 2 24#define OV2740_RGB_DEPTH 10 25 26#define OV2740_REG_CHIP_ID 0x300a 27#define OV2740_CHIP_ID 0x2740 28 29#define OV2740_REG_MODE_SELECT 0x0100 30#define OV2740_MODE_STANDBY 0x00 31#define OV2740_MODE_STREAMING 0x01 32 33/* vertical-timings from sensor */ 34#define OV2740_REG_VTS 0x380e 35 36/* horizontal-timings from sensor */ 37#define OV2740_REG_HTS 0x380c 38 39/* Exposure controls from sensor */ 40#define OV2740_REG_EXPOSURE 0x3500 41#define OV2740_EXPOSURE_MIN 4 42#define OV2740_EXPOSURE_MAX_MARGIN 8 43#define OV2740_EXPOSURE_STEP 1 44 45/* Analog gain controls from sensor */ 46#define OV2740_REG_ANALOG_GAIN 0x3508 47#define OV2740_ANAL_GAIN_MIN 128 48#define OV2740_ANAL_GAIN_MAX 1983 49#define OV2740_ANAL_GAIN_STEP 1 50 51/* Digital gain controls from sensor */ 52#define OV2740_REG_MWB_R_GAIN 0x500a 53#define OV2740_REG_MWB_G_GAIN 0x500c 54#define OV2740_REG_MWB_B_GAIN 0x500e 55#define OV2740_DGTL_GAIN_MIN 1024 56#define OV2740_DGTL_GAIN_MAX 4095 57#define OV2740_DGTL_GAIN_STEP 1 58#define OV2740_DGTL_GAIN_DEFAULT 1024 59 60/* Test Pattern Control */ 61#define OV2740_REG_TEST_PATTERN 0x5040 62#define OV2740_TEST_PATTERN_ENABLE BIT(7) 63#define OV2740_TEST_PATTERN_BAR_SHIFT 2 64 65/* Group Access */ 66#define OV2740_REG_GROUP_ACCESS 0x3208 67#define OV2740_GROUP_HOLD_START 0x0 68#define OV2740_GROUP_HOLD_END 0x10 69#define OV2740_GROUP_HOLD_LAUNCH 0xa0 70 71/* ISP CTRL00 */ 72#define OV2740_REG_ISP_CTRL00 0x5000 73/* ISP CTRL01 */ 74#define OV2740_REG_ISP_CTRL01 0x5001 75/* Customer Addresses: 0x7010 - 0x710F */ 76#define CUSTOMER_USE_OTP_SIZE 0x100 77/* OTP registers from sensor */ 78#define OV2740_REG_OTP_CUSTOMER 0x7010 79 80static const char * const ov2740_supply_name[] = { 81 "AVDD", 82 "DOVDD", 83 "DVDD", 84}; 85 86struct nvm_data { 87 struct nvmem_device *nvmem; 88 struct regmap *regmap; 89 char *nvm_buffer; 90}; 91 92enum { 93 OV2740_LINK_FREQ_360MHZ_INDEX, 94 OV2740_LINK_FREQ_180MHZ_INDEX, 95}; 96 97struct ov2740_reg { 98 u16 address; 99 u8 val; 100}; 101 102struct ov2740_reg_list { 103 u32 num_of_regs; 104 const struct ov2740_reg *regs; 105}; 106 107struct ov2740_link_freq_config { 108 const struct ov2740_reg_list reg_list; 109}; 110 111struct ov2740_mode { 112 /* Frame width in pixels */ 113 u32 width; 114 115 /* Frame height in pixels */ 116 u32 height; 117 118 /* Horizontal timining size */ 119 u32 hts; 120 121 /* Default vertical timining size */ 122 u32 vts_def; 123 124 /* Min vertical timining size */ 125 u32 vts_min; 126 127 /* Max vertical timining size */ 128 u32 vts_max; 129 130 /* Link frequency needed for this resolution */ 131 u32 link_freq_index; 132 133 /* Sensor register settings for this resolution */ 134 const struct ov2740_reg_list reg_list; 135}; 136 137static const struct ov2740_reg mipi_data_rate_720mbps[] = { 138 {0x0302, 0x4b}, 139 {0x030d, 0x4b}, 140 {0x030e, 0x02}, 141 {0x030a, 0x01}, 142 {0x0312, 0x11}, 143}; 144 145static const struct ov2740_reg mipi_data_rate_360mbps[] = { 146 {0x0302, 0x4b}, 147 {0x0303, 0x01}, 148 {0x030d, 0x4b}, 149 {0x030e, 0x02}, 150 {0x030a, 0x01}, 151 {0x0312, 0x11}, 152 {0x4837, 0x2c}, 153}; 154 155static const struct ov2740_reg mode_1932x1092_regs_360mhz[] = { 156 {0x3000, 0x00}, 157 {0x3018, 0x32}, 158 {0x3031, 0x0a}, 159 {0x3080, 0x08}, 160 {0x3083, 0xB4}, 161 {0x3103, 0x00}, 162 {0x3104, 0x01}, 163 {0x3106, 0x01}, 164 {0x3500, 0x00}, 165 {0x3501, 0x44}, 166 {0x3502, 0x40}, 167 {0x3503, 0x88}, 168 {0x3507, 0x00}, 169 {0x3508, 0x00}, 170 {0x3509, 0x80}, 171 {0x350c, 0x00}, 172 {0x350d, 0x80}, 173 {0x3510, 0x00}, 174 {0x3511, 0x00}, 175 {0x3512, 0x20}, 176 {0x3632, 0x00}, 177 {0x3633, 0x10}, 178 {0x3634, 0x10}, 179 {0x3635, 0x10}, 180 {0x3645, 0x13}, 181 {0x3646, 0x81}, 182 {0x3636, 0x10}, 183 {0x3651, 0x0a}, 184 {0x3656, 0x02}, 185 {0x3659, 0x04}, 186 {0x365a, 0xda}, 187 {0x365b, 0xa2}, 188 {0x365c, 0x04}, 189 {0x365d, 0x1d}, 190 {0x365e, 0x1a}, 191 {0x3662, 0xd7}, 192 {0x3667, 0x78}, 193 {0x3669, 0x0a}, 194 {0x366a, 0x92}, 195 {0x3700, 0x54}, 196 {0x3702, 0x10}, 197 {0x3706, 0x42}, 198 {0x3709, 0x30}, 199 {0x370b, 0xc2}, 200 {0x3714, 0x63}, 201 {0x3715, 0x01}, 202 {0x3716, 0x00}, 203 {0x371a, 0x3e}, 204 {0x3732, 0x0e}, 205 {0x3733, 0x10}, 206 {0x375f, 0x0e}, 207 {0x3768, 0x30}, 208 {0x3769, 0x44}, 209 {0x376a, 0x22}, 210 {0x377b, 0x20}, 211 {0x377c, 0x00}, 212 {0x377d, 0x0c}, 213 {0x3798, 0x00}, 214 {0x37a1, 0x55}, 215 {0x37a8, 0x6d}, 216 {0x37c2, 0x04}, 217 {0x37c5, 0x00}, 218 {0x37c8, 0x00}, 219 {0x3800, 0x00}, 220 {0x3801, 0x00}, 221 {0x3802, 0x00}, 222 {0x3803, 0x00}, 223 {0x3804, 0x07}, 224 {0x3805, 0x8f}, 225 {0x3806, 0x04}, 226 {0x3807, 0x47}, 227 {0x3808, 0x07}, 228 {0x3809, 0x88}, 229 {0x380a, 0x04}, 230 {0x380b, 0x40}, 231 {0x380c, 0x04}, 232 {0x380d, 0x38}, 233 {0x380e, 0x04}, 234 {0x380f, 0x60}, 235 {0x3810, 0x00}, 236 {0x3811, 0x04}, 237 {0x3812, 0x00}, 238 {0x3813, 0x04}, 239 {0x3814, 0x01}, 240 {0x3815, 0x01}, 241 {0x3820, 0x80}, 242 {0x3821, 0x46}, 243 {0x3822, 0x84}, 244 {0x3829, 0x00}, 245 {0x382a, 0x01}, 246 {0x382b, 0x01}, 247 {0x3830, 0x04}, 248 {0x3836, 0x01}, 249 {0x3837, 0x08}, 250 {0x3839, 0x01}, 251 {0x383a, 0x00}, 252 {0x383b, 0x08}, 253 {0x383c, 0x00}, 254 {0x3f0b, 0x00}, 255 {0x4001, 0x20}, 256 {0x4009, 0x07}, 257 {0x4003, 0x10}, 258 {0x4010, 0xe0}, 259 {0x4016, 0x00}, 260 {0x4017, 0x10}, 261 {0x4044, 0x02}, 262 {0x4304, 0x08}, 263 {0x4307, 0x30}, 264 {0x4320, 0x80}, 265 {0x4322, 0x00}, 266 {0x4323, 0x00}, 267 {0x4324, 0x00}, 268 {0x4325, 0x00}, 269 {0x4326, 0x00}, 270 {0x4327, 0x00}, 271 {0x4328, 0x00}, 272 {0x4329, 0x00}, 273 {0x432c, 0x03}, 274 {0x432d, 0x81}, 275 {0x4501, 0x84}, 276 {0x4502, 0x40}, 277 {0x4503, 0x18}, 278 {0x4504, 0x04}, 279 {0x4508, 0x02}, 280 {0x4601, 0x10}, 281 {0x4800, 0x00}, 282 {0x4816, 0x52}, 283 {0x4837, 0x16}, 284 {0x5000, 0x7f}, 285 {0x5001, 0x00}, 286 {0x5005, 0x38}, 287 {0x501e, 0x0d}, 288 {0x5040, 0x00}, 289 {0x5901, 0x00}, 290 {0x3800, 0x00}, 291 {0x3801, 0x00}, 292 {0x3802, 0x00}, 293 {0x3803, 0x00}, 294 {0x3804, 0x07}, 295 {0x3805, 0x8f}, 296 {0x3806, 0x04}, 297 {0x3807, 0x47}, 298 {0x3808, 0x07}, 299 {0x3809, 0x8c}, 300 {0x380a, 0x04}, 301 {0x380b, 0x44}, 302 {0x3810, 0x00}, 303 {0x3811, 0x00}, 304 {0x3812, 0x00}, 305 {0x3813, 0x01}, 306}; 307 308static const struct ov2740_reg mode_1932x1092_regs_180mhz[] = { 309 {0x3000, 0x00}, 310 {0x3018, 0x32}, /* 0x32 for 2 lanes, 0x12 for 1 lane */ 311 {0x3031, 0x0a}, 312 {0x3080, 0x08}, 313 {0x3083, 0xB4}, 314 {0x3103, 0x00}, 315 {0x3104, 0x01}, 316 {0x3106, 0x01}, 317 {0x3500, 0x00}, 318 {0x3501, 0x44}, 319 {0x3502, 0x40}, 320 {0x3503, 0x88}, 321 {0x3507, 0x00}, 322 {0x3508, 0x00}, 323 {0x3509, 0x80}, 324 {0x350c, 0x00}, 325 {0x350d, 0x80}, 326 {0x3510, 0x00}, 327 {0x3511, 0x00}, 328 {0x3512, 0x20}, 329 {0x3632, 0x00}, 330 {0x3633, 0x10}, 331 {0x3634, 0x10}, 332 {0x3635, 0x10}, 333 {0x3645, 0x13}, 334 {0x3646, 0x81}, 335 {0x3636, 0x10}, 336 {0x3651, 0x0a}, 337 {0x3656, 0x02}, 338 {0x3659, 0x04}, 339 {0x365a, 0xda}, 340 {0x365b, 0xa2}, 341 {0x365c, 0x04}, 342 {0x365d, 0x1d}, 343 {0x365e, 0x1a}, 344 {0x3662, 0xd7}, 345 {0x3667, 0x78}, 346 {0x3669, 0x0a}, 347 {0x366a, 0x92}, 348 {0x3700, 0x54}, 349 {0x3702, 0x10}, 350 {0x3706, 0x42}, 351 {0x3709, 0x30}, 352 {0x370b, 0xc2}, 353 {0x3714, 0x63}, 354 {0x3715, 0x01}, 355 {0x3716, 0x00}, 356 {0x371a, 0x3e}, 357 {0x3732, 0x0e}, 358 {0x3733, 0x10}, 359 {0x375f, 0x0e}, 360 {0x3768, 0x30}, 361 {0x3769, 0x44}, 362 {0x376a, 0x22}, 363 {0x377b, 0x20}, 364 {0x377c, 0x00}, 365 {0x377d, 0x0c}, 366 {0x3798, 0x00}, 367 {0x37a1, 0x55}, 368 {0x37a8, 0x6d}, 369 {0x37c2, 0x04}, 370 {0x37c5, 0x00}, 371 {0x37c8, 0x00}, 372 {0x3800, 0x00}, 373 {0x3801, 0x00}, 374 {0x3802, 0x00}, 375 {0x3803, 0x00}, 376 {0x3804, 0x07}, 377 {0x3805, 0x8f}, 378 {0x3806, 0x04}, 379 {0x3807, 0x47}, 380 {0x3808, 0x07}, 381 {0x3809, 0x88}, 382 {0x380a, 0x04}, 383 {0x380b, 0x40}, 384 {0x380c, 0x08}, 385 {0x380d, 0x70}, 386 {0x380e, 0x04}, 387 {0x380f, 0x56}, 388 {0x3810, 0x00}, 389 {0x3811, 0x04}, 390 {0x3812, 0x00}, 391 {0x3813, 0x04}, 392 {0x3814, 0x01}, 393 {0x3815, 0x01}, 394 {0x3820, 0x80}, 395 {0x3821, 0x46}, 396 {0x3822, 0x84}, 397 {0x3829, 0x00}, 398 {0x382a, 0x01}, 399 {0x382b, 0x01}, 400 {0x3830, 0x04}, 401 {0x3836, 0x01}, 402 {0x3837, 0x08}, 403 {0x3839, 0x01}, 404 {0x383a, 0x00}, 405 {0x383b, 0x08}, 406 {0x383c, 0x00}, 407 {0x3f0b, 0x00}, 408 {0x4001, 0x20}, 409 {0x4009, 0x07}, 410 {0x4003, 0x10}, 411 {0x4010, 0xe0}, 412 {0x4016, 0x00}, 413 {0x4017, 0x10}, 414 {0x4044, 0x02}, 415 {0x4304, 0x08}, 416 {0x4307, 0x30}, 417 {0x4320, 0x80}, 418 {0x4322, 0x00}, 419 {0x4323, 0x00}, 420 {0x4324, 0x00}, 421 {0x4325, 0x00}, 422 {0x4326, 0x00}, 423 {0x4327, 0x00}, 424 {0x4328, 0x00}, 425 {0x4329, 0x00}, 426 {0x432c, 0x03}, 427 {0x432d, 0x81}, 428 {0x4501, 0x84}, 429 {0x4502, 0x40}, 430 {0x4503, 0x18}, 431 {0x4504, 0x04}, 432 {0x4508, 0x02}, 433 {0x4601, 0x10}, 434 {0x4800, 0x00}, 435 {0x4816, 0x52}, 436 {0x5000, 0x73}, /* 0x7f enable DPC */ 437 {0x5001, 0x00}, 438 {0x5005, 0x38}, 439 {0x501e, 0x0d}, 440 {0x5040, 0x00}, 441 {0x5901, 0x00}, 442 {0x3800, 0x00}, 443 {0x3801, 0x00}, 444 {0x3802, 0x00}, 445 {0x3803, 0x00}, 446 {0x3804, 0x07}, 447 {0x3805, 0x8f}, 448 {0x3806, 0x04}, 449 {0x3807, 0x47}, 450 {0x3808, 0x07}, 451 {0x3809, 0x8c}, 452 {0x380a, 0x04}, 453 {0x380b, 0x44}, 454 {0x3810, 0x00}, 455 {0x3811, 0x00}, 456 {0x3812, 0x00}, 457 {0x3813, 0x01}, 458 {0x4003, 0x40}, /* set Black level to 0x40 */ 459}; 460 461static const char * const ov2740_test_pattern_menu[] = { 462 "Disabled", 463 "Color Bar", 464 "Top-Bottom Darker Color Bar", 465 "Right-Left Darker Color Bar", 466 "Bottom-Top Darker Color Bar", 467}; 468 469static const s64 link_freq_menu_items[] = { 470 OV2740_LINK_FREQ_360MHZ, 471 OV2740_LINK_FREQ_180MHZ, 472}; 473 474static const struct ov2740_link_freq_config link_freq_configs[] = { 475 [OV2740_LINK_FREQ_360MHZ_INDEX] = { 476 .reg_list = { 477 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps), 478 .regs = mipi_data_rate_720mbps, 479 } 480 }, 481 [OV2740_LINK_FREQ_180MHZ_INDEX] = { 482 .reg_list = { 483 .num_of_regs = ARRAY_SIZE(mipi_data_rate_360mbps), 484 .regs = mipi_data_rate_360mbps, 485 } 486 }, 487}; 488 489static const struct ov2740_mode supported_modes_360mhz[] = { 490 { 491 .width = 1932, 492 .height = 1092, 493 .hts = 2160, 494 .vts_min = 1120, 495 .vts_def = 2186, 496 .vts_max = 32767, 497 .reg_list = { 498 .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs_360mhz), 499 .regs = mode_1932x1092_regs_360mhz, 500 }, 501 .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX, 502 }, 503}; 504 505static const struct ov2740_mode supported_modes_180mhz[] = { 506 { 507 .width = 1932, 508 .height = 1092, 509 .hts = 2160, 510 .vts_min = 1110, 511 .vts_def = 1110, 512 .vts_max = 2047, 513 .reg_list = { 514 .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs_180mhz), 515 .regs = mode_1932x1092_regs_180mhz, 516 }, 517 .link_freq_index = OV2740_LINK_FREQ_180MHZ_INDEX, 518 }, 519}; 520 521struct ov2740 { 522 struct device *dev; 523 524 struct v4l2_subdev sd; 525 struct media_pad pad; 526 struct v4l2_ctrl_handler ctrl_handler; 527 528 /* V4L2 Controls */ 529 struct v4l2_ctrl *link_freq; 530 struct v4l2_ctrl *pixel_rate; 531 struct v4l2_ctrl *vblank; 532 struct v4l2_ctrl *hblank; 533 struct v4l2_ctrl *exposure; 534 535 /* GPIOs, clocks, regulators */ 536 struct gpio_desc *reset_gpio; 537 struct gpio_desc *powerdown_gpio; 538 struct clk *clk; 539 struct regulator_bulk_data supplies[ARRAY_SIZE(ov2740_supply_name)]; 540 541 /* Current mode */ 542 const struct ov2740_mode *cur_mode; 543 544 /* NVM data information */ 545 struct nvm_data *nvm; 546 547 /* Supported modes */ 548 const struct ov2740_mode *supported_modes; 549 int supported_modes_count; 550 551 /* True if the device has been identified */ 552 bool identified; 553}; 554 555static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev) 556{ 557 return container_of(subdev, struct ov2740, sd); 558} 559 560static u64 to_pixel_rate(u32 f_index) 561{ 562 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES; 563 564 do_div(pixel_rate, OV2740_RGB_DEPTH); 565 566 return pixel_rate; 567} 568 569static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val) 570{ 571 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 572 struct i2c_msg msgs[2]; 573 u8 addr_buf[2]; 574 u8 data_buf[4] = {0}; 575 int ret; 576 577 if (len > sizeof(data_buf)) 578 return -EINVAL; 579 580 put_unaligned_be16(reg, addr_buf); 581 msgs[0].addr = client->addr; 582 msgs[0].flags = 0; 583 msgs[0].len = sizeof(addr_buf); 584 msgs[0].buf = addr_buf; 585 msgs[1].addr = client->addr; 586 msgs[1].flags = I2C_M_RD; 587 msgs[1].len = len; 588 msgs[1].buf = &data_buf[sizeof(data_buf) - len]; 589 590 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 591 if (ret != ARRAY_SIZE(msgs)) 592 return ret < 0 ? ret : -EIO; 593 594 *val = get_unaligned_be32(data_buf); 595 596 return 0; 597} 598 599static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val) 600{ 601 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 602 u8 buf[6]; 603 int ret; 604 605 if (len > 4) 606 return -EINVAL; 607 608 put_unaligned_be16(reg, buf); 609 put_unaligned_be32(val << 8 * (4 - len), buf + 2); 610 611 ret = i2c_master_send(client, buf, len + 2); 612 if (ret != len + 2) 613 return ret < 0 ? ret : -EIO; 614 615 return 0; 616} 617 618static int ov2740_write_reg_list(struct ov2740 *ov2740, 619 const struct ov2740_reg_list *r_list) 620{ 621 unsigned int i; 622 int ret; 623 624 for (i = 0; i < r_list->num_of_regs; i++) { 625 ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1, 626 r_list->regs[i].val); 627 if (ret) { 628 dev_err_ratelimited(ov2740->dev, 629 "write reg 0x%4.4x return err = %d\n", 630 r_list->regs[i].address, ret); 631 return ret; 632 } 633 } 634 635 return 0; 636} 637 638static int ov2740_identify_module(struct ov2740 *ov2740) 639{ 640 int ret; 641 u32 val; 642 643 if (ov2740->identified) 644 return 0; 645 646 ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val); 647 if (ret) 648 return ret; 649 650 if (val != OV2740_CHIP_ID) { 651 dev_err(ov2740->dev, "chip id mismatch: %x != %x\n", 652 OV2740_CHIP_ID, val); 653 return -ENXIO; 654 } 655 656 dev_dbg(ov2740->dev, "chip id: 0x%x\n", val); 657 658 ov2740->identified = true; 659 660 return 0; 661} 662 663static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain) 664{ 665 int ret; 666 667 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 668 OV2740_GROUP_HOLD_START); 669 if (ret) 670 return ret; 671 672 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain); 673 if (ret) 674 return ret; 675 676 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain); 677 if (ret) 678 return ret; 679 680 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain); 681 if (ret) 682 return ret; 683 684 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 685 OV2740_GROUP_HOLD_END); 686 if (ret) 687 return ret; 688 689 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 690 OV2740_GROUP_HOLD_LAUNCH); 691 return ret; 692} 693 694static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern) 695{ 696 if (pattern) 697 pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT | 698 OV2740_TEST_PATTERN_ENABLE; 699 700 return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern); 701} 702 703static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl) 704{ 705 struct ov2740 *ov2740 = container_of(ctrl->handler, 706 struct ov2740, ctrl_handler); 707 s64 exposure_max; 708 int ret; 709 710 /* Propagate change of current control to all related controls */ 711 if (ctrl->id == V4L2_CID_VBLANK) { 712 /* Update max exposure while meeting expected vblanking */ 713 exposure_max = ov2740->cur_mode->height + ctrl->val - 714 OV2740_EXPOSURE_MAX_MARGIN; 715 __v4l2_ctrl_modify_range(ov2740->exposure, 716 ov2740->exposure->minimum, 717 exposure_max, ov2740->exposure->step, 718 exposure_max); 719 } 720 721 /* V4L2 controls values will be applied only when power is already up */ 722 if (!pm_runtime_get_if_in_use(ov2740->dev)) 723 return 0; 724 725 switch (ctrl->id) { 726 case V4L2_CID_ANALOGUE_GAIN: 727 ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2, 728 ctrl->val); 729 break; 730 731 case V4L2_CID_DIGITAL_GAIN: 732 ret = ov2740_update_digital_gain(ov2740, ctrl->val); 733 break; 734 735 case V4L2_CID_EXPOSURE: 736 /* 4 least significant bits of expsoure are fractional part */ 737 ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3, 738 ctrl->val << 4); 739 break; 740 741 case V4L2_CID_VBLANK: 742 ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2, 743 ov2740->cur_mode->height + ctrl->val); 744 break; 745 746 case V4L2_CID_TEST_PATTERN: 747 ret = ov2740_test_pattern(ov2740, ctrl->val); 748 break; 749 750 default: 751 ret = -EINVAL; 752 break; 753 } 754 755 pm_runtime_put(ov2740->dev); 756 757 return ret; 758} 759 760static const struct v4l2_ctrl_ops ov2740_ctrl_ops = { 761 .s_ctrl = ov2740_set_ctrl, 762}; 763 764static int ov2740_init_controls(struct ov2740 *ov2740) 765{ 766 struct v4l2_ctrl_handler *ctrl_hdlr; 767 s64 exposure_max, h_blank, pixel_rate; 768 u32 vblank_min, vblank_max, vblank_default; 769 struct v4l2_fwnode_device_properties props; 770 int ret; 771 772 ctrl_hdlr = &ov2740->ctrl_handler; 773 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10); 774 if (ret) 775 return ret; 776 777 ov2740->link_freq = 778 v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops, 779 V4L2_CID_LINK_FREQ, 780 ARRAY_SIZE(link_freq_menu_items) - 1, 781 ov2740->supported_modes->link_freq_index, 782 link_freq_menu_items); 783 if (ov2740->link_freq) 784 ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 785 786 pixel_rate = to_pixel_rate(ov2740->supported_modes->link_freq_index); 787 ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 788 V4L2_CID_PIXEL_RATE, 0, 789 pixel_rate, 1, pixel_rate); 790 791 vblank_min = ov2740->cur_mode->vts_min - ov2740->cur_mode->height; 792 vblank_max = ov2740->cur_mode->vts_max - ov2740->cur_mode->height; 793 vblank_default = ov2740->cur_mode->vts_def - ov2740->cur_mode->height; 794 ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 795 V4L2_CID_VBLANK, vblank_min, 796 vblank_max, 1, vblank_default); 797 798 h_blank = ov2740->cur_mode->hts - ov2740->cur_mode->width; 799 ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 800 V4L2_CID_HBLANK, h_blank, h_blank, 1, 801 h_blank); 802 if (ov2740->hblank) 803 ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 804 805 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 806 OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX, 807 OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN); 808 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 809 OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX, 810 OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT); 811 exposure_max = ov2740->cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN; 812 ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 813 V4L2_CID_EXPOSURE, 814 OV2740_EXPOSURE_MIN, exposure_max, 815 OV2740_EXPOSURE_STEP, 816 exposure_max); 817 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops, 818 V4L2_CID_TEST_PATTERN, 819 ARRAY_SIZE(ov2740_test_pattern_menu) - 1, 820 0, 0, ov2740_test_pattern_menu); 821 822 ret = v4l2_fwnode_device_parse(ov2740->dev, &props); 823 if (ret) { 824 v4l2_ctrl_handler_free(ctrl_hdlr); 825 return ret; 826 } 827 828 v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov2740_ctrl_ops, &props); 829 830 if (ctrl_hdlr->error) { 831 v4l2_ctrl_handler_free(ctrl_hdlr); 832 return ctrl_hdlr->error; 833 } 834 835 ov2740->sd.ctrl_handler = ctrl_hdlr; 836 837 return 0; 838} 839 840static void ov2740_update_pad_format(const struct ov2740_mode *mode, 841 struct v4l2_mbus_framefmt *fmt) 842{ 843 fmt->width = mode->width; 844 fmt->height = mode->height; 845 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; 846 fmt->field = V4L2_FIELD_NONE; 847} 848 849static int ov2740_load_otp_data(struct nvm_data *nvm) 850{ 851 struct device *dev = regmap_get_device(nvm->regmap); 852 struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev)); 853 u32 isp_ctrl00 = 0; 854 u32 isp_ctrl01 = 0; 855 int ret; 856 857 if (nvm->nvm_buffer) 858 return 0; 859 860 nvm->nvm_buffer = kzalloc(CUSTOMER_USE_OTP_SIZE, GFP_KERNEL); 861 if (!nvm->nvm_buffer) 862 return -ENOMEM; 863 864 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00); 865 if (ret) { 866 dev_err(dev, "failed to read ISP CTRL00\n"); 867 goto err; 868 } 869 870 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01); 871 if (ret) { 872 dev_err(dev, "failed to read ISP CTRL01\n"); 873 goto err; 874 } 875 876 /* Clear bit 5 of ISP CTRL00 */ 877 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, 878 isp_ctrl00 & ~BIT(5)); 879 if (ret) { 880 dev_err(dev, "failed to set ISP CTRL00\n"); 881 goto err; 882 } 883 884 /* Clear bit 7 of ISP CTRL01 */ 885 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, 886 isp_ctrl01 & ~BIT(7)); 887 if (ret) { 888 dev_err(dev, "failed to set ISP CTRL01\n"); 889 goto err; 890 } 891 892 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 893 OV2740_MODE_STREAMING); 894 if (ret) { 895 dev_err(dev, "failed to set streaming mode\n"); 896 goto err; 897 } 898 899 /* 900 * Users are not allowed to access OTP-related registers and memory 901 * during the 20 ms period after streaming starts (0x100 = 0x01). 902 */ 903 msleep(20); 904 905 ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER, 906 nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE); 907 if (ret) { 908 dev_err(dev, "failed to read OTP data, ret %d\n", ret); 909 goto err; 910 } 911 912 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 913 OV2740_MODE_STANDBY); 914 if (ret) { 915 dev_err(dev, "failed to set streaming mode\n"); 916 goto err; 917 } 918 919 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01); 920 if (ret) { 921 dev_err(dev, "failed to set ISP CTRL01\n"); 922 goto err; 923 } 924 925 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00); 926 if (ret) { 927 dev_err(dev, "failed to set ISP CTRL00\n"); 928 goto err; 929 } 930 931 return 0; 932err: 933 kfree(nvm->nvm_buffer); 934 nvm->nvm_buffer = NULL; 935 936 return ret; 937} 938 939static int ov2740_start_streaming(struct ov2740 *ov2740) 940{ 941 const struct ov2740_reg_list *reg_list; 942 int link_freq_index; 943 int ret; 944 945 ret = ov2740_identify_module(ov2740); 946 if (ret) 947 return ret; 948 949 if (ov2740->nvm) 950 ov2740_load_otp_data(ov2740->nvm); 951 952 /* Reset the sensor */ 953 ret = ov2740_write_reg(ov2740, 0x0103, 1, 0x01); 954 if (ret) { 955 dev_err(ov2740->dev, "failed to reset\n"); 956 return ret; 957 } 958 959 usleep_range(10000, 15000); 960 961 link_freq_index = ov2740->cur_mode->link_freq_index; 962 reg_list = &link_freq_configs[link_freq_index].reg_list; 963 ret = ov2740_write_reg_list(ov2740, reg_list); 964 if (ret) { 965 dev_err(ov2740->dev, "failed to set plls\n"); 966 return ret; 967 } 968 969 reg_list = &ov2740->cur_mode->reg_list; 970 ret = ov2740_write_reg_list(ov2740, reg_list); 971 if (ret) { 972 dev_err(ov2740->dev, "failed to set mode\n"); 973 return ret; 974 } 975 976 ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler); 977 if (ret) 978 return ret; 979 980 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 981 OV2740_MODE_STREAMING); 982 if (ret) 983 dev_err(ov2740->dev, "failed to start streaming\n"); 984 985 return ret; 986} 987 988static void ov2740_stop_streaming(struct ov2740 *ov2740) 989{ 990 if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 991 OV2740_MODE_STANDBY)) 992 dev_err(ov2740->dev, "failed to stop streaming\n"); 993} 994 995static int ov2740_set_stream(struct v4l2_subdev *sd, int enable) 996{ 997 struct ov2740 *ov2740 = to_ov2740(sd); 998 struct v4l2_subdev_state *sd_state; 999 int ret = 0; 1000 1001 sd_state = v4l2_subdev_lock_and_get_active_state(&ov2740->sd); 1002 1003 if (enable) { 1004 ret = pm_runtime_resume_and_get(ov2740->dev); 1005 if (ret < 0) 1006 goto out_unlock; 1007 1008 ret = ov2740_start_streaming(ov2740); 1009 if (ret) { 1010 enable = 0; 1011 ov2740_stop_streaming(ov2740); 1012 pm_runtime_put(ov2740->dev); 1013 } 1014 } else { 1015 ov2740_stop_streaming(ov2740); 1016 pm_runtime_put(ov2740->dev); 1017 } 1018 1019out_unlock: 1020 v4l2_subdev_unlock_state(sd_state); 1021 1022 return ret; 1023} 1024 1025static int ov2740_set_format(struct v4l2_subdev *sd, 1026 struct v4l2_subdev_state *sd_state, 1027 struct v4l2_subdev_format *fmt) 1028{ 1029 struct ov2740 *ov2740 = to_ov2740(sd); 1030 const struct ov2740_mode *mode; 1031 s32 vblank_def, h_blank; 1032 1033 mode = v4l2_find_nearest_size(ov2740->supported_modes, 1034 ov2740->supported_modes_count, 1035 width, height, 1036 fmt->format.width, fmt->format.height); 1037 1038 ov2740_update_pad_format(mode, &fmt->format); 1039 *v4l2_subdev_state_get_format(sd_state, fmt->pad) = fmt->format; 1040 1041 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 1042 return 0; 1043 1044 ov2740->cur_mode = mode; 1045 __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index); 1046 __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate, 1047 to_pixel_rate(mode->link_freq_index)); 1048 1049 /* Update limits and set FPS to default */ 1050 vblank_def = mode->vts_def - mode->height; 1051 __v4l2_ctrl_modify_range(ov2740->vblank, 1052 mode->vts_min - mode->height, 1053 mode->vts_max - mode->height, 1, vblank_def); 1054 __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def); 1055 h_blank = mode->hts - mode->width; 1056 __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1, h_blank); 1057 1058 return 0; 1059} 1060 1061static int ov2740_enum_mbus_code(struct v4l2_subdev *sd, 1062 struct v4l2_subdev_state *sd_state, 1063 struct v4l2_subdev_mbus_code_enum *code) 1064{ 1065 if (code->index > 0) 1066 return -EINVAL; 1067 1068 code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 1069 1070 return 0; 1071} 1072 1073static int ov2740_enum_frame_size(struct v4l2_subdev *sd, 1074 struct v4l2_subdev_state *sd_state, 1075 struct v4l2_subdev_frame_size_enum *fse) 1076{ 1077 struct ov2740 *ov2740 = to_ov2740(sd); 1078 const struct ov2740_mode *supported_modes = ov2740->supported_modes; 1079 1080 if (fse->index >= ov2740->supported_modes_count) 1081 return -EINVAL; 1082 1083 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 1084 return -EINVAL; 1085 1086 fse->min_width = supported_modes[fse->index].width; 1087 fse->max_width = fse->min_width; 1088 fse->min_height = supported_modes[fse->index].height; 1089 fse->max_height = fse->min_height; 1090 1091 return 0; 1092} 1093 1094static int ov2740_init_state(struct v4l2_subdev *sd, 1095 struct v4l2_subdev_state *sd_state) 1096{ 1097 struct ov2740 *ov2740 = to_ov2740(sd); 1098 1099 ov2740_update_pad_format(&ov2740->supported_modes[0], 1100 v4l2_subdev_state_get_format(sd_state, 0)); 1101 return 0; 1102} 1103 1104static const struct v4l2_subdev_video_ops ov2740_video_ops = { 1105 .s_stream = ov2740_set_stream, 1106}; 1107 1108static const struct v4l2_subdev_pad_ops ov2740_pad_ops = { 1109 .get_fmt = v4l2_subdev_get_fmt, 1110 .set_fmt = ov2740_set_format, 1111 .enum_mbus_code = ov2740_enum_mbus_code, 1112 .enum_frame_size = ov2740_enum_frame_size, 1113}; 1114 1115static const struct v4l2_subdev_ops ov2740_subdev_ops = { 1116 .video = &ov2740_video_ops, 1117 .pad = &ov2740_pad_ops, 1118}; 1119 1120static const struct v4l2_subdev_internal_ops ov2740_internal_ops = { 1121 .init_state = ov2740_init_state, 1122}; 1123 1124static const struct media_entity_operations ov2740_subdev_entity_ops = { 1125 .link_validate = v4l2_subdev_link_validate, 1126}; 1127 1128static int ov2740_check_hwcfg(struct ov2740 *ov2740) 1129{ 1130 struct device *dev = ov2740->dev; 1131 struct fwnode_handle *ep; 1132 struct fwnode_handle *fwnode = dev_fwnode(dev); 1133 struct v4l2_fwnode_endpoint bus_cfg = { 1134 .bus_type = V4L2_MBUS_CSI2_DPHY 1135 }; 1136 int ret; 1137 unsigned int i, j; 1138 1139 /* 1140 * Sometimes the fwnode graph is initialized by the bridge driver, 1141 * wait for this. 1142 */ 1143 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 1144 if (!ep) 1145 return dev_err_probe(dev, -EPROBE_DEFER, 1146 "waiting for fwnode graph endpoint\n"); 1147 1148 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 1149 fwnode_handle_put(ep); 1150 if (ret) 1151 return dev_err_probe(dev, ret, "parsing endpoint failed\n"); 1152 1153 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) { 1154 ret = dev_err_probe(dev, -EINVAL, 1155 "number of CSI2 data lanes %d is not supported\n", 1156 bus_cfg.bus.mipi_csi2.num_data_lanes); 1157 goto check_hwcfg_error; 1158 } 1159 1160 if (!bus_cfg.nr_of_link_frequencies) { 1161 ret = dev_err_probe(dev, -EINVAL, "no link frequencies defined\n"); 1162 goto check_hwcfg_error; 1163 } 1164 1165 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { 1166 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { 1167 if (link_freq_menu_items[i] == 1168 bus_cfg.link_frequencies[j]) 1169 break; 1170 } 1171 1172 if (j == bus_cfg.nr_of_link_frequencies) 1173 continue; 1174 1175 switch (i) { 1176 case OV2740_LINK_FREQ_360MHZ_INDEX: 1177 ov2740->supported_modes = supported_modes_360mhz; 1178 ov2740->supported_modes_count = 1179 ARRAY_SIZE(supported_modes_360mhz); 1180 break; 1181 case OV2740_LINK_FREQ_180MHZ_INDEX: 1182 ov2740->supported_modes = supported_modes_180mhz; 1183 ov2740->supported_modes_count = 1184 ARRAY_SIZE(supported_modes_180mhz); 1185 break; 1186 } 1187 1188 break; /* Prefer modes from first available link-freq */ 1189 } 1190 1191 if (!ov2740->supported_modes) 1192 ret = dev_err_probe(dev, -EINVAL, 1193 "no supported link frequencies\n"); 1194 1195check_hwcfg_error: 1196 v4l2_fwnode_endpoint_free(&bus_cfg); 1197 1198 return ret; 1199} 1200 1201static void ov2740_remove(struct i2c_client *client) 1202{ 1203 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1204 1205 v4l2_async_unregister_subdev(sd); 1206 media_entity_cleanup(&sd->entity); 1207 v4l2_subdev_cleanup(sd); 1208 v4l2_ctrl_handler_free(sd->ctrl_handler); 1209 pm_runtime_disable(&client->dev); 1210} 1211 1212static int ov2740_nvmem_read(void *priv, unsigned int off, void *val, 1213 size_t count) 1214{ 1215 struct nvm_data *nvm = priv; 1216 struct device *dev = regmap_get_device(nvm->regmap); 1217 struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev)); 1218 struct v4l2_subdev_state *sd_state; 1219 int ret = 0; 1220 1221 /* Serialise sensor access */ 1222 sd_state = v4l2_subdev_lock_and_get_active_state(&ov2740->sd); 1223 1224 if (nvm->nvm_buffer) { 1225 memcpy(val, nvm->nvm_buffer + off, count); 1226 goto exit; 1227 } 1228 1229 ret = pm_runtime_resume_and_get(dev); 1230 if (ret < 0) { 1231 goto exit; 1232 } 1233 1234 ret = ov2740_load_otp_data(nvm); 1235 if (!ret) 1236 memcpy(val, nvm->nvm_buffer + off, count); 1237 1238 pm_runtime_put(dev); 1239exit: 1240 v4l2_subdev_unlock_state(sd_state); 1241 return ret; 1242} 1243 1244static int ov2740_register_nvmem(struct i2c_client *client, 1245 struct ov2740 *ov2740) 1246{ 1247 struct nvm_data *nvm; 1248 struct regmap_config regmap_config = { }; 1249 struct nvmem_config nvmem_config = { }; 1250 struct regmap *regmap; 1251 struct device *dev = ov2740->dev; 1252 1253 nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL); 1254 if (!nvm) 1255 return -ENOMEM; 1256 1257 regmap_config.val_bits = 8; 1258 regmap_config.reg_bits = 16; 1259 regmap_config.disable_locking = true; 1260 regmap = devm_regmap_init_i2c(client, ®map_config); 1261 if (IS_ERR(regmap)) 1262 return PTR_ERR(regmap); 1263 1264 nvm->regmap = regmap; 1265 1266 nvmem_config.name = dev_name(dev); 1267 nvmem_config.dev = dev; 1268 nvmem_config.read_only = true; 1269 nvmem_config.root_only = true; 1270 nvmem_config.owner = THIS_MODULE; 1271 nvmem_config.compat = true; 1272 nvmem_config.base_dev = dev; 1273 nvmem_config.reg_read = ov2740_nvmem_read; 1274 nvmem_config.reg_write = NULL; 1275 nvmem_config.priv = nvm; 1276 nvmem_config.stride = 1; 1277 nvmem_config.word_size = 1; 1278 nvmem_config.size = CUSTOMER_USE_OTP_SIZE; 1279 1280 nvm->nvmem = devm_nvmem_register(dev, &nvmem_config); 1281 if (IS_ERR(nvm->nvmem)) 1282 return PTR_ERR(nvm->nvmem); 1283 1284 ov2740->nvm = nvm; 1285 return 0; 1286} 1287 1288static int ov2740_suspend(struct device *dev) 1289{ 1290 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1291 struct ov2740 *ov2740 = to_ov2740(sd); 1292 1293 gpiod_set_value_cansleep(ov2740->reset_gpio, 1); 1294 gpiod_set_value_cansleep(ov2740->powerdown_gpio, 1); 1295 clk_disable_unprepare(ov2740->clk); 1296 regulator_bulk_disable(ARRAY_SIZE(ov2740_supply_name), 1297 ov2740->supplies); 1298 return 0; 1299} 1300 1301static int ov2740_resume(struct device *dev) 1302{ 1303 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1304 struct ov2740 *ov2740 = to_ov2740(sd); 1305 int ret; 1306 1307 ret = regulator_bulk_enable(ARRAY_SIZE(ov2740_supply_name), 1308 ov2740->supplies); 1309 if (ret) 1310 return ret; 1311 1312 ret = clk_prepare_enable(ov2740->clk); 1313 if (ret) { 1314 regulator_bulk_disable(ARRAY_SIZE(ov2740_supply_name), 1315 ov2740->supplies); 1316 return ret; 1317 } 1318 1319 gpiod_set_value_cansleep(ov2740->powerdown_gpio, 0); 1320 gpiod_set_value_cansleep(ov2740->reset_gpio, 0); 1321 msleep(20); 1322 1323 return 0; 1324} 1325 1326static int ov2740_probe(struct i2c_client *client) 1327{ 1328 struct device *dev = &client->dev; 1329 struct ov2740 *ov2740; 1330 unsigned long freq; 1331 bool full_power; 1332 unsigned int i; 1333 int ret; 1334 1335 ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL); 1336 if (!ov2740) 1337 return -ENOMEM; 1338 1339 ov2740->dev = &client->dev; 1340 1341 v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops); 1342 ov2740->sd.internal_ops = &ov2740_internal_ops; 1343 1344 ret = ov2740_check_hwcfg(ov2740); 1345 if (ret) 1346 return ret; 1347 1348 ov2740->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 1349 if (IS_ERR(ov2740->reset_gpio)) { 1350 return dev_err_probe(dev, PTR_ERR(ov2740->reset_gpio), 1351 "failed to get reset GPIO\n"); 1352 } 1353 1354 ov2740->powerdown_gpio = devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH); 1355 if (IS_ERR(ov2740->powerdown_gpio)) { 1356 return dev_err_probe(dev, PTR_ERR(ov2740->powerdown_gpio), 1357 "failed to get powerdown GPIO\n"); 1358 } 1359 1360 if (ov2740->reset_gpio || ov2740->powerdown_gpio) { 1361 /* 1362 * Ensure reset/powerdown is asserted for at least 20 ms before 1363 * ov2740_resume() deasserts it. 1364 */ 1365 msleep(20); 1366 } 1367 1368 ov2740->clk = devm_v4l2_sensor_clk_get(dev, "clk"); 1369 if (IS_ERR(ov2740->clk)) 1370 return dev_err_probe(dev, PTR_ERR(ov2740->clk), 1371 "failed to get clock\n"); 1372 1373 freq = clk_get_rate(ov2740->clk); 1374 if (freq != OV2740_MCLK) 1375 return dev_err_probe(dev, -EINVAL, 1376 "external clock %lu is not supported\n", 1377 freq); 1378 1379 for (i = 0; i < ARRAY_SIZE(ov2740_supply_name); i++) 1380 ov2740->supplies[i].supply = ov2740_supply_name[i]; 1381 1382 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ov2740_supply_name), 1383 ov2740->supplies); 1384 if (ret) 1385 return dev_err_probe(dev, ret, "failed to get regulators\n"); 1386 1387 full_power = acpi_dev_state_d0(ov2740->dev); 1388 if (full_power) { 1389 /* ACPI does not always clear the reset GPIO / enable the clock */ 1390 ret = ov2740_resume(dev); 1391 if (ret) 1392 return dev_err_probe(dev, ret, "failed to power on sensor\n"); 1393 1394 ret = ov2740_identify_module(ov2740); 1395 if (ret) { 1396 dev_err_probe(dev, ret, "failed to find sensor\n"); 1397 goto probe_error_power_off; 1398 } 1399 } 1400 1401 ov2740->cur_mode = &ov2740->supported_modes[0]; 1402 ret = ov2740_init_controls(ov2740); 1403 if (ret) { 1404 dev_err_probe(dev, ret, "failed to init controls\n"); 1405 goto probe_error_v4l2_ctrl_handler_free; 1406 } 1407 1408 ov2740->sd.state_lock = ov2740->ctrl_handler.lock; 1409 ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1410 ov2740->sd.entity.ops = &ov2740_subdev_entity_ops; 1411 ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1412 ov2740->pad.flags = MEDIA_PAD_FL_SOURCE; 1413 ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad); 1414 if (ret) { 1415 dev_err_probe(dev, ret, "failed to init entity pads\n"); 1416 goto probe_error_v4l2_ctrl_handler_free; 1417 } 1418 1419 ret = v4l2_subdev_init_finalize(&ov2740->sd); 1420 if (ret) 1421 goto probe_error_media_entity_cleanup; 1422 1423 /* Set the device's state to active if it's in D0 state. */ 1424 if (full_power) 1425 pm_runtime_set_active(ov2740->dev); 1426 pm_runtime_enable(ov2740->dev); 1427 pm_runtime_idle(ov2740->dev); 1428 1429 ret = v4l2_async_register_subdev_sensor(&ov2740->sd); 1430 if (ret < 0) { 1431 dev_err_probe(dev, ret, "failed to register V4L2 subdev\n"); 1432 goto probe_error_v4l2_subdev_cleanup; 1433 } 1434 1435 ret = ov2740_register_nvmem(client, ov2740); 1436 if (ret) 1437 dev_warn(ov2740->dev, "register nvmem failed, ret %d\n", ret); 1438 1439 return 0; 1440 1441probe_error_v4l2_subdev_cleanup: 1442 pm_runtime_disable(ov2740->dev); 1443 pm_runtime_set_suspended(ov2740->dev); 1444 v4l2_subdev_cleanup(&ov2740->sd); 1445 1446probe_error_media_entity_cleanup: 1447 media_entity_cleanup(&ov2740->sd.entity); 1448 1449probe_error_v4l2_ctrl_handler_free: 1450 v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler); 1451 1452probe_error_power_off: 1453 if (full_power) 1454 ov2740_suspend(dev); 1455 1456 return ret; 1457} 1458 1459static DEFINE_RUNTIME_DEV_PM_OPS(ov2740_pm_ops, ov2740_suspend, ov2740_resume, 1460 NULL); 1461 1462static const struct acpi_device_id ov2740_acpi_ids[] = { 1463 {"INT3474"}, 1464 {} 1465}; 1466 1467MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids); 1468 1469static struct i2c_driver ov2740_i2c_driver = { 1470 .driver = { 1471 .name = "ov2740", 1472 .acpi_match_table = ov2740_acpi_ids, 1473 .pm = pm_sleep_ptr(&ov2740_pm_ops), 1474 }, 1475 .probe = ov2740_probe, 1476 .remove = ov2740_remove, 1477 .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE, 1478}; 1479 1480module_i2c_driver(ov2740_i2c_driver); 1481 1482MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>"); 1483MODULE_AUTHOR("Shawn Tu"); 1484MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>"); 1485MODULE_DESCRIPTION("OmniVision OV2740 sensor driver"); 1486MODULE_LICENSE("GPL v2");
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