ov2735.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * V4L2 Support for the OV2735
   4 *
   5 * Copyright (C) 2025 Silicon Signals Pvt. Ltd.
   6 *
   7 * Based on Rockchip ov2735 Camera Driver
   8 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
   9 *
  10 * Inspired from ov8858, imx219, imx283 camera drivers.
  11 */
  12
  13#include <linux/array_size.h>
  14#include <linux/bitops.h>
  15#include <linux/cleanup.h>
  16#include <linux/clk.h>
  17#include <linux/container_of.h>
  18#include <linux/delay.h>
  19#include <linux/device/devres.h>
  20#include <linux/err.h>
  21#include <linux/gpio/consumer.h>
  22#include <linux/i2c.h>
  23#include <linux/module.h>
  24#include <linux/mutex.h>
  25#include <linux/pm_runtime.h>
  26#include <linux/property.h>
  27#include <linux/regulator/consumer.h>
  28#include <linux/units.h>
  29#include <linux/types.h>
  30#include <linux/time.h>
  31
  32#include <media/v4l2-cci.h>
  33#include <media/v4l2-ctrls.h>
  34#include <media/v4l2-device.h>
  35#include <media/v4l2-fwnode.h>
  36#include <media/v4l2-mediabus.h>
  37
  38#define OV2735_XCLK_FREQ			(24 * HZ_PER_MHZ)
  39
  40/* Add page number in CCI private bits [31:28] of the register address */
  41#define OV2735_PAGE_REG8(p, x)	(((p) << CCI_REG_PRIVATE_SHIFT) | CCI_REG8(x))
  42#define OV2735_PAGE_REG16(p, x)	(((p) << CCI_REG_PRIVATE_SHIFT) | CCI_REG16(x))
  43
  44#define OV2735_REG_PAGE_SELECT			CCI_REG8(0xfd)
  45
  46/* Page 0 */
  47#define OV2735_REG_CHIPID			OV2735_PAGE_REG16(0x00, 0x02)
  48#define OV2735_CHIPID				0x2735
  49
  50#define OV2735_REG_SOFT_RESET			OV2735_PAGE_REG8(0x00, 0x20)
  51
  52/* Clock Settings */
  53#define OV2735_REG_PLL_CTRL			OV2735_PAGE_REG8(0x00, 0x2f)
  54#define OV2735_PLL_CTRL_ENABLE			0x7f
  55#define OV2735_REG_PLL_OUTDIV			OV2735_PAGE_REG8(0x00, 0x34)
  56#define OV2735_REG_CLK_MODE			OV2735_PAGE_REG8(0x00, 0x30)
  57#define OV2735_REG_CLOCK_REG1			OV2735_PAGE_REG8(0x00, 0x33)
  58#define OV2735_REG_CLOCK_REG2			OV2735_PAGE_REG8(0x00, 0x35)
  59
  60/* Page 1 */
  61#define OV2735_REG_STREAM_CTRL			OV2735_PAGE_REG8(0x01, 0xa0)
  62#define OV2735_STREAM_CTRL_ON			0x01
  63#define OV2735_STREAM_CTRL_OFF			0x00
  64
  65#define OV2735_REG_UPDOWN_MIRROR		OV2735_PAGE_REG8(0x01, 0x3f)
  66#define OV2735_REG_BINNING_DAC_CODE_MODE	OV2735_PAGE_REG8(0x01, 0x30)
  67#define OV2735_REG_FRAME_LENGTH			OV2735_PAGE_REG16(0x01, 0x0e)
  68#define OV2735_FRAME_LENGTH_MAX			0x0fff
  69#define OV2735_REG_FRAME_EXP_SEPERATE_EN	OV2735_PAGE_REG8(0x01, 0x0d)
  70#define OV2735_FRAME_EXP_SEPERATE_EN		0x10
  71#define OV2735_REG_FRAME_SYNC			OV2735_PAGE_REG8(0x01, 0x01)
  72
  73#define OV2735_REG_HBLANK			OV2735_PAGE_REG16(0x01, 0x09)
  74
  75#define OV2735_REG_HS_MIPI			OV2735_PAGE_REG8(0x01, 0xb1)
  76#define OV2735_REG_MIPI_CTRL1			OV2735_PAGE_REG8(0x01, 0x92)
  77#define OV2735_REG_MIPI_CTRL2			OV2735_PAGE_REG8(0x01, 0x94)
  78#define OV2735_REG_MIPI_CTRL3			OV2735_PAGE_REG8(0x01, 0xa1)
  79#define OV2735_REG_MIPI_CTRL4			OV2735_PAGE_REG8(0x01, 0xb2)
  80#define OV2735_REG_MIPI_CTRL5			OV2735_PAGE_REG8(0x01, 0xb3)
  81#define OV2735_REG_MIPI_CTRL6			OV2735_PAGE_REG8(0x01, 0xb4)
  82#define OV2735_REG_MIPI_CTRL7			OV2735_PAGE_REG8(0x01, 0xb5)
  83#define OV2735_REG_HIGH_SPEED			OV2735_PAGE_REG8(0x01, 0x9d)
  84#define OV2735_REG_PREPARE			OV2735_PAGE_REG8(0x01, 0x95)
  85#define OV2735_REG_R_HS_ZERO			OV2735_PAGE_REG8(0x01, 0x96)
  86#define OV2735_REG_TRAIL			OV2735_PAGE_REG8(0x01, 0x98)
  87#define OV2735_REG_R_CLK_ZERO			OV2735_PAGE_REG8(0x01, 0x9c)
  88#define OV2735_REG_MIPI_COLOMN_NUMBER		OV2735_PAGE_REG16(0x01, 0x8e)
  89#define OV2735_REG_MIPI_LINE_NUMBER		OV2735_PAGE_REG16(0x01, 0x90)
  90
  91/* Timing control registers */
  92#define OV2735_REG_TIMING_CTRL2			OV2735_PAGE_REG8(0x01, 0x1a)
  93#define OV2735_REG_TIMING_CTRL3			OV2735_PAGE_REG8(0x01, 0x1c)
  94#define OV2735_REG_TIMING_CTRL1			OV2735_PAGE_REG8(0x01, 0x16)
  95#define OV2735_REG_RST_NUM			OV2735_PAGE_REG16(0x01, 0x10)
  96#define OV2735_REG_RST_NUM2			OV2735_PAGE_REG16(0x01, 0x32)
  97#define OV2735_REG_BOOST_EN			OV2735_PAGE_REG8(0x01, 0xd0)
  98#define OV2735_REG_B2_NUM			OV2735_PAGE_REG16(0x01, 0xd1)
  99#define OV2735_REG_B4_NUM			OV2735_PAGE_REG16(0x01, 0xd3)
 100#define OV2735_REG_PIXEL_CYCLE_P0		OV2735_PAGE_REG8(0x01, 0x50)
 101#define OV2735_REG_PIXEL_CYCLE_P1		OV2735_PAGE_REG8(0x01, 0x51)
 102#define OV2735_REG_PIXEL_CYCLE_P2		OV2735_PAGE_REG8(0x01, 0x52)
 103#define OV2735_REG_PIXEL_CYCLE_P3		OV2735_PAGE_REG8(0x01, 0x53)
 104#define OV2735_REG_PIXEL_CYCLE_P5		OV2735_PAGE_REG8(0x01, 0x55)
 105#define OV2735_REG_PIXEL_CYCLE_P7		OV2735_PAGE_REG16(0x01, 0x57)
 106#define OV2735_REG_PIXEL_CYCLE_P9		OV2735_PAGE_REG8(0x01, 0x5a)
 107#define OV2735_REG_PIXEL_CYCLE_P10		OV2735_PAGE_REG8(0x01, 0x5b)
 108#define OV2735_REG_PIXEL_CYCLE_P12		OV2735_PAGE_REG8(0x01, 0x5d)
 109#define OV2735_REG_PIXEL_CYCLE_P18		OV2735_PAGE_REG8(0x01, 0x64)
 110#define OV2735_REG_PIXEL_CYCLE_P20		OV2735_PAGE_REG8(0x01, 0x66)
 111#define OV2735_REG_PIXEL_CYCLE_P22		OV2735_PAGE_REG8(0x01, 0x68)
 112#define OV2735_REG_PIXEL_CYCLE_P33		OV2735_PAGE_REG16(0x01, 0x74)
 113#define OV2735_REG_PIXEL_CYCLE_P34		OV2735_PAGE_REG8(0x01, 0x76)
 114#define OV2735_REG_PIXEL_CYCLE_P35_P36		OV2735_PAGE_REG8(0x01, 0x77)
 115#define OV2735_REG_PIXEL_CYCLE_P37_P38		OV2735_PAGE_REG8(0x01, 0x78)
 116#define OV2735_REG_PIXEL_CYCLE_P31		OV2735_PAGE_REG8(0x01, 0x72)
 117#define OV2735_REG_PIXEL_CYCLE_P32		OV2735_PAGE_REG8(0x01, 0x73)
 118#define OV2735_REG_PIXEL_CYCLE_P44		OV2735_PAGE_REG8(0x01, 0x7d)
 119#define OV2735_REG_PIXEL_CYCLE_P45		OV2735_PAGE_REG8(0x01, 0x7e)
 120#define OV2735_REG_PIXEL_BIAS_CTRL_RH_RL	OV2735_PAGE_REG8(0x01, 0x8a)
 121#define OV2735_REG_PIXEL_BIAS_CTRL_SH_SL	OV2735_PAGE_REG8(0x01, 0x8b)
 122
 123/* Analog Control registers */
 124#define OV2735_REG_ICOMP			OV2735_PAGE_REG8(0x01, 0x19)
 125#define OV2735_REG_PCP_RST_SEL			OV2735_PAGE_REG8(0x01, 0x21)
 126#define OV2735_REG_VNCP				OV2735_PAGE_REG8(0x01, 0x20)
 127#define OV2735_REG_ANALOG_CTRL3			OV2735_PAGE_REG8(0x01, 0x25)
 128#define OV2735_REG_ANALOG_CTRL4			OV2735_PAGE_REG8(0x01, 0x26)
 129#define OV2735_REG_ANALOG_CTRL5			OV2735_PAGE_REG8(0x01, 0x29)
 130#define OV2735_REG_ANALOG_CTRL6			OV2735_PAGE_REG8(0x01, 0x2a)
 131#define OV2735_REG_ANALOG_CTRL8			OV2735_PAGE_REG8(0x01, 0x2c)
 132
 133/* BLC registers */
 134#define OV2735_REG_BLC_GAIN_BLUE		OV2735_PAGE_REG8(0x01, 0x86)
 135#define OV2735_REG_BLC_GAIN_RED			OV2735_PAGE_REG8(0x01, 0x87)
 136#define OV2735_REG_BLC_GAIN_GR			OV2735_PAGE_REG8(0x01, 0x88)
 137#define OV2735_REG_BLC_GAIN_GB			OV2735_PAGE_REG8(0x01, 0x89)
 138#define OV2735_REG_GB_SUBOFFSET			OV2735_PAGE_REG8(0x01, 0xf0)
 139#define OV2735_REG_BLUE_SUBOFFSET		OV2735_PAGE_REG8(0x01, 0xf1)
 140#define OV2735_REG_RED_SUBOFFSET		OV2735_PAGE_REG8(0x01, 0xf2)
 141#define OV2735_REG_GR_SUBOFFSET			OV2735_PAGE_REG8(0x01, 0xf3)
 142#define OV2735_REG_BLC_BPC_TH_P			OV2735_PAGE_REG8(0x01, 0xfc)
 143#define OV2735_REG_BLC_BPC_TH_N			OV2735_PAGE_REG8(0x01, 0xfe)
 144#define OV2735_REG_ABL				OV2735_PAGE_REG8(0x01, 0xfb)
 145
 146#define OV2735_REG_TEST_PATTERN			OV2735_PAGE_REG8(0x01, 0xb2)
 147#define OV2735_TEST_PATTERN_ENABLE		0x01
 148#define OV2735_TEST_PATTERN_DISABLE		0xfe
 149
 150#define OV2735_REG_LONG_EXPOSURE		OV2735_PAGE_REG16(0x01, 0x03)
 151#define OV2735_EXPOSURE_MIN			4
 152#define OV2735_EXPOSURE_STEP			1
 153#define OV2735_EXPOSURE_MARGIN			4
 154
 155#define OV2735_REG_ANALOG_GAIN			OV2735_PAGE_REG8(0x01, 0x24)
 156#define OV2735_ANALOG_GAIN_MIN			0x10
 157#define OV2735_ANALOG_GAIN_MAX			0xff
 158#define OV2735_ANALOG_GAIN_STEP			1
 159#define OV2735_ANALOG_GAIN_DEFAULT		0x10
 160
 161/* Page 2 */
 162#define OV2735_REG_V_START			OV2735_PAGE_REG16(0x02, 0xa0)
 163#define OV2735_REG_V_SIZE			OV2735_PAGE_REG16(0x02, 0xa2)
 164#define OV2735_REG_H_START			OV2735_PAGE_REG16(0x02, 0xa4)
 165#define OV2735_REG_H_SIZE			OV2735_PAGE_REG16(0x02, 0xa6)
 166
 167#define OV2735_LINK_FREQ_420MHZ			(420 * HZ_PER_MHZ)
 168#define OV2735_PIXEL_RATE			(168 * HZ_PER_MHZ)
 169
 170/* OV2735 native and active pixel array size */
 171static const struct v4l2_rect ov2735_native_area = {
 172	.top = 0,
 173	.left = 0,
 174	.width = 1936,
 175	.height = 1096,
 176};
 177
 178static const struct v4l2_rect ov2735_active_area = {
 179	.top = 8,
 180	.left = 8,
 181	.width = 1920,
 182	.height = 1080,
 183};
 184
 185static const char * const ov2735_supply_name[] = {
 186	"avdd",		/* Analog power */
 187	"dovdd",	/* Digital I/O power */
 188	"dvdd",		/* Digital core power */
 189};
 190
 191/* PLL_OUT = [PLL_IN * (pll_nc +3)] / [(pll_mc + 1) * (pll_outdiv + 1)] */
 192struct ov2735_pll_parameters {
 193	u8 pll_nc;
 194	u8 pll_mc;
 195	u8 pll_outdiv;
 196};
 197
 198struct ov2735 {
 199	struct device *dev;
 200	struct regmap *cci;
 201	struct v4l2_subdev sd;
 202	struct media_pad pad;
 203	struct clk *xclk;
 204	struct gpio_desc *reset_gpio;
 205	struct gpio_desc *enable_gpio;
 206	struct regulator_bulk_data supplies[ARRAY_SIZE(ov2735_supply_name)];
 207
 208	/* V4L2 Controls */
 209	struct v4l2_ctrl_handler handler;
 210	struct v4l2_ctrl *link_freq;
 211	struct v4l2_ctrl *pixel_rate;
 212	struct v4l2_ctrl *hblank;
 213	struct v4l2_ctrl *vblank;
 214	struct v4l2_ctrl *gain;
 215	struct v4l2_ctrl *exposure;
 216	struct v4l2_ctrl *test_pattern;
 217
 218	u32 link_freq_index;
 219
 220	u8 current_page;
 221	struct mutex page_lock;
 222};
 223
 224struct ov2735_mode {
 225	u32 width;
 226	u32 height;
 227	u32 hts_def;
 228	u32 vts_def;
 229	u32 exp_def;
 230	struct v4l2_rect crop;
 231};
 232
 233static const struct cci_reg_sequence ov2735_common_regs[] = {
 234	{ OV2735_REG_CLK_MODE,			0x15 },
 235	{ OV2735_REG_CLOCK_REG1,		0x01 },
 236	{ OV2735_REG_CLOCK_REG2,		0x20 },
 237	{ OV2735_REG_BINNING_DAC_CODE_MODE,	0x00 },
 238	{ OV2735_REG_ABL,			0x73 },
 239	{ OV2735_REG_FRAME_SYNC,		0x01 },
 240
 241	/* Timing ctrl */
 242	{ OV2735_REG_TIMING_CTRL2,		0x6b },
 243	{ OV2735_REG_TIMING_CTRL3,		0xea },
 244	{ OV2735_REG_TIMING_CTRL1,		0x0c },
 245	{ OV2735_REG_RST_NUM,			0x0063 },
 246	{ OV2735_REG_RST_NUM2,			0x006f },
 247	{ OV2735_REG_BOOST_EN,			0x02 },
 248	{ OV2735_REG_B2_NUM,			0x0120 },
 249	{ OV2735_REG_B4_NUM,			0x042a },
 250	{ OV2735_REG_PIXEL_CYCLE_P0,		0x00 },
 251	{ OV2735_REG_PIXEL_CYCLE_P1,		0x2c },
 252	{ OV2735_REG_PIXEL_CYCLE_P2,		0x29 },
 253	{ OV2735_REG_PIXEL_CYCLE_P3,		0x00 },
 254	{ OV2735_REG_PIXEL_CYCLE_P5,		0x44 },
 255	{ OV2735_REG_PIXEL_CYCLE_P7,		0x0029 },
 256	{ OV2735_REG_PIXEL_CYCLE_P9,		0x00 },
 257	{ OV2735_REG_PIXEL_CYCLE_P10,		0x00 },
 258	{ OV2735_REG_PIXEL_CYCLE_P12,		0x00 },
 259	{ OV2735_REG_PIXEL_CYCLE_P18,		0x2f },
 260	{ OV2735_REG_PIXEL_CYCLE_P20,		0x62 },
 261	{ OV2735_REG_PIXEL_CYCLE_P22,		0x5b },
 262	{ OV2735_REG_PIXEL_CYCLE_P33,		0x0046 },
 263	{ OV2735_REG_PIXEL_CYCLE_P34,		0x36 },
 264	{ OV2735_REG_PIXEL_CYCLE_P35_P36,	0x4f },
 265	{ OV2735_REG_PIXEL_CYCLE_P37_P38,	0xef },
 266	{ OV2735_REG_PIXEL_CYCLE_P31,		0xcf },
 267	{ OV2735_REG_PIXEL_CYCLE_P32,		0x36 },
 268	{ OV2735_REG_PIXEL_CYCLE_P44,		0x0d },
 269	{ OV2735_REG_PIXEL_CYCLE_P45,		0x0d },
 270	{ OV2735_REG_PIXEL_BIAS_CTRL_RH_RL,	0x77 },
 271	{ OV2735_REG_PIXEL_BIAS_CTRL_SH_SL,	0x77 },
 272
 273	/* Analog ctrl */
 274	{ OV2735_REG_ANALOG_CTRL4,		0x5a },
 275	{ OV2735_REG_ANALOG_CTRL5,		0x01 },
 276	{ OV2735_REG_ANALOG_CTRL6,		0xd2 },
 277	{ OV2735_REG_ANALOG_CTRL8,		0x40 },
 278	{ OV2735_REG_PCP_RST_SEL,		0x00 },
 279	{ OV2735_REG_ICOMP,			0xc3 },
 280
 281	{ OV2735_REG_HS_MIPI,			0x83 },
 282	{ OV2735_REG_MIPI_CTRL5,		0x0b },
 283	{ OV2735_REG_MIPI_CTRL6,		0x14 },
 284	{ OV2735_REG_HIGH_SPEED,		0x40 },
 285	{ OV2735_REG_MIPI_CTRL3,		0x05 },
 286	{ OV2735_REG_MIPI_CTRL2,		0x44 },
 287	{ OV2735_REG_PREPARE,			0x33 },
 288	{ OV2735_REG_R_HS_ZERO,			0x1f },
 289	{ OV2735_REG_TRAIL,			0x45 },
 290	{ OV2735_REG_R_CLK_ZERO,		0x10 },
 291	{ OV2735_REG_MIPI_CTRL7,		0x70 },
 292	{ OV2735_REG_ANALOG_CTRL3,		0xe0 },
 293	{ OV2735_REG_VNCP,			0x7b },
 294
 295	/* BLC */
 296	{ OV2735_REG_BLC_GAIN_BLUE,		0x77 },
 297	{ OV2735_REG_BLC_GAIN_GB,		0x77 },
 298	{ OV2735_REG_BLC_GAIN_RED,		0x74 },
 299	{ OV2735_REG_BLC_GAIN_GR,		0x74 },
 300	{ OV2735_REG_BLC_BPC_TH_P,		0xe0 },
 301	{ OV2735_REG_BLC_BPC_TH_N,		0xe0 },
 302	{ OV2735_REG_GB_SUBOFFSET,		0x40 },
 303	{ OV2735_REG_BLUE_SUBOFFSET,		0x40 },
 304	{ OV2735_REG_RED_SUBOFFSET,		0x40 },
 305	{ OV2735_REG_GR_SUBOFFSET,		0x40 },
 306};
 307
 308static const struct ov2735_mode supported_modes[] = {
 309	{
 310		.width = 1920,
 311		.height = 1080,
 312		.exp_def = 399,
 313		.hts_def = 2200,
 314		.vts_def = 2545,
 315		.crop = {
 316			.top = 8,
 317			.left = 8,
 318			.width = 1920,
 319			.height = 1080,
 320		},
 321	},
 322};
 323
 324static const s64 link_freq_menu_items[] = {
 325	OV2735_LINK_FREQ_420MHZ,
 326};
 327
 328static const struct ov2735_pll_parameters pll_configs[] = {
 329	/* For 420MHz pll_configs */
 330	{
 331		.pll_nc = 4,
 332		.pll_mc = 0,
 333		.pll_outdiv = 1,
 334	},
 335};
 336
 337static const char * const ov2735_test_pattern_menu[] = {
 338	"Disabled",
 339	"Vertical Color",
 340};
 341
 342static int ov2735_page_access(struct ov2735 *ov2735, u32 reg, int *err)
 343{
 344	u8 page = reg >> CCI_REG_PRIVATE_SHIFT;
 345	int ret = 0;
 346
 347	if (err && *err)
 348		return *err;
 349
 350	guard(mutex)(&ov2735->page_lock);
 351
 352	/* Perform page access before read/write */
 353	if (ov2735->current_page == page)
 354		return ret;
 355
 356	ret = cci_write(ov2735->cci, OV2735_REG_PAGE_SELECT, page, err);
 357	if (!ret)
 358		ov2735->current_page = page;
 359
 360	return ret;
 361}
 362
 363static int ov2735_read(struct ov2735 *ov2735, u32 reg, u64 *val, int *err)
 364{
 365	u32 addr = reg & ~CCI_REG_PRIVATE_MASK;
 366	int ret;
 367
 368	ret = ov2735_page_access(ov2735, reg, err);
 369	if (ret)
 370		return ret;
 371
 372	return cci_read(ov2735->cci, addr, val, err);
 373}
 374
 375static int ov2735_write(struct ov2735 *ov2735, u32 reg, u64 val, int *err)
 376{
 377	u32 addr = reg & ~CCI_REG_PRIVATE_MASK;
 378	int ret;
 379
 380	ret = ov2735_page_access(ov2735, reg, err);
 381	if (ret)
 382		return ret;
 383
 384	return cci_write(ov2735->cci, addr, val, err);
 385}
 386
 387static int ov2735_multi_reg_write(struct ov2735 *ov2735,
 388				  const struct cci_reg_sequence *regs,
 389				  unsigned int num_regs, int *err)
 390{
 391	unsigned int i;
 392	int ret;
 393
 394	for (i = 0; i < num_regs; i++) {
 395		ret = ov2735_write(ov2735, regs[i].reg, regs[i].val, err);
 396		if (ret)
 397			return ret;
 398	}
 399
 400	return 0;
 401}
 402
 403static inline struct ov2735 *to_ov2735(struct v4l2_subdev *_sd)
 404{
 405	return container_of_const(_sd, struct ov2735, sd);
 406}
 407
 408static int ov2735_enable_test_pattern(struct ov2735 *ov2735, u32 pattern)
 409{
 410	int ret;
 411	u64 val;
 412
 413	ret = ov2735_read(ov2735, OV2735_REG_TEST_PATTERN, &val, NULL);
 414	if (ret)
 415		return ret;
 416
 417	switch (pattern) {
 418	case 0:
 419		val &= ~OV2735_TEST_PATTERN_ENABLE;
 420		break;
 421	case 1:
 422		val |= OV2735_TEST_PATTERN_ENABLE;
 423		break;
 424	}
 425
 426	return ov2735_write(ov2735, OV2735_REG_TEST_PATTERN, val, NULL);
 427}
 428
 429static int ov2735_set_ctrl(struct v4l2_ctrl *ctrl)
 430{
 431	struct ov2735 *ov2735 =
 432		container_of_const(ctrl->handler, struct ov2735, handler);
 433	struct v4l2_mbus_framefmt *fmt;
 434	struct v4l2_subdev_state *state;
 435	u64 vts;
 436	int ret = 0;
 437
 438	state = v4l2_subdev_get_locked_active_state(&ov2735->sd);
 439	fmt = v4l2_subdev_state_get_format(state, 0);
 440
 441	if (ctrl->id == V4L2_CID_VBLANK) {
 442		/* Honour the VBLANK limits when setting exposure */
 443		s64 max = fmt->height + ctrl->val - OV2735_EXPOSURE_MARGIN;
 444
 445		ret = __v4l2_ctrl_modify_range(ov2735->exposure,
 446					       ov2735->exposure->minimum, max,
 447					       ov2735->exposure->step,
 448					       ov2735->exposure->default_value);
 449		if (ret)
 450			return ret;
 451	}
 452
 453	if (pm_runtime_get_if_in_use(ov2735->dev) == 0)
 454		return 0;
 455
 456	switch (ctrl->id) {
 457	case V4L2_CID_EXPOSURE:
 458		ov2735_write(ov2735, OV2735_REG_LONG_EXPOSURE, ctrl->val, &ret);
 459		break;
 460	case V4L2_CID_ANALOGUE_GAIN:
 461		ov2735_write(ov2735, OV2735_REG_ANALOG_GAIN, ctrl->val, &ret);
 462		break;
 463	case V4L2_CID_HBLANK:
 464		ov2735_write(ov2735, OV2735_REG_HBLANK, ctrl->val, &ret);
 465		break;
 466	case V4L2_CID_VBLANK:
 467		vts = ctrl->val + fmt->height;
 468		ov2735_write(ov2735, OV2735_REG_FRAME_EXP_SEPERATE_EN,
 469			     OV2735_FRAME_EXP_SEPERATE_EN, &ret);
 470		ov2735_write(ov2735, OV2735_REG_FRAME_LENGTH, vts, &ret);
 471		break;
 472	case V4L2_CID_TEST_PATTERN:
 473		ret = ov2735_enable_test_pattern(ov2735, ctrl->val);
 474		break;
 475	default:
 476		ret = -EINVAL;
 477		break;
 478	}
 479	ov2735_write(ov2735, OV2735_REG_FRAME_SYNC, 0x01, &ret);
 480
 481	pm_runtime_put(ov2735->dev);
 482
 483	return ret;
 484}
 485
 486static const struct v4l2_ctrl_ops ov2735_ctrl_ops = {
 487	.s_ctrl = ov2735_set_ctrl,
 488};
 489
 490static int ov2735_init_controls(struct ov2735 *ov2735)
 491{
 492	struct v4l2_ctrl_handler *ctrl_hdlr;
 493	struct v4l2_fwnode_device_properties props;
 494	const struct ov2735_mode *mode = &supported_modes[0];
 495	u64 hblank_def, vblank_def, exp_max;
 496	int ret;
 497
 498	ctrl_hdlr = &ov2735->handler;
 499	v4l2_ctrl_handler_init(ctrl_hdlr, 9);
 500
 501	ov2735->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2735_ctrl_ops,
 502					       V4L2_CID_PIXEL_RATE, 0,
 503					       OV2735_PIXEL_RATE, 1,
 504					       OV2735_PIXEL_RATE);
 505
 506	ov2735->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2735_ctrl_ops,
 507						   V4L2_CID_LINK_FREQ,
 508						   ov2735->link_freq_index,
 509						   0, link_freq_menu_items);
 510	if (ov2735->link_freq)
 511		ov2735->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
 512
 513	hblank_def = mode->hts_def - mode->width;
 514	ov2735->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2735_ctrl_ops,
 515					   V4L2_CID_HBLANK, hblank_def,
 516					   hblank_def, 1, hblank_def);
 517
 518	vblank_def = mode->vts_def - mode->height;
 519	ov2735->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2735_ctrl_ops,
 520					   V4L2_CID_VBLANK, vblank_def,
 521					   OV2735_FRAME_LENGTH_MAX - mode->height,
 522					   1, vblank_def);
 523
 524	exp_max = mode->vts_def - OV2735_EXPOSURE_MARGIN;
 525	ov2735->exposure =
 526		v4l2_ctrl_new_std(ctrl_hdlr, &ov2735_ctrl_ops,
 527				  V4L2_CID_EXPOSURE,
 528				  OV2735_EXPOSURE_MIN, exp_max,
 529				  OV2735_EXPOSURE_STEP, mode->exp_def);
 530
 531	ov2735->gain =
 532		v4l2_ctrl_new_std(ctrl_hdlr, &ov2735_ctrl_ops,
 533				  V4L2_CID_ANALOGUE_GAIN, OV2735_ANALOG_GAIN_MIN,
 534				  OV2735_ANALOG_GAIN_MAX, OV2735_ANALOG_GAIN_STEP,
 535				  OV2735_ANALOG_GAIN_DEFAULT);
 536
 537	ov2735->test_pattern =
 538		v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2735_ctrl_ops,
 539					     V4L2_CID_TEST_PATTERN,
 540					     ARRAY_SIZE(ov2735_test_pattern_menu) - 1,
 541					     0, 0, ov2735_test_pattern_menu);
 542
 543	if (ctrl_hdlr->error) {
 544		ret = ctrl_hdlr->error;
 545		dev_err(ov2735->dev, "control init failed (%d)\n", ret);
 546		goto err_handler_free;
 547	}
 548
 549	ret = v4l2_fwnode_device_parse(ov2735->dev, &props);
 550	if (ret)
 551		goto err_handler_free;
 552
 553	ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr,
 554					      &ov2735_ctrl_ops, &props);
 555	if (ret)
 556		goto err_handler_free;
 557
 558	ov2735->sd.ctrl_handler = ctrl_hdlr;
 559
 560	return 0;
 561
 562err_handler_free:
 563	v4l2_ctrl_handler_free(ctrl_hdlr);
 564
 565	return ret;
 566}
 567
 568static int ov2735_set_pll_ctrl(struct ov2735 *ov2735)
 569{
 570	const struct ov2735_pll_parameters *pll_parameters;
 571	u8 pll_ctrl;
 572	u8 pll_outdiv;
 573	int ret = 0;
 574
 575	pll_parameters = &pll_configs[ov2735->link_freq_index];
 576
 577	/* BIT[7]: pll_clk_sel, BIT[6:2]: pll_nc, BIT[1:0]: pll_mc */
 578	pll_ctrl = ((pll_parameters->pll_nc << 2) | (pll_parameters->pll_mc << 0)) &
 579		    OV2735_PLL_CTRL_ENABLE;
 580
 581	pll_outdiv = pll_parameters->pll_outdiv;
 582
 583	ov2735_write(ov2735, OV2735_REG_PLL_CTRL, pll_ctrl, &ret);
 584	ov2735_write(ov2735, OV2735_REG_PLL_OUTDIV, pll_outdiv, &ret);
 585
 586	return ret;
 587}
 588
 589static int ov2735_set_framefmt(struct ov2735 *ov2735,
 590			       struct v4l2_subdev_state *state)
 591{
 592	const struct v4l2_mbus_framefmt *format;
 593	const struct v4l2_rect *crop;
 594	int ret = 0;
 595
 596	format = v4l2_subdev_state_get_format(state, 0);
 597	crop = v4l2_subdev_state_get_crop(state, 0);
 598
 599	ov2735_write(ov2735, OV2735_REG_V_START, crop->top, &ret);
 600	ov2735_write(ov2735, OV2735_REG_V_SIZE, format->height, &ret);
 601	ov2735_write(ov2735, OV2735_REG_MIPI_LINE_NUMBER, format->height, &ret);
 602	ov2735_write(ov2735, OV2735_REG_H_START, crop->left, &ret);
 603	/* OV2735_REG_H_SIZE: Image half horizontal size */
 604	ov2735_write(ov2735, OV2735_REG_H_SIZE, (format->width / 2), &ret);
 605	ov2735_write(ov2735, OV2735_REG_MIPI_COLOMN_NUMBER, format->width, &ret);
 606
 607	return ret;
 608}
 609
 610static int ov2735_enable_streams(struct v4l2_subdev *sd,
 611				 struct v4l2_subdev_state *state, u32 pad,
 612				 u64 streams_mask)
 613{
 614	struct ov2735 *ov2735 = to_ov2735(sd);
 615	int ret;
 616
 617	ret = pm_runtime_resume_and_get(ov2735->dev);
 618	if (ret < 0)
 619		return ret;
 620
 621	/* Apply pll settings */
 622	ret = ov2735_set_pll_ctrl(ov2735);
 623	if (ret) {
 624		dev_err(ov2735->dev, "failed to set frame format: %d\n", ret);
 625		goto err_rpm_put;
 626	}
 627
 628	ret = ov2735_multi_reg_write(ov2735, ov2735_common_regs,
 629				     ARRAY_SIZE(ov2735_common_regs), NULL);
 630	if (ret) {
 631		dev_err(ov2735->dev, "failed to write common registers\n");
 632		goto err_rpm_put;
 633	}
 634
 635	/* Apply format settings */
 636	ret = ov2735_set_framefmt(ov2735, state);
 637	if (ret) {
 638		dev_err(ov2735->dev, "failed to set frame format: %d\n", ret);
 639		goto err_rpm_put;
 640	}
 641
 642	/* Apply customized values from user */
 643	ret = __v4l2_ctrl_handler_setup(ov2735->sd.ctrl_handler);
 644	if (ret)
 645		goto err_rpm_put;
 646
 647	ret = ov2735_write(ov2735, OV2735_REG_STREAM_CTRL,
 648			   OV2735_STREAM_CTRL_ON, NULL);
 649	if (ret)
 650		goto err_rpm_put;
 651
 652	return 0;
 653
 654err_rpm_put:
 655	pm_runtime_put(ov2735->dev);
 656	return ret;
 657}
 658
 659static int ov2735_disable_streams(struct v4l2_subdev *sd,
 660				  struct v4l2_subdev_state *state, u32 pad,
 661				  u64 streams_mask)
 662{
 663	struct ov2735 *ov2735 = to_ov2735(sd);
 664	int ret;
 665
 666	ret = ov2735_write(ov2735, OV2735_REG_STREAM_CTRL,
 667			   OV2735_STREAM_CTRL_OFF, NULL);
 668	if (ret)
 669		dev_err(ov2735->dev, "%s failed to set stream\n", __func__);
 670
 671	pm_runtime_put(ov2735->dev);
 672
 673	return ret;
 674}
 675
 676static int ov2735_get_selection(struct v4l2_subdev *sd,
 677				struct v4l2_subdev_state *sd_state,
 678				struct v4l2_subdev_selection *sel)
 679{
 680	switch (sel->target) {
 681	case V4L2_SEL_TGT_CROP:
 682		sel->r = *v4l2_subdev_state_get_crop(sd_state, 0);
 683		return 0;
 684	case V4L2_SEL_TGT_NATIVE_SIZE:
 685		sel->r = ov2735_native_area;
 686		return 0;
 687	case V4L2_SEL_TGT_CROP_DEFAULT:
 688	case V4L2_SEL_TGT_CROP_BOUNDS:
 689		sel->r = ov2735_active_area;
 690		return 0;
 691	default:
 692		return -EINVAL;
 693	}
 694}
 695
 696static int ov2735_enum_mbus_code(struct v4l2_subdev *sd,
 697				 struct v4l2_subdev_state *sd_state,
 698				 struct v4l2_subdev_mbus_code_enum *code)
 699{
 700	if (code->index)
 701		return -EINVAL;
 702
 703	code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
 704
 705	return 0;
 706}
 707
 708static int ov2735_enum_frame_size(struct v4l2_subdev *sd,
 709				  struct v4l2_subdev_state *sd_state,
 710				  struct v4l2_subdev_frame_size_enum *fse)
 711{
 712	if (fse->index >= ARRAY_SIZE(supported_modes))
 713		return -EINVAL;
 714
 715	if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
 716		return -EINVAL;
 717
 718	fse->min_width = supported_modes[fse->index].width;
 719	fse->max_width = fse->min_width;
 720	fse->min_height = supported_modes[fse->index].height;
 721	fse->max_height = fse->min_height;
 722
 723	return 0;
 724}
 725
 726static int ov2735_set_framing_limits(struct ov2735 *ov2735,
 727				     const struct ov2735_mode *mode)
 728{
 729	u32 hblank, vblank_def;
 730	int ret;
 731
 732	hblank = mode->hts_def - mode->width;
 733	ret = __v4l2_ctrl_modify_range(ov2735->hblank, hblank, hblank, 1,
 734				       hblank);
 735	if (ret)
 736		return ret;
 737
 738	vblank_def = mode->vts_def - mode->height;
 739	return __v4l2_ctrl_modify_range(ov2735->vblank, vblank_def,
 740					OV2735_FRAME_LENGTH_MAX - mode->height,
 741					1, vblank_def);
 742}
 743
 744static int ov2735_set_pad_format(struct v4l2_subdev *sd,
 745				 struct v4l2_subdev_state *sd_state,
 746				 struct v4l2_subdev_format *fmt)
 747{
 748	struct v4l2_mbus_framefmt *format;
 749	const struct ov2735_mode *mode;
 750	struct v4l2_rect *crop;
 751	struct ov2735 *ov2735 = to_ov2735(sd);
 752	int ret;
 753
 754	format = v4l2_subdev_state_get_format(sd_state, 0);
 755
 756	mode = v4l2_find_nearest_size(supported_modes,
 757				      ARRAY_SIZE(supported_modes),
 758				      width, height,
 759				      fmt->format.width, fmt->format.height);
 760
 761	fmt->format.width = mode->width;
 762	fmt->format.height = mode->height;
 763	fmt->format.field = V4L2_FIELD_NONE;
 764	fmt->format.colorspace = V4L2_COLORSPACE_RAW;
 765	fmt->format.quantization = V4L2_QUANTIZATION_FULL_RANGE;
 766	fmt->format.xfer_func = V4L2_XFER_FUNC_NONE;
 767
 768	if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
 769		ret = ov2735_set_framing_limits(ov2735, mode);
 770		if (ret)
 771			return ret;
 772	}
 773
 774	*format = fmt->format;
 775
 776	/* Initialize crop rectangle */
 777	crop = v4l2_subdev_state_get_crop(sd_state, 0);
 778	*crop = mode->crop;
 779
 780	return 0;
 781}
 782
 783static int ov2735_init_state(struct v4l2_subdev *sd,
 784			     struct v4l2_subdev_state *state)
 785{
 786	struct v4l2_subdev_format fmt = {
 787		.which = V4L2_SUBDEV_FORMAT_TRY,
 788		.format = {
 789			.code = MEDIA_BUS_FMT_SGRBG10_1X10,
 790			.width = supported_modes[0].width,
 791			.height = supported_modes[0].height,
 792		},
 793	};
 794
 795	ov2735_set_pad_format(sd, state, &fmt);
 796
 797	return 0;
 798}
 799
 800static const struct v4l2_subdev_video_ops ov2735_video_ops = {
 801	.s_stream = v4l2_subdev_s_stream_helper,
 802};
 803
 804static const struct v4l2_subdev_pad_ops ov2735_pad_ops = {
 805	.enum_mbus_code = ov2735_enum_mbus_code,
 806	.get_fmt = v4l2_subdev_get_fmt,
 807	.set_fmt = ov2735_set_pad_format,
 808	.get_selection = ov2735_get_selection,
 809	.enum_frame_size = ov2735_enum_frame_size,
 810	.enable_streams = ov2735_enable_streams,
 811	.disable_streams = ov2735_disable_streams,
 812};
 813
 814static const struct v4l2_subdev_ops ov2735_subdev_ops = {
 815	.video = &ov2735_video_ops,
 816	.pad = &ov2735_pad_ops,
 817};
 818
 819static const struct v4l2_subdev_internal_ops ov2735_internal_ops = {
 820	.init_state = ov2735_init_state,
 821};
 822
 823static int ov2735_power_on(struct device *dev)
 824{
 825	struct v4l2_subdev *sd = dev_get_drvdata(dev);
 826	struct ov2735 *ov2735 = to_ov2735(sd);
 827	int ret;
 828
 829	ret = regulator_bulk_enable(ARRAY_SIZE(ov2735_supply_name),
 830				    ov2735->supplies);
 831	if (ret) {
 832		dev_err(ov2735->dev, "failed to enable regulators\n");
 833		return ret;
 834	}
 835
 836	gpiod_set_value_cansleep(ov2735->enable_gpio, 1);
 837	/* T4: delay from PWDN pulling low to RSTB pulling high */
 838	fsleep(4 * USEC_PER_MSEC);
 839
 840	ret = clk_prepare_enable(ov2735->xclk);
 841	if (ret) {
 842		dev_err(ov2735->dev, "failed to enable clock\n");
 843		goto err_regulator_off;
 844	}
 845
 846	gpiod_set_value_cansleep(ov2735->reset_gpio, 0);
 847	/* T5: delay from RSTB pulling high to first I2C command */
 848	fsleep(5 * USEC_PER_MSEC);
 849
 850	return 0;
 851
 852err_regulator_off:
 853	regulator_bulk_disable(ARRAY_SIZE(ov2735_supply_name), ov2735->supplies);
 854	return ret;
 855}
 856
 857static int ov2735_power_off(struct device *dev)
 858{
 859	struct v4l2_subdev *sd = dev_get_drvdata(dev);
 860	struct ov2735 *ov2735 = to_ov2735(sd);
 861
 862	gpiod_set_value_cansleep(ov2735->enable_gpio, 0);
 863	clk_disable_unprepare(ov2735->xclk);
 864	gpiod_set_value_cansleep(ov2735->reset_gpio, 1);
 865	regulator_bulk_disable(ARRAY_SIZE(ov2735_supply_name), ov2735->supplies);
 866
 867	return 0;
 868}
 869
 870static int ov2735_get_regulators(struct ov2735 *ov2735)
 871{
 872	unsigned int i;
 873
 874	for (i = 0; i < ARRAY_SIZE(ov2735_supply_name); i++)
 875		ov2735->supplies[i].supply = ov2735_supply_name[i];
 876
 877	return devm_regulator_bulk_get(ov2735->dev,
 878				       ARRAY_SIZE(ov2735_supply_name),
 879				       ov2735->supplies);
 880}
 881
 882static int ov2735_identify_module(struct ov2735 *ov2735)
 883{
 884	u64 chip_id;
 885	int ret;
 886
 887	ret = ov2735_read(ov2735, OV2735_REG_CHIPID, &chip_id, NULL);
 888	if (ret)
 889		return dev_err_probe(ov2735->dev, ret,
 890				     "failed to read chip id %x\n",
 891				     OV2735_CHIPID);
 892
 893	if (chip_id != OV2735_CHIPID)
 894		return dev_err_probe(ov2735->dev, -EIO,
 895				     "chip id mismatch: %x!=%llx\n",
 896				     OV2735_CHIPID, chip_id);
 897
 898	return 0;
 899}
 900
 901static int ov2735_parse_endpoint(struct ov2735 *ov2735)
 902{
 903	struct v4l2_fwnode_endpoint bus_cfg = {
 904		.bus_type = V4L2_MBUS_CSI2_DPHY,
 905	};
 906	struct fwnode_handle *ep;
 907	unsigned long link_freq_bitmap;
 908	int ret;
 909
 910	ep = fwnode_graph_get_next_endpoint(dev_fwnode(ov2735->dev), NULL);
 911	if (!ep)
 912		return dev_err_probe(ov2735->dev, -ENXIO,
 913				     "Failed to get next endpoint\n");
 914
 915	ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
 916	fwnode_handle_put(ep);
 917	if (ret)
 918		return ret;
 919
 920	if (bus_cfg.bus.mipi_csi2.num_data_lanes != 2) {
 921		ret = dev_err_probe(ov2735->dev, -EINVAL,
 922				    "only 2 data lanes are supported\n");
 923		goto error_out;
 924	}
 925
 926	ret = v4l2_link_freq_to_bitmap(ov2735->dev, bus_cfg.link_frequencies,
 927				       bus_cfg.nr_of_link_frequencies,
 928				       link_freq_menu_items,
 929				       ARRAY_SIZE(link_freq_menu_items),
 930				       &link_freq_bitmap);
 931	if (ret) {
 932		ret = dev_err_probe(ov2735->dev, -EINVAL,
 933				    "only 420MHz frequency is available\n");
 934		goto error_out;
 935	}
 936
 937	ov2735->link_freq_index = __ffs(link_freq_bitmap);
 938
 939error_out:
 940	v4l2_fwnode_endpoint_free(&bus_cfg);
 941
 942	return ret;
 943};
 944
 945static int ov2735_probe(struct i2c_client *client)
 946{
 947	struct ov2735 *ov2735;
 948	unsigned int xclk_freq;
 949	int ret;
 950
 951	ov2735 = devm_kzalloc(&client->dev, sizeof(*ov2735), GFP_KERNEL);
 952	if (!ov2735)
 953		return -ENOMEM;
 954
 955	ov2735->dev = &client->dev;
 956
 957	v4l2_i2c_subdev_init(&ov2735->sd, client, &ov2735_subdev_ops);
 958	ov2735->sd.internal_ops = &ov2735_internal_ops;
 959
 960	ov2735->cci = devm_cci_regmap_init_i2c(client, 8);
 961	if (IS_ERR(ov2735->cci))
 962		return dev_err_probe(ov2735->dev, PTR_ERR(ov2735->cci),
 963				     "failed to initialize CCI\n");
 964
 965	/* Set Current page to 0 */
 966	ov2735->current_page = 0;
 967
 968	ret = devm_mutex_init(ov2735->dev, &ov2735->page_lock);
 969	if (ret)
 970		return dev_err_probe(ov2735->dev, ret,
 971				     "Failed to initialize lock\n");
 972
 973	/* Get system clock (xvclk) */
 974	ov2735->xclk = devm_v4l2_sensor_clk_get(ov2735->dev, NULL);
 975	if (IS_ERR(ov2735->xclk))
 976		return dev_err_probe(ov2735->dev, PTR_ERR(ov2735->xclk),
 977				     "failed to get xclk\n");
 978
 979	xclk_freq = clk_get_rate(ov2735->xclk);
 980	if (xclk_freq != OV2735_XCLK_FREQ)
 981		return dev_err_probe(ov2735->dev, -EINVAL,
 982				     "xclk frequency not supported: %u Hz\n",
 983				     xclk_freq);
 984
 985	ret = ov2735_get_regulators(ov2735);
 986	if (ret)
 987		return dev_err_probe(ov2735->dev, ret,
 988				     "failed to get regulators\n");
 989
 990	ret = ov2735_parse_endpoint(ov2735);
 991	if (ret)
 992		return dev_err_probe(ov2735->dev, ret,
 993				     "failed to parse endpoint configuration\n");
 994
 995	ov2735->reset_gpio = devm_gpiod_get_optional(ov2735->dev,
 996						     "reset", GPIOD_OUT_LOW);
 997	if (IS_ERR(ov2735->reset_gpio))
 998		return dev_err_probe(ov2735->dev, PTR_ERR(ov2735->reset_gpio),
 999				     "failed to get reset GPIO\n");
1000
1001	ov2735->enable_gpio = devm_gpiod_get_optional(ov2735->dev,
1002						      "enable", GPIOD_OUT_LOW);
1003	if (IS_ERR(ov2735->enable_gpio))
1004		return dev_err_probe(ov2735->dev, PTR_ERR(ov2735->enable_gpio),
1005				     "failed to get enable GPIO\n");
1006
1007	ret = ov2735_power_on(ov2735->dev);
1008	if (ret)
1009		return ret;
1010
1011	ret = ov2735_identify_module(ov2735);
1012	if (ret)
1013		goto error_power_off;
1014
1015	ret = ov2735_init_controls(ov2735);
1016	if (ret)
1017		goto error_power_off;
1018
1019	/* Initialize subdev */
1020	ov2735->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1021	ov2735->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1022	ov2735->pad.flags = MEDIA_PAD_FL_SOURCE;
1023
1024	ret = media_entity_pads_init(&ov2735->sd.entity, 1, &ov2735->pad);
1025	if (ret) {
1026		dev_err_probe(ov2735->dev, ret, "failed to init entity pads\n");
1027		goto error_handler_free;
1028	}
1029
1030	ov2735->sd.state_lock = ov2735->handler.lock;
1031	ret = v4l2_subdev_init_finalize(&ov2735->sd);
1032	if (ret) {
1033		dev_err_probe(ov2735->dev, ret, "subdev init error\n");
1034		goto error_media_entity;
1035	}
1036
1037	ret = devm_pm_runtime_get_noresume(ov2735->dev);
1038	if (ret) {
1039		dev_err_probe(ov2735->dev, ret,
1040			      "failed to get runtime PM noresume\n");
1041		goto error_subdev_cleanup;
1042	}
1043
1044	ret = devm_pm_runtime_set_active_enabled(ov2735->dev);
1045	if (ret) {
1046		dev_err_probe(ov2735->dev, ret,
1047			      "failed to set runtime PM active+enabled\n");
1048		goto error_subdev_cleanup;
1049	}
1050
1051	ret = v4l2_async_register_subdev_sensor(&ov2735->sd);
1052	if (ret) {
1053		dev_err_probe(ov2735->dev, ret,
1054			      "failed to register ov2735 sub-device\n");
1055		goto error_subdev_cleanup;
1056	}
1057
1058	return 0;
1059
1060error_subdev_cleanup:
1061	v4l2_subdev_cleanup(&ov2735->sd);
1062
1063error_media_entity:
1064	media_entity_cleanup(&ov2735->sd.entity);
1065
1066error_handler_free:
1067	v4l2_ctrl_handler_free(ov2735->sd.ctrl_handler);
1068
1069error_power_off:
1070	ov2735_power_off(ov2735->dev);
1071
1072	return ret;
1073}
1074
1075static void ov2735_remove(struct i2c_client *client)
1076{
1077	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1078	struct ov2735 *ov2735 = to_ov2735(sd);
1079
1080	v4l2_async_unregister_subdev(sd);
1081	v4l2_subdev_cleanup(&ov2735->sd);
1082	media_entity_cleanup(&sd->entity);
1083	v4l2_ctrl_handler_free(ov2735->sd.ctrl_handler);
1084}
1085
1086static DEFINE_RUNTIME_DEV_PM_OPS(ov2735_pm_ops,
1087				 ov2735_power_off, ov2735_power_on, NULL);
1088
1089static const struct of_device_id ov2735_id[] = {
1090	{ .compatible = "ovti,ov2735" },
1091	{ /* sentinel */ }
1092};
1093MODULE_DEVICE_TABLE(of, ov2735_id);
1094
1095static struct i2c_driver ov2735_driver = {
1096	.driver = {
1097		.name = "ov2735",
1098		.pm = pm_ptr(&ov2735_pm_ops),
1099		.of_match_table = ov2735_id,
1100	},
1101	.probe = ov2735_probe,
1102	.remove = ov2735_remove,
1103};
1104module_i2c_driver(ov2735_driver);
1105
1106MODULE_DESCRIPTION("OV2735 Camera Sensor Driver");
1107MODULE_AUTHOR("Hardevsinh Palaniya <hardevsinh.palaniya@siliconsignals.io>");
1108MODULE_AUTHOR("Himanshu Bhavani <himanshu.bhavani@siliconsignals.io>");
1109MODULE_LICENSE("GPL");