ov13858.c

   1// SPDX-License-Identifier: GPL-2.0
   2// Copyright (c) 2017 Intel Corporation.
   3
   4#include <linux/acpi.h>
   5#include <linux/clk.h>
   6#include <linux/i2c.h>
   7#include <linux/module.h>
   8#include <linux/pm_runtime.h>
   9#include <media/v4l2-ctrls.h>
  10#include <media/v4l2-device.h>
  11#include <media/v4l2-event.h>
  12#include <media/v4l2-fwnode.h>
  13
  14#define OV13858_REG_VALUE_08BIT		1
  15#define OV13858_REG_VALUE_16BIT		2
  16#define OV13858_REG_VALUE_24BIT		3
  17
  18#define OV13858_REG_MODE_SELECT		0x0100
  19#define OV13858_MODE_STANDBY		0x00
  20#define OV13858_MODE_STREAMING		0x01
  21
  22#define OV13858_REG_SOFTWARE_RST	0x0103
  23#define OV13858_SOFTWARE_RST		0x01
  24
  25/* PLL1 generates PCLK and MIPI_PHY_CLK */
  26#define OV13858_REG_PLL1_CTRL_0		0x0300
  27#define OV13858_REG_PLL1_CTRL_1		0x0301
  28#define OV13858_REG_PLL1_CTRL_2		0x0302
  29#define OV13858_REG_PLL1_CTRL_3		0x0303
  30#define OV13858_REG_PLL1_CTRL_4		0x0304
  31#define OV13858_REG_PLL1_CTRL_5		0x0305
  32
  33/* PLL2 generates DAC_CLK, SCLK and SRAM_CLK */
  34#define OV13858_REG_PLL2_CTRL_B		0x030b
  35#define OV13858_REG_PLL2_CTRL_C		0x030c
  36#define OV13858_REG_PLL2_CTRL_D		0x030d
  37#define OV13858_REG_PLL2_CTRL_E		0x030e
  38#define OV13858_REG_PLL2_CTRL_F		0x030f
  39#define OV13858_REG_PLL2_CTRL_12	0x0312
  40#define OV13858_REG_MIPI_SC_CTRL0	0x3016
  41#define OV13858_REG_MIPI_SC_CTRL1	0x3022
  42
  43/* Chip ID */
  44#define OV13858_REG_CHIP_ID		0x300a
  45#define OV13858_CHIP_ID			0x00d855
  46
  47/* V_TIMING internal */
  48#define OV13858_REG_VTS			0x380e
  49#define OV13858_VTS_30FPS		0x0c8e /* 30 fps */
  50#define OV13858_VTS_60FPS		0x0648 /* 60 fps */
  51#define OV13858_VTS_MAX			0x7fff
  52
  53/* HBLANK control - read only */
  54#define OV13858_PPL_270MHZ		2244
  55#define OV13858_PPL_540MHZ		4488
  56
  57/* Exposure control */
  58#define OV13858_REG_EXPOSURE		0x3500
  59#define OV13858_EXPOSURE_MIN		4
  60#define OV13858_EXPOSURE_STEP		1
  61#define OV13858_EXPOSURE_DEFAULT	0x640
  62
  63/* Analog gain control */
  64#define OV13858_REG_ANALOG_GAIN		0x3508
  65#define OV13858_ANA_GAIN_MIN		0
  66#define OV13858_ANA_GAIN_MAX		0x1fff
  67#define OV13858_ANA_GAIN_STEP		1
  68#define OV13858_ANA_GAIN_DEFAULT	0x80
  69
  70/* Digital gain control */
  71#define OV13858_REG_B_MWB_GAIN		0x5100
  72#define OV13858_REG_G_MWB_GAIN		0x5102
  73#define OV13858_REG_R_MWB_GAIN		0x5104
  74#define OV13858_DGTL_GAIN_MIN		0
  75#define OV13858_DGTL_GAIN_MAX		16384	/* Max = 16 X */
  76#define OV13858_DGTL_GAIN_DEFAULT	1024	/* Default gain = 1 X */
  77#define OV13858_DGTL_GAIN_STEP		1	/* Each step = 1/1024 */
  78
  79/* Test Pattern Control */
  80#define OV13858_REG_TEST_PATTERN	0x4503
  81#define OV13858_TEST_PATTERN_ENABLE	BIT(7)
  82#define OV13858_TEST_PATTERN_MASK	0xfc
  83
  84/* Number of frames to skip */
  85#define OV13858_NUM_OF_SKIP_FRAMES	2
  86
  87struct ov13858_reg {
  88	u16 address;
  89	u8 val;
  90};
  91
  92struct ov13858_reg_list {
  93	u32 num_of_regs;
  94	const struct ov13858_reg *regs;
  95};
  96
  97/* Link frequency config */
  98struct ov13858_link_freq_config {
  99	u32 pixels_per_line;
 100
 101	/* PLL registers for this link frequency */
 102	struct ov13858_reg_list reg_list;
 103};
 104
 105/* Mode : resolution and related config&values */
 106struct ov13858_mode {
 107	/* Frame width */
 108	u32 width;
 109	/* Frame height */
 110	u32 height;
 111
 112	/* V-timing */
 113	u32 vts_def;
 114	u32 vts_min;
 115
 116	/* Index of Link frequency config to be used */
 117	u32 link_freq_index;
 118	/* Default register values */
 119	struct ov13858_reg_list reg_list;
 120};
 121
 122/* 4224x3136 needs 1080Mbps/lane, 4 lanes */
 123static const struct ov13858_reg mipi_data_rate_1080mbps[] = {
 124	/* PLL1 registers */
 125	{OV13858_REG_PLL1_CTRL_0, 0x07},
 126	{OV13858_REG_PLL1_CTRL_1, 0x01},
 127	{OV13858_REG_PLL1_CTRL_2, 0xc2},
 128	{OV13858_REG_PLL1_CTRL_3, 0x00},
 129	{OV13858_REG_PLL1_CTRL_4, 0x00},
 130	{OV13858_REG_PLL1_CTRL_5, 0x01},
 131
 132	/* PLL2 registers */
 133	{OV13858_REG_PLL2_CTRL_B, 0x05},
 134	{OV13858_REG_PLL2_CTRL_C, 0x01},
 135	{OV13858_REG_PLL2_CTRL_D, 0x0e},
 136	{OV13858_REG_PLL2_CTRL_E, 0x05},
 137	{OV13858_REG_PLL2_CTRL_F, 0x01},
 138	{OV13858_REG_PLL2_CTRL_12, 0x01},
 139	{OV13858_REG_MIPI_SC_CTRL0, 0x72},
 140	{OV13858_REG_MIPI_SC_CTRL1, 0x01},
 141};
 142
 143/*
 144 * 2112x1568, 2112x1188, 1056x784 need 540Mbps/lane,
 145 * 4 lanes
 146 */
 147static const struct ov13858_reg mipi_data_rate_540mbps[] = {
 148	/* PLL1 registers */
 149	{OV13858_REG_PLL1_CTRL_0, 0x07},
 150	{OV13858_REG_PLL1_CTRL_1, 0x01},
 151	{OV13858_REG_PLL1_CTRL_2, 0xc2},
 152	{OV13858_REG_PLL1_CTRL_3, 0x01},
 153	{OV13858_REG_PLL1_CTRL_4, 0x00},
 154	{OV13858_REG_PLL1_CTRL_5, 0x01},
 155
 156	/* PLL2 registers */
 157	{OV13858_REG_PLL2_CTRL_B, 0x05},
 158	{OV13858_REG_PLL2_CTRL_C, 0x01},
 159	{OV13858_REG_PLL2_CTRL_D, 0x0e},
 160	{OV13858_REG_PLL2_CTRL_E, 0x05},
 161	{OV13858_REG_PLL2_CTRL_F, 0x01},
 162	{OV13858_REG_PLL2_CTRL_12, 0x01},
 163	{OV13858_REG_MIPI_SC_CTRL0, 0x72},
 164	{OV13858_REG_MIPI_SC_CTRL1, 0x01},
 165};
 166
 167static const struct ov13858_reg mode_4224x3136_regs[] = {
 168	{0x3013, 0x32},
 169	{0x301b, 0xf0},
 170	{0x301f, 0xd0},
 171	{0x3106, 0x15},
 172	{0x3107, 0x23},
 173	{0x350a, 0x00},
 174	{0x350e, 0x00},
 175	{0x3510, 0x00},
 176	{0x3511, 0x02},
 177	{0x3512, 0x00},
 178	{0x3600, 0x2b},
 179	{0x3601, 0x52},
 180	{0x3602, 0x60},
 181	{0x3612, 0x05},
 182	{0x3613, 0xa4},
 183	{0x3620, 0x80},
 184	{0x3621, 0x10},
 185	{0x3622, 0x30},
 186	{0x3624, 0x1c},
 187	{0x3640, 0x10},
 188	{0x3641, 0x70},
 189	{0x3660, 0x04},
 190	{0x3661, 0x80},
 191	{0x3662, 0x12},
 192	{0x3664, 0x73},
 193	{0x3665, 0xa7},
 194	{0x366e, 0xff},
 195	{0x366f, 0xf4},
 196	{0x3674, 0x00},
 197	{0x3679, 0x0c},
 198	{0x367f, 0x01},
 199	{0x3680, 0x0c},
 200	{0x3681, 0x50},
 201	{0x3682, 0x50},
 202	{0x3683, 0xa9},
 203	{0x3684, 0xa9},
 204	{0x3709, 0x5f},
 205	{0x3714, 0x24},
 206	{0x371a, 0x3e},
 207	{0x3737, 0x04},
 208	{0x3738, 0xcc},
 209	{0x3739, 0x12},
 210	{0x373d, 0x26},
 211	{0x3764, 0x20},
 212	{0x3765, 0x20},
 213	{0x37a1, 0x36},
 214	{0x37a8, 0x3b},
 215	{0x37ab, 0x31},
 216	{0x37c2, 0x04},
 217	{0x37c3, 0xf1},
 218	{0x37c5, 0x00},
 219	{0x37d8, 0x03},
 220	{0x37d9, 0x0c},
 221	{0x37da, 0xc2},
 222	{0x37dc, 0x02},
 223	{0x37e0, 0x00},
 224	{0x37e1, 0x0a},
 225	{0x37e2, 0x14},
 226	{0x37e3, 0x04},
 227	{0x37e4, 0x2a},
 228	{0x37e5, 0x03},
 229	{0x37e6, 0x04},
 230	{0x3800, 0x00},
 231	{0x3801, 0x00},
 232	{0x3802, 0x00},
 233	{0x3803, 0x08},
 234	{0x3804, 0x10},
 235	{0x3805, 0x9f},
 236	{0x3806, 0x0c},
 237	{0x3807, 0x57},
 238	{0x3808, 0x10},
 239	{0x3809, 0x80},
 240	{0x380a, 0x0c},
 241	{0x380b, 0x40},
 242	{0x380c, 0x04},
 243	{0x380d, 0x62},
 244	{0x380e, 0x0c},
 245	{0x380f, 0x8e},
 246	{0x3811, 0x04},
 247	{0x3813, 0x05},
 248	{0x3814, 0x01},
 249	{0x3815, 0x01},
 250	{0x3816, 0x01},
 251	{0x3817, 0x01},
 252	{0x3820, 0xa8},
 253	{0x3821, 0x00},
 254	{0x3822, 0xc2},
 255	{0x3823, 0x18},
 256	{0x3826, 0x11},
 257	{0x3827, 0x1c},
 258	{0x3829, 0x03},
 259	{0x3832, 0x00},
 260	{0x3c80, 0x00},
 261	{0x3c87, 0x01},
 262	{0x3c8c, 0x19},
 263	{0x3c8d, 0x1c},
 264	{0x3c90, 0x00},
 265	{0x3c91, 0x00},
 266	{0x3c92, 0x00},
 267	{0x3c93, 0x00},
 268	{0x3c94, 0x40},
 269	{0x3c95, 0x54},
 270	{0x3c96, 0x34},
 271	{0x3c97, 0x04},
 272	{0x3c98, 0x00},
 273	{0x3d8c, 0x73},
 274	{0x3d8d, 0xc0},
 275	{0x3f00, 0x0b},
 276	{0x3f03, 0x00},
 277	{0x4001, 0xe0},
 278	{0x4008, 0x00},
 279	{0x4009, 0x0f},
 280	{0x4011, 0xf0},
 281	{0x4017, 0x08},
 282	{0x4050, 0x04},
 283	{0x4051, 0x0b},
 284	{0x4052, 0x00},
 285	{0x4053, 0x80},
 286	{0x4054, 0x00},
 287	{0x4055, 0x80},
 288	{0x4056, 0x00},
 289	{0x4057, 0x80},
 290	{0x4058, 0x00},
 291	{0x4059, 0x80},
 292	{0x405e, 0x20},
 293	{0x4500, 0x07},
 294	{0x4503, 0x00},
 295	{0x450a, 0x04},
 296	{0x4809, 0x04},
 297	{0x480c, 0x12},
 298	{0x481f, 0x30},
 299	{0x4833, 0x10},
 300	{0x4837, 0x0e},
 301	{0x4902, 0x01},
 302	{0x4d00, 0x03},
 303	{0x4d01, 0xc9},
 304	{0x4d02, 0xbc},
 305	{0x4d03, 0xd7},
 306	{0x4d04, 0xf0},
 307	{0x4d05, 0xa2},
 308	{0x5000, 0xfd},
 309	{0x5001, 0x01},
 310	{0x5040, 0x39},
 311	{0x5041, 0x10},
 312	{0x5042, 0x10},
 313	{0x5043, 0x84},
 314	{0x5044, 0x62},
 315	{0x5180, 0x00},
 316	{0x5181, 0x10},
 317	{0x5182, 0x02},
 318	{0x5183, 0x0f},
 319	{0x5200, 0x1b},
 320	{0x520b, 0x07},
 321	{0x520c, 0x0f},
 322	{0x5300, 0x04},
 323	{0x5301, 0x0c},
 324	{0x5302, 0x0c},
 325	{0x5303, 0x0f},
 326	{0x5304, 0x00},
 327	{0x5305, 0x70},
 328	{0x5306, 0x00},
 329	{0x5307, 0x80},
 330	{0x5308, 0x00},
 331	{0x5309, 0xa5},
 332	{0x530a, 0x00},
 333	{0x530b, 0xd3},
 334	{0x530c, 0x00},
 335	{0x530d, 0xf0},
 336	{0x530e, 0x01},
 337	{0x530f, 0x10},
 338	{0x5310, 0x01},
 339	{0x5311, 0x20},
 340	{0x5312, 0x01},
 341	{0x5313, 0x20},
 342	{0x5314, 0x01},
 343	{0x5315, 0x20},
 344	{0x5316, 0x08},
 345	{0x5317, 0x08},
 346	{0x5318, 0x10},
 347	{0x5319, 0x88},
 348	{0x531a, 0x88},
 349	{0x531b, 0xa9},
 350	{0x531c, 0xaa},
 351	{0x531d, 0x0a},
 352	{0x5405, 0x02},
 353	{0x5406, 0x67},
 354	{0x5407, 0x01},
 355	{0x5408, 0x4a},
 356};
 357
 358static const struct ov13858_reg mode_2112x1568_regs[] = {
 359	{0x3013, 0x32},
 360	{0x301b, 0xf0},
 361	{0x301f, 0xd0},
 362	{0x3106, 0x15},
 363	{0x3107, 0x23},
 364	{0x350a, 0x00},
 365	{0x350e, 0x00},
 366	{0x3510, 0x00},
 367	{0x3511, 0x02},
 368	{0x3512, 0x00},
 369	{0x3600, 0x2b},
 370	{0x3601, 0x52},
 371	{0x3602, 0x60},
 372	{0x3612, 0x05},
 373	{0x3613, 0xa4},
 374	{0x3620, 0x80},
 375	{0x3621, 0x10},
 376	{0x3622, 0x30},
 377	{0x3624, 0x1c},
 378	{0x3640, 0x10},
 379	{0x3641, 0x70},
 380	{0x3660, 0x04},
 381	{0x3661, 0x80},
 382	{0x3662, 0x10},
 383	{0x3664, 0x73},
 384	{0x3665, 0xa7},
 385	{0x366e, 0xff},
 386	{0x366f, 0xf4},
 387	{0x3674, 0x00},
 388	{0x3679, 0x0c},
 389	{0x367f, 0x01},
 390	{0x3680, 0x0c},
 391	{0x3681, 0x50},
 392	{0x3682, 0x50},
 393	{0x3683, 0xa9},
 394	{0x3684, 0xa9},
 395	{0x3709, 0x5f},
 396	{0x3714, 0x28},
 397	{0x371a, 0x3e},
 398	{0x3737, 0x08},
 399	{0x3738, 0xcc},
 400	{0x3739, 0x20},
 401	{0x373d, 0x26},
 402	{0x3764, 0x20},
 403	{0x3765, 0x20},
 404	{0x37a1, 0x36},
 405	{0x37a8, 0x3b},
 406	{0x37ab, 0x31},
 407	{0x37c2, 0x14},
 408	{0x37c3, 0xf1},
 409	{0x37c5, 0x00},
 410	{0x37d8, 0x03},
 411	{0x37d9, 0x0c},
 412	{0x37da, 0xc2},
 413	{0x37dc, 0x02},
 414	{0x37e0, 0x00},
 415	{0x37e1, 0x0a},
 416	{0x37e2, 0x14},
 417	{0x37e3, 0x08},
 418	{0x37e4, 0x38},
 419	{0x37e5, 0x03},
 420	{0x37e6, 0x08},
 421	{0x3800, 0x00},
 422	{0x3801, 0x00},
 423	{0x3802, 0x00},
 424	{0x3803, 0x00},
 425	{0x3804, 0x10},
 426	{0x3805, 0x9f},
 427	{0x3806, 0x0c},
 428	{0x3807, 0x5f},
 429	{0x3808, 0x08},
 430	{0x3809, 0x40},
 431	{0x380a, 0x06},
 432	{0x380b, 0x20},
 433	{0x380c, 0x04},
 434	{0x380d, 0x62},
 435	{0x380e, 0x0c},
 436	{0x380f, 0x8e},
 437	{0x3811, 0x04},
 438	{0x3813, 0x05},
 439	{0x3814, 0x03},
 440	{0x3815, 0x01},
 441	{0x3816, 0x03},
 442	{0x3817, 0x01},
 443	{0x3820, 0xab},
 444	{0x3821, 0x00},
 445	{0x3822, 0xc2},
 446	{0x3823, 0x18},
 447	{0x3826, 0x04},
 448	{0x3827, 0x90},
 449	{0x3829, 0x07},
 450	{0x3832, 0x00},
 451	{0x3c80, 0x00},
 452	{0x3c87, 0x01},
 453	{0x3c8c, 0x19},
 454	{0x3c8d, 0x1c},
 455	{0x3c90, 0x00},
 456	{0x3c91, 0x00},
 457	{0x3c92, 0x00},
 458	{0x3c93, 0x00},
 459	{0x3c94, 0x40},
 460	{0x3c95, 0x54},
 461	{0x3c96, 0x34},
 462	{0x3c97, 0x04},
 463	{0x3c98, 0x00},
 464	{0x3d8c, 0x73},
 465	{0x3d8d, 0xc0},
 466	{0x3f00, 0x0b},
 467	{0x3f03, 0x00},
 468	{0x4001, 0xe0},
 469	{0x4008, 0x00},
 470	{0x4009, 0x0d},
 471	{0x4011, 0xf0},
 472	{0x4017, 0x08},
 473	{0x4050, 0x04},
 474	{0x4051, 0x0b},
 475	{0x4052, 0x00},
 476	{0x4053, 0x80},
 477	{0x4054, 0x00},
 478	{0x4055, 0x80},
 479	{0x4056, 0x00},
 480	{0x4057, 0x80},
 481	{0x4058, 0x00},
 482	{0x4059, 0x80},
 483	{0x405e, 0x20},
 484	{0x4500, 0x07},
 485	{0x4503, 0x00},
 486	{0x450a, 0x04},
 487	{0x4809, 0x04},
 488	{0x480c, 0x12},
 489	{0x481f, 0x30},
 490	{0x4833, 0x10},
 491	{0x4837, 0x1c},
 492	{0x4902, 0x01},
 493	{0x4d00, 0x03},
 494	{0x4d01, 0xc9},
 495	{0x4d02, 0xbc},
 496	{0x4d03, 0xd7},
 497	{0x4d04, 0xf0},
 498	{0x4d05, 0xa2},
 499	{0x5000, 0xfd},
 500	{0x5001, 0x01},
 501	{0x5040, 0x39},
 502	{0x5041, 0x10},
 503	{0x5042, 0x10},
 504	{0x5043, 0x84},
 505	{0x5044, 0x62},
 506	{0x5180, 0x00},
 507	{0x5181, 0x10},
 508	{0x5182, 0x02},
 509	{0x5183, 0x0f},
 510	{0x5200, 0x1b},
 511	{0x520b, 0x07},
 512	{0x520c, 0x0f},
 513	{0x5300, 0x04},
 514	{0x5301, 0x0c},
 515	{0x5302, 0x0c},
 516	{0x5303, 0x0f},
 517	{0x5304, 0x00},
 518	{0x5305, 0x70},
 519	{0x5306, 0x00},
 520	{0x5307, 0x80},
 521	{0x5308, 0x00},
 522	{0x5309, 0xa5},
 523	{0x530a, 0x00},
 524	{0x530b, 0xd3},
 525	{0x530c, 0x00},
 526	{0x530d, 0xf0},
 527	{0x530e, 0x01},
 528	{0x530f, 0x10},
 529	{0x5310, 0x01},
 530	{0x5311, 0x20},
 531	{0x5312, 0x01},
 532	{0x5313, 0x20},
 533	{0x5314, 0x01},
 534	{0x5315, 0x20},
 535	{0x5316, 0x08},
 536	{0x5317, 0x08},
 537	{0x5318, 0x10},
 538	{0x5319, 0x88},
 539	{0x531a, 0x88},
 540	{0x531b, 0xa9},
 541	{0x531c, 0xaa},
 542	{0x531d, 0x0a},
 543	{0x5405, 0x02},
 544	{0x5406, 0x67},
 545	{0x5407, 0x01},
 546	{0x5408, 0x4a},
 547};
 548
 549static const struct ov13858_reg mode_2112x1188_regs[] = {
 550	{0x3013, 0x32},
 551	{0x301b, 0xf0},
 552	{0x301f, 0xd0},
 553	{0x3106, 0x15},
 554	{0x3107, 0x23},
 555	{0x350a, 0x00},
 556	{0x350e, 0x00},
 557	{0x3510, 0x00},
 558	{0x3511, 0x02},
 559	{0x3512, 0x00},
 560	{0x3600, 0x2b},
 561	{0x3601, 0x52},
 562	{0x3602, 0x60},
 563	{0x3612, 0x05},
 564	{0x3613, 0xa4},
 565	{0x3620, 0x80},
 566	{0x3621, 0x10},
 567	{0x3622, 0x30},
 568	{0x3624, 0x1c},
 569	{0x3640, 0x10},
 570	{0x3641, 0x70},
 571	{0x3660, 0x04},
 572	{0x3661, 0x80},
 573	{0x3662, 0x10},
 574	{0x3664, 0x73},
 575	{0x3665, 0xa7},
 576	{0x366e, 0xff},
 577	{0x366f, 0xf4},
 578	{0x3674, 0x00},
 579	{0x3679, 0x0c},
 580	{0x367f, 0x01},
 581	{0x3680, 0x0c},
 582	{0x3681, 0x50},
 583	{0x3682, 0x50},
 584	{0x3683, 0xa9},
 585	{0x3684, 0xa9},
 586	{0x3709, 0x5f},
 587	{0x3714, 0x28},
 588	{0x371a, 0x3e},
 589	{0x3737, 0x08},
 590	{0x3738, 0xcc},
 591	{0x3739, 0x20},
 592	{0x373d, 0x26},
 593	{0x3764, 0x20},
 594	{0x3765, 0x20},
 595	{0x37a1, 0x36},
 596	{0x37a8, 0x3b},
 597	{0x37ab, 0x31},
 598	{0x37c2, 0x14},
 599	{0x37c3, 0xf1},
 600	{0x37c5, 0x00},
 601	{0x37d8, 0x03},
 602	{0x37d9, 0x0c},
 603	{0x37da, 0xc2},
 604	{0x37dc, 0x02},
 605	{0x37e0, 0x00},
 606	{0x37e1, 0x0a},
 607	{0x37e2, 0x14},
 608	{0x37e3, 0x08},
 609	{0x37e4, 0x38},
 610	{0x37e5, 0x03},
 611	{0x37e6, 0x08},
 612	{0x3800, 0x00},
 613	{0x3801, 0x00},
 614	{0x3802, 0x01},
 615	{0x3803, 0x84},
 616	{0x3804, 0x10},
 617	{0x3805, 0x9f},
 618	{0x3806, 0x0a},
 619	{0x3807, 0xd3},
 620	{0x3808, 0x08},
 621	{0x3809, 0x40},
 622	{0x380a, 0x04},
 623	{0x380b, 0xa4},
 624	{0x380c, 0x04},
 625	{0x380d, 0x62},
 626	{0x380e, 0x0c},
 627	{0x380f, 0x8e},
 628	{0x3811, 0x08},
 629	{0x3813, 0x03},
 630	{0x3814, 0x03},
 631	{0x3815, 0x01},
 632	{0x3816, 0x03},
 633	{0x3817, 0x01},
 634	{0x3820, 0xab},
 635	{0x3821, 0x00},
 636	{0x3822, 0xc2},
 637	{0x3823, 0x18},
 638	{0x3826, 0x04},
 639	{0x3827, 0x90},
 640	{0x3829, 0x07},
 641	{0x3832, 0x00},
 642	{0x3c80, 0x00},
 643	{0x3c87, 0x01},
 644	{0x3c8c, 0x19},
 645	{0x3c8d, 0x1c},
 646	{0x3c90, 0x00},
 647	{0x3c91, 0x00},
 648	{0x3c92, 0x00},
 649	{0x3c93, 0x00},
 650	{0x3c94, 0x40},
 651	{0x3c95, 0x54},
 652	{0x3c96, 0x34},
 653	{0x3c97, 0x04},
 654	{0x3c98, 0x00},
 655	{0x3d8c, 0x73},
 656	{0x3d8d, 0xc0},
 657	{0x3f00, 0x0b},
 658	{0x3f03, 0x00},
 659	{0x4001, 0xe0},
 660	{0x4008, 0x00},
 661	{0x4009, 0x0d},
 662	{0x4011, 0xf0},
 663	{0x4017, 0x08},
 664	{0x4050, 0x04},
 665	{0x4051, 0x0b},
 666	{0x4052, 0x00},
 667	{0x4053, 0x80},
 668	{0x4054, 0x00},
 669	{0x4055, 0x80},
 670	{0x4056, 0x00},
 671	{0x4057, 0x80},
 672	{0x4058, 0x00},
 673	{0x4059, 0x80},
 674	{0x405e, 0x20},
 675	{0x4500, 0x07},
 676	{0x4503, 0x00},
 677	{0x450a, 0x04},
 678	{0x4809, 0x04},
 679	{0x480c, 0x12},
 680	{0x481f, 0x30},
 681	{0x4833, 0x10},
 682	{0x4837, 0x1c},
 683	{0x4902, 0x01},
 684	{0x4d00, 0x03},
 685	{0x4d01, 0xc9},
 686	{0x4d02, 0xbc},
 687	{0x4d03, 0xd7},
 688	{0x4d04, 0xf0},
 689	{0x4d05, 0xa2},
 690	{0x5000, 0xfd},
 691	{0x5001, 0x01},
 692	{0x5040, 0x39},
 693	{0x5041, 0x10},
 694	{0x5042, 0x10},
 695	{0x5043, 0x84},
 696	{0x5044, 0x62},
 697	{0x5180, 0x00},
 698	{0x5181, 0x10},
 699	{0x5182, 0x02},
 700	{0x5183, 0x0f},
 701	{0x5200, 0x1b},
 702	{0x520b, 0x07},
 703	{0x520c, 0x0f},
 704	{0x5300, 0x04},
 705	{0x5301, 0x0c},
 706	{0x5302, 0x0c},
 707	{0x5303, 0x0f},
 708	{0x5304, 0x00},
 709	{0x5305, 0x70},
 710	{0x5306, 0x00},
 711	{0x5307, 0x80},
 712	{0x5308, 0x00},
 713	{0x5309, 0xa5},
 714	{0x530a, 0x00},
 715	{0x530b, 0xd3},
 716	{0x530c, 0x00},
 717	{0x530d, 0xf0},
 718	{0x530e, 0x01},
 719	{0x530f, 0x10},
 720	{0x5310, 0x01},
 721	{0x5311, 0x20},
 722	{0x5312, 0x01},
 723	{0x5313, 0x20},
 724	{0x5314, 0x01},
 725	{0x5315, 0x20},
 726	{0x5316, 0x08},
 727	{0x5317, 0x08},
 728	{0x5318, 0x10},
 729	{0x5319, 0x88},
 730	{0x531a, 0x88},
 731	{0x531b, 0xa9},
 732	{0x531c, 0xaa},
 733	{0x531d, 0x0a},
 734	{0x5405, 0x02},
 735	{0x5406, 0x67},
 736	{0x5407, 0x01},
 737	{0x5408, 0x4a},
 738};
 739
 740static const struct ov13858_reg mode_1056x784_regs[] = {
 741	{0x3013, 0x32},
 742	{0x301b, 0xf0},
 743	{0x301f, 0xd0},
 744	{0x3106, 0x15},
 745	{0x3107, 0x23},
 746	{0x350a, 0x00},
 747	{0x350e, 0x00},
 748	{0x3510, 0x00},
 749	{0x3511, 0x02},
 750	{0x3512, 0x00},
 751	{0x3600, 0x2b},
 752	{0x3601, 0x52},
 753	{0x3602, 0x60},
 754	{0x3612, 0x05},
 755	{0x3613, 0xa4},
 756	{0x3620, 0x80},
 757	{0x3621, 0x10},
 758	{0x3622, 0x30},
 759	{0x3624, 0x1c},
 760	{0x3640, 0x10},
 761	{0x3641, 0x70},
 762	{0x3660, 0x04},
 763	{0x3661, 0x80},
 764	{0x3662, 0x08},
 765	{0x3664, 0x73},
 766	{0x3665, 0xa7},
 767	{0x366e, 0xff},
 768	{0x366f, 0xf4},
 769	{0x3674, 0x00},
 770	{0x3679, 0x0c},
 771	{0x367f, 0x01},
 772	{0x3680, 0x0c},
 773	{0x3681, 0x50},
 774	{0x3682, 0x50},
 775	{0x3683, 0xa9},
 776	{0x3684, 0xa9},
 777	{0x3709, 0x5f},
 778	{0x3714, 0x30},
 779	{0x371a, 0x3e},
 780	{0x3737, 0x08},
 781	{0x3738, 0xcc},
 782	{0x3739, 0x20},
 783	{0x373d, 0x26},
 784	{0x3764, 0x20},
 785	{0x3765, 0x20},
 786	{0x37a1, 0x36},
 787	{0x37a8, 0x3b},
 788	{0x37ab, 0x31},
 789	{0x37c2, 0x2c},
 790	{0x37c3, 0xf1},
 791	{0x37c5, 0x00},
 792	{0x37d8, 0x03},
 793	{0x37d9, 0x06},
 794	{0x37da, 0xc2},
 795	{0x37dc, 0x02},
 796	{0x37e0, 0x00},
 797	{0x37e1, 0x0a},
 798	{0x37e2, 0x14},
 799	{0x37e3, 0x08},
 800	{0x37e4, 0x36},
 801	{0x37e5, 0x03},
 802	{0x37e6, 0x08},
 803	{0x3800, 0x00},
 804	{0x3801, 0x00},
 805	{0x3802, 0x00},
 806	{0x3803, 0x00},
 807	{0x3804, 0x10},
 808	{0x3805, 0x9f},
 809	{0x3806, 0x0c},
 810	{0x3807, 0x5f},
 811	{0x3808, 0x04},
 812	{0x3809, 0x20},
 813	{0x380a, 0x03},
 814	{0x380b, 0x10},
 815	{0x380c, 0x04},
 816	{0x380d, 0x62},
 817	{0x380e, 0x0c},
 818	{0x380f, 0x8e},
 819	{0x3811, 0x04},
 820	{0x3813, 0x05},
 821	{0x3814, 0x07},
 822	{0x3815, 0x01},
 823	{0x3816, 0x07},
 824	{0x3817, 0x01},
 825	{0x3820, 0xac},
 826	{0x3821, 0x00},
 827	{0x3822, 0xc2},
 828	{0x3823, 0x18},
 829	{0x3826, 0x04},
 830	{0x3827, 0x48},
 831	{0x3829, 0x03},
 832	{0x3832, 0x00},
 833	{0x3c80, 0x00},
 834	{0x3c87, 0x01},
 835	{0x3c8c, 0x19},
 836	{0x3c8d, 0x1c},
 837	{0x3c90, 0x00},
 838	{0x3c91, 0x00},
 839	{0x3c92, 0x00},
 840	{0x3c93, 0x00},
 841	{0x3c94, 0x40},
 842	{0x3c95, 0x54},
 843	{0x3c96, 0x34},
 844	{0x3c97, 0x04},
 845	{0x3c98, 0x00},
 846	{0x3d8c, 0x73},
 847	{0x3d8d, 0xc0},
 848	{0x3f00, 0x0b},
 849	{0x3f03, 0x00},
 850	{0x4001, 0xe0},
 851	{0x4008, 0x00},
 852	{0x4009, 0x05},
 853	{0x4011, 0xf0},
 854	{0x4017, 0x08},
 855	{0x4050, 0x02},
 856	{0x4051, 0x05},
 857	{0x4052, 0x00},
 858	{0x4053, 0x80},
 859	{0x4054, 0x00},
 860	{0x4055, 0x80},
 861	{0x4056, 0x00},
 862	{0x4057, 0x80},
 863	{0x4058, 0x00},
 864	{0x4059, 0x80},
 865	{0x405e, 0x20},
 866	{0x4500, 0x07},
 867	{0x4503, 0x00},
 868	{0x450a, 0x04},
 869	{0x4809, 0x04},
 870	{0x480c, 0x12},
 871	{0x481f, 0x30},
 872	{0x4833, 0x10},
 873	{0x4837, 0x1e},
 874	{0x4902, 0x02},
 875	{0x4d00, 0x03},
 876	{0x4d01, 0xc9},
 877	{0x4d02, 0xbc},
 878	{0x4d03, 0xd7},
 879	{0x4d04, 0xf0},
 880	{0x4d05, 0xa2},
 881	{0x5000, 0xfd},
 882	{0x5001, 0x01},
 883	{0x5040, 0x39},
 884	{0x5041, 0x10},
 885	{0x5042, 0x10},
 886	{0x5043, 0x84},
 887	{0x5044, 0x62},
 888	{0x5180, 0x00},
 889	{0x5181, 0x10},
 890	{0x5182, 0x02},
 891	{0x5183, 0x0f},
 892	{0x5200, 0x1b},
 893	{0x520b, 0x07},
 894	{0x520c, 0x0f},
 895	{0x5300, 0x04},
 896	{0x5301, 0x0c},
 897	{0x5302, 0x0c},
 898	{0x5303, 0x0f},
 899	{0x5304, 0x00},
 900	{0x5305, 0x70},
 901	{0x5306, 0x00},
 902	{0x5307, 0x80},
 903	{0x5308, 0x00},
 904	{0x5309, 0xa5},
 905	{0x530a, 0x00},
 906	{0x530b, 0xd3},
 907	{0x530c, 0x00},
 908	{0x530d, 0xf0},
 909	{0x530e, 0x01},
 910	{0x530f, 0x10},
 911	{0x5310, 0x01},
 912	{0x5311, 0x20},
 913	{0x5312, 0x01},
 914	{0x5313, 0x20},
 915	{0x5314, 0x01},
 916	{0x5315, 0x20},
 917	{0x5316, 0x08},
 918	{0x5317, 0x08},
 919	{0x5318, 0x10},
 920	{0x5319, 0x88},
 921	{0x531a, 0x88},
 922	{0x531b, 0xa9},
 923	{0x531c, 0xaa},
 924	{0x531d, 0x0a},
 925	{0x5405, 0x02},
 926	{0x5406, 0x67},
 927	{0x5407, 0x01},
 928	{0x5408, 0x4a},
 929};
 930
 931static const char * const ov13858_test_pattern_menu[] = {
 932	"Disabled",
 933	"Vertical Color Bar Type 1",
 934	"Vertical Color Bar Type 2",
 935	"Vertical Color Bar Type 3",
 936	"Vertical Color Bar Type 4"
 937};
 938
 939/* Configurations for supported link frequencies */
 940#define OV13858_NUM_OF_LINK_FREQS	2
 941#define OV13858_LINK_FREQ_540MHZ	540000000ULL
 942#define OV13858_LINK_FREQ_270MHZ	270000000ULL
 943#define OV13858_LINK_FREQ_INDEX_0	0
 944#define OV13858_LINK_FREQ_INDEX_1	1
 945
 946/*
 947 * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample
 948 * data rate => double data rate; number of lanes => 4; bits per pixel => 10
 949 */
 950static u64 link_freq_to_pixel_rate(u64 f)
 951{
 952	f *= 2 * 4;
 953	do_div(f, 10);
 954
 955	return f;
 956}
 957
 958/* Menu items for LINK_FREQ V4L2 control */
 959static const s64 link_freq_menu_items[OV13858_NUM_OF_LINK_FREQS] = {
 960	OV13858_LINK_FREQ_540MHZ,
 961	OV13858_LINK_FREQ_270MHZ
 962};
 963
 964/* Link frequency configs */
 965static const struct ov13858_link_freq_config
 966			link_freq_configs[OV13858_NUM_OF_LINK_FREQS] = {
 967	{
 968		.pixels_per_line = OV13858_PPL_540MHZ,
 969		.reg_list = {
 970			.num_of_regs = ARRAY_SIZE(mipi_data_rate_1080mbps),
 971			.regs = mipi_data_rate_1080mbps,
 972		}
 973	},
 974	{
 975		.pixels_per_line = OV13858_PPL_270MHZ,
 976		.reg_list = {
 977			.num_of_regs = ARRAY_SIZE(mipi_data_rate_540mbps),
 978			.regs = mipi_data_rate_540mbps,
 979		}
 980	}
 981};
 982
 983/* Mode configs */
 984static const struct ov13858_mode supported_modes[] = {
 985	{
 986		.width = 4224,
 987		.height = 3136,
 988		.vts_def = OV13858_VTS_30FPS,
 989		.vts_min = OV13858_VTS_30FPS,
 990		.reg_list = {
 991			.num_of_regs = ARRAY_SIZE(mode_4224x3136_regs),
 992			.regs = mode_4224x3136_regs,
 993		},
 994		.link_freq_index = OV13858_LINK_FREQ_INDEX_0,
 995	},
 996	{
 997		.width = 2112,
 998		.height = 1568,
 999		.vts_def = OV13858_VTS_30FPS,
1000		.vts_min = 1608,
1001		.reg_list = {
1002			.num_of_regs = ARRAY_SIZE(mode_2112x1568_regs),
1003			.regs = mode_2112x1568_regs,
1004		},
1005		.link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1006	},
1007	{
1008		.width = 2112,
1009		.height = 1188,
1010		.vts_def = OV13858_VTS_30FPS,
1011		.vts_min = 1608,
1012		.reg_list = {
1013			.num_of_regs = ARRAY_SIZE(mode_2112x1188_regs),
1014			.regs = mode_2112x1188_regs,
1015		},
1016		.link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1017	},
1018	{
1019		.width = 1056,
1020		.height = 784,
1021		.vts_def = OV13858_VTS_30FPS,
1022		.vts_min = 804,
1023		.reg_list = {
1024			.num_of_regs = ARRAY_SIZE(mode_1056x784_regs),
1025			.regs = mode_1056x784_regs,
1026		},
1027		.link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1028	}
1029};
1030
1031struct ov13858 {
1032	struct device *dev;
1033	struct clk *clk;
1034
1035	struct v4l2_subdev sd;
1036	struct media_pad pad;
1037
1038	struct v4l2_ctrl_handler ctrl_handler;
1039	/* V4L2 Controls */
1040	struct v4l2_ctrl *link_freq;
1041	struct v4l2_ctrl *pixel_rate;
1042	struct v4l2_ctrl *vblank;
1043	struct v4l2_ctrl *hblank;
1044	struct v4l2_ctrl *exposure;
1045
1046	/* Current mode */
1047	const struct ov13858_mode *cur_mode;
1048
1049	/* Mutex for serialized access */
1050	struct mutex mutex;
1051};
1052
1053#define to_ov13858(_sd)	container_of(_sd, struct ov13858, sd)
1054
1055/* Read registers up to 4 at a time */
1056static int ov13858_read_reg(struct ov13858 *ov13858, u16 reg, u32 len,
1057			    u32 *val)
1058{
1059	struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1060	struct i2c_msg msgs[2];
1061	u8 *data_be_p;
1062	int ret;
1063	__be32 data_be = 0;
1064	__be16 reg_addr_be = cpu_to_be16(reg);
1065
1066	if (len > 4)
1067		return -EINVAL;
1068
1069	data_be_p = (u8 *)&data_be;
1070	/* Write register address */
1071	msgs[0].addr = client->addr;
1072	msgs[0].flags = 0;
1073	msgs[0].len = 2;
1074	msgs[0].buf = (u8 *)&reg_addr_be;
1075
1076	/* Read data from register */
1077	msgs[1].addr = client->addr;
1078	msgs[1].flags = I2C_M_RD;
1079	msgs[1].len = len;
1080	msgs[1].buf = &data_be_p[4 - len];
1081
1082	ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1083	if (ret != ARRAY_SIZE(msgs))
1084		return -EIO;
1085
1086	*val = be32_to_cpu(data_be);
1087
1088	return 0;
1089}
1090
1091/* Write registers up to 4 at a time */
1092static int ov13858_write_reg(struct ov13858 *ov13858, u16 reg, u32 len,
1093			     u32 __val)
1094{
1095	struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1096	int buf_i, val_i;
1097	u8 buf[6], *val_p;
1098	__be32 val;
1099
1100	if (len > 4)
1101		return -EINVAL;
1102
1103	buf[0] = reg >> 8;
1104	buf[1] = reg & 0xff;
1105
1106	val = cpu_to_be32(__val);
1107	val_p = (u8 *)&val;
1108	buf_i = 2;
1109	val_i = 4 - len;
1110
1111	while (val_i < 4)
1112		buf[buf_i++] = val_p[val_i++];
1113
1114	if (i2c_master_send(client, buf, len + 2) != len + 2)
1115		return -EIO;
1116
1117	return 0;
1118}
1119
1120/* Write a list of registers */
1121static int ov13858_write_regs(struct ov13858 *ov13858,
1122			      const struct ov13858_reg *regs, u32 len)
1123{
1124	int ret;
1125	u32 i;
1126
1127	for (i = 0; i < len; i++) {
1128		ret = ov13858_write_reg(ov13858, regs[i].address, 1,
1129					regs[i].val);
1130		if (ret) {
1131			dev_err_ratelimited(
1132				ov13858->dev,
1133				"Failed to write reg 0x%4.4x. error = %d\n",
1134				regs[i].address, ret);
1135
1136			return ret;
1137		}
1138	}
1139
1140	return 0;
1141}
1142
1143static int ov13858_write_reg_list(struct ov13858 *ov13858,
1144				  const struct ov13858_reg_list *r_list)
1145{
1146	return ov13858_write_regs(ov13858, r_list->regs, r_list->num_of_regs);
1147}
1148
1149/* Open sub-device */
1150static int ov13858_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1151{
1152	struct ov13858 *ov13858 = to_ov13858(sd);
1153	struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_state_get_format(fh->state,
1154									  0);
1155
1156	mutex_lock(&ov13858->mutex);
1157
1158	/* Initialize try_fmt */
1159	try_fmt->width = ov13858->cur_mode->width;
1160	try_fmt->height = ov13858->cur_mode->height;
1161	try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1162	try_fmt->field = V4L2_FIELD_NONE;
1163
1164	/* No crop or compose */
1165	mutex_unlock(&ov13858->mutex);
1166
1167	return 0;
1168}
1169
1170static int ov13858_update_digital_gain(struct ov13858 *ov13858, u32 d_gain)
1171{
1172	int ret;
1173
1174	ret = ov13858_write_reg(ov13858, OV13858_REG_B_MWB_GAIN,
1175				OV13858_REG_VALUE_16BIT, d_gain);
1176	if (ret)
1177		return ret;
1178
1179	ret = ov13858_write_reg(ov13858, OV13858_REG_G_MWB_GAIN,
1180				OV13858_REG_VALUE_16BIT, d_gain);
1181	if (ret)
1182		return ret;
1183
1184	ret = ov13858_write_reg(ov13858, OV13858_REG_R_MWB_GAIN,
1185				OV13858_REG_VALUE_16BIT, d_gain);
1186
1187	return ret;
1188}
1189
1190static int ov13858_enable_test_pattern(struct ov13858 *ov13858, u32 pattern)
1191{
1192	int ret;
1193	u32 val;
1194
1195	ret = ov13858_read_reg(ov13858, OV13858_REG_TEST_PATTERN,
1196			       OV13858_REG_VALUE_08BIT, &val);
1197	if (ret)
1198		return ret;
1199
1200	if (pattern) {
1201		val &= OV13858_TEST_PATTERN_MASK;
1202		val |= (pattern - 1) | OV13858_TEST_PATTERN_ENABLE;
1203	} else {
1204		val &= ~OV13858_TEST_PATTERN_ENABLE;
1205	}
1206
1207	return ov13858_write_reg(ov13858, OV13858_REG_TEST_PATTERN,
1208				 OV13858_REG_VALUE_08BIT, val);
1209}
1210
1211static int ov13858_set_ctrl(struct v4l2_ctrl *ctrl)
1212{
1213	struct ov13858 *ov13858 = container_of(ctrl->handler,
1214					       struct ov13858, ctrl_handler);
1215	s64 max;
1216	int ret;
1217
1218	/* Propagate change of current control to all related controls */
1219	switch (ctrl->id) {
1220	case V4L2_CID_VBLANK:
1221		/* Update max exposure while meeting expected vblanking */
1222		max = ov13858->cur_mode->height + ctrl->val - 8;
1223		__v4l2_ctrl_modify_range(ov13858->exposure,
1224					 ov13858->exposure->minimum,
1225					 max, ov13858->exposure->step, max);
1226		break;
1227	}
1228
1229	/*
1230	 * Applying V4L2 control value only happens
1231	 * when power is up for streaming
1232	 */
1233	if (!pm_runtime_get_if_in_use(ov13858->dev))
1234		return 0;
1235
1236	ret = 0;
1237	switch (ctrl->id) {
1238	case V4L2_CID_ANALOGUE_GAIN:
1239		ret = ov13858_write_reg(ov13858, OV13858_REG_ANALOG_GAIN,
1240					OV13858_REG_VALUE_16BIT, ctrl->val);
1241		break;
1242	case V4L2_CID_DIGITAL_GAIN:
1243		ret = ov13858_update_digital_gain(ov13858, ctrl->val);
1244		break;
1245	case V4L2_CID_EXPOSURE:
1246		ret = ov13858_write_reg(ov13858, OV13858_REG_EXPOSURE,
1247					OV13858_REG_VALUE_24BIT,
1248					ctrl->val << 4);
1249		break;
1250	case V4L2_CID_VBLANK:
1251		/* Update VTS that meets expected vertical blanking */
1252		ret = ov13858_write_reg(ov13858, OV13858_REG_VTS,
1253					OV13858_REG_VALUE_16BIT,
1254					ov13858->cur_mode->height
1255					  + ctrl->val);
1256		break;
1257	case V4L2_CID_TEST_PATTERN:
1258		ret = ov13858_enable_test_pattern(ov13858, ctrl->val);
1259		break;
1260	default:
1261		dev_info(ov13858->dev,
1262			 "ctrl(id:0x%x,val:0x%x) is not handled\n",
1263			 ctrl->id, ctrl->val);
1264		break;
1265	}
1266
1267	pm_runtime_put(ov13858->dev);
1268
1269	return ret;
1270}
1271
1272static const struct v4l2_ctrl_ops ov13858_ctrl_ops = {
1273	.s_ctrl = ov13858_set_ctrl,
1274};
1275
1276static int ov13858_enum_mbus_code(struct v4l2_subdev *sd,
1277				  struct v4l2_subdev_state *sd_state,
1278				  struct v4l2_subdev_mbus_code_enum *code)
1279{
1280	/* Only one bayer order(GRBG) is supported */
1281	if (code->index > 0)
1282		return -EINVAL;
1283
1284	code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1285
1286	return 0;
1287}
1288
1289static int ov13858_enum_frame_size(struct v4l2_subdev *sd,
1290				   struct v4l2_subdev_state *sd_state,
1291				   struct v4l2_subdev_frame_size_enum *fse)
1292{
1293	if (fse->index >= ARRAY_SIZE(supported_modes))
1294		return -EINVAL;
1295
1296	if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
1297		return -EINVAL;
1298
1299	fse->min_width = supported_modes[fse->index].width;
1300	fse->max_width = fse->min_width;
1301	fse->min_height = supported_modes[fse->index].height;
1302	fse->max_height = fse->min_height;
1303
1304	return 0;
1305}
1306
1307static void ov13858_update_pad_format(const struct ov13858_mode *mode,
1308				      struct v4l2_subdev_format *fmt)
1309{
1310	fmt->format.width = mode->width;
1311	fmt->format.height = mode->height;
1312	fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1313	fmt->format.field = V4L2_FIELD_NONE;
1314}
1315
1316static int ov13858_do_get_pad_format(struct ov13858 *ov13858,
1317				     struct v4l2_subdev_state *sd_state,
1318				     struct v4l2_subdev_format *fmt)
1319{
1320	struct v4l2_mbus_framefmt *framefmt;
1321
1322	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1323		framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad);
1324		fmt->format = *framefmt;
1325	} else {
1326		ov13858_update_pad_format(ov13858->cur_mode, fmt);
1327	}
1328
1329	return 0;
1330}
1331
1332static int ov13858_get_pad_format(struct v4l2_subdev *sd,
1333				  struct v4l2_subdev_state *sd_state,
1334				  struct v4l2_subdev_format *fmt)
1335{
1336	struct ov13858 *ov13858 = to_ov13858(sd);
1337	int ret;
1338
1339	mutex_lock(&ov13858->mutex);
1340	ret = ov13858_do_get_pad_format(ov13858, sd_state, fmt);
1341	mutex_unlock(&ov13858->mutex);
1342
1343	return ret;
1344}
1345
1346static int
1347ov13858_set_pad_format(struct v4l2_subdev *sd,
1348		       struct v4l2_subdev_state *sd_state,
1349		       struct v4l2_subdev_format *fmt)
1350{
1351	struct ov13858 *ov13858 = to_ov13858(sd);
1352	const struct ov13858_mode *mode;
1353	struct v4l2_mbus_framefmt *framefmt;
1354	s32 vblank_def;
1355	s32 vblank_min;
1356	s64 h_blank;
1357	s64 pixel_rate;
1358	s64 link_freq;
1359
1360	mutex_lock(&ov13858->mutex);
1361
1362	/* Only one raw bayer(GRBG) order is supported */
1363	if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10)
1364		fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1365
1366	mode = v4l2_find_nearest_size(supported_modes,
1367				      ARRAY_SIZE(supported_modes),
1368				      width, height,
1369				      fmt->format.width, fmt->format.height);
1370	ov13858_update_pad_format(mode, fmt);
1371	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1372		framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad);
1373		*framefmt = fmt->format;
1374	} else {
1375		ov13858->cur_mode = mode;
1376		__v4l2_ctrl_s_ctrl(ov13858->link_freq, mode->link_freq_index);
1377		link_freq = link_freq_menu_items[mode->link_freq_index];
1378		pixel_rate = link_freq_to_pixel_rate(link_freq);
1379		__v4l2_ctrl_s_ctrl_int64(ov13858->pixel_rate, pixel_rate);
1380
1381		/* Update limits and set FPS to default */
1382		vblank_def = ov13858->cur_mode->vts_def -
1383			     ov13858->cur_mode->height;
1384		vblank_min = ov13858->cur_mode->vts_min -
1385			     ov13858->cur_mode->height;
1386		__v4l2_ctrl_modify_range(
1387			ov13858->vblank, vblank_min,
1388			OV13858_VTS_MAX - ov13858->cur_mode->height, 1,
1389			vblank_def);
1390		__v4l2_ctrl_s_ctrl(ov13858->vblank, vblank_def);
1391		h_blank =
1392			link_freq_configs[mode->link_freq_index].pixels_per_line
1393			 - ov13858->cur_mode->width;
1394		__v4l2_ctrl_modify_range(ov13858->hblank, h_blank,
1395					 h_blank, 1, h_blank);
1396	}
1397
1398	mutex_unlock(&ov13858->mutex);
1399
1400	return 0;
1401}
1402
1403static int ov13858_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)
1404{
1405	*frames = OV13858_NUM_OF_SKIP_FRAMES;
1406
1407	return 0;
1408}
1409
1410/* Start streaming */
1411static int ov13858_start_streaming(struct ov13858 *ov13858)
1412{
1413	const struct ov13858_reg_list *reg_list;
1414	int ret, link_freq_index;
1415
1416	/* Get out of from software reset */
1417	ret = ov13858_write_reg(ov13858, OV13858_REG_SOFTWARE_RST,
1418				OV13858_REG_VALUE_08BIT, OV13858_SOFTWARE_RST);
1419	if (ret) {
1420		dev_err(ov13858->dev, "%s failed to set powerup registers\n",
1421			__func__);
1422		return ret;
1423	}
1424
1425	/* Setup PLL */
1426	link_freq_index = ov13858->cur_mode->link_freq_index;
1427	reg_list = &link_freq_configs[link_freq_index].reg_list;
1428	ret = ov13858_write_reg_list(ov13858, reg_list);
1429	if (ret) {
1430		dev_err(ov13858->dev, "%s failed to set plls\n", __func__);
1431		return ret;
1432	}
1433
1434	/* Apply default values of current mode */
1435	reg_list = &ov13858->cur_mode->reg_list;
1436	ret = ov13858_write_reg_list(ov13858, reg_list);
1437	if (ret) {
1438		dev_err(ov13858->dev, "%s failed to set mode\n", __func__);
1439		return ret;
1440	}
1441
1442	/* Apply customized values from user */
1443	ret =  __v4l2_ctrl_handler_setup(ov13858->sd.ctrl_handler);
1444	if (ret)
1445		return ret;
1446
1447	return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT,
1448				 OV13858_REG_VALUE_08BIT,
1449				 OV13858_MODE_STREAMING);
1450}
1451
1452/* Stop streaming */
1453static int ov13858_stop_streaming(struct ov13858 *ov13858)
1454{
1455	return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT,
1456				 OV13858_REG_VALUE_08BIT, OV13858_MODE_STANDBY);
1457}
1458
1459static int ov13858_set_stream(struct v4l2_subdev *sd, int enable)
1460{
1461	struct ov13858 *ov13858 = to_ov13858(sd);
1462	int ret = 0;
1463
1464	mutex_lock(&ov13858->mutex);
1465
1466	if (enable) {
1467		ret = pm_runtime_resume_and_get(ov13858->dev);
1468		if (ret < 0)
1469			goto err_unlock;
1470
1471		/*
1472		 * Apply default & customized values
1473		 * and then start streaming.
1474		 */
1475		ret = ov13858_start_streaming(ov13858);
1476		if (ret)
1477			goto err_rpm_put;
1478	} else {
1479		ov13858_stop_streaming(ov13858);
1480		pm_runtime_put(ov13858->dev);
1481	}
1482
1483	mutex_unlock(&ov13858->mutex);
1484
1485	return ret;
1486
1487err_rpm_put:
1488	pm_runtime_put(ov13858->dev);
1489err_unlock:
1490	mutex_unlock(&ov13858->mutex);
1491
1492	return ret;
1493}
1494
1495/* Verify chip ID */
1496static int ov13858_identify_module(struct ov13858 *ov13858)
1497{
1498	int ret;
1499	u32 val;
1500
1501	ret = ov13858_read_reg(ov13858, OV13858_REG_CHIP_ID,
1502			       OV13858_REG_VALUE_24BIT, &val);
1503	if (ret)
1504		return ret;
1505
1506	if (val != OV13858_CHIP_ID) {
1507		dev_err(ov13858->dev, "chip id mismatch: %x!=%x\n",
1508			OV13858_CHIP_ID, val);
1509		return -EIO;
1510	}
1511
1512	return 0;
1513}
1514
1515static const struct v4l2_subdev_core_ops ov13858_core_ops = {
1516	.log_status = v4l2_ctrl_subdev_log_status,
1517	.subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1518	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
1519};
1520
1521static const struct v4l2_subdev_video_ops ov13858_video_ops = {
1522	.s_stream = ov13858_set_stream,
1523};
1524
1525static const struct v4l2_subdev_pad_ops ov13858_pad_ops = {
1526	.enum_mbus_code = ov13858_enum_mbus_code,
1527	.get_fmt = ov13858_get_pad_format,
1528	.set_fmt = ov13858_set_pad_format,
1529	.enum_frame_size = ov13858_enum_frame_size,
1530};
1531
1532static const struct v4l2_subdev_sensor_ops ov13858_sensor_ops = {
1533	.g_skip_frames = ov13858_get_skip_frames,
1534};
1535
1536static const struct v4l2_subdev_ops ov13858_subdev_ops = {
1537	.core = &ov13858_core_ops,
1538	.video = &ov13858_video_ops,
1539	.pad = &ov13858_pad_ops,
1540	.sensor = &ov13858_sensor_ops,
1541};
1542
1543static const struct media_entity_operations ov13858_subdev_entity_ops = {
1544	.link_validate = v4l2_subdev_link_validate,
1545};
1546
1547static const struct v4l2_subdev_internal_ops ov13858_internal_ops = {
1548	.open = ov13858_open,
1549};
1550
1551/* Initialize control handlers */
1552static int ov13858_init_controls(struct ov13858 *ov13858)
1553{
1554	struct v4l2_fwnode_device_properties props;
1555	struct v4l2_ctrl_handler *ctrl_hdlr;
1556	s64 exposure_max;
1557	s64 vblank_def;
1558	s64 vblank_min;
1559	s64 hblank;
1560	s64 pixel_rate_min;
1561	s64 pixel_rate_max;
1562	const struct ov13858_mode *mode;
1563	int ret;
1564
1565	ctrl_hdlr = &ov13858->ctrl_handler;
1566	ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
1567	if (ret)
1568		return ret;
1569
1570	mutex_init(&ov13858->mutex);
1571	ctrl_hdlr->lock = &ov13858->mutex;
1572	ov13858->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
1573				&ov13858_ctrl_ops,
1574				V4L2_CID_LINK_FREQ,
1575				OV13858_NUM_OF_LINK_FREQS - 1,
1576				0,
1577				link_freq_menu_items);
1578	if (ov13858->link_freq)
1579		ov13858->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1580
1581	pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]);
1582	pixel_rate_min = link_freq_to_pixel_rate(link_freq_menu_items[1]);
1583	/* By default, PIXEL_RATE is read only */
1584	ov13858->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops,
1585						V4L2_CID_PIXEL_RATE,
1586						pixel_rate_min, pixel_rate_max,
1587						1, pixel_rate_max);
1588
1589	mode = ov13858->cur_mode;
1590	vblank_def = mode->vts_def - mode->height;
1591	vblank_min = mode->vts_min - mode->height;
1592	ov13858->vblank = v4l2_ctrl_new_std(
1593				ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_VBLANK,
1594				vblank_min, OV13858_VTS_MAX - mode->height, 1,
1595				vblank_def);
1596
1597	hblank = link_freq_configs[mode->link_freq_index].pixels_per_line -
1598		 mode->width;
1599	ov13858->hblank = v4l2_ctrl_new_std(
1600				ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_HBLANK,
1601				hblank, hblank, 1, hblank);
1602	if (ov13858->hblank)
1603		ov13858->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1604
1605	exposure_max = mode->vts_def - 8;
1606	ov13858->exposure = v4l2_ctrl_new_std(
1607				ctrl_hdlr, &ov13858_ctrl_ops,
1608				V4L2_CID_EXPOSURE, OV13858_EXPOSURE_MIN,
1609				exposure_max, OV13858_EXPOSURE_STEP,
1610				OV13858_EXPOSURE_DEFAULT);
1611
1612	v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1613			  OV13858_ANA_GAIN_MIN, OV13858_ANA_GAIN_MAX,
1614			  OV13858_ANA_GAIN_STEP, OV13858_ANA_GAIN_DEFAULT);
1615
1616	/* Digital gain */
1617	v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1618			  OV13858_DGTL_GAIN_MIN, OV13858_DGTL_GAIN_MAX,
1619			  OV13858_DGTL_GAIN_STEP, OV13858_DGTL_GAIN_DEFAULT);
1620
1621	v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov13858_ctrl_ops,
1622				     V4L2_CID_TEST_PATTERN,
1623				     ARRAY_SIZE(ov13858_test_pattern_menu) - 1,
1624				     0, 0, ov13858_test_pattern_menu);
1625	if (ctrl_hdlr->error) {
1626		ret = ctrl_hdlr->error;
1627		dev_err(ov13858->dev, "%s control init failed (%d)\n",
1628			__func__, ret);
1629		goto error;
1630	}
1631
1632	ret = v4l2_fwnode_device_parse(ov13858->dev, &props);
1633	if (ret)
1634		goto error;
1635
1636	ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov13858_ctrl_ops,
1637					      &props);
1638	if (ret)
1639		goto error;
1640
1641	ov13858->sd.ctrl_handler = ctrl_hdlr;
1642
1643	return 0;
1644
1645error:
1646	v4l2_ctrl_handler_free(ctrl_hdlr);
1647	mutex_destroy(&ov13858->mutex);
1648
1649	return ret;
1650}
1651
1652static void ov13858_free_controls(struct ov13858 *ov13858)
1653{
1654	v4l2_ctrl_handler_free(ov13858->sd.ctrl_handler);
1655	mutex_destroy(&ov13858->mutex);
1656}
1657
1658static int ov13858_probe(struct i2c_client *client)
1659{
1660	struct ov13858 *ov13858;
1661	unsigned long freq;
1662	int ret;
1663
1664	ov13858 = devm_kzalloc(&client->dev, sizeof(*ov13858), GFP_KERNEL);
1665	if (!ov13858)
1666		return -ENOMEM;
1667
1668	ov13858->dev = &client->dev;
1669
1670	ov13858->clk = devm_v4l2_sensor_clk_get(ov13858->dev, NULL);
1671	if (IS_ERR(ov13858->clk))
1672		return dev_err_probe(ov13858->dev, PTR_ERR(ov13858->clk),
1673				     "failed to get clock\n");
1674
1675	freq = clk_get_rate(ov13858->clk);
1676	if (freq != 19200000)
1677		return dev_err_probe(ov13858->dev, -EINVAL,
1678				     "external clock %lu is not supported\n",
1679				     freq);
1680
1681	/* Initialize subdev */
1682	v4l2_i2c_subdev_init(&ov13858->sd, client, &ov13858_subdev_ops);
1683
1684	/* Check module identity */
1685	ret = ov13858_identify_module(ov13858);
1686	if (ret) {
1687		dev_err(ov13858->dev, "failed to find sensor: %d\n", ret);
1688		return ret;
1689	}
1690
1691	/* Set default mode to max resolution */
1692	ov13858->cur_mode = &supported_modes[0];
1693
1694	ret = ov13858_init_controls(ov13858);
1695	if (ret)
1696		return ret;
1697
1698	/* Initialize subdev */
1699	ov13858->sd.internal_ops = &ov13858_internal_ops;
1700	ov13858->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1701			     V4L2_SUBDEV_FL_HAS_EVENTS;
1702	ov13858->sd.entity.ops = &ov13858_subdev_entity_ops;
1703	ov13858->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1704
1705	/* Initialize source pad */
1706	ov13858->pad.flags = MEDIA_PAD_FL_SOURCE;
1707	ret = media_entity_pads_init(&ov13858->sd.entity, 1, &ov13858->pad);
1708	if (ret) {
1709		dev_err(ov13858->dev, "%s failed:%d\n", __func__, ret);
1710		goto error_handler_free;
1711	}
1712
1713	ret = v4l2_async_register_subdev_sensor(&ov13858->sd);
1714	if (ret < 0)
1715		goto error_media_entity;
1716
1717	/*
1718	 * Device is already turned on by i2c-core with ACPI domain PM.
1719	 * Enable runtime PM and turn off the device.
1720	 */
1721	pm_runtime_set_active(ov13858->dev);
1722	pm_runtime_enable(ov13858->dev);
1723	pm_runtime_idle(ov13858->dev);
1724
1725	return 0;
1726
1727error_media_entity:
1728	media_entity_cleanup(&ov13858->sd.entity);
1729
1730error_handler_free:
1731	ov13858_free_controls(ov13858);
1732	dev_err(ov13858->dev, "%s failed:%d\n", __func__, ret);
1733
1734	return ret;
1735}
1736
1737static void ov13858_remove(struct i2c_client *client)
1738{
1739	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1740	struct ov13858 *ov13858 = to_ov13858(sd);
1741
1742	v4l2_async_unregister_subdev(sd);
1743	media_entity_cleanup(&sd->entity);
1744	ov13858_free_controls(ov13858);
1745
1746	pm_runtime_disable(ov13858->dev);
1747}
1748
1749static const struct i2c_device_id ov13858_id_table[] = {
1750	{ "ov13858" },
1751	{}
1752};
1753
1754MODULE_DEVICE_TABLE(i2c, ov13858_id_table);
1755
1756#ifdef CONFIG_ACPI
1757static const struct acpi_device_id ov13858_acpi_ids[] = {
1758	{"OVTID858"},
1759	{ /* sentinel */ }
1760};
1761
1762MODULE_DEVICE_TABLE(acpi, ov13858_acpi_ids);
1763#endif
1764
1765static struct i2c_driver ov13858_i2c_driver = {
1766	.driver = {
1767		.name = "ov13858",
1768		.acpi_match_table = ACPI_PTR(ov13858_acpi_ids),
1769	},
1770	.probe = ov13858_probe,
1771	.remove = ov13858_remove,
1772	.id_table = ov13858_id_table,
1773};
1774
1775module_i2c_driver(ov13858_i2c_driver);
1776
1777MODULE_AUTHOR("Kan, Chris <chris.kan@intel.com>");
1778MODULE_AUTHOR("Rapolu, Chiranjeevi");
1779MODULE_AUTHOR("Yang, Hyungwoo");
1780MODULE_DESCRIPTION("Omnivision ov13858 sensor driver");
1781MODULE_LICENSE("GPL v2");