FILE
ov08x40.c
File preview with syntax highlighting.
linux-6.19.14/drivers/media/i2c/ov08x40.c
1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2022 Intel Corporation. 3 4#include <linux/acpi.h> 5#include <linux/clk.h> 6#include <linux/delay.h> 7#include <linux/gpio/consumer.h> 8#include <linux/i2c.h> 9#include <linux/module.h> 10#include <linux/pm_runtime.h> 11#include <linux/regulator/consumer.h> 12#include <linux/unaligned.h> 13 14#include <media/v4l2-common.h> 15#include <media/v4l2-ctrls.h> 16#include <media/v4l2-device.h> 17#include <media/v4l2-fwnode.h> 18 19#define OV08X40_REG_VALUE_08BIT 1 20#define OV08X40_REG_VALUE_16BIT 2 21#define OV08X40_REG_VALUE_24BIT 3 22 23#define OV08X40_REG_MODE_SELECT 0x0100 24#define OV08X40_MODE_STANDBY 0x00 25#define OV08X40_MODE_STREAMING 0x01 26 27#define OV08X40_REG_AO_STANDBY 0x1000 28#define OV08X40_AO_STREAMING 0x04 29 30#define OV08X40_REG_MS_SELECT 0x1001 31#define OV08X40_MS_STANDBY 0x00 32#define OV08X40_MS_STREAMING 0x04 33 34#define OV08X40_REG_SOFTWARE_RST 0x0103 35#define OV08X40_SOFTWARE_RST 0x01 36 37/* Chip ID */ 38#define OV08X40_REG_CHIP_ID 0x300a 39#define OV08X40_CHIP_ID 0x560858 40 41/* V_TIMING internal */ 42#define OV08X40_REG_VTS 0x380e 43#define OV08X40_VTS_30FPS 0x09c4 /* the VTS need to be half in normal mode */ 44#define OV08X40_VTS_BIN_30FPS 0x115c 45#define OV08X40_VTS_MAX 0x7fff 46 47/* H TIMING internal */ 48#define OV08X40_REG_HTS 0x380c 49#define OV08X40_HTS_30FPS 0x0280 50 51/* Exposure control */ 52#define OV08X40_REG_EXPOSURE 0x3500 53#define OV08X40_EXPOSURE_MAX_MARGIN 8 54#define OV08X40_EXPOSURE_BIN_MAX_MARGIN 2 55#define OV08X40_EXPOSURE_MIN 4 56#define OV08X40_EXPOSURE_STEP 1 57#define OV08X40_EXPOSURE_DEFAULT 0x40 58 59/* Short Exposure control */ 60#define OV08X40_REG_SHORT_EXPOSURE 0x3540 61 62/* Analog gain control */ 63#define OV08X40_REG_ANALOG_GAIN 0x3508 64#define OV08X40_ANA_GAIN_MIN 0x80 65#define OV08X40_ANA_GAIN_MAX 0x07c0 66#define OV08X40_ANA_GAIN_STEP 1 67#define OV08X40_ANA_GAIN_DEFAULT 0x80 68 69/* Digital gain control */ 70#define OV08X40_REG_DGTL_GAIN_H 0x350a 71#define OV08X40_REG_DGTL_GAIN_M 0x350b 72#define OV08X40_REG_DGTL_GAIN_L 0x350c 73 74#define OV08X40_DGTL_GAIN_MIN 1024 /* Min = 1 X */ 75#define OV08X40_DGTL_GAIN_MAX (4096 - 1) /* Max = 4 X */ 76#define OV08X40_DGTL_GAIN_DEFAULT 2560 /* Default gain = 2.5 X */ 77#define OV08X40_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */ 78 79#define OV08X40_DGTL_GAIN_L_SHIFT 6 80#define OV08X40_DGTL_GAIN_L_MASK 0x3 81#define OV08X40_DGTL_GAIN_M_SHIFT 2 82#define OV08X40_DGTL_GAIN_M_MASK 0xff 83#define OV08X40_DGTL_GAIN_H_SHIFT 10 84#define OV08X40_DGTL_GAIN_H_MASK 0x1F 85 86/* Test Pattern Control */ 87#define OV08X40_REG_TEST_PATTERN 0x50C1 88#define OV08X40_REG_ISP 0x5000 89#define OV08X40_REG_SHORT_TEST_PATTERN 0x53C1 90#define OV08X40_TEST_PATTERN_ENABLE BIT(0) 91#define OV08X40_TEST_PATTERN_MASK 0xcf 92#define OV08X40_TEST_PATTERN_BAR_SHIFT 4 93 94/* Flip Control */ 95#define OV08X40_REG_VFLIP 0x3820 96#define OV08X40_REG_MIRROR 0x3821 97 98/* Horizontal Window Offset */ 99#define OV08X40_REG_H_WIN_OFFSET 0x3811 100 101/* Vertical Window Offset */ 102#define OV08X40_REG_V_WIN_OFFSET 0x3813 103 104/* Burst Register */ 105#define OV08X40_REG_XTALK_FIRST_A 0x5a80 106#define OV08X40_REG_XTALK_LAST_A 0x5b9f 107#define OV08X40_REG_XTALK_FIRST_B 0x5bc0 108#define OV08X40_REG_XTALK_LAST_B 0x5f1f 109 110enum { 111 OV08X40_LINK_FREQ_400MHZ_INDEX, 112 OV08X40_LINK_FREQ_749MHZ_INDEX, 113}; 114 115struct ov08x40_reg { 116 u16 address; 117 u8 val; 118}; 119 120struct ov08x40_reg_list { 121 u32 num_of_regs; 122 const struct ov08x40_reg *regs; 123}; 124 125/* Link frequency config */ 126struct ov08x40_link_freq_config { 127 /* registers for this link frequency */ 128 struct ov08x40_reg_list reg_list; 129}; 130 131/* Mode : resolution and related config&values */ 132struct ov08x40_mode { 133 /* Frame width */ 134 u32 width; 135 /* Frame height */ 136 u32 height; 137 138 u32 lanes; 139 /* V-timing */ 140 u32 vts_def; 141 u32 vts_min; 142 143 /* Line Length Pixels */ 144 u32 llp; 145 146 /* Index of Link frequency config to be used */ 147 u32 link_freq_index; 148 /* Default register values */ 149 struct ov08x40_reg_list reg_list; 150 151 /* Exposure calculation */ 152 u16 exposure_margin; 153 u16 exposure_shift; 154}; 155 156static const struct ov08x40_reg ov08x40_global_regs[] = { 157 {0x1216, 0x60}, 158 {0x1217, 0x5b}, 159 {0x1218, 0x00}, 160 {0x1220, 0x24}, 161 {0x198a, 0x00}, 162 {0x198b, 0x01}, 163 {0x198e, 0x00}, 164 {0x198f, 0x01}, 165 {0x3009, 0x04}, 166 {0x3015, 0x00}, 167 {0x3016, 0xb0}, 168 {0x3017, 0xf0}, 169 {0x3018, 0xf0}, 170 {0x3019, 0xd2}, 171 {0x301a, 0xb0}, 172 {0x301c, 0x81}, 173 {0x301d, 0x02}, 174 {0x301e, 0x80}, 175 {0x3022, 0xf0}, 176 {0x3025, 0x89}, 177 {0x3030, 0x03}, 178 {0x3044, 0xc2}, 179 {0x3050, 0x35}, 180 {0x3051, 0x60}, 181 {0x3052, 0x25}, 182 {0x3053, 0x00}, 183 {0x3054, 0x00}, 184 {0x3055, 0x02}, 185 {0x3056, 0x80}, 186 {0x3057, 0x80}, 187 {0x3058, 0x80}, 188 {0x3059, 0x00}, 189 {0x3107, 0x86}, 190 {0x3401, 0x80}, 191 {0x3402, 0x8c}, 192 {0x3404, 0x01}, 193 {0x3407, 0x01}, 194 {0x341b, 0x30}, 195 {0x3420, 0x00}, 196 {0x3421, 0x00}, 197 {0x3422, 0x00}, 198 {0x3423, 0x00}, 199 {0x3424, 0x00}, 200 {0x3425, 0x00}, 201 {0x3426, 0x10}, 202 {0x3427, 0x00}, 203 {0x3428, 0x0f}, 204 {0x3429, 0x00}, 205 {0x342a, 0x00}, 206 {0x342b, 0x00}, 207 {0x342c, 0x00}, 208 {0x342d, 0x00}, 209 {0x342e, 0x00}, 210 {0x342f, 0x11}, 211 {0x3430, 0x11}, 212 {0x3431, 0x10}, 213 {0x3432, 0x00}, 214 {0x3433, 0x00}, 215 {0x3434, 0x00}, 216 {0x3435, 0x00}, 217 {0x3436, 0x00}, 218 {0x3437, 0x00}, 219 {0x3442, 0x02}, 220 {0x3443, 0x02}, 221 {0x3444, 0x07}, 222 {0x3450, 0x00}, 223 {0x3451, 0x00}, 224 {0x3452, 0x18}, 225 {0x3453, 0x18}, 226 {0x3454, 0x00}, 227 {0x3455, 0x80}, 228 {0x3456, 0x08}, 229 {0x3500, 0x00}, 230 {0x3502, 0x10}, 231 {0x3504, 0x4c}, 232 {0x3506, 0x30}, 233 {0x3507, 0x00}, 234 {0x350a, 0x01}, 235 {0x350b, 0x00}, 236 {0x350c, 0x00}, 237 {0x3540, 0x00}, 238 {0x3544, 0x4c}, 239 {0x3546, 0x30}, 240 {0x3547, 0x00}, 241 {0x3549, 0x00}, 242 {0x354a, 0x01}, 243 {0x354b, 0x00}, 244 {0x354c, 0x00}, 245 {0x3601, 0x40}, 246 {0x3602, 0x90}, 247 {0x3608, 0x0a}, 248 {0x3609, 0x08}, 249 {0x360f, 0x99}, 250 {0x3680, 0xa4}, 251 {0x3682, 0x80}, 252 {0x3688, 0x02}, 253 {0x368a, 0x2e}, 254 {0x368e, 0x71}, 255 {0x3696, 0xd1}, 256 {0x3699, 0x00}, 257 {0x369a, 0x00}, 258 {0x36a4, 0x00}, 259 {0x36a6, 0x00}, 260 {0x3711, 0x00}, 261 {0x3713, 0x00}, 262 {0x3716, 0x00}, 263 {0x3718, 0x07}, 264 {0x371a, 0x1c}, 265 {0x371b, 0x00}, 266 {0x3720, 0x08}, 267 {0x3725, 0x32}, 268 {0x3727, 0x05}, 269 {0x3760, 0x02}, 270 {0x3762, 0x02}, 271 {0x3763, 0x02}, 272 {0x3764, 0x02}, 273 {0x3765, 0x2c}, 274 {0x3766, 0x04}, 275 {0x3767, 0x2c}, 276 {0x3768, 0x02}, 277 {0x3769, 0x00}, 278 {0x376b, 0x20}, 279 {0x37b2, 0x01}, 280 {0x3800, 0x00}, 281 {0x3801, 0x00}, 282 {0x3802, 0x00}, 283 {0x3804, 0x0f}, 284 {0x3805, 0x1f}, 285 {0x3806, 0x09}, 286 {0x380c, 0x02}, 287 {0x3810, 0x00}, 288 {0x3812, 0x00}, 289 {0x3814, 0x11}, 290 {0x3815, 0x11}, 291 {0x3822, 0x00}, 292 {0x3828, 0x0f}, 293 {0x382a, 0x80}, 294 {0x382e, 0x41}, 295 {0x3837, 0x08}, 296 {0x383a, 0x81}, 297 {0x383b, 0x81}, 298 {0x383c, 0x11}, 299 {0x383d, 0x11}, 300 {0x383e, 0x00}, 301 {0x383f, 0x38}, 302 {0x3840, 0x00}, 303 {0x3847, 0x00}, 304 {0x384a, 0x00}, 305 {0x384c, 0x02}, 306 {0x3856, 0x50}, 307 {0x3857, 0x30}, 308 {0x3858, 0x80}, 309 {0x3859, 0x40}, 310 {0x3860, 0x00}, 311 {0x3888, 0x00}, 312 {0x3889, 0x00}, 313 {0x388a, 0x00}, 314 {0x388b, 0x00}, 315 {0x388c, 0x00}, 316 {0x388d, 0x00}, 317 {0x388e, 0x00}, 318 {0x388f, 0x00}, 319 {0x3895, 0x00}, 320 {0x3911, 0x90}, 321 {0x3913, 0x90}, 322 {0x3921, 0x0f}, 323 {0x3928, 0x15}, 324 {0x3929, 0x2a}, 325 {0x392c, 0x02}, 326 {0x392e, 0x04}, 327 {0x392f, 0x03}, 328 {0x3931, 0x07}, 329 {0x3932, 0x10}, 330 {0x3938, 0x09}, 331 {0x3a1f, 0x8a}, 332 {0x3a22, 0x91}, 333 {0x3a23, 0x15}, 334 {0x3a25, 0x96}, 335 {0x3a28, 0xb4}, 336 {0x3a29, 0x26}, 337 {0x3a2b, 0xba}, 338 {0x3a2e, 0xbf}, 339 {0x3a2f, 0x18}, 340 {0x3a31, 0xc1}, 341 {0x3a74, 0x84}, 342 {0x3a99, 0x84}, 343 {0x3ab9, 0xa6}, 344 {0x3aba, 0xba}, 345 {0x3b0a, 0x01}, 346 {0x3b0b, 0x00}, 347 {0x3b0e, 0x01}, 348 {0x3b0f, 0x00}, 349 {0x3b12, 0x84}, 350 {0x3b14, 0xbb}, 351 {0x3b15, 0xbf}, 352 {0x3b1b, 0xc9}, 353 {0x3b21, 0xc9}, 354 {0x3b3f, 0x9d}, 355 {0x3b45, 0x9d}, 356 {0x3c84, 0x00}, 357 {0x3d84, 0x04}, 358 {0x3d85, 0x8b}, 359 {0x3daa, 0x80}, 360 {0x3dab, 0x14}, 361 {0x3dac, 0x80}, 362 {0x3dad, 0xc8}, 363 {0x3dae, 0x81}, 364 {0x3daf, 0x7b}, 365 {0x3f00, 0x10}, 366 {0x3f01, 0x11}, 367 {0x3f06, 0x0d}, 368 {0x3f07, 0x0b}, 369 {0x3f08, 0x0d}, 370 {0x3f09, 0x0b}, 371 {0x3f0a, 0x01}, 372 {0x3f0b, 0x11}, 373 {0x3f0c, 0x33}, 374 {0x4001, 0x07}, 375 {0x4007, 0x20}, 376 {0x4008, 0x00}, 377 {0x4009, 0x05}, 378 {0x400a, 0x00}, 379 {0x400c, 0x00}, 380 {0x400e, 0x14}, 381 {0x4010, 0xf4}, 382 {0x4011, 0x03}, 383 {0x4012, 0x55}, 384 {0x4015, 0x00}, 385 {0x4017, 0x00}, 386 {0x4018, 0x0f}, 387 {0x4019, 0x00}, 388 {0x401a, 0x40}, 389 {0x401b, 0x08}, 390 {0x401c, 0x00}, 391 {0x401d, 0x10}, 392 {0x401e, 0x02}, 393 {0x401f, 0x00}, 394 {0x4020, 0x04}, 395 {0x4021, 0x00}, 396 {0x4022, 0x04}, 397 {0x4023, 0x00}, 398 {0x4024, 0x04}, 399 {0x4025, 0x00}, 400 {0x4026, 0x04}, 401 {0x4027, 0x00}, 402 {0x4030, 0x00}, 403 {0x4031, 0x00}, 404 {0x4032, 0x00}, 405 {0x4033, 0x00}, 406 {0x4034, 0x00}, 407 {0x4035, 0x00}, 408 {0x4036, 0x00}, 409 {0x4037, 0x00}, 410 {0x4040, 0x00}, 411 {0x4041, 0x80}, 412 {0x4042, 0x00}, 413 {0x4043, 0x80}, 414 {0x4044, 0x00}, 415 {0x4045, 0x80}, 416 {0x4046, 0x00}, 417 {0x4047, 0x80}, 418 {0x4050, 0x06}, 419 {0x4051, 0xff}, 420 {0x4052, 0xff}, 421 {0x4053, 0xff}, 422 {0x4054, 0xff}, 423 {0x4055, 0xff}, 424 {0x4056, 0xff}, 425 {0x4057, 0x7f}, 426 {0x4058, 0x00}, 427 {0x4059, 0x00}, 428 {0x405a, 0x00}, 429 {0x405b, 0x00}, 430 {0x405c, 0x07}, 431 {0x405d, 0xff}, 432 {0x405e, 0x07}, 433 {0x405f, 0xff}, 434 {0x4060, 0x00}, 435 {0x4061, 0x00}, 436 {0x4062, 0x00}, 437 {0x4063, 0x00}, 438 {0x4064, 0x00}, 439 {0x4065, 0x00}, 440 {0x4066, 0x00}, 441 {0x4067, 0x00}, 442 {0x4068, 0x00}, 443 {0x4069, 0x00}, 444 {0x406a, 0x00}, 445 {0x406b, 0x00}, 446 {0x406c, 0x00}, 447 {0x406d, 0x00}, 448 {0x406e, 0x00}, 449 {0x406f, 0x00}, 450 {0x4070, 0x00}, 451 {0x4071, 0x00}, 452 {0x4072, 0x00}, 453 {0x4073, 0x00}, 454 {0x4074, 0x00}, 455 {0x4075, 0x00}, 456 {0x4076, 0x00}, 457 {0x4077, 0x00}, 458 {0x4078, 0x00}, 459 {0x4079, 0x00}, 460 {0x407a, 0x00}, 461 {0x407b, 0x00}, 462 {0x407c, 0x00}, 463 {0x407d, 0x00}, 464 {0x407e, 0x00}, 465 {0x407f, 0x00}, 466 {0x4080, 0x78}, 467 {0x4081, 0x78}, 468 {0x4082, 0x78}, 469 {0x4083, 0x78}, 470 {0x40e0, 0x00}, 471 {0x40e1, 0x00}, 472 {0x40e2, 0x00}, 473 {0x40e3, 0x00}, 474 {0x40e4, 0x00}, 475 {0x40e5, 0x00}, 476 {0x40e6, 0x00}, 477 {0x40e7, 0x00}, 478 {0x40e8, 0x00}, 479 {0x40e9, 0x80}, 480 {0x40ea, 0x00}, 481 {0x40eb, 0x80}, 482 {0x40ec, 0x00}, 483 {0x40ed, 0x80}, 484 {0x40ee, 0x00}, 485 {0x40ef, 0x80}, 486 {0x40f0, 0x02}, 487 {0x40f1, 0x04}, 488 {0x4300, 0x00}, 489 {0x4301, 0x00}, 490 {0x4302, 0x00}, 491 {0x4303, 0x00}, 492 {0x4304, 0x00}, 493 {0x4305, 0x00}, 494 {0x4306, 0x00}, 495 {0x4307, 0x00}, 496 {0x4308, 0x00}, 497 {0x4309, 0x00}, 498 {0x430a, 0x00}, 499 {0x430b, 0xff}, 500 {0x430c, 0xff}, 501 {0x430d, 0x00}, 502 {0x430e, 0x00}, 503 {0x4315, 0x00}, 504 {0x4316, 0x00}, 505 {0x4317, 0x00}, 506 {0x4318, 0x00}, 507 {0x4319, 0x00}, 508 {0x431a, 0x00}, 509 {0x431b, 0x00}, 510 {0x431c, 0x00}, 511 {0x4500, 0x07}, 512 {0x4502, 0x00}, 513 {0x4503, 0x0f}, 514 {0x4504, 0x80}, 515 {0x4506, 0x01}, 516 {0x4509, 0x05}, 517 {0x450c, 0x00}, 518 {0x450d, 0x20}, 519 {0x450e, 0x00}, 520 {0x450f, 0x00}, 521 {0x4510, 0x00}, 522 {0x4523, 0x00}, 523 {0x4526, 0x00}, 524 {0x4543, 0x00}, 525 {0x4544, 0x00}, 526 {0x4545, 0x00}, 527 {0x4546, 0x00}, 528 {0x4547, 0x10}, 529 {0x4602, 0x00}, 530 {0x4603, 0x15}, 531 {0x460b, 0x07}, 532 {0x4680, 0x11}, 533 {0x4686, 0x00}, 534 {0x4687, 0x00}, 535 {0x4700, 0x00}, 536 {0x4800, 0x64}, 537 {0x4806, 0x40}, 538 {0x480b, 0x10}, 539 {0x480c, 0x80}, 540 {0x480f, 0x32}, 541 {0x4813, 0xe4}, 542 {0x4884, 0x04}, 543 {0x4c00, 0xf8}, 544 {0x4c01, 0x44}, 545 {0x4c03, 0x00}, 546 {0x4d00, 0x00}, 547 {0x4d01, 0x16}, 548 {0x4d04, 0x10}, 549 {0x4d05, 0x00}, 550 {0x4d06, 0x0c}, 551 {0x4d07, 0x00}, 552 {0x5008, 0xb0}, 553 {0x50c1, 0x00}, 554 {0x53c1, 0x00}, 555 {0x5f40, 0x00}, 556 {0x5f41, 0x40}, 557}; 558 559static const struct ov08x40_reg_list ov08x40_global_setting = { 560 .num_of_regs = ARRAY_SIZE(ov08x40_global_regs), 561 .regs = ov08x40_global_regs, 562}; 563 564static const struct ov08x40_reg mipi_data_rate_800mbps[] = { 565 {0x0103, 0x01}, 566 {0x1000, 0x00}, 567 {0x1601, 0xd0}, 568 {0x1001, 0x04}, 569 {0x5004, 0x53}, 570 {0x5110, 0x00}, 571 {0x5111, 0x14}, 572 {0x5112, 0x01}, 573 {0x5113, 0x7b}, 574 {0x5114, 0x00}, 575 {0x5152, 0xa3}, 576 {0x5a52, 0x1f}, 577 {0x5a1a, 0x0e}, 578 {0x5a1b, 0x10}, 579 {0x5a1f, 0x0e}, 580 {0x5a27, 0x0e}, 581 {0x6002, 0x2e}, 582 {0x0300, 0x3a}, /* PLL CTRL */ 583 {0x0301, 0xc8}, 584 {0x0302, 0x31}, 585 {0x0303, 0x03}, 586 {0x0304, 0x01}, 587 {0x0305, 0xa1}, 588 {0x0306, 0x04}, 589 {0x0307, 0x01}, 590 {0x0308, 0x03}, 591 {0x0309, 0x03}, 592 {0x0310, 0x0a}, 593 {0x0311, 0x02}, 594 {0x0312, 0x01}, 595 {0x0313, 0x08}, 596 {0x0314, 0x66}, 597 {0x0315, 0x00}, 598 {0x0316, 0x34}, 599 {0x0320, 0x02}, 600 {0x0321, 0x03}, 601 {0x0323, 0x05}, 602 {0x0324, 0x01}, 603 {0x0325, 0xb8}, 604 {0x0326, 0x4a}, 605 {0x0327, 0x04}, 606 {0x0329, 0x00}, 607 {0x032a, 0x05}, 608 {0x032b, 0x00}, 609 {0x032c, 0x00}, 610 {0x032d, 0x00}, 611 {0x032e, 0x02}, 612 {0x032f, 0xa0}, 613 {0x0350, 0x00}, 614 {0x0360, 0x01}, 615 {0x3012, 0x41}, /* MIPI SC Lanes */ 616}; 617 618static const struct ov08x40_reg mipi_data_rate_1500mbps[] = { 619 {0x0103, 0x01}, 620 {0x1000, 0x00}, 621 {0x1601, 0xd0}, 622 {0x1001, 0x04}, 623 {0x5004, 0x53}, 624 {0x5110, 0x00}, 625 {0x5111, 0x14}, 626 {0x5112, 0x01}, 627 {0x5113, 0x7b}, 628 {0x5114, 0x00}, 629 {0x5152, 0xa3}, 630 {0x5a52, 0x1f}, 631 {0x5a1a, 0x0e}, 632 {0x5a1b, 0x10}, 633 {0x5a1f, 0x0e}, 634 {0x5a27, 0x0e}, 635 {0x6002, 0x2e}, 636 {0x0300, 0x3a}, /* PLL */ 637 {0x0301, 0x88}, 638 {0x0302, 0x31}, 639 {0x0303, 0x05}, 640 {0x0304, 0x01}, 641 {0x0305, 0x38}, 642 {0x0306, 0x04}, 643 {0x0307, 0x00}, 644 {0x0308, 0x03}, 645 {0x0309, 0x02}, 646 {0x0310, 0x0a}, 647 {0x0311, 0x02}, 648 {0x0312, 0x01}, 649 {0x0313, 0x08}, 650 {0x0314, 0x00}, 651 {0x0315, 0x00}, 652 {0x0316, 0x2c}, 653 {0x0320, 0x02}, 654 {0x0321, 0x03}, 655 {0x0323, 0x05}, 656 {0x0324, 0x01}, 657 {0x0325, 0xb8}, 658 {0x0326, 0x4a}, 659 {0x0327, 0x04}, 660 {0x0329, 0x00}, 661 {0x032a, 0x05}, 662 {0x032b, 0x00}, 663 {0x032c, 0x00}, 664 {0x032d, 0x00}, 665 {0x032e, 0x02}, 666 {0x032f, 0xa0}, 667 {0x0350, 0x00}, 668 {0x0360, 0x01}, 669 {0x3012, 0x21}, /* MIPI SC Lanes */ 670}; 671 672static const struct ov08x40_reg mode_3856x2176_regs_800mbps[] = { 673 {0x5000, 0x5d}, 674 {0x5001, 0x20}, 675 {0x3012, 0x41}, 676 {0x3400, 0x1c}, 677 {0x3419, 0x13}, 678 {0x341a, 0x89}, 679 {0x3426, 0x00}, 680 {0x3501, 0x02}, 681 {0x3502, 0x00}, 682 {0x3508, 0x01}, 683 {0x3509, 0x00}, 684 {0x3541, 0x01}, 685 {0x3542, 0x00}, 686 {0x3548, 0x01}, 687 {0x3712, 0x51}, 688 {0x3714, 0x24}, 689 {0x3761, 0x17}, 690 {0x376e, 0x03}, 691 {0x37b0, 0x00}, 692 {0x37b1, 0xab}, 693 {0x37b3, 0x82}, 694 {0x37b4, 0x00}, 695 {0x37b5, 0xe4}, 696 {0x37b6, 0x01}, 697 {0x37b7, 0xee}, 698 {0x3820, 0x00}, 699 {0x3821, 0x04}, 700 {0x3823, 0x04}, 701 {0x384d, 0x80}, 702 {0x3894, 0x00}, 703 {0x400b, 0x08}, 704 {0x400d, 0x08}, 705 {0x4016, 0x2d}, 706 {0x4501, 0x00}, 707 {0x4542, 0x00}, 708 {0x4837, 0x14}, 709 {0x4850, 0x42}, 710 {0x3a20, 0x00}, 711 {0x3939, 0x9d}, 712 {0x3902, 0x0e}, 713 {0x3903, 0x0e}, 714 {0x3904, 0x0e}, 715 {0x3905, 0x0e}, 716 {0x3906, 0x07}, 717 {0x3907, 0x0d}, 718 {0x3908, 0x11}, 719 {0x3909, 0x12}, 720 {0x390c, 0x33}, 721 {0x390d, 0x66}, 722 {0x390e, 0xaa}, 723 {0x3915, 0x90}, 724 {0x3917, 0x90}, 725 {0x3440, 0xa4}, 726 {0x3a26, 0x1d}, 727 {0x3a2c, 0x4a}, 728 {0x3a32, 0x55}, 729 {0x392d, 0x02}, 730 {0x3930, 0x08}, 731 {0x3933, 0x0c}, 732 {0x392a, 0x54}, 733 {0x392b, 0xa8}, 734 {0x380d, 0x80}, 735 {0x380e, 0x13}, 736 {0x380f, 0x88}, 737 {0x3803, 0x70}, 738 {0x3807, 0x0f}, 739 {0x3808, 0x0f}, 740 {0x3809, 0x10}, 741 {0x380a, 0x08}, 742 {0x380b, 0x80}, 743 {0x3811, 0x08}, 744 {0x3813, 0x10}, 745 {0x3501, 0x10}, 746 {0x3508, 0x0f}, 747 {0x3509, 0x80}, 748 {0x3813, 0x0f}, 749}; 750 751/* OV08X 1C 3856x2176_DPHY1500M-2L */ 752static const struct ov08x40_reg mode_3856x2176_regs_1500mbps[] = { 753 {0x5000, 0x5d}, 754 {0x5001, 0x20}, 755 {0x3012, 0x21}, 756 {0x3400, 0x1c}, 757 {0x3419, 0x12}, 758 {0x341a, 0x99}, 759 {0x3426, 0x00}, 760 {0x3501, 0x02}, 761 {0x3502, 0x00}, 762 {0x3508, 0x01}, 763 {0x3509, 0x00}, 764 {0x3541, 0x01}, 765 {0x3542, 0x00}, 766 {0x3548, 0x01}, 767 {0x3712, 0x51}, 768 {0x3714, 0x24}, 769 {0x3761, 0x17}, 770 {0x376e, 0x03}, 771 {0x37b0, 0x00}, 772 {0x37b1, 0xab}, 773 {0x37b3, 0x82}, 774 {0x37b4, 0x00}, 775 {0x37b5, 0xe4}, 776 {0x37b6, 0x01}, 777 {0x37b7, 0xee}, 778 {0x3803, 0x70}, 779 {0x3807, 0x0f}, 780 {0x3808, 0x0f}, 781 {0x3809, 0x10}, 782 {0x380a, 0x08}, 783 {0x380b, 0x80}, 784 {0x380d, 0xa0}, 785 {0x380e, 0x12}, 786 {0x380f, 0x98}, 787 {0x3811, 0x08}, 788 {0x3813, 0x10}, 789 {0x3820, 0x00}, 790 {0x3821, 0x04}, 791 {0x3823, 0x04}, 792 {0x384d, 0xa0}, 793 {0x3894, 0x00}, 794 {0x400b, 0x08}, 795 {0x400d, 0x08}, 796 {0x4016, 0x2d}, 797 {0x4501, 0x00}, 798 {0x4542, 0x00}, 799 {0x4837, 0x0a}, 800 {0x4850, 0x47}, 801 {0x3a20, 0x00}, 802 {0x3939, 0x9d}, 803 {0x3902, 0x0e}, 804 {0x3903, 0x0e}, 805 {0x3904, 0x0e}, 806 {0x3905, 0x0e}, 807 {0x3906, 0x07}, 808 {0x3907, 0x0d}, 809 {0x3908, 0x11}, 810 {0x3909, 0x12}, 811 {0x390c, 0x33}, 812 {0x390d, 0x66}, 813 {0x390e, 0xaa}, 814 {0x3915, 0x90}, 815 {0x3917, 0x90}, 816 {0x3440, 0xa4}, 817 {0x3a26, 0x1d}, 818 {0x3a2c, 0x4a}, 819 {0x3a32, 0x55}, 820 {0x392d, 0x02}, 821 {0x3930, 0x08}, 822 {0x3933, 0x0c}, 823 {0x392a, 0x54}, 824 {0x392b, 0xa8}, 825 {0x3501, 0x10}, 826 {0x3508, 0x0f}, 827 {0x3509, 0x80}, 828 {0x3813, 0x0f}, 829}; 830 831/* OV08X 4C1stg 1928x1088_DPHY1500M-2L 30fps */ 832static const struct ov08x40_reg mode_1928x1088_regs_1500mbps[] = { 833 {0x5000, 0x55}, 834 {0x5001, 0x00}, 835 {0x3012, 0x21}, 836 {0x3400, 0x30}, 837 {0x3419, 0x08}, 838 {0x341a, 0x4f}, 839 {0x3426, 0x00}, 840 {0x3501, 0x02}, 841 {0x3502, 0x00}, 842 {0x3508, 0x01}, 843 {0x3509, 0x00}, 844 {0x3541, 0x01}, 845 {0x3542, 0x00}, 846 {0x3548, 0x01}, 847 {0x3712, 0x50}, 848 {0x3714, 0x21}, 849 {0x3761, 0x28}, 850 {0x376e, 0x07}, 851 {0x37b0, 0x01}, 852 {0x37b1, 0x0f}, 853 {0x37b3, 0xd6}, 854 {0x37b4, 0x01}, 855 {0x37b5, 0x48}, 856 {0x37b6, 0x02}, 857 {0x37b7, 0x40}, 858 {0x3803, 0x78}, 859 {0x3807, 0x07}, 860 {0x3808, 0x07}, 861 {0x3809, 0x88}, 862 {0x380a, 0x04}, 863 {0x380b, 0x40}, 864 {0x380d, 0xf0}, 865 {0x380e, 0x08}, 866 {0x380f, 0x4e}, 867 {0x3811, 0x04}, 868 {0x3813, 0x03}, 869 {0x3820, 0x02}, 870 {0x3821, 0x14}, 871 {0x3823, 0x84}, 872 {0x384d, 0xf0}, 873 {0x3894, 0x03}, 874 {0x400b, 0x04}, 875 {0x400d, 0x04}, 876 {0x4016, 0x27}, 877 {0x4501, 0x10}, 878 {0x4542, 0x01}, 879 {0x4837, 0x0a}, 880 {0x4850, 0x47}, 881 {0x4911, 0x00}, 882 {0x4919, 0x00}, 883 {0x491a, 0x40}, 884 {0x4920, 0x04}, 885 {0x4921, 0x00}, 886 {0x4922, 0x04}, 887 {0x4923, 0x00}, 888 {0x4924, 0x04}, 889 {0x4925, 0x00}, 890 {0x4926, 0x04}, 891 {0x4927, 0x00}, 892 {0x4930, 0x00}, 893 {0x4931, 0x00}, 894 {0x4932, 0x00}, 895 {0x4933, 0x00}, 896 {0x4934, 0x00}, 897 {0x4935, 0x00}, 898 {0x4936, 0x00}, 899 {0x4937, 0x00}, 900 {0x4940, 0x00}, 901 {0x4941, 0x80}, 902 {0x4942, 0x00}, 903 {0x4943, 0x80}, 904 {0x4944, 0x00}, 905 {0x4945, 0x80}, 906 {0x4946, 0x00}, 907 {0x4947, 0x80}, 908 {0x4960, 0x00}, 909 {0x4961, 0x00}, 910 {0x4962, 0x00}, 911 {0x4963, 0x00}, 912 {0x4964, 0x00}, 913 {0x4965, 0x00}, 914 {0x4966, 0x00}, 915 {0x4967, 0x00}, 916 {0x4968, 0x00}, 917 {0x4969, 0x00}, 918 {0x496a, 0x00}, 919 {0x496b, 0x00}, 920 {0x496c, 0x00}, 921 {0x496d, 0x00}, 922 {0x496e, 0x00}, 923 {0x496f, 0x00}, 924 {0x4970, 0x00}, 925 {0x4971, 0x00}, 926 {0x4972, 0x00}, 927 {0x4973, 0x00}, 928 {0x4974, 0x00}, 929 {0x4975, 0x00}, 930 {0x4976, 0x00}, 931 {0x4977, 0x00}, 932 {0x4978, 0x00}, 933 {0x4979, 0x00}, 934 {0x497a, 0x00}, 935 {0x497b, 0x00}, 936 {0x497c, 0x00}, 937 {0x497d, 0x00}, 938 {0x497e, 0x00}, 939 {0x497f, 0x00}, 940 {0x49e0, 0x00}, 941 {0x49e1, 0x00}, 942 {0x49e2, 0x00}, 943 {0x49e3, 0x00}, 944 {0x49e4, 0x00}, 945 {0x49e5, 0x00}, 946 {0x49e6, 0x00}, 947 {0x49e7, 0x00}, 948 {0x49e8, 0x00}, 949 {0x49e9, 0x80}, 950 {0x49ea, 0x00}, 951 {0x49eb, 0x80}, 952 {0x49ec, 0x00}, 953 {0x49ed, 0x80}, 954 {0x49ee, 0x00}, 955 {0x49ef, 0x80}, 956 {0x49f0, 0x02}, 957 {0x49f1, 0x04}, 958 {0x3a20, 0x05}, 959 {0x3939, 0x6b}, 960 {0x3902, 0x10}, 961 {0x3903, 0x10}, 962 {0x3904, 0x10}, 963 {0x3905, 0x10}, 964 {0x3906, 0x01}, 965 {0x3907, 0x0b}, 966 {0x3908, 0x10}, 967 {0x3909, 0x13}, 968 {0x390b, 0x11}, 969 {0x390c, 0x21}, 970 {0x390d, 0x32}, 971 {0x390e, 0x76}, 972 {0x3a1a, 0x1c}, 973 {0x3a26, 0x17}, 974 {0x3a2c, 0x50}, 975 {0x3a32, 0x4f}, 976 {0x3ace, 0x01}, 977 {0x3ad2, 0x01}, 978 {0x3ad6, 0x01}, 979 {0x3ada, 0x01}, 980 {0x3ade, 0x01}, 981 {0x3ae2, 0x01}, 982 {0x3aee, 0x01}, 983 {0x3af2, 0x01}, 984 {0x3af6, 0x01}, 985 {0x3afa, 0x01}, 986 {0x3afe, 0x01}, 987 {0x3b02, 0x01}, 988 {0x3b06, 0x01}, 989 {0x392d, 0x01}, 990 {0x3930, 0x09}, 991 {0x3933, 0x0d}, 992 {0x392a, 0x52}, 993 {0x392b, 0xa3}, 994 {0x340b, 0x1b}, 995 {0x3501, 0x01}, 996 {0x3508, 0x0f}, 997 {0x3509, 0x00}, 998 {0x3541, 0x00}, 999 {0x3542, 0x80}, 1000 {0x3548, 0x0f}, 1001 {0x3813, 0x03}, 1002}; 1003 1004static const struct ov08x40_reg mode_3856x2416_regs[] = { 1005 {0x5000, 0x5d}, 1006 {0x5001, 0x20}, 1007 {0x3012, 0x41}, 1008 {0x3400, 0x1c}, 1009 {0x3419, 0x13}, 1010 {0x341a, 0x89}, 1011 {0x3426, 0x00}, 1012 {0x3501, 0x02}, 1013 {0x3502, 0x00}, 1014 {0x3508, 0x01}, 1015 {0x3509, 0x00}, 1016 {0x3541, 0x01}, 1017 {0x3542, 0x00}, 1018 {0x3548, 0x01}, 1019 {0x3712, 0x51}, 1020 {0x3714, 0x24}, 1021 {0x3761, 0x17}, 1022 {0x376e, 0x03}, 1023 {0x37b0, 0x00}, 1024 {0x37b1, 0xab}, 1025 {0x37b3, 0x82}, 1026 {0x37b4, 0x00}, 1027 {0x37b5, 0xe4}, 1028 {0x37b6, 0x01}, 1029 {0x37b7, 0xee}, 1030 {0x3803, 0x00}, 1031 {0x3807, 0x7f}, 1032 {0x3808, 0x0f}, 1033 {0x3809, 0x10}, 1034 {0x380a, 0x09}, 1035 {0x380b, 0x70}, 1036 {0x380d, 0x80}, 1037 {0x380e, 0x13}, 1038 {0x380f, 0x88}, 1039 {0x3811, 0x08}, 1040 {0x3813, 0x07}, 1041 {0x3820, 0x00}, 1042 {0x3821, 0x04}, 1043 {0x3823, 0x04}, 1044 {0x384d, 0x80}, 1045 {0x3894, 0x00}, 1046 {0x400b, 0x08}, 1047 {0x400d, 0x08}, 1048 {0x4016, 0x2d}, 1049 {0x4501, 0x00}, 1050 {0x4542, 0x00}, 1051 {0x4837, 0x14}, 1052 {0x4850, 0x42}, 1053 {0x3a20, 0x00}, 1054 {0x3939, 0x9d}, 1055 {0x3902, 0x0e}, 1056 {0x3903, 0x0e}, 1057 {0x3904, 0x0e}, 1058 {0x3905, 0x0e}, 1059 {0x3906, 0x07}, 1060 {0x3907, 0x0d}, 1061 {0x3908, 0x11}, 1062 {0x3909, 0x12}, 1063 {0x390c, 0x33}, 1064 {0x390d, 0x66}, 1065 {0x390e, 0xaa}, 1066 {0x3915, 0x90}, 1067 {0x3917, 0x90}, 1068 {0x3440, 0xa4}, 1069 {0x3a26, 0x1d}, 1070 {0x3a2c, 0x4a}, 1071 {0x3a32, 0x55}, 1072 {0x392d, 0x02}, 1073 {0x3930, 0x08}, 1074 {0x3933, 0x0c}, 1075 {0x392a, 0x54}, 1076 {0x392b, 0xa8}, 1077 {0x3501, 0x10}, 1078 {0x3508, 0x0f}, 1079 {0x3509, 0x80}, 1080}; 1081 1082static const struct ov08x40_reg mode_1928x1208_regs[] = { 1083 {0x5000, 0x55}, 1084 {0x5001, 0x00}, 1085 {0x3012, 0x41}, 1086 {0x3400, 0x1c}, 1087 {0x3419, 0x08}, 1088 {0x341a, 0xaf}, 1089 {0x3426, 0x00}, 1090 {0x3501, 0x02}, 1091 {0x3502, 0x00}, 1092 {0x3508, 0x01}, 1093 {0x3509, 0x00}, 1094 {0x3541, 0x01}, 1095 {0x3542, 0x00}, 1096 {0x3548, 0x01}, 1097 {0x3712, 0x50}, 1098 {0x3714, 0x21}, 1099 {0x3761, 0x28}, 1100 {0x376e, 0x07}, 1101 {0x37b0, 0x01}, 1102 {0x37b1, 0x0f}, 1103 {0x37b3, 0xd6}, 1104 {0x37b4, 0x01}, 1105 {0x37b5, 0x48}, 1106 {0x37b6, 0x02}, 1107 {0x37b7, 0x40}, 1108 {0x3803, 0x00}, 1109 {0x3807, 0x7f}, 1110 {0x3808, 0x07}, 1111 {0x3809, 0x88}, 1112 {0x380a, 0x04}, 1113 {0x380b, 0xb8}, 1114 {0x380d, 0xd0}, 1115 {0x380e, 0x11}, 1116 {0x380f, 0x5c}, 1117 {0x3811, 0x04}, 1118 {0x3813, 0x03}, 1119 {0x3820, 0x02}, 1120 {0x3821, 0x14}, 1121 {0x3823, 0x04}, 1122 {0x384d, 0xd0}, 1123 {0x3894, 0x00}, 1124 {0x400b, 0x04}, 1125 {0x400d, 0x04}, 1126 {0x4016, 0x27}, 1127 {0x4501, 0x10}, 1128 {0x4542, 0x00}, 1129 {0x4837, 0x14}, 1130 {0x4850, 0x42}, 1131 {0x3a20, 0x05}, 1132 {0x3939, 0x6b}, 1133 {0x3902, 0x10}, 1134 {0x3903, 0x10}, 1135 {0x3904, 0x10}, 1136 {0x3905, 0x10}, 1137 {0x3906, 0x01}, 1138 {0x3907, 0x0b}, 1139 {0x3908, 0x10}, 1140 {0x3909, 0x13}, 1141 {0x390b, 0x11}, 1142 {0x390c, 0x21}, 1143 {0x390d, 0x32}, 1144 {0x390e, 0x76}, 1145 {0x3a1a, 0x1c}, 1146 {0x3a26, 0x17}, 1147 {0x3a2c, 0x50}, 1148 {0x3a32, 0x4f}, 1149 {0x3ace, 0x01}, 1150 {0x3ad2, 0x01}, 1151 {0x3ad6, 0x01}, 1152 {0x3ada, 0x01}, 1153 {0x3ade, 0x01}, 1154 {0x3ae2, 0x01}, 1155 {0x3aee, 0x01}, 1156 {0x3af2, 0x01}, 1157 {0x3af6, 0x01}, 1158 {0x3afa, 0x01}, 1159 {0x3afe, 0x01}, 1160 {0x3b02, 0x01}, 1161 {0x3b06, 0x01}, 1162 {0x392d, 0x01}, 1163 {0x3930, 0x09}, 1164 {0x3933, 0x0d}, 1165 {0x392a, 0x52}, 1166 {0x392b, 0xa3}, 1167 {0x340b, 0x1b}, 1168 {0x3501, 0x08}, 1169 {0x3508, 0x04}, 1170 {0x3509, 0x00}, 1171}; 1172 1173static const char * const ov08x40_test_pattern_menu[] = { 1174 "Disabled", 1175 "Vertical Color Bar Type 1", 1176 "Vertical Color Bar Type 2", 1177 "Vertical Color Bar Type 3", 1178 "Vertical Color Bar Type 4" 1179}; 1180 1181/* Configurations for supported link frequencies */ 1182#define OV08X40_LINK_FREQ_400MHZ 400000000ULL 1183#define OV08X40_LINK_FREQ_749MHZ 749000000ULL 1184#define OV08X40_SCLK_96MHZ 96000000ULL 1185#define OV08X40_XVCLK 19200000 1186#define OV08X40_DATA_LANES 4 1187 1188/* 1189 * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample 1190 * data rate => double data rate; number of lanes => 4; bits per pixel => 10 1191 */ 1192static u64 link_freq_to_pixel_rate(u64 f) 1193{ 1194 f *= 2 * OV08X40_DATA_LANES; 1195 do_div(f, 10); 1196 1197 return f; 1198} 1199 1200/* Menu items for LINK_FREQ V4L2 control */ 1201static const s64 link_freq_menu_items[] = { 1202 OV08X40_LINK_FREQ_400MHZ, 1203 OV08X40_LINK_FREQ_749MHZ, 1204}; 1205 1206/* Link frequency configs */ 1207static const struct ov08x40_link_freq_config link_freq_configs[] = { 1208 [OV08X40_LINK_FREQ_400MHZ_INDEX] = { 1209 .reg_list = { 1210 .num_of_regs = ARRAY_SIZE(mipi_data_rate_800mbps), 1211 .regs = mipi_data_rate_800mbps, 1212 } 1213 }, 1214 [OV08X40_LINK_FREQ_749MHZ_INDEX] = { 1215 .reg_list = { 1216 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1500mbps), 1217 .regs = mipi_data_rate_1500mbps, 1218 } 1219 }, 1220}; 1221 1222/* Mode configs */ 1223static const struct ov08x40_mode supported_modes[] = { 1224 { 1225 .width = 3856, 1226 .height = 2416, 1227 .vts_def = OV08X40_VTS_30FPS, 1228 .vts_min = OV08X40_VTS_30FPS, 1229 .llp = 0x10aa, /* in normal mode, tline time = 2 * HTS / SCLK */ 1230 .lanes = 4, 1231 .reg_list = { 1232 .num_of_regs = ARRAY_SIZE(mode_3856x2416_regs), 1233 .regs = mode_3856x2416_regs, 1234 }, 1235 .link_freq_index = OV08X40_LINK_FREQ_400MHZ_INDEX, 1236 .exposure_shift = 1, 1237 .exposure_margin = OV08X40_EXPOSURE_MAX_MARGIN, 1238 }, 1239 { 1240 .width = 3856, 1241 .height = 2176, 1242 .vts_def = OV08X40_VTS_30FPS, 1243 .vts_min = OV08X40_VTS_30FPS, 1244 .llp = 0x10aa, /* in normal mode, tline time = 2 * HTS / SCLK */ 1245 .lanes = 4, 1246 .reg_list = { 1247 .num_of_regs = ARRAY_SIZE(mode_3856x2176_regs_800mbps), 1248 .regs = mode_3856x2176_regs_800mbps, 1249 }, 1250 .link_freq_index = OV08X40_LINK_FREQ_400MHZ_INDEX, 1251 .exposure_shift = 1, 1252 .exposure_margin = OV08X40_EXPOSURE_MAX_MARGIN, 1253 }, 1254 1255 { 1256 .width = 1928, 1257 .height = 1208, 1258 .vts_def = OV08X40_VTS_BIN_30FPS, 1259 .vts_min = OV08X40_VTS_BIN_30FPS, 1260 .llp = 0x960, 1261 .lanes = 4, 1262 .reg_list = { 1263 .num_of_regs = ARRAY_SIZE(mode_1928x1208_regs), 1264 .regs = mode_1928x1208_regs, 1265 }, 1266 .link_freq_index = OV08X40_LINK_FREQ_400MHZ_INDEX, 1267 .exposure_shift = 0, 1268 .exposure_margin = OV08X40_EXPOSURE_BIN_MAX_MARGIN, 1269 }, 1270 { 1271 .width = 3856, 1272 .height = 2176, 1273 .vts_def = OV08X40_VTS_30FPS, 1274 .vts_min = OV08X40_VTS_30FPS, 1275 .llp = 0x10aa, /* in normal mode, tline time = 2 * HTS / SCLK */ 1276 .lanes = 2, 1277 .reg_list = { 1278 .num_of_regs = ARRAY_SIZE(mode_3856x2176_regs_1500mbps), 1279 .regs = mode_3856x2176_regs_1500mbps, 1280 }, 1281 .link_freq_index = OV08X40_LINK_FREQ_749MHZ_INDEX, 1282 .exposure_shift = 1, 1283 .exposure_margin = OV08X40_EXPOSURE_MAX_MARGIN, 1284 }, 1285 { 1286 .width = 1928, 1287 .height = 1088, 1288 .vts_def = OV08X40_VTS_BIN_30FPS, 1289 .vts_min = OV08X40_VTS_BIN_30FPS, 1290 .llp = 0x960, 1291 .lanes = 2, 1292 .reg_list = { 1293 .num_of_regs = ARRAY_SIZE(mode_1928x1088_regs_1500mbps), 1294 .regs = mode_1928x1088_regs_1500mbps, 1295 }, 1296 .link_freq_index = OV08X40_LINK_FREQ_749MHZ_INDEX, 1297 .exposure_shift = 0, 1298 .exposure_margin = OV08X40_EXPOSURE_MAX_MARGIN, 1299 }, 1300}; 1301 1302static const char * const ov08x40_supply_names[] = { 1303 "dovdd", /* Digital I/O power */ 1304 "avdd", /* Analog power */ 1305 "dvdd", /* Digital core power */ 1306}; 1307 1308struct ov08x40 { 1309 struct device *dev; 1310 1311 struct v4l2_subdev sd; 1312 struct media_pad pad; 1313 1314 struct v4l2_ctrl_handler ctrl_handler; 1315 /* V4L2 Controls */ 1316 struct v4l2_ctrl *link_freq; 1317 struct v4l2_ctrl *pixel_rate; 1318 struct v4l2_ctrl *vblank; 1319 struct v4l2_ctrl *hblank; 1320 struct v4l2_ctrl *exposure; 1321 1322 struct clk *xvclk; 1323 struct gpio_desc *reset_gpio; 1324 struct regulator_bulk_data supplies[ARRAY_SIZE(ov08x40_supply_names)]; 1325 1326 /* Current mode */ 1327 const struct ov08x40_mode *cur_mode; 1328 1329 /* Mutex for serialized access */ 1330 struct mutex mutex; 1331 1332 /* data lanes */ 1333 u8 mipi_lanes; 1334 1335 /* True if the device has been identified */ 1336 bool identified; 1337 1338 unsigned long link_freq_bitmap; 1339}; 1340 1341#define to_ov08x40(_sd) container_of(_sd, struct ov08x40, sd) 1342 1343static int ov08x40_power_on(struct device *dev) 1344{ 1345 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1346 struct ov08x40 *ov08x = to_ov08x40(sd); 1347 int ret; 1348 1349 ret = clk_prepare_enable(ov08x->xvclk); 1350 if (ret < 0) { 1351 dev_err(dev, "failed to enable xvclk\n"); 1352 return ret; 1353 } 1354 1355 if (ov08x->reset_gpio) { 1356 gpiod_set_value_cansleep(ov08x->reset_gpio, 1); 1357 usleep_range(1000, 2000); 1358 } 1359 1360 ret = regulator_bulk_enable(ARRAY_SIZE(ov08x40_supply_names), 1361 ov08x->supplies); 1362 if (ret < 0) { 1363 dev_err(dev, "failed to enable regulators\n"); 1364 goto disable_clk; 1365 } 1366 1367 gpiod_set_value_cansleep(ov08x->reset_gpio, 0); 1368 usleep_range(5000, 5500); 1369 1370 return 0; 1371 1372disable_clk: 1373 gpiod_set_value_cansleep(ov08x->reset_gpio, 1); 1374 clk_disable_unprepare(ov08x->xvclk); 1375 1376 return ret; 1377} 1378 1379static int ov08x40_power_off(struct device *dev) 1380{ 1381 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1382 struct ov08x40 *ov08x = to_ov08x40(sd); 1383 1384 gpiod_set_value_cansleep(ov08x->reset_gpio, 1); 1385 regulator_bulk_disable(ARRAY_SIZE(ov08x40_supply_names), 1386 ov08x->supplies); 1387 clk_disable_unprepare(ov08x->xvclk); 1388 1389 return 0; 1390} 1391 1392/* Read registers up to 4 at a time */ 1393static int ov08x40_read_reg(struct ov08x40 *ov08x, 1394 u16 reg, u32 len, u32 *val) 1395{ 1396 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd); 1397 struct i2c_msg msgs[2]; 1398 u8 *data_be_p; 1399 int ret; 1400 __be32 data_be = 0; 1401 __be16 reg_addr_be = cpu_to_be16(reg); 1402 1403 if (len > 4) 1404 return -EINVAL; 1405 1406 data_be_p = (u8 *)&data_be; 1407 /* Write register address */ 1408 msgs[0].addr = client->addr; 1409 msgs[0].flags = 0; 1410 msgs[0].len = 2; 1411 msgs[0].buf = (u8 *)®_addr_be; 1412 1413 /* Read data from register */ 1414 msgs[1].addr = client->addr; 1415 msgs[1].flags = I2C_M_RD; 1416 msgs[1].len = len; 1417 msgs[1].buf = &data_be_p[4 - len]; 1418 1419 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 1420 if (ret != ARRAY_SIZE(msgs)) 1421 return ret < 0 ? ret : -EIO; 1422 1423 *val = be32_to_cpu(data_be); 1424 1425 return 0; 1426} 1427 1428static int __ov08x40_burst_fill_regs(struct i2c_client *client, u16 first_reg, 1429 u16 last_reg, size_t num_regs, u8 val) 1430{ 1431 struct i2c_msg msgs; 1432 size_t i; 1433 int ret; 1434 1435 msgs.addr = client->addr; 1436 msgs.flags = 0; 1437 msgs.len = 2 + num_regs; 1438 msgs.buf = kmalloc(msgs.len, GFP_KERNEL); 1439 1440 if (!msgs.buf) 1441 return -ENOMEM; 1442 1443 put_unaligned_be16(first_reg, msgs.buf); 1444 1445 for (i = 0; i < num_regs; ++i) 1446 msgs.buf[2 + i] = val; 1447 1448 ret = i2c_transfer(client->adapter, &msgs, 1); 1449 1450 kfree(msgs.buf); 1451 1452 if (ret != 1) { 1453 dev_err(&client->dev, "Failed regs transferred: %d\n", ret); 1454 return -EIO; 1455 } 1456 1457 return 0; 1458} 1459 1460static int ov08x40_burst_fill_regs(struct ov08x40 *ov08x, u16 first_reg, 1461 u16 last_reg, u8 val) 1462{ 1463 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd); 1464 size_t num_regs, num_write_regs; 1465 int ret; 1466 1467 num_regs = last_reg - first_reg + 1; 1468 num_write_regs = num_regs; 1469 1470 if (client->adapter->quirks && client->adapter->quirks->max_write_len) 1471 num_write_regs = client->adapter->quirks->max_write_len - 2; 1472 1473 while (first_reg < last_reg) { 1474 ret = __ov08x40_burst_fill_regs(client, first_reg, last_reg, 1475 num_write_regs, val); 1476 if (ret) 1477 return ret; 1478 1479 first_reg += num_write_regs; 1480 } 1481 1482 return 0; 1483} 1484 1485/* Write registers up to 4 at a time */ 1486static int ov08x40_write_reg(struct ov08x40 *ov08x, 1487 u16 reg, u32 len, u32 __val) 1488{ 1489 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd); 1490 int buf_i, val_i, ret; 1491 u8 buf[6], *val_p; 1492 __be32 val; 1493 1494 if (len > 4) 1495 return -EINVAL; 1496 1497 buf[0] = reg >> 8; 1498 buf[1] = reg & 0xff; 1499 1500 val = cpu_to_be32(__val); 1501 val_p = (u8 *)&val; 1502 buf_i = 2; 1503 val_i = 4 - len; 1504 1505 while (val_i < 4) 1506 buf[buf_i++] = val_p[val_i++]; 1507 1508 ret = i2c_master_send(client, buf, len + 2); 1509 if (ret != len + 2) 1510 return ret < 0 ? ret : -EIO; 1511 1512 return 0; 1513} 1514 1515/* Write a list of registers */ 1516static int ov08x40_write_regs(struct ov08x40 *ov08x, 1517 const struct ov08x40_reg *regs, u32 len) 1518{ 1519 int ret; 1520 u32 i; 1521 1522 for (i = 0; i < len; i++) { 1523 ret = ov08x40_write_reg(ov08x, regs[i].address, 1, 1524 regs[i].val); 1525 1526 if (ret) { 1527 dev_err_ratelimited(ov08x->dev, 1528 "Failed to write reg 0x%4.4x. error = %d\n", 1529 regs[i].address, ret); 1530 1531 return ret; 1532 } 1533 } 1534 1535 return 0; 1536} 1537 1538static int ov08x40_write_reg_list(struct ov08x40 *ov08x, 1539 const struct ov08x40_reg_list *r_list) 1540{ 1541 return ov08x40_write_regs(ov08x, r_list->regs, r_list->num_of_regs); 1542} 1543 1544static int ov08x40_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 1545{ 1546 const struct ov08x40_mode *default_mode = &supported_modes[0]; 1547 struct ov08x40 *ov08x = to_ov08x40(sd); 1548 struct v4l2_mbus_framefmt *try_fmt = 1549 v4l2_subdev_state_get_format(fh->state, 0); 1550 1551 mutex_lock(&ov08x->mutex); 1552 1553 /* Initialize try_fmt */ 1554 try_fmt->width = default_mode->width; 1555 try_fmt->height = default_mode->height; 1556 try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; 1557 try_fmt->field = V4L2_FIELD_NONE; 1558 1559 /* No crop or compose */ 1560 mutex_unlock(&ov08x->mutex); 1561 1562 return 0; 1563} 1564 1565static int ov08x40_update_digital_gain(struct ov08x40 *ov08x, u32 d_gain) 1566{ 1567 int ret; 1568 u32 val; 1569 1570 /* 1571 * 0x350C[1:0], 0x350B[7:0], 0x350A[4:0] 1572 */ 1573 1574 val = (d_gain & OV08X40_DGTL_GAIN_L_MASK) << OV08X40_DGTL_GAIN_L_SHIFT; 1575 ret = ov08x40_write_reg(ov08x, OV08X40_REG_DGTL_GAIN_L, 1576 OV08X40_REG_VALUE_08BIT, val); 1577 if (ret) 1578 return ret; 1579 1580 val = (d_gain >> OV08X40_DGTL_GAIN_M_SHIFT) & OV08X40_DGTL_GAIN_M_MASK; 1581 ret = ov08x40_write_reg(ov08x, OV08X40_REG_DGTL_GAIN_M, 1582 OV08X40_REG_VALUE_08BIT, val); 1583 if (ret) 1584 return ret; 1585 1586 val = (d_gain >> OV08X40_DGTL_GAIN_H_SHIFT) & OV08X40_DGTL_GAIN_H_MASK; 1587 1588 return ov08x40_write_reg(ov08x, OV08X40_REG_DGTL_GAIN_H, 1589 OV08X40_REG_VALUE_08BIT, val); 1590} 1591 1592static int ov08x40_enable_test_pattern(struct ov08x40 *ov08x, u32 pattern) 1593{ 1594 int ret; 1595 u32 val; 1596 1597 ret = ov08x40_read_reg(ov08x, OV08X40_REG_TEST_PATTERN, 1598 OV08X40_REG_VALUE_08BIT, &val); 1599 if (ret) 1600 return ret; 1601 1602 if (pattern) { 1603 ret = ov08x40_read_reg(ov08x, OV08X40_REG_ISP, 1604 OV08X40_REG_VALUE_08BIT, &val); 1605 if (ret) 1606 return ret; 1607 1608 ret = ov08x40_write_reg(ov08x, OV08X40_REG_ISP, 1609 OV08X40_REG_VALUE_08BIT, 1610 val | BIT(1)); 1611 if (ret) 1612 return ret; 1613 1614 ret = ov08x40_read_reg(ov08x, OV08X40_REG_SHORT_TEST_PATTERN, 1615 OV08X40_REG_VALUE_08BIT, &val); 1616 if (ret) 1617 return ret; 1618 1619 ret = ov08x40_write_reg(ov08x, OV08X40_REG_SHORT_TEST_PATTERN, 1620 OV08X40_REG_VALUE_08BIT, 1621 val | BIT(0)); 1622 if (ret) 1623 return ret; 1624 1625 ret = ov08x40_read_reg(ov08x, OV08X40_REG_TEST_PATTERN, 1626 OV08X40_REG_VALUE_08BIT, &val); 1627 if (ret) 1628 return ret; 1629 1630 val &= OV08X40_TEST_PATTERN_MASK; 1631 val |= ((pattern - 1) << OV08X40_TEST_PATTERN_BAR_SHIFT) | 1632 OV08X40_TEST_PATTERN_ENABLE; 1633 } else { 1634 val &= ~OV08X40_TEST_PATTERN_ENABLE; 1635 } 1636 1637 return ov08x40_write_reg(ov08x, OV08X40_REG_TEST_PATTERN, 1638 OV08X40_REG_VALUE_08BIT, val); 1639} 1640 1641static int ov08x40_set_ctrl_hflip(struct ov08x40 *ov08x, u32 ctrl_val) 1642{ 1643 int ret; 1644 u32 val; 1645 1646 ret = ov08x40_read_reg(ov08x, OV08X40_REG_MIRROR, 1647 OV08X40_REG_VALUE_08BIT, &val); 1648 if (ret) 1649 return ret; 1650 1651 return ov08x40_write_reg(ov08x, OV08X40_REG_MIRROR, 1652 OV08X40_REG_VALUE_08BIT, 1653 ctrl_val ? val & ~BIT(2) : val | BIT(2)); 1654} 1655 1656static int ov08x40_set_ctrl_vflip(struct ov08x40 *ov08x, u32 ctrl_val) 1657{ 1658 int ret; 1659 u32 val; 1660 1661 ret = ov08x40_read_reg(ov08x, OV08X40_REG_VFLIP, 1662 OV08X40_REG_VALUE_08BIT, &val); 1663 if (ret) 1664 return ret; 1665 1666 return ov08x40_write_reg(ov08x, OV08X40_REG_VFLIP, 1667 OV08X40_REG_VALUE_08BIT, 1668 ctrl_val ? val | BIT(2) : val & ~BIT(2)); 1669} 1670 1671static int ov08x40_set_ctrl(struct v4l2_ctrl *ctrl) 1672{ 1673 struct ov08x40 *ov08x = container_of(ctrl->handler, 1674 struct ov08x40, ctrl_handler); 1675 s64 max; 1676 int exp; 1677 int fll; 1678 int ret = 0; 1679 1680 /* Propagate change of current control to all related controls */ 1681 switch (ctrl->id) { 1682 case V4L2_CID_VBLANK: 1683 /* Update max exposure while meeting expected vblanking */ 1684 /* 1685 * because in normal mode, 1 HTS = 0.5 tline 1686 * fps = sclk / hts / vts 1687 * so the vts value needs to be double 1688 */ 1689 max = ((ov08x->cur_mode->height + ctrl->val) << 1690 ov08x->cur_mode->exposure_shift) - 1691 ov08x->cur_mode->exposure_margin; 1692 1693 __v4l2_ctrl_modify_range(ov08x->exposure, 1694 ov08x->exposure->minimum, 1695 max, ov08x->exposure->step, max); 1696 break; 1697 } 1698 1699 /* 1700 * Applying V4L2 control value only happens 1701 * when power is up for streaming 1702 */ 1703 if (!pm_runtime_get_if_in_use(ov08x->dev)) 1704 return 0; 1705 1706 switch (ctrl->id) { 1707 case V4L2_CID_ANALOGUE_GAIN: 1708 ret = ov08x40_write_reg(ov08x, OV08X40_REG_ANALOG_GAIN, 1709 OV08X40_REG_VALUE_16BIT, 1710 ctrl->val << 1); 1711 break; 1712 case V4L2_CID_DIGITAL_GAIN: 1713 ret = ov08x40_update_digital_gain(ov08x, ctrl->val); 1714 break; 1715 case V4L2_CID_EXPOSURE: 1716 exp = (ctrl->val << ov08x->cur_mode->exposure_shift) - 1717 ov08x->cur_mode->exposure_margin; 1718 1719 ret = ov08x40_write_reg(ov08x, OV08X40_REG_EXPOSURE, 1720 OV08X40_REG_VALUE_24BIT, 1721 exp); 1722 break; 1723 case V4L2_CID_VBLANK: 1724 fll = ((ov08x->cur_mode->height + ctrl->val) << 1725 ov08x->cur_mode->exposure_shift); 1726 1727 ret = ov08x40_write_reg(ov08x, OV08X40_REG_VTS, 1728 OV08X40_REG_VALUE_16BIT, 1729 fll); 1730 break; 1731 case V4L2_CID_TEST_PATTERN: 1732 ret = ov08x40_enable_test_pattern(ov08x, ctrl->val); 1733 break; 1734 case V4L2_CID_HFLIP: 1735 ov08x40_set_ctrl_hflip(ov08x, ctrl->val); 1736 break; 1737 case V4L2_CID_VFLIP: 1738 ov08x40_set_ctrl_vflip(ov08x, ctrl->val); 1739 break; 1740 default: 1741 dev_info(ov08x->dev, 1742 "ctrl(id:0x%x,val:0x%x) is not handled\n", 1743 ctrl->id, ctrl->val); 1744 break; 1745 } 1746 1747 pm_runtime_put(ov08x->dev); 1748 1749 return ret; 1750} 1751 1752static bool filter_by_mipi_lanes(const void *array, size_t index, 1753 const void *context) 1754{ 1755 const struct ov08x40_mode *mode = array; 1756 const struct ov08x40 *ov08x = context; 1757 1758 return mode->lanes == ov08x->mipi_lanes; 1759} 1760 1761static const struct v4l2_ctrl_ops ov08x40_ctrl_ops = { 1762 .s_ctrl = ov08x40_set_ctrl, 1763}; 1764 1765static int ov08x40_enum_mbus_code(struct v4l2_subdev *sd, 1766 struct v4l2_subdev_state *sd_state, 1767 struct v4l2_subdev_mbus_code_enum *code) 1768{ 1769 /* Only one bayer order(GRBG) is supported */ 1770 if (code->index > 0) 1771 return -EINVAL; 1772 1773 code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 1774 1775 return 0; 1776} 1777 1778static int ov08x40_enum_frame_size(struct v4l2_subdev *sd, 1779 struct v4l2_subdev_state *sd_state, 1780 struct v4l2_subdev_frame_size_enum *fse) 1781{ 1782 struct ov08x40 *ov08x = to_ov08x40(sd); 1783 size_t i, count = 0; 1784 1785 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 1786 return -EINVAL; 1787 1788 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { 1789 if (!filter_by_mipi_lanes(&supported_modes[i], i, ov08x)) 1790 continue; 1791 1792 if (count == fse->index) { 1793 fse->min_width = supported_modes[i].width; 1794 fse->max_width = fse->min_width; 1795 fse->min_height = supported_modes[i].height; 1796 fse->max_height = fse->min_height; 1797 return 0; 1798 } 1799 1800 count++; 1801 } 1802 1803 return -EINVAL; 1804} 1805 1806static void ov08x40_update_pad_format(const struct ov08x40_mode *mode, 1807 struct v4l2_subdev_format *fmt) 1808{ 1809 fmt->format.width = mode->width; 1810 fmt->format.height = mode->height; 1811 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; 1812 fmt->format.field = V4L2_FIELD_NONE; 1813} 1814 1815static int ov08x40_do_get_pad_format(struct ov08x40 *ov08x, 1816 struct v4l2_subdev_state *sd_state, 1817 struct v4l2_subdev_format *fmt) 1818{ 1819 struct v4l2_mbus_framefmt *framefmt; 1820 1821 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1822 framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad); 1823 fmt->format = *framefmt; 1824 } else { 1825 ov08x40_update_pad_format(ov08x->cur_mode, fmt); 1826 } 1827 1828 return 0; 1829} 1830 1831static int ov08x40_get_pad_format(struct v4l2_subdev *sd, 1832 struct v4l2_subdev_state *sd_state, 1833 struct v4l2_subdev_format *fmt) 1834{ 1835 struct ov08x40 *ov08x = to_ov08x40(sd); 1836 int ret; 1837 1838 mutex_lock(&ov08x->mutex); 1839 ret = ov08x40_do_get_pad_format(ov08x, sd_state, fmt); 1840 mutex_unlock(&ov08x->mutex); 1841 1842 return ret; 1843} 1844 1845static int 1846ov08x40_set_pad_format(struct v4l2_subdev *sd, 1847 struct v4l2_subdev_state *sd_state, 1848 struct v4l2_subdev_format *fmt) 1849{ 1850 struct ov08x40 *ov08x = to_ov08x40(sd); 1851 const struct ov08x40_mode *mode; 1852 struct v4l2_mbus_framefmt *framefmt; 1853 s32 vblank_def; 1854 s32 vblank_min; 1855 s64 h_blank; 1856 s64 pixel_rate; 1857 s64 link_freq; 1858 u64 steps; 1859 1860 mutex_lock(&ov08x->mutex); 1861 1862 /* Only one raw bayer(GRBG) order is supported */ 1863 if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10) 1864 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; 1865 1866 mode = v4l2_find_nearest_size_conditional(supported_modes, 1867 ARRAY_SIZE(supported_modes), 1868 width, height, 1869 fmt->format.width, 1870 fmt->format.height, 1871 filter_by_mipi_lanes, 1872 ov08x); 1873 ov08x40_update_pad_format(mode, fmt); 1874 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1875 framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad); 1876 *framefmt = fmt->format; 1877 } else { 1878 ov08x->cur_mode = mode; 1879 __v4l2_ctrl_s_ctrl(ov08x->link_freq, mode->link_freq_index); 1880 link_freq = link_freq_menu_items[mode->link_freq_index]; 1881 pixel_rate = link_freq_to_pixel_rate(link_freq); 1882 __v4l2_ctrl_s_ctrl_int64(ov08x->pixel_rate, pixel_rate); 1883 1884 /* Update limits and set FPS to default */ 1885 vblank_def = ov08x->cur_mode->vts_def - 1886 ov08x->cur_mode->height; 1887 vblank_min = ov08x->cur_mode->vts_min - 1888 ov08x->cur_mode->height; 1889 1890 /* 1891 * The frame length line should be aligned to a multiple of 4, 1892 * as provided by the sensor vendor, in normal mode. 1893 */ 1894 steps = mode->exposure_shift == 1 ? 4 : 1; 1895 1896 __v4l2_ctrl_modify_range(ov08x->vblank, vblank_min, 1897 OV08X40_VTS_MAX 1898 - ov08x->cur_mode->height, 1899 steps, 1900 vblank_def); 1901 __v4l2_ctrl_s_ctrl(ov08x->vblank, vblank_def); 1902 1903 h_blank = ov08x->cur_mode->llp - ov08x->cur_mode->width; 1904 1905 __v4l2_ctrl_modify_range(ov08x->hblank, h_blank, 1906 h_blank, 1, h_blank); 1907 } 1908 1909 mutex_unlock(&ov08x->mutex); 1910 1911 return 0; 1912} 1913 1914static int ov08x40_start_streaming(struct ov08x40 *ov08x) 1915{ 1916 const struct ov08x40_reg_list *reg_list; 1917 int ret, link_freq_index; 1918 1919 /* Get out of from software reset */ 1920 ret = ov08x40_write_reg(ov08x, OV08X40_REG_SOFTWARE_RST, 1921 OV08X40_REG_VALUE_08BIT, OV08X40_SOFTWARE_RST); 1922 if (ret) { 1923 dev_err(ov08x->dev, "%s failed to set powerup registers\n", 1924 __func__); 1925 return ret; 1926 } 1927 1928 link_freq_index = ov08x->cur_mode->link_freq_index; 1929 reg_list = &link_freq_configs[link_freq_index].reg_list; 1930 1931 ret = ov08x40_write_reg_list(ov08x, reg_list); 1932 if (ret) { 1933 dev_err(ov08x->dev, "%s failed to set plls\n", __func__); 1934 return ret; 1935 } 1936 1937 reg_list = &ov08x40_global_setting; 1938 ret = ov08x40_write_reg_list(ov08x, reg_list); 1939 if (ret) { 1940 dev_err(ov08x->dev, "%s failed to set global setting\n", 1941 __func__); 1942 return ret; 1943 } 1944 1945 /* Apply default values of current mode */ 1946 reg_list = &ov08x->cur_mode->reg_list; 1947 ret = ov08x40_write_reg_list(ov08x, reg_list); 1948 if (ret) { 1949 dev_err(ov08x->dev, "%s failed to set mode\n", __func__); 1950 return ret; 1951 } 1952 1953 /* Use i2c burst to write register on full size registers */ 1954 if (ov08x->cur_mode->exposure_shift == 1) { 1955 ret = ov08x40_burst_fill_regs(ov08x, OV08X40_REG_XTALK_FIRST_A, 1956 OV08X40_REG_XTALK_LAST_A, 0x75); 1957 if (ret == 0) 1958 ret = ov08x40_burst_fill_regs(ov08x, 1959 OV08X40_REG_XTALK_FIRST_B, 1960 OV08X40_REG_XTALK_LAST_B, 1961 0x75); 1962 } 1963 1964 if (ret) { 1965 dev_err(ov08x->dev, "%s failed to set regs\n", __func__); 1966 return ret; 1967 } 1968 1969 /* Apply customized values from user */ 1970 ret = __v4l2_ctrl_handler_setup(ov08x->sd.ctrl_handler); 1971 if (ret) 1972 return ret; 1973 1974 return ov08x40_write_reg(ov08x, OV08X40_REG_MODE_SELECT, 1975 OV08X40_REG_VALUE_08BIT, 1976 OV08X40_MODE_STREAMING); 1977} 1978 1979/* Stop streaming */ 1980static int ov08x40_stop_streaming(struct ov08x40 *ov08x) 1981{ 1982 return ov08x40_write_reg(ov08x, OV08X40_REG_MODE_SELECT, 1983 OV08X40_REG_VALUE_08BIT, OV08X40_MODE_STANDBY); 1984} 1985 1986/* Verify chip ID */ 1987static int ov08x40_identify_module(struct ov08x40 *ov08x) 1988{ 1989 int ret; 1990 u32 val; 1991 1992 if (ov08x->identified) 1993 return 0; 1994 1995 ret = ov08x40_read_reg(ov08x, OV08X40_REG_CHIP_ID, 1996 OV08X40_REG_VALUE_24BIT, &val); 1997 if (ret) { 1998 dev_err(ov08x->dev, "error reading chip-id register: %d\n", ret); 1999 return ret; 2000 } 2001 2002 if (val != OV08X40_CHIP_ID) { 2003 dev_err(ov08x->dev, "chip id mismatch: %x!=%x\n", 2004 OV08X40_CHIP_ID, val); 2005 return -ENXIO; 2006 } 2007 2008 dev_dbg(ov08x->dev, "chip id 0x%x\n", val); 2009 ov08x->identified = true; 2010 2011 return 0; 2012} 2013 2014static int ov08x40_set_stream(struct v4l2_subdev *sd, int enable) 2015{ 2016 struct ov08x40 *ov08x = to_ov08x40(sd); 2017 int ret = 0; 2018 2019 mutex_lock(&ov08x->mutex); 2020 2021 if (enable) { 2022 ret = pm_runtime_resume_and_get(ov08x->dev); 2023 if (ret < 0) 2024 goto err_unlock; 2025 2026 ret = ov08x40_identify_module(ov08x); 2027 if (ret) 2028 goto err_rpm_put; 2029 2030 /* 2031 * Apply default & customized values 2032 * and then start streaming. 2033 */ 2034 ret = ov08x40_start_streaming(ov08x); 2035 if (ret) 2036 goto err_rpm_put; 2037 } else { 2038 ov08x40_stop_streaming(ov08x); 2039 pm_runtime_put(ov08x->dev); 2040 } 2041 2042 mutex_unlock(&ov08x->mutex); 2043 2044 return ret; 2045 2046err_rpm_put: 2047 pm_runtime_put(ov08x->dev); 2048err_unlock: 2049 mutex_unlock(&ov08x->mutex); 2050 2051 return ret; 2052} 2053 2054static const struct v4l2_subdev_video_ops ov08x40_video_ops = { 2055 .s_stream = ov08x40_set_stream, 2056}; 2057 2058static const struct v4l2_subdev_pad_ops ov08x40_pad_ops = { 2059 .enum_mbus_code = ov08x40_enum_mbus_code, 2060 .get_fmt = ov08x40_get_pad_format, 2061 .set_fmt = ov08x40_set_pad_format, 2062 .enum_frame_size = ov08x40_enum_frame_size, 2063}; 2064 2065static const struct v4l2_subdev_ops ov08x40_subdev_ops = { 2066 .video = &ov08x40_video_ops, 2067 .pad = &ov08x40_pad_ops, 2068}; 2069 2070static const struct media_entity_operations ov08x40_subdev_entity_ops = { 2071 .link_validate = v4l2_subdev_link_validate, 2072}; 2073 2074static const struct v4l2_subdev_internal_ops ov08x40_internal_ops = { 2075 .open = ov08x40_open, 2076}; 2077 2078static int ov08x40_init_controls(struct ov08x40 *ov08x) 2079{ 2080 struct v4l2_fwnode_device_properties props; 2081 struct v4l2_ctrl_handler *ctrl_hdlr; 2082 s64 exposure_max; 2083 s64 vblank_def; 2084 s64 vblank_min; 2085 s64 hblank; 2086 s64 pixel_rate_min; 2087 s64 pixel_rate_max; 2088 const struct ov08x40_mode *mode; 2089 int ret; 2090 2091 ctrl_hdlr = &ov08x->ctrl_handler; 2092 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10); 2093 if (ret) 2094 return ret; 2095 2096 mutex_init(&ov08x->mutex); 2097 ctrl_hdlr->lock = &ov08x->mutex; 2098 ov08x->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, 2099 &ov08x40_ctrl_ops, 2100 V4L2_CID_LINK_FREQ, 2101 __fls(ov08x->link_freq_bitmap), 2102 __ffs(ov08x->link_freq_bitmap), 2103 link_freq_menu_items); 2104 if (ov08x->link_freq) 2105 ov08x->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 2106 2107 pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]); 2108 pixel_rate_min = 0; 2109 /* By default, PIXEL_RATE is read only */ 2110 ov08x->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, 2111 V4L2_CID_PIXEL_RATE, 2112 pixel_rate_min, pixel_rate_max, 2113 1, pixel_rate_max); 2114 2115 mode = ov08x->cur_mode; 2116 vblank_def = mode->vts_def - mode->height; 2117 vblank_min = mode->vts_min - mode->height; 2118 ov08x->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, 2119 V4L2_CID_VBLANK, 2120 vblank_min, 2121 OV08X40_VTS_MAX - mode->height, 1, 2122 vblank_def); 2123 2124 hblank = ov08x->cur_mode->llp - ov08x->cur_mode->width; 2125 2126 ov08x->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, 2127 V4L2_CID_HBLANK, 2128 hblank, hblank, 1, hblank); 2129 if (ov08x->hblank) 2130 ov08x->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 2131 2132 exposure_max = mode->vts_def - OV08X40_EXPOSURE_MAX_MARGIN; 2133 ov08x->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, 2134 V4L2_CID_EXPOSURE, 2135 OV08X40_EXPOSURE_MIN, 2136 exposure_max, OV08X40_EXPOSURE_STEP, 2137 exposure_max); 2138 2139 v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 2140 OV08X40_ANA_GAIN_MIN, OV08X40_ANA_GAIN_MAX, 2141 OV08X40_ANA_GAIN_STEP, OV08X40_ANA_GAIN_DEFAULT); 2142 2143 /* Digital gain */ 2144 v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 2145 OV08X40_DGTL_GAIN_MIN, OV08X40_DGTL_GAIN_MAX, 2146 OV08X40_DGTL_GAIN_STEP, OV08X40_DGTL_GAIN_DEFAULT); 2147 2148 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov08x40_ctrl_ops, 2149 V4L2_CID_TEST_PATTERN, 2150 ARRAY_SIZE(ov08x40_test_pattern_menu) - 1, 2151 0, 0, ov08x40_test_pattern_menu); 2152 2153 v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, 2154 V4L2_CID_HFLIP, 0, 1, 1, 0); 2155 v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, 2156 V4L2_CID_VFLIP, 0, 1, 1, 0); 2157 2158 if (ctrl_hdlr->error) { 2159 ret = ctrl_hdlr->error; 2160 dev_err(ov08x->dev, "%s control init failed (%d)\n", 2161 __func__, ret); 2162 goto error; 2163 } 2164 2165 ret = v4l2_fwnode_device_parse(ov08x->dev, &props); 2166 if (ret) 2167 goto error; 2168 2169 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov08x40_ctrl_ops, 2170 &props); 2171 if (ret) 2172 goto error; 2173 2174 ov08x->sd.ctrl_handler = ctrl_hdlr; 2175 2176 return 0; 2177 2178error: 2179 v4l2_ctrl_handler_free(ctrl_hdlr); 2180 mutex_destroy(&ov08x->mutex); 2181 2182 return ret; 2183} 2184 2185static void ov08x40_free_controls(struct ov08x40 *ov08x) 2186{ 2187 v4l2_ctrl_handler_free(ov08x->sd.ctrl_handler); 2188 mutex_destroy(&ov08x->mutex); 2189} 2190 2191static int ov08x40_check_hwcfg(struct ov08x40 *ov08x) 2192{ 2193 struct v4l2_fwnode_endpoint bus_cfg = { 2194 .bus_type = V4L2_MBUS_CSI2_DPHY 2195 }; 2196 struct device *dev = ov08x->dev; 2197 struct fwnode_handle *ep; 2198 struct fwnode_handle *fwnode = dev_fwnode(dev); 2199 unsigned int i; 2200 int ret; 2201 u32 xvclk_rate; 2202 2203 /* 2204 * Sometimes the fwnode graph is initialized by the bridge driver. 2205 * Bridge drivers doing this also add sensor properties, wait for this. 2206 */ 2207 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 2208 if (!ep) 2209 return dev_err_probe(dev, -EPROBE_DEFER, 2210 "waiting for fwnode graph endpoint\n"); 2211 2212 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 2213 fwnode_handle_put(ep); 2214 if (ret) 2215 return dev_err_probe(dev, ret, "parsing endpoint failed\n"); 2216 2217 ov08x->reset_gpio = devm_gpiod_get_optional(dev, "reset", 2218 GPIOD_OUT_HIGH); 2219 if (IS_ERR(ov08x->reset_gpio)) { 2220 ret = dev_err_probe(dev, PTR_ERR(ov08x->reset_gpio), 2221 "getting reset GPIO\n"); 2222 goto out_err; 2223 } 2224 2225 for (i = 0; i < ARRAY_SIZE(ov08x40_supply_names); i++) 2226 ov08x->supplies[i].supply = ov08x40_supply_names[i]; 2227 2228 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ov08x40_supply_names), 2229 ov08x->supplies); 2230 if (ret) 2231 goto out_err; 2232 2233 ov08x->xvclk = devm_v4l2_sensor_clk_get(dev, NULL); 2234 if (IS_ERR(ov08x->xvclk)) { 2235 ret = dev_err_probe(dev, PTR_ERR(ov08x->xvclk), 2236 "getting xvclk\n"); 2237 goto out_err; 2238 } 2239 2240 xvclk_rate = clk_get_rate(ov08x->xvclk); 2241 if (xvclk_rate != OV08X40_XVCLK) { 2242 dev_err(dev, "external clock %d is not supported\n", 2243 xvclk_rate); 2244 ret = -EINVAL; 2245 goto out_err; 2246 } 2247 2248 switch (bus_cfg.bus.mipi_csi2.num_data_lanes) { 2249 case 2: 2250 case 4: 2251 ov08x->mipi_lanes = bus_cfg.bus.mipi_csi2.num_data_lanes; 2252 break; 2253 default: 2254 dev_err(dev, "number of CSI2 data lanes %d is not supported\n", 2255 bus_cfg.bus.mipi_csi2.num_data_lanes); 2256 ret = -EINVAL; 2257 goto out_err; 2258 } 2259 2260 if (!bus_cfg.nr_of_link_frequencies) { 2261 dev_err(dev, "no link frequencies defined\n"); 2262 ret = -EINVAL; 2263 goto out_err; 2264 } 2265 ret = v4l2_link_freq_to_bitmap(dev, bus_cfg.link_frequencies, 2266 bus_cfg.nr_of_link_frequencies, 2267 link_freq_menu_items, 2268 ARRAY_SIZE(link_freq_menu_items), 2269 &ov08x->link_freq_bitmap); 2270 2271out_err: 2272 v4l2_fwnode_endpoint_free(&bus_cfg); 2273 2274 return ret; 2275} 2276 2277static int ov08x40_probe(struct i2c_client *client) 2278{ struct ov08x40 *ov08x; 2279 int ret; 2280 bool full_power; 2281 2282 ov08x = devm_kzalloc(&client->dev, sizeof(*ov08x), GFP_KERNEL); 2283 if (!ov08x) 2284 return -ENOMEM; 2285 2286 ov08x->dev = &client->dev; 2287 2288 /* Check HW config */ 2289 ret = ov08x40_check_hwcfg(ov08x); 2290 if (ret) 2291 return ret; 2292 2293 /* Initialize subdev */ 2294 v4l2_i2c_subdev_init(&ov08x->sd, client, &ov08x40_subdev_ops); 2295 2296 full_power = acpi_dev_state_d0(ov08x->dev); 2297 if (full_power) { 2298 ret = ov08x40_power_on(ov08x->dev); 2299 if (ret) { 2300 dev_err(ov08x->dev, "failed to power on\n"); 2301 return ret; 2302 } 2303 2304 /* Check module identity */ 2305 ret = ov08x40_identify_module(ov08x); 2306 if (ret) 2307 goto probe_power_off; 2308 } 2309 2310 /* Set default mode to max resolution */ 2311 ov08x->cur_mode = &supported_modes[0]; 2312 2313 ret = ov08x40_init_controls(ov08x); 2314 if (ret) 2315 goto probe_power_off; 2316 2317 /* Initialize subdev */ 2318 ov08x->sd.internal_ops = &ov08x40_internal_ops; 2319 ov08x->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 2320 ov08x->sd.entity.ops = &ov08x40_subdev_entity_ops; 2321 ov08x->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 2322 2323 /* Initialize source pad */ 2324 ov08x->pad.flags = MEDIA_PAD_FL_SOURCE; 2325 ret = media_entity_pads_init(&ov08x->sd.entity, 1, &ov08x->pad); 2326 if (ret) { 2327 dev_err(ov08x->dev, "%s failed:%d\n", __func__, ret); 2328 goto error_handler_free; 2329 } 2330 2331 ret = v4l2_async_register_subdev_sensor(&ov08x->sd); 2332 if (ret < 0) 2333 goto error_media_entity; 2334 2335 if (full_power) 2336 pm_runtime_set_active(ov08x->dev); 2337 pm_runtime_enable(ov08x->dev); 2338 pm_runtime_idle(ov08x->dev); 2339 2340 return 0; 2341 2342error_media_entity: 2343 media_entity_cleanup(&ov08x->sd.entity); 2344 2345error_handler_free: 2346 ov08x40_free_controls(ov08x); 2347 2348probe_power_off: 2349 ov08x40_power_off(ov08x->dev); 2350 2351 return ret; 2352} 2353 2354static void ov08x40_remove(struct i2c_client *client) 2355{ 2356 struct v4l2_subdev *sd = i2c_get_clientdata(client); 2357 struct ov08x40 *ov08x = to_ov08x40(sd); 2358 2359 v4l2_async_unregister_subdev(sd); 2360 media_entity_cleanup(&sd->entity); 2361 ov08x40_free_controls(ov08x); 2362 2363 pm_runtime_disable(ov08x->dev); 2364 if (!pm_runtime_status_suspended(ov08x->dev)) 2365 ov08x40_power_off(ov08x->dev); 2366 pm_runtime_set_suspended(ov08x->dev); 2367} 2368 2369static DEFINE_RUNTIME_DEV_PM_OPS(ov08x40_pm_ops, ov08x40_power_off, 2370 ov08x40_power_on, NULL); 2371 2372#ifdef CONFIG_ACPI 2373static const struct acpi_device_id ov08x40_acpi_ids[] = { 2374 {"OVTI08F4"}, 2375 { /* sentinel */ } 2376}; 2377 2378MODULE_DEVICE_TABLE(acpi, ov08x40_acpi_ids); 2379#endif 2380 2381static const struct of_device_id ov08x40_of_match[] = { 2382 { .compatible = "ovti,ov08x40" }, 2383 { /* sentinel */ } 2384}; 2385MODULE_DEVICE_TABLE(of, ov08x40_of_match); 2386 2387static struct i2c_driver ov08x40_i2c_driver = { 2388 .driver = { 2389 .name = "ov08x40", 2390 .acpi_match_table = ACPI_PTR(ov08x40_acpi_ids), 2391 .of_match_table = ov08x40_of_match, 2392 .pm = pm_sleep_ptr(&ov08x40_pm_ops), 2393 }, 2394 .probe = ov08x40_probe, 2395 .remove = ov08x40_remove, 2396 .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE, 2397}; 2398 2399module_i2c_driver(ov08x40_i2c_driver); 2400 2401MODULE_AUTHOR("Jason Chen <jason.z.chen@intel.com>"); 2402MODULE_AUTHOR("Qingwu Zhang <qingwu.zhang@intel.com>"); 2403MODULE_AUTHOR("Shawn Tu"); 2404MODULE_DESCRIPTION("OmniVision OV08X40 sensor driver"); 2405MODULE_LICENSE("GPL");
~/
Read-only file preview.