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mt9v032.c
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linux-6.19.14/drivers/media/i2c/mt9v032.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Driver for MT9V022, MT9V024, MT9V032, and MT9V034 CMOS Image Sensors 4 * 5 * Copyright (C) 2010, Laurent Pinchart <laurent.pinchart@ideasonboard.com> 6 * 7 * Based on the MT9M001 driver, 8 * 9 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> 10 */ 11 12#include <linux/clk.h> 13#include <linux/delay.h> 14#include <linux/gpio/consumer.h> 15#include <linux/i2c.h> 16#include <linux/log2.h> 17#include <linux/mod_devicetable.h> 18#include <linux/module.h> 19#include <linux/mutex.h> 20#include <linux/of.h> 21#include <linux/of_graph.h> 22#include <linux/regmap.h> 23#include <linux/slab.h> 24#include <linux/v4l2-mediabus.h> 25#include <linux/videodev2.h> 26 27#include <media/v4l2-ctrls.h> 28#include <media/v4l2-device.h> 29#include <media/v4l2-fwnode.h> 30#include <media/v4l2-subdev.h> 31 32/* The first four rows are black rows. The active area spans 753x481 pixels. */ 33#define MT9V032_PIXEL_ARRAY_HEIGHT 485 34#define MT9V032_PIXEL_ARRAY_WIDTH 753 35 36#define MT9V032_SYSCLK_FREQ_DEF 26600000 37 38#define MT9V032_CHIP_VERSION 0x00 39#define MT9V032_CHIP_ID_REV1 0x1311 40#define MT9V032_CHIP_ID_REV3 0x1313 41#define MT9V034_CHIP_ID_REV1 0X1324 42#define MT9V032_COLUMN_START 0x01 43#define MT9V032_COLUMN_START_MIN 1 44#define MT9V032_COLUMN_START_DEF 1 45#define MT9V032_COLUMN_START_MAX 752 46#define MT9V032_ROW_START 0x02 47#define MT9V032_ROW_START_MIN 4 48#define MT9V032_ROW_START_DEF 5 49#define MT9V032_ROW_START_MAX 482 50#define MT9V032_WINDOW_HEIGHT 0x03 51#define MT9V032_WINDOW_HEIGHT_MIN 1 52#define MT9V032_WINDOW_HEIGHT_DEF 480 53#define MT9V032_WINDOW_HEIGHT_MAX 480 54#define MT9V032_WINDOW_WIDTH 0x04 55#define MT9V032_WINDOW_WIDTH_MIN 1 56#define MT9V032_WINDOW_WIDTH_DEF 752 57#define MT9V032_WINDOW_WIDTH_MAX 752 58#define MT9V032_HORIZONTAL_BLANKING 0x05 59#define MT9V032_HORIZONTAL_BLANKING_MIN 43 60#define MT9V034_HORIZONTAL_BLANKING_MIN 61 61#define MT9V032_HORIZONTAL_BLANKING_DEF 94 62#define MT9V032_HORIZONTAL_BLANKING_MAX 1023 63#define MT9V032_VERTICAL_BLANKING 0x06 64#define MT9V032_VERTICAL_BLANKING_MIN 4 65#define MT9V034_VERTICAL_BLANKING_MIN 2 66#define MT9V032_VERTICAL_BLANKING_DEF 45 67#define MT9V032_VERTICAL_BLANKING_MAX 3000 68#define MT9V034_VERTICAL_BLANKING_MAX 32288 69#define MT9V032_CHIP_CONTROL 0x07 70#define MT9V032_CHIP_CONTROL_MASTER_MODE (1 << 3) 71#define MT9V032_CHIP_CONTROL_DOUT_ENABLE (1 << 7) 72#define MT9V032_CHIP_CONTROL_SEQUENTIAL (1 << 8) 73#define MT9V032_SHUTTER_WIDTH1 0x08 74#define MT9V032_SHUTTER_WIDTH2 0x09 75#define MT9V032_SHUTTER_WIDTH_CONTROL 0x0a 76#define MT9V032_TOTAL_SHUTTER_WIDTH 0x0b 77#define MT9V032_TOTAL_SHUTTER_WIDTH_MIN 1 78#define MT9V034_TOTAL_SHUTTER_WIDTH_MIN 0 79#define MT9V032_TOTAL_SHUTTER_WIDTH_DEF 480 80#define MT9V032_TOTAL_SHUTTER_WIDTH_MAX 32767 81#define MT9V034_TOTAL_SHUTTER_WIDTH_MAX 32765 82#define MT9V032_RESET 0x0c 83#define MT9V032_READ_MODE 0x0d 84#define MT9V032_READ_MODE_ROW_BIN_MASK (3 << 0) 85#define MT9V032_READ_MODE_ROW_BIN_SHIFT 0 86#define MT9V032_READ_MODE_COLUMN_BIN_MASK (3 << 2) 87#define MT9V032_READ_MODE_COLUMN_BIN_SHIFT 2 88#define MT9V032_READ_MODE_ROW_FLIP (1 << 4) 89#define MT9V032_READ_MODE_COLUMN_FLIP (1 << 5) 90#define MT9V032_READ_MODE_DARK_COLUMNS (1 << 6) 91#define MT9V032_READ_MODE_DARK_ROWS (1 << 7) 92#define MT9V032_READ_MODE_RESERVED 0x0300 93#define MT9V032_PIXEL_OPERATION_MODE 0x0f 94#define MT9V034_PIXEL_OPERATION_MODE_HDR (1 << 0) 95#define MT9V034_PIXEL_OPERATION_MODE_COLOR (1 << 1) 96#define MT9V032_PIXEL_OPERATION_MODE_COLOR (1 << 2) 97#define MT9V032_PIXEL_OPERATION_MODE_HDR (1 << 6) 98#define MT9V032_ANALOG_GAIN 0x35 99#define MT9V032_ANALOG_GAIN_MIN 16 100#define MT9V032_ANALOG_GAIN_DEF 16 101#define MT9V032_ANALOG_GAIN_MAX 64 102#define MT9V032_MAX_ANALOG_GAIN 0x36 103#define MT9V032_MAX_ANALOG_GAIN_MAX 127 104#define MT9V032_FRAME_DARK_AVERAGE 0x42 105#define MT9V032_DARK_AVG_THRESH 0x46 106#define MT9V032_DARK_AVG_LOW_THRESH_MASK (255 << 0) 107#define MT9V032_DARK_AVG_LOW_THRESH_SHIFT 0 108#define MT9V032_DARK_AVG_HIGH_THRESH_MASK (255 << 8) 109#define MT9V032_DARK_AVG_HIGH_THRESH_SHIFT 8 110#define MT9V032_ROW_NOISE_CORR_CONTROL 0x70 111#define MT9V034_ROW_NOISE_CORR_ENABLE (1 << 0) 112#define MT9V034_ROW_NOISE_CORR_USE_BLK_AVG (1 << 1) 113#define MT9V032_ROW_NOISE_CORR_ENABLE (1 << 5) 114#define MT9V032_ROW_NOISE_CORR_USE_BLK_AVG (1 << 7) 115#define MT9V032_PIXEL_CLOCK 0x74 116#define MT9V034_PIXEL_CLOCK 0x72 117#define MT9V032_PIXEL_CLOCK_INV_LINE (1 << 0) 118#define MT9V032_PIXEL_CLOCK_INV_FRAME (1 << 1) 119#define MT9V032_PIXEL_CLOCK_XOR_LINE (1 << 2) 120#define MT9V032_PIXEL_CLOCK_CONT_LINE (1 << 3) 121#define MT9V032_PIXEL_CLOCK_INV_PXL_CLK (1 << 4) 122#define MT9V032_TEST_PATTERN 0x7f 123#define MT9V032_TEST_PATTERN_DATA_MASK (1023 << 0) 124#define MT9V032_TEST_PATTERN_DATA_SHIFT 0 125#define MT9V032_TEST_PATTERN_USE_DATA (1 << 10) 126#define MT9V032_TEST_PATTERN_GRAY_MASK (3 << 11) 127#define MT9V032_TEST_PATTERN_GRAY_NONE (0 << 11) 128#define MT9V032_TEST_PATTERN_GRAY_VERTICAL (1 << 11) 129#define MT9V032_TEST_PATTERN_GRAY_HORIZONTAL (2 << 11) 130#define MT9V032_TEST_PATTERN_GRAY_DIAGONAL (3 << 11) 131#define MT9V032_TEST_PATTERN_ENABLE (1 << 13) 132#define MT9V032_TEST_PATTERN_FLIP (1 << 14) 133#define MT9V032_AEGC_DESIRED_BIN 0xa5 134#define MT9V032_AEC_UPDATE_FREQUENCY 0xa6 135#define MT9V032_AEC_LPF 0xa8 136#define MT9V032_AGC_UPDATE_FREQUENCY 0xa9 137#define MT9V032_AGC_LPF 0xaa 138#define MT9V032_AEC_AGC_ENABLE 0xaf 139#define MT9V032_AEC_ENABLE (1 << 0) 140#define MT9V032_AGC_ENABLE (1 << 1) 141#define MT9V034_AEC_MAX_SHUTTER_WIDTH 0xad 142#define MT9V032_AEC_MAX_SHUTTER_WIDTH 0xbd 143#define MT9V032_THERMAL_INFO 0xc1 144 145enum mt9v032_model { 146 MT9V032_MODEL_V022_COLOR, /* MT9V022IX7ATC */ 147 MT9V032_MODEL_V022_MONO, /* MT9V022IX7ATM */ 148 MT9V032_MODEL_V024_COLOR, /* MT9V024IA7XTC */ 149 MT9V032_MODEL_V024_MONO, /* MT9V024IA7XTM */ 150 MT9V032_MODEL_V032_COLOR, /* MT9V032C12STM */ 151 MT9V032_MODEL_V032_MONO, /* MT9V032C12STC */ 152 MT9V032_MODEL_V034_COLOR, 153 MT9V032_MODEL_V034_MONO, 154}; 155 156struct mt9v032_model_version { 157 unsigned int version; 158 const char *name; 159}; 160 161struct mt9v032_model_data { 162 unsigned int min_row_time; 163 unsigned int min_hblank; 164 unsigned int min_vblank; 165 unsigned int max_vblank; 166 unsigned int min_shutter; 167 unsigned int max_shutter; 168 unsigned int pclk_reg; 169 unsigned int aec_max_shutter_reg; 170 const struct v4l2_ctrl_config * const aec_max_shutter_v4l2_ctrl; 171}; 172 173struct mt9v032_model_info { 174 const struct mt9v032_model_data *data; 175 bool color; 176}; 177 178static const struct mt9v032_model_version mt9v032_versions[] = { 179 { MT9V032_CHIP_ID_REV1, "MT9V022/MT9V032 rev1/2" }, 180 { MT9V032_CHIP_ID_REV3, "MT9V022/MT9V032 rev3" }, 181 { MT9V034_CHIP_ID_REV1, "MT9V024/MT9V034 rev1" }, 182}; 183 184struct mt9v032_platform_data { 185 unsigned int clk_pol:1; 186 187 const s64 *link_freqs; 188 s64 link_def_freq; 189}; 190 191struct mt9v032 { 192 struct device *dev; 193 194 struct v4l2_subdev subdev; 195 struct media_pad pad; 196 197 struct v4l2_mbus_framefmt format; 198 struct v4l2_rect crop; 199 unsigned int hratio; 200 unsigned int vratio; 201 202 struct v4l2_ctrl_handler ctrls; 203 struct { 204 struct v4l2_ctrl *link_freq; 205 struct v4l2_ctrl *pixel_rate; 206 }; 207 208 struct mutex power_lock; 209 int power_count; 210 211 struct regmap *regmap; 212 struct clk *clk; 213 struct gpio_desc *reset_gpio; 214 struct gpio_desc *standby_gpio; 215 216 struct mt9v032_platform_data pdata; 217 const struct mt9v032_model_info *model; 218 const struct mt9v032_model_version *version; 219 220 u32 sysclk; 221 u16 aec_agc; 222 u16 hblank; 223 struct { 224 struct v4l2_ctrl *test_pattern; 225 struct v4l2_ctrl *test_pattern_color; 226 }; 227}; 228 229static struct mt9v032 *to_mt9v032(struct v4l2_subdev *sd) 230{ 231 return container_of(sd, struct mt9v032, subdev); 232} 233 234static int 235mt9v032_update_aec_agc(struct mt9v032 *mt9v032, u16 which, int enable) 236{ 237 struct regmap *map = mt9v032->regmap; 238 u16 value = mt9v032->aec_agc; 239 int ret; 240 241 if (enable) 242 value |= which; 243 else 244 value &= ~which; 245 246 ret = regmap_write(map, MT9V032_AEC_AGC_ENABLE, value); 247 if (ret < 0) 248 return ret; 249 250 mt9v032->aec_agc = value; 251 return 0; 252} 253 254static int 255mt9v032_update_hblank(struct mt9v032 *mt9v032) 256{ 257 struct v4l2_rect *crop = &mt9v032->crop; 258 unsigned int min_hblank = mt9v032->model->data->min_hblank; 259 unsigned int hblank; 260 261 if (mt9v032->version->version == MT9V034_CHIP_ID_REV1) 262 min_hblank += (mt9v032->hratio - 1) * 10; 263 min_hblank = max_t(int, mt9v032->model->data->min_row_time - crop->width, 264 min_hblank); 265 hblank = max_t(unsigned int, mt9v032->hblank, min_hblank); 266 267 return regmap_write(mt9v032->regmap, MT9V032_HORIZONTAL_BLANKING, 268 hblank); 269} 270 271static int mt9v032_power_on(struct mt9v032 *mt9v032) 272{ 273 struct regmap *map = mt9v032->regmap; 274 int ret; 275 276 gpiod_set_value_cansleep(mt9v032->reset_gpio, 1); 277 278 ret = clk_set_rate(mt9v032->clk, mt9v032->sysclk); 279 if (ret < 0) 280 return ret; 281 282 /* System clock has to be enabled before releasing the reset */ 283 ret = clk_prepare_enable(mt9v032->clk); 284 if (ret) 285 return ret; 286 287 udelay(1); 288 289 if (mt9v032->reset_gpio) { 290 gpiod_set_value_cansleep(mt9v032->reset_gpio, 0); 291 292 /* After releasing reset we need to wait 10 clock cycles 293 * before accessing the sensor over I2C. As the minimum SYSCLK 294 * frequency is 13MHz, waiting 1µs will be enough in the worst 295 * case. 296 */ 297 udelay(1); 298 } 299 300 /* Reset the chip and stop data read out */ 301 ret = regmap_write(map, MT9V032_RESET, 1); 302 if (ret < 0) 303 goto err; 304 305 ret = regmap_write(map, MT9V032_RESET, 0); 306 if (ret < 0) 307 goto err; 308 309 ret = regmap_write(map, MT9V032_CHIP_CONTROL, 310 MT9V032_CHIP_CONTROL_MASTER_MODE); 311 if (ret < 0) 312 goto err; 313 314 return 0; 315 316err: 317 clk_disable_unprepare(mt9v032->clk); 318 return ret; 319} 320 321static void mt9v032_power_off(struct mt9v032 *mt9v032) 322{ 323 clk_disable_unprepare(mt9v032->clk); 324} 325 326static int __mt9v032_set_power(struct mt9v032 *mt9v032, bool on) 327{ 328 struct regmap *map = mt9v032->regmap; 329 int ret; 330 331 if (!on) { 332 mt9v032_power_off(mt9v032); 333 return 0; 334 } 335 336 ret = mt9v032_power_on(mt9v032); 337 if (ret < 0) 338 return ret; 339 340 /* Configure the pixel clock polarity */ 341 if (mt9v032->pdata.clk_pol) { 342 ret = regmap_write(map, mt9v032->model->data->pclk_reg, 343 MT9V032_PIXEL_CLOCK_INV_PXL_CLK); 344 if (ret < 0) 345 return ret; 346 } 347 348 /* Disable the noise correction algorithm and restore the controls. */ 349 ret = regmap_write(map, MT9V032_ROW_NOISE_CORR_CONTROL, 0); 350 if (ret < 0) 351 return ret; 352 353 return v4l2_ctrl_handler_setup(&mt9v032->ctrls); 354} 355 356/* ----------------------------------------------------------------------------- 357 * V4L2 subdev video operations 358 */ 359 360static struct v4l2_mbus_framefmt * 361__mt9v032_get_pad_format(struct mt9v032 *mt9v032, 362 struct v4l2_subdev_state *sd_state, 363 unsigned int pad, enum v4l2_subdev_format_whence which) 364{ 365 switch (which) { 366 case V4L2_SUBDEV_FORMAT_TRY: 367 return v4l2_subdev_state_get_format(sd_state, pad); 368 case V4L2_SUBDEV_FORMAT_ACTIVE: 369 return &mt9v032->format; 370 default: 371 return NULL; 372 } 373} 374 375static struct v4l2_rect * 376__mt9v032_get_pad_crop(struct mt9v032 *mt9v032, 377 struct v4l2_subdev_state *sd_state, 378 unsigned int pad, enum v4l2_subdev_format_whence which) 379{ 380 switch (which) { 381 case V4L2_SUBDEV_FORMAT_TRY: 382 return v4l2_subdev_state_get_crop(sd_state, pad); 383 case V4L2_SUBDEV_FORMAT_ACTIVE: 384 return &mt9v032->crop; 385 default: 386 return NULL; 387 } 388} 389 390static int mt9v032_s_stream(struct v4l2_subdev *subdev, int enable) 391{ 392 const u16 mode = MT9V032_CHIP_CONTROL_DOUT_ENABLE 393 | MT9V032_CHIP_CONTROL_SEQUENTIAL; 394 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 395 struct v4l2_rect *crop = &mt9v032->crop; 396 struct regmap *map = mt9v032->regmap; 397 unsigned int hbin; 398 unsigned int vbin; 399 int ret; 400 401 if (!enable) 402 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, 0); 403 404 /* Configure the window size and row/column bin */ 405 hbin = fls(mt9v032->hratio) - 1; 406 vbin = fls(mt9v032->vratio) - 1; 407 ret = regmap_update_bits(map, MT9V032_READ_MODE, 408 ~MT9V032_READ_MODE_RESERVED, 409 hbin << MT9V032_READ_MODE_COLUMN_BIN_SHIFT | 410 vbin << MT9V032_READ_MODE_ROW_BIN_SHIFT); 411 if (ret < 0) 412 return ret; 413 414 ret = regmap_write(map, MT9V032_COLUMN_START, crop->left); 415 if (ret < 0) 416 return ret; 417 418 ret = regmap_write(map, MT9V032_ROW_START, crop->top); 419 if (ret < 0) 420 return ret; 421 422 ret = regmap_write(map, MT9V032_WINDOW_WIDTH, crop->width); 423 if (ret < 0) 424 return ret; 425 426 ret = regmap_write(map, MT9V032_WINDOW_HEIGHT, crop->height); 427 if (ret < 0) 428 return ret; 429 430 ret = mt9v032_update_hblank(mt9v032); 431 if (ret < 0) 432 return ret; 433 434 /* Switch to master "normal" mode */ 435 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, mode); 436} 437 438static int mt9v032_enum_mbus_code(struct v4l2_subdev *subdev, 439 struct v4l2_subdev_state *sd_state, 440 struct v4l2_subdev_mbus_code_enum *code) 441{ 442 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 443 444 if (code->index > 0) 445 return -EINVAL; 446 447 code->code = mt9v032->format.code; 448 return 0; 449} 450 451static int mt9v032_enum_frame_size(struct v4l2_subdev *subdev, 452 struct v4l2_subdev_state *sd_state, 453 struct v4l2_subdev_frame_size_enum *fse) 454{ 455 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 456 457 if (fse->index >= 3) 458 return -EINVAL; 459 if (mt9v032->format.code != fse->code) 460 return -EINVAL; 461 462 fse->min_width = MT9V032_WINDOW_WIDTH_DEF / (1 << fse->index); 463 fse->max_width = fse->min_width; 464 fse->min_height = MT9V032_WINDOW_HEIGHT_DEF / (1 << fse->index); 465 fse->max_height = fse->min_height; 466 467 return 0; 468} 469 470static int mt9v032_get_format(struct v4l2_subdev *subdev, 471 struct v4l2_subdev_state *sd_state, 472 struct v4l2_subdev_format *format) 473{ 474 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 475 476 format->format = *__mt9v032_get_pad_format(mt9v032, sd_state, 477 format->pad, 478 format->which); 479 return 0; 480} 481 482static void mt9v032_configure_pixel_rate(struct mt9v032 *mt9v032) 483{ 484 int ret; 485 486 ret = v4l2_ctrl_s_ctrl_int64(mt9v032->pixel_rate, 487 mt9v032->sysclk / mt9v032->hratio); 488 if (ret < 0) 489 dev_warn(mt9v032->dev, "failed to set pixel rate (%d)\n", ret); 490} 491 492static unsigned int mt9v032_calc_ratio(unsigned int input, unsigned int output) 493{ 494 /* Compute the power-of-two binning factor closest to the input size to 495 * output size ratio. Given that the output size is bounded by input/4 496 * and input, a generic implementation would be an ineffective luxury. 497 */ 498 if (output * 3 > input * 2) 499 return 1; 500 if (output * 3 > input) 501 return 2; 502 return 4; 503} 504 505static int mt9v032_set_format(struct v4l2_subdev *subdev, 506 struct v4l2_subdev_state *sd_state, 507 struct v4l2_subdev_format *format) 508{ 509 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 510 struct v4l2_mbus_framefmt *__format; 511 struct v4l2_rect *__crop; 512 unsigned int width; 513 unsigned int height; 514 unsigned int hratio; 515 unsigned int vratio; 516 517 __crop = __mt9v032_get_pad_crop(mt9v032, sd_state, format->pad, 518 format->which); 519 520 /* Clamp the width and height to avoid dividing by zero. */ 521 width = clamp(ALIGN(format->format.width, 2), 522 max_t(unsigned int, __crop->width / 4, 523 MT9V032_WINDOW_WIDTH_MIN), 524 __crop->width); 525 height = clamp(ALIGN(format->format.height, 2), 526 max_t(unsigned int, __crop->height / 4, 527 MT9V032_WINDOW_HEIGHT_MIN), 528 __crop->height); 529 530 hratio = mt9v032_calc_ratio(__crop->width, width); 531 vratio = mt9v032_calc_ratio(__crop->height, height); 532 533 __format = __mt9v032_get_pad_format(mt9v032, sd_state, format->pad, 534 format->which); 535 __format->width = __crop->width / hratio; 536 __format->height = __crop->height / vratio; 537 538 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 539 mt9v032->hratio = hratio; 540 mt9v032->vratio = vratio; 541 mt9v032_configure_pixel_rate(mt9v032); 542 } 543 544 format->format = *__format; 545 546 return 0; 547} 548 549static int mt9v032_get_selection(struct v4l2_subdev *subdev, 550 struct v4l2_subdev_state *sd_state, 551 struct v4l2_subdev_selection *sel) 552{ 553 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 554 555 if (sel->target != V4L2_SEL_TGT_CROP) 556 return -EINVAL; 557 558 sel->r = *__mt9v032_get_pad_crop(mt9v032, sd_state, sel->pad, 559 sel->which); 560 return 0; 561} 562 563static int mt9v032_set_selection(struct v4l2_subdev *subdev, 564 struct v4l2_subdev_state *sd_state, 565 struct v4l2_subdev_selection *sel) 566{ 567 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 568 struct v4l2_mbus_framefmt *__format; 569 struct v4l2_rect *__crop; 570 struct v4l2_rect rect; 571 572 if (sel->target != V4L2_SEL_TGT_CROP) 573 return -EINVAL; 574 575 /* Clamp the crop rectangle boundaries and align them to a non multiple 576 * of 2 pixels to ensure a GRBG Bayer pattern. 577 */ 578 rect.left = clamp(ALIGN(sel->r.left + 1, 2) - 1, 579 MT9V032_COLUMN_START_MIN, 580 MT9V032_COLUMN_START_MAX); 581 rect.top = clamp(ALIGN(sel->r.top + 1, 2) - 1, 582 MT9V032_ROW_START_MIN, 583 MT9V032_ROW_START_MAX); 584 rect.width = clamp_t(unsigned int, ALIGN(sel->r.width, 2), 585 MT9V032_WINDOW_WIDTH_MIN, 586 MT9V032_WINDOW_WIDTH_MAX); 587 rect.height = clamp_t(unsigned int, ALIGN(sel->r.height, 2), 588 MT9V032_WINDOW_HEIGHT_MIN, 589 MT9V032_WINDOW_HEIGHT_MAX); 590 591 rect.width = min_t(unsigned int, 592 rect.width, MT9V032_PIXEL_ARRAY_WIDTH - rect.left); 593 rect.height = min_t(unsigned int, 594 rect.height, MT9V032_PIXEL_ARRAY_HEIGHT - rect.top); 595 596 __crop = __mt9v032_get_pad_crop(mt9v032, sd_state, sel->pad, 597 sel->which); 598 599 if (rect.width != __crop->width || rect.height != __crop->height) { 600 /* Reset the output image size if the crop rectangle size has 601 * been modified. 602 */ 603 __format = __mt9v032_get_pad_format(mt9v032, sd_state, 604 sel->pad, 605 sel->which); 606 __format->width = rect.width; 607 __format->height = rect.height; 608 if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 609 mt9v032->hratio = 1; 610 mt9v032->vratio = 1; 611 mt9v032_configure_pixel_rate(mt9v032); 612 } 613 } 614 615 *__crop = rect; 616 sel->r = rect; 617 618 return 0; 619} 620 621/* ----------------------------------------------------------------------------- 622 * V4L2 subdev control operations 623 */ 624 625#define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001) 626/* 627 * Value between 1 and 64 to set the desired bin. This is effectively a measure 628 * of how bright the image is supposed to be. Both AGC and AEC try to reach 629 * this. 630 */ 631#define V4L2_CID_AEGC_DESIRED_BIN (V4L2_CID_USER_BASE | 0x1002) 632/* 633 * LPF is the low pass filter capability of the chip. Both AEC and AGC have 634 * this setting. This limits the speed in which AGC/AEC adjust their settings. 635 * Possible values are 0-2. 0 means no LPF. For 1 and 2 this equation is used: 636 * 637 * if |(calculated new exp - current exp)| > (current exp / 4) 638 * next exp = calculated new exp 639 * else 640 * next exp = current exp + ((calculated new exp - current exp) / 2^LPF) 641 */ 642#define V4L2_CID_AEC_LPF (V4L2_CID_USER_BASE | 0x1003) 643#define V4L2_CID_AGC_LPF (V4L2_CID_USER_BASE | 0x1004) 644/* 645 * Value between 0 and 15. This is the number of frames being skipped before 646 * updating the auto exposure/gain. 647 */ 648#define V4L2_CID_AEC_UPDATE_INTERVAL (V4L2_CID_USER_BASE | 0x1005) 649#define V4L2_CID_AGC_UPDATE_INTERVAL (V4L2_CID_USER_BASE | 0x1006) 650/* 651 * Maximum shutter width used for AEC. 652 */ 653#define V4L2_CID_AEC_MAX_SHUTTER_WIDTH (V4L2_CID_USER_BASE | 0x1007) 654 655static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl) 656{ 657 struct mt9v032 *mt9v032 = 658 container_of(ctrl->handler, struct mt9v032, ctrls); 659 struct regmap *map = mt9v032->regmap; 660 u32 freq; 661 u16 data; 662 663 switch (ctrl->id) { 664 case V4L2_CID_AUTOGAIN: 665 return mt9v032_update_aec_agc(mt9v032, MT9V032_AGC_ENABLE, 666 ctrl->val); 667 668 case V4L2_CID_GAIN: 669 return regmap_write(map, MT9V032_ANALOG_GAIN, ctrl->val); 670 671 case V4L2_CID_EXPOSURE_AUTO: 672 return mt9v032_update_aec_agc(mt9v032, MT9V032_AEC_ENABLE, 673 !ctrl->val); 674 675 case V4L2_CID_EXPOSURE: 676 return regmap_write(map, MT9V032_TOTAL_SHUTTER_WIDTH, 677 ctrl->val); 678 679 case V4L2_CID_HBLANK: 680 mt9v032->hblank = ctrl->val; 681 return mt9v032_update_hblank(mt9v032); 682 683 case V4L2_CID_VBLANK: 684 return regmap_write(map, MT9V032_VERTICAL_BLANKING, 685 ctrl->val); 686 687 case V4L2_CID_PIXEL_RATE: 688 case V4L2_CID_LINK_FREQ: 689 if (mt9v032->link_freq == NULL) 690 break; 691 692 freq = mt9v032->pdata.link_freqs[mt9v032->link_freq->val]; 693 *mt9v032->pixel_rate->p_new.p_s64 = freq; 694 mt9v032->sysclk = freq; 695 break; 696 697 case V4L2_CID_TEST_PATTERN: 698 switch (mt9v032->test_pattern->val) { 699 case 0: 700 data = 0; 701 break; 702 case 1: 703 data = MT9V032_TEST_PATTERN_GRAY_VERTICAL 704 | MT9V032_TEST_PATTERN_ENABLE; 705 break; 706 case 2: 707 data = MT9V032_TEST_PATTERN_GRAY_HORIZONTAL 708 | MT9V032_TEST_PATTERN_ENABLE; 709 break; 710 case 3: 711 data = MT9V032_TEST_PATTERN_GRAY_DIAGONAL 712 | MT9V032_TEST_PATTERN_ENABLE; 713 break; 714 default: 715 data = (mt9v032->test_pattern_color->val << 716 MT9V032_TEST_PATTERN_DATA_SHIFT) 717 | MT9V032_TEST_PATTERN_USE_DATA 718 | MT9V032_TEST_PATTERN_ENABLE 719 | MT9V032_TEST_PATTERN_FLIP; 720 break; 721 } 722 return regmap_write(map, MT9V032_TEST_PATTERN, data); 723 724 case V4L2_CID_AEGC_DESIRED_BIN: 725 return regmap_write(map, MT9V032_AEGC_DESIRED_BIN, ctrl->val); 726 727 case V4L2_CID_AEC_LPF: 728 return regmap_write(map, MT9V032_AEC_LPF, ctrl->val); 729 730 case V4L2_CID_AGC_LPF: 731 return regmap_write(map, MT9V032_AGC_LPF, ctrl->val); 732 733 case V4L2_CID_AEC_UPDATE_INTERVAL: 734 return regmap_write(map, MT9V032_AEC_UPDATE_FREQUENCY, 735 ctrl->val); 736 737 case V4L2_CID_AGC_UPDATE_INTERVAL: 738 return regmap_write(map, MT9V032_AGC_UPDATE_FREQUENCY, 739 ctrl->val); 740 741 case V4L2_CID_AEC_MAX_SHUTTER_WIDTH: 742 return regmap_write(map, 743 mt9v032->model->data->aec_max_shutter_reg, 744 ctrl->val); 745 } 746 747 return 0; 748} 749 750static const struct v4l2_ctrl_ops mt9v032_ctrl_ops = { 751 .s_ctrl = mt9v032_s_ctrl, 752}; 753 754static const char * const mt9v032_test_pattern_menu[] = { 755 "Disabled", 756 "Gray Vertical Shade", 757 "Gray Horizontal Shade", 758 "Gray Diagonal Shade", 759 "Plain", 760}; 761 762static const struct v4l2_ctrl_config mt9v032_test_pattern_color = { 763 .ops = &mt9v032_ctrl_ops, 764 .id = V4L2_CID_TEST_PATTERN_COLOR, 765 .type = V4L2_CTRL_TYPE_INTEGER, 766 .name = "Test Pattern Color", 767 .min = 0, 768 .max = 1023, 769 .step = 1, 770 .def = 0, 771 .flags = 0, 772}; 773 774static const struct v4l2_ctrl_config mt9v032_aegc_controls[] = { 775 { 776 .ops = &mt9v032_ctrl_ops, 777 .id = V4L2_CID_AEGC_DESIRED_BIN, 778 .type = V4L2_CTRL_TYPE_INTEGER, 779 .name = "AEC/AGC Desired Bin", 780 .min = 1, 781 .max = 64, 782 .step = 1, 783 .def = 58, 784 .flags = 0, 785 }, { 786 .ops = &mt9v032_ctrl_ops, 787 .id = V4L2_CID_AEC_LPF, 788 .type = V4L2_CTRL_TYPE_INTEGER, 789 .name = "AEC Low Pass Filter", 790 .min = 0, 791 .max = 2, 792 .step = 1, 793 .def = 0, 794 .flags = 0, 795 }, { 796 .ops = &mt9v032_ctrl_ops, 797 .id = V4L2_CID_AGC_LPF, 798 .type = V4L2_CTRL_TYPE_INTEGER, 799 .name = "AGC Low Pass Filter", 800 .min = 0, 801 .max = 2, 802 .step = 1, 803 .def = 2, 804 .flags = 0, 805 }, { 806 .ops = &mt9v032_ctrl_ops, 807 .id = V4L2_CID_AEC_UPDATE_INTERVAL, 808 .type = V4L2_CTRL_TYPE_INTEGER, 809 .name = "AEC Update Interval", 810 .min = 0, 811 .max = 16, 812 .step = 1, 813 .def = 2, 814 .flags = 0, 815 }, { 816 .ops = &mt9v032_ctrl_ops, 817 .id = V4L2_CID_AGC_UPDATE_INTERVAL, 818 .type = V4L2_CTRL_TYPE_INTEGER, 819 .name = "AGC Update Interval", 820 .min = 0, 821 .max = 16, 822 .step = 1, 823 .def = 2, 824 .flags = 0, 825 } 826}; 827 828static const struct v4l2_ctrl_config mt9v032_aec_max_shutter_width = { 829 .ops = &mt9v032_ctrl_ops, 830 .id = V4L2_CID_AEC_MAX_SHUTTER_WIDTH, 831 .type = V4L2_CTRL_TYPE_INTEGER, 832 .name = "AEC Max Shutter Width", 833 .min = 1, 834 .max = 2047, 835 .step = 1, 836 .def = 480, 837 .flags = 0, 838}; 839 840static const struct v4l2_ctrl_config mt9v034_aec_max_shutter_width = { 841 .ops = &mt9v032_ctrl_ops, 842 .id = V4L2_CID_AEC_MAX_SHUTTER_WIDTH, 843 .type = V4L2_CTRL_TYPE_INTEGER, 844 .name = "AEC Max Shutter Width", 845 .min = 1, 846 .max = 32765, 847 .step = 1, 848 .def = 480, 849 .flags = 0, 850}; 851 852/* ----------------------------------------------------------------------------- 853 * V4L2 subdev core operations 854 */ 855 856static int mt9v032_set_power(struct v4l2_subdev *subdev, int on) 857{ 858 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 859 int ret = 0; 860 861 mutex_lock(&mt9v032->power_lock); 862 863 /* If the power count is modified from 0 to != 0 or from != 0 to 0, 864 * update the power state. 865 */ 866 if (mt9v032->power_count == !on) { 867 ret = __mt9v032_set_power(mt9v032, !!on); 868 if (ret < 0) 869 goto done; 870 } 871 872 /* Update the power count. */ 873 mt9v032->power_count += on ? 1 : -1; 874 WARN_ON(mt9v032->power_count < 0); 875 876done: 877 mutex_unlock(&mt9v032->power_lock); 878 return ret; 879} 880 881/* ----------------------------------------------------------------------------- 882 * V4L2 subdev internal operations 883 */ 884 885static int mt9v032_registered(struct v4l2_subdev *subdev) 886{ 887 struct i2c_client *client = v4l2_get_subdevdata(subdev); 888 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 889 unsigned int i; 890 u32 version; 891 int ret; 892 893 dev_info(mt9v032->dev, "Probing MT9V032 at address 0x%02x\n", 894 client->addr); 895 896 ret = mt9v032_power_on(mt9v032); 897 if (ret < 0) { 898 dev_err(mt9v032->dev, "MT9V032 power up failed\n"); 899 return ret; 900 } 901 902 /* Read and check the sensor version */ 903 ret = regmap_read(mt9v032->regmap, MT9V032_CHIP_VERSION, &version); 904 905 mt9v032_power_off(mt9v032); 906 907 if (ret < 0) { 908 dev_err(mt9v032->dev, "Failed reading chip version\n"); 909 return ret; 910 } 911 912 for (i = 0; i < ARRAY_SIZE(mt9v032_versions); ++i) { 913 if (mt9v032_versions[i].version == version) { 914 mt9v032->version = &mt9v032_versions[i]; 915 break; 916 } 917 } 918 919 if (mt9v032->version == NULL) { 920 dev_err(mt9v032->dev, "Unsupported chip version 0x%04x\n", 921 version); 922 return -ENODEV; 923 } 924 925 dev_info(mt9v032->dev, "%s detected at address 0x%02x\n", 926 mt9v032->version->name, client->addr); 927 928 mt9v032_configure_pixel_rate(mt9v032); 929 930 return ret; 931} 932 933static int mt9v032_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) 934{ 935 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 936 struct v4l2_mbus_framefmt *format; 937 struct v4l2_rect *crop; 938 939 crop = v4l2_subdev_state_get_crop(fh->state, 0); 940 crop->left = MT9V032_COLUMN_START_DEF; 941 crop->top = MT9V032_ROW_START_DEF; 942 crop->width = MT9V032_WINDOW_WIDTH_DEF; 943 crop->height = MT9V032_WINDOW_HEIGHT_DEF; 944 945 format = v4l2_subdev_state_get_format(fh->state, 0); 946 947 if (mt9v032->model->color) 948 format->code = MEDIA_BUS_FMT_SGRBG10_1X10; 949 else 950 format->code = MEDIA_BUS_FMT_Y10_1X10; 951 952 format->width = MT9V032_WINDOW_WIDTH_DEF; 953 format->height = MT9V032_WINDOW_HEIGHT_DEF; 954 format->field = V4L2_FIELD_NONE; 955 format->colorspace = V4L2_COLORSPACE_SRGB; 956 957 return mt9v032_set_power(subdev, 1); 958} 959 960static int mt9v032_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) 961{ 962 return mt9v032_set_power(subdev, 0); 963} 964 965static const struct v4l2_subdev_core_ops mt9v032_subdev_core_ops = { 966 .s_power = mt9v032_set_power, 967}; 968 969static const struct v4l2_subdev_video_ops mt9v032_subdev_video_ops = { 970 .s_stream = mt9v032_s_stream, 971}; 972 973static const struct v4l2_subdev_pad_ops mt9v032_subdev_pad_ops = { 974 .enum_mbus_code = mt9v032_enum_mbus_code, 975 .enum_frame_size = mt9v032_enum_frame_size, 976 .get_fmt = mt9v032_get_format, 977 .set_fmt = mt9v032_set_format, 978 .get_selection = mt9v032_get_selection, 979 .set_selection = mt9v032_set_selection, 980}; 981 982static const struct v4l2_subdev_ops mt9v032_subdev_ops = { 983 .core = &mt9v032_subdev_core_ops, 984 .video = &mt9v032_subdev_video_ops, 985 .pad = &mt9v032_subdev_pad_ops, 986}; 987 988static const struct v4l2_subdev_internal_ops mt9v032_subdev_internal_ops = { 989 .registered = mt9v032_registered, 990 .open = mt9v032_open, 991 .close = mt9v032_close, 992}; 993 994static const struct regmap_config mt9v032_regmap_config = { 995 .reg_bits = 8, 996 .val_bits = 16, 997 .max_register = 0xff, 998 .cache_type = REGCACHE_MAPLE, 999}; 1000 1001/* ----------------------------------------------------------------------------- 1002 * Driver initialization and probing 1003 */ 1004 1005static int mt9v032_get_pdata(struct mt9v032 *mt9v032) 1006{ 1007 struct mt9v032_platform_data *pdata = &mt9v032->pdata; 1008 struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 }; 1009 struct device_node *np __free(device_node) = NULL; 1010 struct property *prop; 1011 1012 np = of_graph_get_endpoint_by_regs(mt9v032->dev->of_node, 0, -1); 1013 if (!np) 1014 return -EINVAL; 1015 1016 if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint) < 0) 1017 return -EINVAL; 1018 1019 prop = of_find_property(np, "link-frequencies", NULL); 1020 if (prop) { 1021 u64 *link_freqs; 1022 size_t size = prop->length / sizeof(*link_freqs); 1023 1024 link_freqs = devm_kcalloc(mt9v032->dev, size, 1025 sizeof(*link_freqs), GFP_KERNEL); 1026 if (!link_freqs) 1027 return -EINVAL; 1028 1029 if (of_property_read_u64_array(np, "link-frequencies", 1030 link_freqs, size) < 0) 1031 return -EINVAL; 1032 1033 pdata->link_freqs = link_freqs; 1034 pdata->link_def_freq = link_freqs[0]; 1035 } 1036 1037 pdata->clk_pol = !!(endpoint.bus.parallel.flags & 1038 V4L2_MBUS_PCLK_SAMPLE_RISING); 1039 1040 return 0; 1041} 1042 1043static int mt9v032_probe(struct i2c_client *client) 1044{ 1045 struct mt9v032 *mt9v032; 1046 unsigned int i; 1047 int ret; 1048 1049 mt9v032 = devm_kzalloc(&client->dev, sizeof(*mt9v032), GFP_KERNEL); 1050 if (!mt9v032) 1051 return -ENOMEM; 1052 1053 mt9v032->dev = &client->dev; 1054 1055 mt9v032->regmap = devm_regmap_init_i2c(client, &mt9v032_regmap_config); 1056 if (IS_ERR(mt9v032->regmap)) 1057 return PTR_ERR(mt9v032->regmap); 1058 1059 mt9v032->clk = devm_v4l2_sensor_clk_get(mt9v032->dev, NULL); 1060 if (IS_ERR(mt9v032->clk)) 1061 return dev_err_probe(mt9v032->dev, PTR_ERR(mt9v032->clk), 1062 "failed to get the clock\n"); 1063 1064 mt9v032->reset_gpio = devm_gpiod_get_optional(mt9v032->dev, "reset", 1065 GPIOD_OUT_HIGH); 1066 if (IS_ERR(mt9v032->reset_gpio)) 1067 return PTR_ERR(mt9v032->reset_gpio); 1068 1069 mt9v032->standby_gpio = devm_gpiod_get_optional(mt9v032->dev, "standby", 1070 GPIOD_OUT_LOW); 1071 if (IS_ERR(mt9v032->standby_gpio)) 1072 return PTR_ERR(mt9v032->standby_gpio); 1073 1074 mutex_init(&mt9v032->power_lock); 1075 1076 ret = mt9v032_get_pdata(mt9v032); 1077 if (ret) 1078 return dev_err_probe(mt9v032->dev, -EINVAL, 1079 "Failed to parse DT properties\n"); 1080 1081 mt9v032->model = device_get_match_data(mt9v032->dev); 1082 1083 v4l2_ctrl_handler_init(&mt9v032->ctrls, 11 + 1084 ARRAY_SIZE(mt9v032_aegc_controls)); 1085 1086 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1087 V4L2_CID_AUTOGAIN, 0, 1, 1, 1); 1088 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1089 V4L2_CID_GAIN, MT9V032_ANALOG_GAIN_MIN, 1090 MT9V032_ANALOG_GAIN_MAX, 1, MT9V032_ANALOG_GAIN_DEF); 1091 v4l2_ctrl_new_std_menu(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1092 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0, 1093 V4L2_EXPOSURE_AUTO); 1094 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1095 V4L2_CID_EXPOSURE, mt9v032->model->data->min_shutter, 1096 mt9v032->model->data->max_shutter, 1, 1097 MT9V032_TOTAL_SHUTTER_WIDTH_DEF); 1098 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1099 V4L2_CID_HBLANK, mt9v032->model->data->min_hblank, 1100 MT9V032_HORIZONTAL_BLANKING_MAX, 1, 1101 MT9V032_HORIZONTAL_BLANKING_DEF); 1102 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1103 V4L2_CID_VBLANK, mt9v032->model->data->min_vblank, 1104 mt9v032->model->data->max_vblank, 1, 1105 MT9V032_VERTICAL_BLANKING_DEF); 1106 mt9v032->test_pattern = v4l2_ctrl_new_std_menu_items(&mt9v032->ctrls, 1107 &mt9v032_ctrl_ops, V4L2_CID_TEST_PATTERN, 1108 ARRAY_SIZE(mt9v032_test_pattern_menu) - 1, 0, 0, 1109 mt9v032_test_pattern_menu); 1110 mt9v032->test_pattern_color = v4l2_ctrl_new_custom(&mt9v032->ctrls, 1111 &mt9v032_test_pattern_color, NULL); 1112 1113 v4l2_ctrl_new_custom(&mt9v032->ctrls, 1114 mt9v032->model->data->aec_max_shutter_v4l2_ctrl, 1115 NULL); 1116 for (i = 0; i < ARRAY_SIZE(mt9v032_aegc_controls); ++i) 1117 v4l2_ctrl_new_custom(&mt9v032->ctrls, &mt9v032_aegc_controls[i], 1118 NULL); 1119 1120 v4l2_ctrl_cluster(2, &mt9v032->test_pattern); 1121 1122 mt9v032->pixel_rate = 1123 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1124 V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1); 1125 1126 if (mt9v032->pdata.link_freqs) { 1127 const struct mt9v032_platform_data *pdata = &mt9v032->pdata; 1128 unsigned int def = 0; 1129 1130 for (i = 0; pdata->link_freqs[i]; ++i) { 1131 if (pdata->link_freqs[i] == pdata->link_def_freq) 1132 def = i; 1133 } 1134 1135 mt9v032->link_freq = 1136 v4l2_ctrl_new_int_menu(&mt9v032->ctrls, 1137 &mt9v032_ctrl_ops, 1138 V4L2_CID_LINK_FREQ, i - 1, def, 1139 pdata->link_freqs); 1140 v4l2_ctrl_cluster(2, &mt9v032->link_freq); 1141 } 1142 1143 1144 mt9v032->subdev.ctrl_handler = &mt9v032->ctrls; 1145 1146 if (mt9v032->ctrls.error) { 1147 dev_err(mt9v032->dev, "control initialization error %d\n", 1148 mt9v032->ctrls.error); 1149 ret = mt9v032->ctrls.error; 1150 goto err; 1151 } 1152 1153 mt9v032->crop.left = MT9V032_COLUMN_START_DEF; 1154 mt9v032->crop.top = MT9V032_ROW_START_DEF; 1155 mt9v032->crop.width = MT9V032_WINDOW_WIDTH_DEF; 1156 mt9v032->crop.height = MT9V032_WINDOW_HEIGHT_DEF; 1157 1158 if (mt9v032->model->color) 1159 mt9v032->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; 1160 else 1161 mt9v032->format.code = MEDIA_BUS_FMT_Y10_1X10; 1162 1163 mt9v032->format.width = MT9V032_WINDOW_WIDTH_DEF; 1164 mt9v032->format.height = MT9V032_WINDOW_HEIGHT_DEF; 1165 mt9v032->format.field = V4L2_FIELD_NONE; 1166 mt9v032->format.colorspace = V4L2_COLORSPACE_SRGB; 1167 1168 mt9v032->hratio = 1; 1169 mt9v032->vratio = 1; 1170 1171 mt9v032->aec_agc = MT9V032_AEC_ENABLE | MT9V032_AGC_ENABLE; 1172 mt9v032->hblank = MT9V032_HORIZONTAL_BLANKING_DEF; 1173 mt9v032->sysclk = MT9V032_SYSCLK_FREQ_DEF; 1174 1175 v4l2_i2c_subdev_init(&mt9v032->subdev, client, &mt9v032_subdev_ops); 1176 mt9v032->subdev.internal_ops = &mt9v032_subdev_internal_ops; 1177 mt9v032->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1178 1179 mt9v032->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1180 mt9v032->pad.flags = MEDIA_PAD_FL_SOURCE; 1181 ret = media_entity_pads_init(&mt9v032->subdev.entity, 1, &mt9v032->pad); 1182 if (ret < 0) 1183 goto err; 1184 1185 mt9v032->subdev.dev = mt9v032->dev; 1186 ret = v4l2_async_register_subdev(&mt9v032->subdev); 1187 if (ret < 0) 1188 goto err; 1189 1190 return 0; 1191 1192err: 1193 media_entity_cleanup(&mt9v032->subdev.entity); 1194 v4l2_ctrl_handler_free(&mt9v032->ctrls); 1195 return ret; 1196} 1197 1198static void mt9v032_remove(struct i2c_client *client) 1199{ 1200 struct v4l2_subdev *subdev = i2c_get_clientdata(client); 1201 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 1202 1203 v4l2_async_unregister_subdev(subdev); 1204 v4l2_ctrl_handler_free(&mt9v032->ctrls); 1205 media_entity_cleanup(&subdev->entity); 1206} 1207 1208static const struct mt9v032_model_data mt9v032_model_data[] = { 1209 { 1210 /* MT9V022, MT9V032 revisions 1/2/3 */ 1211 .min_row_time = 660, 1212 .min_hblank = MT9V032_HORIZONTAL_BLANKING_MIN, 1213 .min_vblank = MT9V032_VERTICAL_BLANKING_MIN, 1214 .max_vblank = MT9V032_VERTICAL_BLANKING_MAX, 1215 .min_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MIN, 1216 .max_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MAX, 1217 .pclk_reg = MT9V032_PIXEL_CLOCK, 1218 .aec_max_shutter_reg = MT9V032_AEC_MAX_SHUTTER_WIDTH, 1219 .aec_max_shutter_v4l2_ctrl = &mt9v032_aec_max_shutter_width, 1220 }, { 1221 /* MT9V024, MT9V034 */ 1222 .min_row_time = 690, 1223 .min_hblank = MT9V034_HORIZONTAL_BLANKING_MIN, 1224 .min_vblank = MT9V034_VERTICAL_BLANKING_MIN, 1225 .max_vblank = MT9V034_VERTICAL_BLANKING_MAX, 1226 .min_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MIN, 1227 .max_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MAX, 1228 .pclk_reg = MT9V034_PIXEL_CLOCK, 1229 .aec_max_shutter_reg = MT9V034_AEC_MAX_SHUTTER_WIDTH, 1230 .aec_max_shutter_v4l2_ctrl = &mt9v034_aec_max_shutter_width, 1231 }, 1232}; 1233 1234static const struct mt9v032_model_info mt9v032_models[] = { 1235 [MT9V032_MODEL_V022_COLOR] = { 1236 .data = &mt9v032_model_data[0], 1237 .color = true, 1238 }, 1239 [MT9V032_MODEL_V022_MONO] = { 1240 .data = &mt9v032_model_data[0], 1241 .color = false, 1242 }, 1243 [MT9V032_MODEL_V024_COLOR] = { 1244 .data = &mt9v032_model_data[1], 1245 .color = true, 1246 }, 1247 [MT9V032_MODEL_V024_MONO] = { 1248 .data = &mt9v032_model_data[1], 1249 .color = false, 1250 }, 1251 [MT9V032_MODEL_V032_COLOR] = { 1252 .data = &mt9v032_model_data[0], 1253 .color = true, 1254 }, 1255 [MT9V032_MODEL_V032_MONO] = { 1256 .data = &mt9v032_model_data[0], 1257 .color = false, 1258 }, 1259 [MT9V032_MODEL_V034_COLOR] = { 1260 .data = &mt9v032_model_data[1], 1261 .color = true, 1262 }, 1263 [MT9V032_MODEL_V034_MONO] = { 1264 .data = &mt9v032_model_data[1], 1265 .color = false, 1266 }, 1267}; 1268 1269static const struct of_device_id mt9v032_of_match[] = { 1270 { .compatible = "aptina,mt9v022", .data = &mt9v032_models[MT9V032_MODEL_V022_COLOR] }, 1271 { .compatible = "aptina,mt9v022m", .data = &mt9v032_models[MT9V032_MODEL_V022_MONO] }, 1272 { .compatible = "aptina,mt9v024", .data = &mt9v032_models[MT9V032_MODEL_V024_COLOR] }, 1273 { .compatible = "aptina,mt9v024m", .data = &mt9v032_models[MT9V032_MODEL_V024_MONO] }, 1274 { .compatible = "aptina,mt9v032", .data = &mt9v032_models[MT9V032_MODEL_V032_COLOR] }, 1275 { .compatible = "aptina,mt9v032m", .data = &mt9v032_models[MT9V032_MODEL_V032_MONO] }, 1276 { .compatible = "aptina,mt9v034", .data = &mt9v032_models[MT9V032_MODEL_V034_COLOR] }, 1277 { .compatible = "aptina,mt9v034m", .data = &mt9v032_models[MT9V032_MODEL_V034_MONO] }, 1278 { /* Sentinel */ } 1279}; 1280MODULE_DEVICE_TABLE(of, mt9v032_of_match); 1281 1282static struct i2c_driver mt9v032_driver = { 1283 .driver = { 1284 .name = "mt9v032", 1285 .of_match_table = mt9v032_of_match, 1286 }, 1287 .probe = mt9v032_probe, 1288 .remove = mt9v032_remove, 1289}; 1290 1291module_i2c_driver(mt9v032_driver); 1292 1293MODULE_DESCRIPTION("Aptina MT9V032 Camera driver"); 1294MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); 1295MODULE_LICENSE("GPL");
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