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max96717.c
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linux-6.19.14/drivers/media/i2c/max96717.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Maxim GMSL2 Serializer Driver 4 * 5 * Copyright (C) 2024 Collabora Ltd. 6 */ 7 8#include <linux/bitfield.h> 9#include <linux/clk.h> 10#include <linux/clk-provider.h> 11#include <linux/delay.h> 12#include <linux/gpio/driver.h> 13#include <linux/i2c-mux.h> 14#include <linux/i2c.h> 15#include <linux/property.h> 16#include <linux/regmap.h> 17 18#include <media/v4l2-cci.h> 19#include <media/v4l2-ctrls.h> 20#include <media/v4l2-fwnode.h> 21#include <media/v4l2-subdev.h> 22 23#define MAX96717_DEVICE_ID 0xbf 24#define MAX96717F_DEVICE_ID 0xc8 25#define MAX96717_PORTS 2 26#define MAX96717_PAD_SINK 0 27#define MAX96717_PAD_SOURCE 1 28#define MAX96717_CSI_NLANES 4 29 30#define MAX96717_DEFAULT_CLKOUT_RATE 24000000UL 31 32/* DEV */ 33#define MAX96717_REG3 CCI_REG8(0x3) 34#define MAX96717_RCLKSEL GENMASK(1, 0) 35#define RCLKSEL_REF_PLL CCI_REG8(0x3) 36#define MAX96717_REG6 CCI_REG8(0x6) 37#define RCLKEN BIT(5) 38#define MAX96717_DEV_ID CCI_REG8(0xd) 39#define MAX96717_DEV_REV CCI_REG8(0xe) 40#define MAX96717_DEV_REV_MASK GENMASK(3, 0) 41 42/* VID_TX Z */ 43#define MAX96717_VIDEO_TX0 CCI_REG8(0x110) 44#define MAX96717_VIDEO_AUTO_BPP BIT(3) 45#define MAX96717_VIDEO_TX2 CCI_REG8(0x112) 46#define MAX96717_VIDEO_PCLKDET BIT(7) 47 48/* VTX_Z */ 49#define MAX96717_VTX0 CCI_REG8(0x24e) 50#define MAX96717_VTX1 CCI_REG8(0x24f) 51#define MAX96717_PATTERN_CLK_FREQ GENMASK(3, 1) 52#define MAX96717_VTX_VS_DLY CCI_REG24(0x250) 53#define MAX96717_VTX_VS_HIGH CCI_REG24(0x253) 54#define MAX96717_VTX_VS_LOW CCI_REG24(0x256) 55#define MAX96717_VTX_V2H CCI_REG24(0x259) 56#define MAX96717_VTX_HS_HIGH CCI_REG16(0x25c) 57#define MAX96717_VTX_HS_LOW CCI_REG16(0x25e) 58#define MAX96717_VTX_HS_CNT CCI_REG16(0x260) 59#define MAX96717_VTX_V2D CCI_REG24(0x262) 60#define MAX96717_VTX_DE_HIGH CCI_REG16(0x265) 61#define MAX96717_VTX_DE_LOW CCI_REG16(0x267) 62#define MAX96717_VTX_DE_CNT CCI_REG16(0x269) 63#define MAX96717_VTX29 CCI_REG8(0x26b) 64#define MAX96717_VTX_MODE GENMASK(1, 0) 65#define MAX96717_VTX_GRAD_INC CCI_REG8(0x26c) 66#define MAX96717_VTX_CHKB_COLOR_A CCI_REG24(0x26d) 67#define MAX96717_VTX_CHKB_COLOR_B CCI_REG24(0x270) 68#define MAX96717_VTX_CHKB_RPT_CNT_A CCI_REG8(0x273) 69#define MAX96717_VTX_CHKB_RPT_CNT_B CCI_REG8(0x274) 70#define MAX96717_VTX_CHKB_ALT CCI_REG8(0x275) 71 72/* GPIO */ 73#define MAX96717_NUM_GPIO 11 74#define MAX96717_GPIO_REG_A(gpio) CCI_REG8(0x2be + (gpio) * 3) 75#define MAX96717_GPIO_OUT BIT(4) 76#define MAX96717_GPIO_IN BIT(3) 77#define MAX96717_GPIO_RX_EN BIT(2) 78#define MAX96717_GPIO_TX_EN BIT(1) 79#define MAX96717_GPIO_OUT_DIS BIT(0) 80 81/* FRONTTOP */ 82/* MAX96717 only have CSI port 'B' */ 83#define MAX96717_FRONTOP0 CCI_REG8(0x308) 84#define MAX96717_START_PORT_B BIT(5) 85 86/* MIPI_RX */ 87#define MAX96717_MIPI_RX1 CCI_REG8(0x331) 88#define MAX96717_MIPI_LANES_CNT GENMASK(5, 4) 89#define MAX96717_MIPI_RX2 CCI_REG8(0x332) /* phy1 Lanes map */ 90#define MAX96717_PHY2_LANES_MAP GENMASK(7, 4) 91#define MAX96717_MIPI_RX3 CCI_REG8(0x333) /* phy2 Lanes map */ 92#define MAX96717_PHY1_LANES_MAP GENMASK(3, 0) 93#define MAX96717_MIPI_RX4 CCI_REG8(0x334) /* phy1 lane polarities */ 94#define MAX96717_PHY1_LANES_POL GENMASK(6, 4) 95#define MAX96717_MIPI_RX5 CCI_REG8(0x335) /* phy2 lane polarities */ 96#define MAX96717_PHY2_LANES_POL GENMASK(2, 0) 97 98/* MIPI_RX_EXT */ 99#define MAX96717_MIPI_RX_EXT11 CCI_REG8(0x383) 100#define MAX96717_TUN_MODE BIT(7) 101 102/* REF_VTG */ 103#define REF_VTG0 CCI_REG8(0x3f0) 104#define REFGEN_PREDEF_EN BIT(6) 105#define REFGEN_PREDEF_FREQ_MASK GENMASK(5, 4) 106#define REFGEN_PREDEF_FREQ_ALT BIT(3) 107#define REFGEN_RST BIT(1) 108#define REFGEN_EN BIT(0) 109 110/* MISC */ 111#define PIO_SLEW_1 CCI_REG8(0x570) 112 113enum max96717_vpg_mode { 114 MAX96717_VPG_DISABLED = 0, 115 MAX96717_VPG_CHECKERBOARD = 1, 116 MAX96717_VPG_GRADIENT = 2, 117}; 118 119struct max96717_priv { 120 struct i2c_client *client; 121 struct regmap *regmap; 122 struct i2c_mux_core *mux; 123 struct v4l2_mbus_config_mipi_csi2 mipi_csi2; 124 struct v4l2_subdev sd; 125 struct media_pad pads[MAX96717_PORTS]; 126 struct v4l2_ctrl_handler ctrl_handler; 127 struct v4l2_async_notifier notifier; 128 struct v4l2_subdev *source_sd; 129 u16 source_sd_pad; 130 u64 enabled_source_streams; 131 u8 pll_predef_index; 132 struct clk_hw clk_hw; 133 struct gpio_chip gpio_chip; 134 enum max96717_vpg_mode pattern; 135}; 136 137static inline struct max96717_priv *sd_to_max96717(struct v4l2_subdev *sd) 138{ 139 return container_of(sd, struct max96717_priv, sd); 140} 141 142static inline struct max96717_priv *clk_hw_to_max96717(struct clk_hw *hw) 143{ 144 return container_of(hw, struct max96717_priv, clk_hw); 145} 146 147static int max96717_i2c_mux_select(struct i2c_mux_core *mux, u32 chan) 148{ 149 return 0; 150} 151 152static int max96717_i2c_mux_init(struct max96717_priv *priv) 153{ 154 priv->mux = i2c_mux_alloc(priv->client->adapter, &priv->client->dev, 155 1, 0, I2C_MUX_LOCKED | I2C_MUX_GATE, 156 max96717_i2c_mux_select, NULL); 157 if (!priv->mux) 158 return -ENOMEM; 159 160 return i2c_mux_add_adapter(priv->mux, 0, 0); 161} 162 163static inline int max96717_start_csi(struct max96717_priv *priv, bool start) 164{ 165 return cci_update_bits(priv->regmap, MAX96717_FRONTOP0, 166 MAX96717_START_PORT_B, 167 start ? MAX96717_START_PORT_B : 0, NULL); 168} 169 170static int max96717_apply_patgen_timing(struct max96717_priv *priv, 171 struct v4l2_subdev_state *state) 172{ 173 struct v4l2_mbus_framefmt *fmt = 174 v4l2_subdev_state_get_format(state, MAX96717_PAD_SOURCE); 175 const u32 h_active = fmt->width; 176 const u32 h_fp = 88; 177 const u32 h_sw = 44; 178 const u32 h_bp = 148; 179 u32 h_tot; 180 const u32 v_active = fmt->height; 181 const u32 v_fp = 4; 182 const u32 v_sw = 5; 183 const u32 v_bp = 36; 184 u32 v_tot; 185 int ret = 0; 186 187 h_tot = h_active + h_fp + h_sw + h_bp; 188 v_tot = v_active + v_fp + v_sw + v_bp; 189 190 /* 75 Mhz pixel clock */ 191 cci_update_bits(priv->regmap, MAX96717_VTX1, 192 MAX96717_PATTERN_CLK_FREQ, 0xa, &ret); 193 194 dev_info(&priv->client->dev, "height: %d width: %d\n", fmt->height, 195 fmt->width); 196 197 cci_write(priv->regmap, MAX96717_VTX_VS_DLY, 0, &ret); 198 cci_write(priv->regmap, MAX96717_VTX_VS_HIGH, v_sw * h_tot, &ret); 199 cci_write(priv->regmap, MAX96717_VTX_VS_LOW, 200 (v_active + v_fp + v_bp) * h_tot, &ret); 201 cci_write(priv->regmap, MAX96717_VTX_HS_HIGH, h_sw, &ret); 202 cci_write(priv->regmap, MAX96717_VTX_HS_LOW, h_active + h_fp + h_bp, 203 &ret); 204 cci_write(priv->regmap, MAX96717_VTX_V2D, 205 h_tot * (v_sw + v_bp) + (h_sw + h_bp), &ret); 206 cci_write(priv->regmap, MAX96717_VTX_HS_CNT, v_tot, &ret); 207 cci_write(priv->regmap, MAX96717_VTX_DE_HIGH, h_active, &ret); 208 cci_write(priv->regmap, MAX96717_VTX_DE_LOW, h_fp + h_sw + h_bp, 209 &ret); 210 cci_write(priv->regmap, MAX96717_VTX_DE_CNT, v_active, &ret); 211 /* B G R */ 212 cci_write(priv->regmap, MAX96717_VTX_CHKB_COLOR_A, 0xfecc00, &ret); 213 /* B G R */ 214 cci_write(priv->regmap, MAX96717_VTX_CHKB_COLOR_B, 0x006aa7, &ret); 215 cci_write(priv->regmap, MAX96717_VTX_CHKB_RPT_CNT_A, 0x3c, &ret); 216 cci_write(priv->regmap, MAX96717_VTX_CHKB_RPT_CNT_B, 0x3c, &ret); 217 cci_write(priv->regmap, MAX96717_VTX_CHKB_ALT, 0x3c, &ret); 218 cci_write(priv->regmap, MAX96717_VTX_GRAD_INC, 0x10, &ret); 219 220 return ret; 221} 222 223static int max96717_apply_patgen(struct max96717_priv *priv, 224 struct v4l2_subdev_state *state) 225{ 226 unsigned int val; 227 int ret = 0; 228 229 if (priv->pattern) 230 ret = max96717_apply_patgen_timing(priv, state); 231 232 cci_write(priv->regmap, MAX96717_VTX0, priv->pattern ? 0xfb : 0, 233 &ret); 234 235 val = FIELD_PREP(MAX96717_VTX_MODE, priv->pattern); 236 cci_update_bits(priv->regmap, MAX96717_VTX29, MAX96717_VTX_MODE, 237 val, &ret); 238 return ret; 239} 240 241static int max96717_s_ctrl(struct v4l2_ctrl *ctrl) 242{ 243 struct max96717_priv *priv = 244 container_of(ctrl->handler, struct max96717_priv, ctrl_handler); 245 int ret; 246 247 switch (ctrl->id) { 248 case V4L2_CID_TEST_PATTERN: 249 if (priv->enabled_source_streams) 250 return -EBUSY; 251 priv->pattern = ctrl->val; 252 break; 253 default: 254 return -EINVAL; 255 } 256 257 /* Use bpp from bpp register */ 258 ret = cci_update_bits(priv->regmap, MAX96717_VIDEO_TX0, 259 MAX96717_VIDEO_AUTO_BPP, 260 priv->pattern ? 0 : MAX96717_VIDEO_AUTO_BPP, 261 NULL); 262 263 /* 264 * Pattern generator doesn't work with tunnel mode. 265 * Needs RGB color format and deserializer tunnel mode must be disabled. 266 */ 267 return cci_update_bits(priv->regmap, MAX96717_MIPI_RX_EXT11, 268 MAX96717_TUN_MODE, 269 priv->pattern ? 0 : MAX96717_TUN_MODE, &ret); 270} 271 272static const char * const max96717_test_pattern[] = { 273 "Disabled", 274 "Checkerboard", 275 "Gradient" 276}; 277 278static const struct v4l2_ctrl_ops max96717_ctrl_ops = { 279 .s_ctrl = max96717_s_ctrl, 280}; 281 282static int max96717_gpiochip_get(struct gpio_chip *gpiochip, 283 unsigned int offset) 284{ 285 struct max96717_priv *priv = gpiochip_get_data(gpiochip); 286 u64 val; 287 int ret; 288 289 ret = cci_read(priv->regmap, MAX96717_GPIO_REG_A(offset), 290 &val, NULL); 291 if (ret) 292 return ret; 293 294 if (val & MAX96717_GPIO_OUT_DIS) 295 return !!(val & MAX96717_GPIO_IN); 296 else 297 return !!(val & MAX96717_GPIO_OUT); 298} 299 300static int max96717_gpiochip_set(struct gpio_chip *gpiochip, 301 unsigned int offset, int value) 302{ 303 struct max96717_priv *priv = gpiochip_get_data(gpiochip); 304 305 return cci_update_bits(priv->regmap, MAX96717_GPIO_REG_A(offset), 306 MAX96717_GPIO_OUT, MAX96717_GPIO_OUT, NULL); 307} 308 309static int max96717_gpio_get_direction(struct gpio_chip *gpiochip, 310 unsigned int offset) 311{ 312 struct max96717_priv *priv = gpiochip_get_data(gpiochip); 313 u64 val; 314 int ret; 315 316 ret = cci_read(priv->regmap, MAX96717_GPIO_REG_A(offset), &val, NULL); 317 if (ret < 0) 318 return ret; 319 320 return !!(val & MAX96717_GPIO_OUT_DIS); 321} 322 323static int max96717_gpio_direction_out(struct gpio_chip *gpiochip, 324 unsigned int offset, int value) 325{ 326 struct max96717_priv *priv = gpiochip_get_data(gpiochip); 327 328 return cci_update_bits(priv->regmap, MAX96717_GPIO_REG_A(offset), 329 MAX96717_GPIO_OUT_DIS | MAX96717_GPIO_OUT, 330 value ? MAX96717_GPIO_OUT : 0, NULL); 331} 332 333static int max96717_gpio_direction_in(struct gpio_chip *gpiochip, 334 unsigned int offset) 335{ 336 struct max96717_priv *priv = gpiochip_get_data(gpiochip); 337 338 return cci_update_bits(priv->regmap, MAX96717_GPIO_REG_A(offset), 339 MAX96717_GPIO_OUT_DIS, MAX96717_GPIO_OUT_DIS, 340 NULL); 341} 342 343static int max96717_gpiochip_probe(struct max96717_priv *priv) 344{ 345 struct device *dev = &priv->client->dev; 346 struct gpio_chip *gc = &priv->gpio_chip; 347 int i, ret = 0; 348 349 gc->label = dev_name(dev); 350 gc->parent = dev; 351 gc->owner = THIS_MODULE; 352 gc->ngpio = MAX96717_NUM_GPIO; 353 gc->base = -1; 354 gc->can_sleep = true; 355 gc->get_direction = max96717_gpio_get_direction; 356 gc->direction_input = max96717_gpio_direction_in; 357 gc->direction_output = max96717_gpio_direction_out; 358 gc->set = max96717_gpiochip_set; 359 gc->get = max96717_gpiochip_get; 360 361 /* Disable GPIO forwarding */ 362 for (i = 0; i < gc->ngpio; i++) 363 cci_update_bits(priv->regmap, MAX96717_GPIO_REG_A(i), 364 MAX96717_GPIO_RX_EN | MAX96717_GPIO_TX_EN, 365 0, &ret); 366 367 if (ret) 368 return ret; 369 370 ret = devm_gpiochip_add_data(dev, gc, priv); 371 if (ret) { 372 dev_err(dev, "Unable to create gpio_chip\n"); 373 return ret; 374 } 375 376 return 0; 377} 378 379static int _max96717_set_routing(struct v4l2_subdev *sd, 380 struct v4l2_subdev_state *state, 381 struct v4l2_subdev_krouting *routing) 382{ 383 static const struct v4l2_mbus_framefmt format = { 384 .width = 1280, 385 .height = 1080, 386 .code = MEDIA_BUS_FMT_Y8_1X8, 387 .field = V4L2_FIELD_NONE, 388 }; 389 int ret; 390 391 ret = v4l2_subdev_routing_validate(sd, routing, 392 V4L2_SUBDEV_ROUTING_ONLY_1_TO_1); 393 if (ret) 394 return ret; 395 396 ret = v4l2_subdev_set_routing_with_fmt(sd, state, routing, &format); 397 if (ret) 398 return ret; 399 400 return 0; 401} 402 403static int max96717_set_routing(struct v4l2_subdev *sd, 404 struct v4l2_subdev_state *state, 405 enum v4l2_subdev_format_whence which, 406 struct v4l2_subdev_krouting *routing) 407{ 408 struct max96717_priv *priv = sd_to_max96717(sd); 409 410 if (which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->enabled_source_streams) 411 return -EBUSY; 412 413 return _max96717_set_routing(sd, state, routing); 414} 415 416static int max96717_set_fmt(struct v4l2_subdev *sd, 417 struct v4l2_subdev_state *state, 418 struct v4l2_subdev_format *format) 419{ 420 struct max96717_priv *priv = sd_to_max96717(sd); 421 struct v4l2_mbus_framefmt *fmt; 422 u64 stream_source_mask; 423 424 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE && 425 priv->enabled_source_streams) 426 return -EBUSY; 427 428 /* No transcoding, source and sink formats must match. */ 429 if (format->pad == MAX96717_PAD_SOURCE) 430 return v4l2_subdev_get_fmt(sd, state, format); 431 432 /* Set sink format */ 433 fmt = v4l2_subdev_state_get_format(state, format->pad, format->stream); 434 if (!fmt) 435 return -EINVAL; 436 437 *fmt = format->format; 438 439 /* Propagate to source format */ 440 fmt = v4l2_subdev_state_get_opposite_stream_format(state, format->pad, 441 format->stream); 442 if (!fmt) 443 return -EINVAL; 444 *fmt = format->format; 445 446 stream_source_mask = BIT(format->stream); 447 448 return v4l2_subdev_state_xlate_streams(state, MAX96717_PAD_SOURCE, 449 MAX96717_PAD_SINK, 450 &stream_source_mask); 451} 452 453static int max96717_init_state(struct v4l2_subdev *sd, 454 struct v4l2_subdev_state *state) 455{ 456 struct v4l2_subdev_route routes[] = { 457 { 458 .sink_pad = MAX96717_PAD_SINK, 459 .sink_stream = 0, 460 .source_pad = MAX96717_PAD_SOURCE, 461 .source_stream = 0, 462 .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE, 463 }, 464 }; 465 struct v4l2_subdev_krouting routing = { 466 .num_routes = ARRAY_SIZE(routes), 467 .routes = routes, 468 }; 469 470 return _max96717_set_routing(sd, state, &routing); 471} 472 473static bool max96717_pipe_pclkdet(struct max96717_priv *priv) 474{ 475 u64 val = 0; 476 477 cci_read(priv->regmap, MAX96717_VIDEO_TX2, &val, NULL); 478 479 return val & MAX96717_VIDEO_PCLKDET; 480} 481 482static int max96717_log_status(struct v4l2_subdev *sd) 483{ 484 struct max96717_priv *priv = sd_to_max96717(sd); 485 struct device *dev = &priv->client->dev; 486 487 dev_info(dev, "Serializer: max96717\n"); 488 dev_info(dev, "Pipe: pclkdet:%d\n", max96717_pipe_pclkdet(priv)); 489 490 return 0; 491} 492 493static int max96717_enable_streams(struct v4l2_subdev *sd, 494 struct v4l2_subdev_state *state, u32 pad, 495 u64 streams_mask) 496{ 497 struct max96717_priv *priv = sd_to_max96717(sd); 498 u64 sink_streams; 499 int ret; 500 501 if (!priv->enabled_source_streams) 502 max96717_start_csi(priv, true); 503 504 ret = max96717_apply_patgen(priv, state); 505 if (ret) 506 goto stop_csi; 507 508 if (!priv->pattern) { 509 sink_streams = 510 v4l2_subdev_state_xlate_streams(state, 511 MAX96717_PAD_SOURCE, 512 MAX96717_PAD_SINK, 513 &streams_mask); 514 515 ret = v4l2_subdev_enable_streams(priv->source_sd, 516 priv->source_sd_pad, 517 sink_streams); 518 if (ret) 519 goto stop_csi; 520 } 521 522 priv->enabled_source_streams |= streams_mask; 523 524 return 0; 525 526stop_csi: 527 if (!priv->enabled_source_streams) 528 max96717_start_csi(priv, false); 529 530 return ret; 531} 532 533static int max96717_disable_streams(struct v4l2_subdev *sd, 534 struct v4l2_subdev_state *state, u32 pad, 535 u64 streams_mask) 536{ 537 struct max96717_priv *priv = sd_to_max96717(sd); 538 u64 sink_streams; 539 540 /* 541 * Stop the CSI receiver first then the source, 542 * otherwise the device may become unresponsive 543 * while holding the I2C bus low. 544 */ 545 priv->enabled_source_streams &= ~streams_mask; 546 if (!priv->enabled_source_streams) 547 max96717_start_csi(priv, false); 548 549 if (!priv->pattern) { 550 int ret; 551 552 sink_streams = 553 v4l2_subdev_state_xlate_streams(state, 554 MAX96717_PAD_SOURCE, 555 MAX96717_PAD_SINK, 556 &streams_mask); 557 558 ret = v4l2_subdev_disable_streams(priv->source_sd, 559 priv->source_sd_pad, 560 sink_streams); 561 if (ret) 562 return ret; 563 } 564 565 return 0; 566} 567 568static const struct v4l2_subdev_pad_ops max96717_pad_ops = { 569 .enable_streams = max96717_enable_streams, 570 .disable_streams = max96717_disable_streams, 571 .set_routing = max96717_set_routing, 572 .get_fmt = v4l2_subdev_get_fmt, 573 .set_fmt = max96717_set_fmt, 574}; 575 576static const struct v4l2_subdev_core_ops max96717_subdev_core_ops = { 577 .log_status = max96717_log_status, 578}; 579 580static const struct v4l2_subdev_internal_ops max96717_internal_ops = { 581 .init_state = max96717_init_state, 582}; 583 584static const struct v4l2_subdev_ops max96717_subdev_ops = { 585 .core = &max96717_subdev_core_ops, 586 .pad = &max96717_pad_ops, 587}; 588 589static const struct media_entity_operations max96717_entity_ops = { 590 .link_validate = v4l2_subdev_link_validate, 591}; 592 593static int max96717_notify_bound(struct v4l2_async_notifier *notifier, 594 struct v4l2_subdev *source_subdev, 595 struct v4l2_async_connection *asd) 596{ 597 struct max96717_priv *priv = sd_to_max96717(notifier->sd); 598 struct device *dev = &priv->client->dev; 599 int ret; 600 601 ret = media_entity_get_fwnode_pad(&source_subdev->entity, 602 source_subdev->fwnode, 603 MEDIA_PAD_FL_SOURCE); 604 if (ret < 0) { 605 dev_err(dev, "Failed to find pad for %s\n", 606 source_subdev->name); 607 return ret; 608 } 609 610 priv->source_sd = source_subdev; 611 priv->source_sd_pad = ret; 612 613 ret = media_create_pad_link(&source_subdev->entity, priv->source_sd_pad, 614 &priv->sd.entity, 0, 615 MEDIA_LNK_FL_ENABLED | 616 MEDIA_LNK_FL_IMMUTABLE); 617 if (ret) { 618 dev_err(dev, "Unable to link %s:%u -> %s:0\n", 619 source_subdev->name, priv->source_sd_pad, 620 priv->sd.name); 621 return ret; 622 } 623 624 return 0; 625} 626 627static const struct v4l2_async_notifier_operations max96717_notify_ops = { 628 .bound = max96717_notify_bound, 629}; 630 631static int max96717_v4l2_notifier_register(struct max96717_priv *priv) 632{ 633 struct device *dev = &priv->client->dev; 634 struct v4l2_async_connection *asd; 635 struct fwnode_handle *ep_fwnode; 636 int ret; 637 638 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 639 MAX96717_PAD_SINK, 0, 0); 640 if (!ep_fwnode) { 641 dev_err(dev, "No graph endpoint\n"); 642 return -ENODEV; 643 } 644 645 v4l2_async_subdev_nf_init(&priv->notifier, &priv->sd); 646 647 asd = v4l2_async_nf_add_fwnode_remote(&priv->notifier, ep_fwnode, 648 struct v4l2_async_connection); 649 650 fwnode_handle_put(ep_fwnode); 651 652 if (IS_ERR(asd)) { 653 dev_err(dev, "Failed to add subdev: %pe", asd); 654 v4l2_async_nf_cleanup(&priv->notifier); 655 return PTR_ERR(asd); 656 } 657 658 priv->notifier.ops = &max96717_notify_ops; 659 660 ret = v4l2_async_nf_register(&priv->notifier); 661 if (ret) { 662 dev_err(dev, "Failed to register subdev_notifier"); 663 v4l2_async_nf_cleanup(&priv->notifier); 664 return ret; 665 } 666 667 return 0; 668} 669 670static int max96717_subdev_init(struct max96717_priv *priv) 671{ 672 struct device *dev = &priv->client->dev; 673 int ret; 674 675 v4l2_i2c_subdev_init(&priv->sd, priv->client, &max96717_subdev_ops); 676 priv->sd.internal_ops = &max96717_internal_ops; 677 678 v4l2_ctrl_handler_init(&priv->ctrl_handler, 1); 679 priv->sd.ctrl_handler = &priv->ctrl_handler; 680 681 v4l2_ctrl_new_std_menu_items(&priv->ctrl_handler, 682 &max96717_ctrl_ops, 683 V4L2_CID_TEST_PATTERN, 684 ARRAY_SIZE(max96717_test_pattern) - 1, 685 0, 0, max96717_test_pattern); 686 if (priv->ctrl_handler.error) { 687 ret = priv->ctrl_handler.error; 688 goto err_free_ctrl; 689 } 690 691 priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_STREAMS; 692 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 693 priv->sd.entity.ops = &max96717_entity_ops; 694 695 priv->pads[MAX96717_PAD_SINK].flags = MEDIA_PAD_FL_SINK; 696 priv->pads[MAX96717_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; 697 698 ret = media_entity_pads_init(&priv->sd.entity, 2, priv->pads); 699 if (ret) { 700 dev_err_probe(dev, ret, "Failed to init pads\n"); 701 goto err_free_ctrl; 702 } 703 704 ret = v4l2_subdev_init_finalize(&priv->sd); 705 if (ret) { 706 dev_err_probe(dev, ret, 707 "v4l2 subdev init finalized failed\n"); 708 goto err_entity_cleanup; 709 } 710 ret = max96717_v4l2_notifier_register(priv); 711 if (ret) { 712 dev_err_probe(dev, ret, 713 "v4l2 subdev notifier register failed\n"); 714 goto err_free_state; 715 } 716 717 ret = v4l2_async_register_subdev(&priv->sd); 718 if (ret) { 719 dev_err_probe(dev, ret, "v4l2_async_register_subdev error\n"); 720 goto err_unreg_notif; 721 } 722 723 return 0; 724 725err_unreg_notif: 726 v4l2_async_nf_unregister(&priv->notifier); 727 v4l2_async_nf_cleanup(&priv->notifier); 728err_free_state: 729 v4l2_subdev_cleanup(&priv->sd); 730err_entity_cleanup: 731 media_entity_cleanup(&priv->sd.entity); 732err_free_ctrl: 733 v4l2_ctrl_handler_free(&priv->ctrl_handler); 734 735 return ret; 736} 737 738static void max96717_subdev_uninit(struct max96717_priv *priv) 739{ 740 v4l2_async_unregister_subdev(&priv->sd); 741 v4l2_async_nf_unregister(&priv->notifier); 742 v4l2_async_nf_cleanup(&priv->notifier); 743 v4l2_subdev_cleanup(&priv->sd); 744 media_entity_cleanup(&priv->sd.entity); 745 v4l2_ctrl_handler_free(&priv->ctrl_handler); 746} 747 748struct max96717_pll_predef_freq { 749 unsigned long freq; 750 bool is_alt; 751 u8 val; 752}; 753 754static const struct max96717_pll_predef_freq max96717_predef_freqs[] = { 755 { 13500000, true, 0 }, { 19200000, false, 0 }, 756 { 24000000, true, 1 }, { 27000000, false, 1 }, 757 { 37125000, false, 2 }, { 74250000, false, 3 }, 758}; 759 760static unsigned long 761max96717_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 762{ 763 struct max96717_priv *priv = clk_hw_to_max96717(hw); 764 765 return max96717_predef_freqs[priv->pll_predef_index].freq; 766} 767 768static unsigned int max96717_clk_find_best_index(struct max96717_priv *priv, 769 unsigned long rate) 770{ 771 unsigned int i, idx = 0; 772 unsigned long diff_new, diff_old = U32_MAX; 773 774 for (i = 0; i < ARRAY_SIZE(max96717_predef_freqs); i++) { 775 diff_new = abs(rate - max96717_predef_freqs[i].freq); 776 if (diff_new < diff_old) { 777 diff_old = diff_new; 778 idx = i; 779 } 780 } 781 782 return idx; 783} 784 785static int max96717_clk_determine_rate(struct clk_hw *hw, 786 struct clk_rate_request *req) 787{ 788 struct max96717_priv *priv = clk_hw_to_max96717(hw); 789 struct device *dev = &priv->client->dev; 790 unsigned int idx; 791 792 idx = max96717_clk_find_best_index(priv, req->rate); 793 794 if (req->rate != max96717_predef_freqs[idx].freq) { 795 dev_warn(dev, "Request CLK freq:%lu, found CLK freq:%lu\n", 796 req->rate, max96717_predef_freqs[idx].freq); 797 } 798 799 req->rate = max96717_predef_freqs[idx].freq; 800 801 return 0; 802} 803 804static int max96717_clk_set_rate(struct clk_hw *hw, unsigned long rate, 805 unsigned long parent_rate) 806{ 807 struct max96717_priv *priv = clk_hw_to_max96717(hw); 808 unsigned int val, idx; 809 int ret = 0; 810 811 idx = max96717_clk_find_best_index(priv, rate); 812 813 val = FIELD_PREP(REFGEN_PREDEF_FREQ_MASK, 814 max96717_predef_freqs[idx].val); 815 816 if (max96717_predef_freqs[idx].is_alt) 817 val |= REFGEN_PREDEF_FREQ_ALT; 818 819 val |= REFGEN_RST | REFGEN_PREDEF_EN; 820 821 cci_write(priv->regmap, REF_VTG0, val, &ret); 822 cci_update_bits(priv->regmap, REF_VTG0, REFGEN_RST | REFGEN_EN, 823 REFGEN_EN, &ret); 824 if (ret) 825 return ret; 826 827 priv->pll_predef_index = idx; 828 829 return 0; 830} 831 832static int max96717_clk_prepare(struct clk_hw *hw) 833{ 834 struct max96717_priv *priv = clk_hw_to_max96717(hw); 835 836 return cci_update_bits(priv->regmap, MAX96717_REG6, RCLKEN, 837 RCLKEN, NULL); 838} 839 840static void max96717_clk_unprepare(struct clk_hw *hw) 841{ 842 struct max96717_priv *priv = clk_hw_to_max96717(hw); 843 844 cci_update_bits(priv->regmap, MAX96717_REG6, RCLKEN, 0, NULL); 845} 846 847static const struct clk_ops max96717_clk_ops = { 848 .prepare = max96717_clk_prepare, 849 .unprepare = max96717_clk_unprepare, 850 .set_rate = max96717_clk_set_rate, 851 .recalc_rate = max96717_clk_recalc_rate, 852 .determine_rate = max96717_clk_determine_rate, 853}; 854 855static int max96717_register_clkout(struct max96717_priv *priv) 856{ 857 struct device *dev = &priv->client->dev; 858 struct clk_init_data init = { .ops = &max96717_clk_ops }; 859 int ret; 860 861 init.name = kasprintf(GFP_KERNEL, "max96717.%s.clk_out", dev_name(dev)); 862 if (!init.name) 863 return -ENOMEM; 864 865 /* RCLKSEL Reference PLL output */ 866 ret = cci_update_bits(priv->regmap, MAX96717_REG3, MAX96717_RCLKSEL, 867 MAX96717_RCLKSEL, NULL); 868 /* MFP4 fastest slew rate */ 869 cci_update_bits(priv->regmap, PIO_SLEW_1, BIT(5) | BIT(4), 0, &ret); 870 if (ret) 871 goto free_init_name; 872 873 priv->clk_hw.init = &init; 874 875 /* Initialize to 24 MHz */ 876 ret = max96717_clk_set_rate(&priv->clk_hw, 877 MAX96717_DEFAULT_CLKOUT_RATE, 0); 878 if (ret < 0) 879 goto free_init_name; 880 881 ret = devm_clk_hw_register(dev, &priv->clk_hw); 882 kfree(init.name); 883 if (ret) 884 return dev_err_probe(dev, ret, "Cannot register clock HW\n"); 885 886 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 887 &priv->clk_hw); 888 if (ret) 889 return dev_err_probe(dev, ret, 890 "Cannot add OF clock provider\n"); 891 892 return 0; 893 894free_init_name: 895 kfree(init.name); 896 return ret; 897} 898 899static int max96717_init_csi_lanes(struct max96717_priv *priv) 900{ 901 struct v4l2_mbus_config_mipi_csi2 *mipi = &priv->mipi_csi2; 902 unsigned long lanes_used = 0; 903 unsigned int nlanes, lane, val = 0; 904 int ret; 905 906 nlanes = mipi->num_data_lanes; 907 908 ret = cci_update_bits(priv->regmap, MAX96717_MIPI_RX1, 909 MAX96717_MIPI_LANES_CNT, 910 FIELD_PREP(MAX96717_MIPI_LANES_CNT, 911 nlanes - 1), NULL); 912 913 /* lanes polarity */ 914 for (lane = 0; lane < nlanes + 1; lane++) { 915 if (!mipi->lane_polarities[lane]) 916 continue; 917 /* Clock lane */ 918 if (lane == 0) 919 val |= BIT(2); 920 else if (lane < 3) 921 val |= BIT(lane - 1); 922 else 923 val |= BIT(lane); 924 } 925 926 cci_update_bits(priv->regmap, MAX96717_MIPI_RX5, 927 MAX96717_PHY2_LANES_POL, 928 FIELD_PREP(MAX96717_PHY2_LANES_POL, val), &ret); 929 930 cci_update_bits(priv->regmap, MAX96717_MIPI_RX4, 931 MAX96717_PHY1_LANES_POL, 932 FIELD_PREP(MAX96717_PHY1_LANES_POL, 933 val >> 3), &ret); 934 /* lanes mapping */ 935 for (lane = 0, val = 0; lane < nlanes; lane++) { 936 val |= (mipi->data_lanes[lane] - 1) << (lane * 2); 937 lanes_used |= BIT(mipi->data_lanes[lane] - 1); 938 } 939 940 /* 941 * Unused lanes need to be mapped as well to not have 942 * the same lanes mapped twice. 943 */ 944 for (; lane < MAX96717_CSI_NLANES; lane++) { 945 unsigned int idx = find_first_zero_bit(&lanes_used, 946 MAX96717_CSI_NLANES); 947 948 val |= idx << (lane * 2); 949 lanes_used |= BIT(idx); 950 } 951 952 cci_update_bits(priv->regmap, MAX96717_MIPI_RX3, 953 MAX96717_PHY1_LANES_MAP, 954 FIELD_PREP(MAX96717_PHY1_LANES_MAP, val), &ret); 955 956 return cci_update_bits(priv->regmap, MAX96717_MIPI_RX2, 957 MAX96717_PHY2_LANES_MAP, 958 FIELD_PREP(MAX96717_PHY2_LANES_MAP, val >> 4), 959 &ret); 960} 961 962static int max96717_hw_init(struct max96717_priv *priv) 963{ 964 struct device *dev = &priv->client->dev; 965 u64 dev_id, val; 966 int ret; 967 968 ret = cci_read(priv->regmap, MAX96717_DEV_ID, &dev_id, NULL); 969 if (ret) 970 return dev_err_probe(dev, ret, 971 "Fail to read the device id\n"); 972 973 if (dev_id != MAX96717_DEVICE_ID && dev_id != MAX96717F_DEVICE_ID) 974 return dev_err_probe(dev, -EOPNOTSUPP, 975 "Unsupported device id got %x\n", (u8)dev_id); 976 977 ret = cci_read(priv->regmap, MAX96717_DEV_REV, &val, NULL); 978 if (ret) 979 return dev_err_probe(dev, ret, 980 "Fail to read device revision"); 981 982 dev_dbg(dev, "Found %x (rev %lx)\n", (u8)dev_id, 983 (u8)val & MAX96717_DEV_REV_MASK); 984 985 ret = cci_read(priv->regmap, MAX96717_MIPI_RX_EXT11, &val, NULL); 986 if (ret) 987 return dev_err_probe(dev, ret, 988 "Fail to read mipi rx extension"); 989 990 if (!(val & MAX96717_TUN_MODE)) 991 return dev_err_probe(dev, -EOPNOTSUPP, 992 "Only supporting tunnel mode"); 993 994 return max96717_init_csi_lanes(priv); 995} 996 997static int max96717_parse_dt(struct max96717_priv *priv) 998{ 999 struct device *dev = &priv->client->dev; 1000 struct v4l2_fwnode_endpoint vep = { .bus_type = V4L2_MBUS_CSI2_DPHY }; 1001 struct fwnode_handle *ep_fwnode; 1002 unsigned char num_data_lanes; 1003 int ret; 1004 1005 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 1006 MAX96717_PAD_SINK, 0, 0); 1007 if (!ep_fwnode) 1008 return dev_err_probe(dev, -ENOENT, "no endpoint found\n"); 1009 1010 ret = v4l2_fwnode_endpoint_parse(ep_fwnode, &vep); 1011 1012 fwnode_handle_put(ep_fwnode); 1013 1014 if (ret < 0) 1015 return dev_err_probe(dev, ret, "Failed to parse sink endpoint"); 1016 1017 num_data_lanes = vep.bus.mipi_csi2.num_data_lanes; 1018 if (num_data_lanes < 1 || num_data_lanes > MAX96717_CSI_NLANES) 1019 return dev_err_probe(dev, -EINVAL, 1020 "Invalid data lanes must be 1 to 4\n"); 1021 1022 priv->mipi_csi2 = vep.bus.mipi_csi2; 1023 1024 return 0; 1025} 1026 1027static int max96717_probe(struct i2c_client *client) 1028{ 1029 struct device *dev = &client->dev; 1030 struct max96717_priv *priv; 1031 int ret; 1032 1033 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1034 if (!priv) 1035 return -ENOMEM; 1036 1037 priv->client = client; 1038 priv->regmap = devm_cci_regmap_init_i2c(client, 16); 1039 if (IS_ERR(priv->regmap)) { 1040 ret = PTR_ERR(priv->regmap); 1041 return dev_err_probe(dev, ret, "Failed to init regmap\n"); 1042 } 1043 1044 ret = max96717_parse_dt(priv); 1045 if (ret) 1046 return dev_err_probe(dev, ret, "Failed to parse the dt\n"); 1047 1048 ret = max96717_hw_init(priv); 1049 if (ret) 1050 return dev_err_probe(dev, ret, 1051 "Failed to initialize the hardware\n"); 1052 1053 ret = max96717_gpiochip_probe(priv); 1054 if (ret) 1055 return dev_err_probe(&client->dev, ret, 1056 "Failed to init gpiochip\n"); 1057 1058 ret = max96717_register_clkout(priv); 1059 if (ret) 1060 return dev_err_probe(dev, ret, "Failed to register clkout\n"); 1061 1062 ret = max96717_subdev_init(priv); 1063 if (ret) 1064 return dev_err_probe(dev, ret, 1065 "Failed to initialize v4l2 subdev\n"); 1066 1067 ret = max96717_i2c_mux_init(priv); 1068 if (ret) { 1069 dev_err_probe(dev, ret, "failed to add remote i2c adapter\n"); 1070 max96717_subdev_uninit(priv); 1071 } 1072 1073 return ret; 1074} 1075 1076static void max96717_remove(struct i2c_client *client) 1077{ 1078 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1079 struct max96717_priv *priv = sd_to_max96717(sd); 1080 1081 max96717_subdev_uninit(priv); 1082 i2c_mux_del_adapters(priv->mux); 1083} 1084 1085static const struct of_device_id max96717_of_ids[] = { 1086 { .compatible = "maxim,max96717f" }, 1087 { } 1088}; 1089MODULE_DEVICE_TABLE(of, max96717_of_ids); 1090 1091static struct i2c_driver max96717_i2c_driver = { 1092 .driver = { 1093 .name = "max96717", 1094 .of_match_table = max96717_of_ids, 1095 }, 1096 .probe = max96717_probe, 1097 .remove = max96717_remove, 1098}; 1099 1100module_i2c_driver(max96717_i2c_driver); 1101 1102MODULE_DESCRIPTION("Maxim GMSL2 MAX96717 Serializer Driver"); 1103MODULE_AUTHOR("Julien Massot <julien.massot@collabora.com>"); 1104MODULE_LICENSE("GPL");
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