max9286.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Maxim MAX9286 GMSL Deserializer Driver
   4 *
   5 * Copyright (C) 2017-2019 Jacopo Mondi
   6 * Copyright (C) 2017-2019 Kieran Bingham
   7 * Copyright (C) 2017-2019 Laurent Pinchart
   8 * Copyright (C) 2017-2019 Niklas Söderlund
   9 * Copyright (C) 2016 Renesas Electronics Corporation
  10 * Copyright (C) 2015 Cogent Embedded, Inc.
  11 */
  12
  13#include <linux/delay.h>
  14#include <linux/device.h>
  15#include <linux/fwnode.h>
  16#include <linux/gpio/consumer.h>
  17#include <linux/gpio/driver.h>
  18#include <linux/gpio/machine.h>
  19#include <linux/i2c.h>
  20#include <linux/i2c-mux.h>
  21#include <linux/module.h>
  22#include <linux/of_graph.h>
  23#include <linux/regulator/consumer.h>
  24#include <linux/slab.h>
  25
  26#include <media/v4l2-async.h>
  27#include <media/v4l2-ctrls.h>
  28#include <media/v4l2-device.h>
  29#include <media/v4l2-fwnode.h>
  30#include <media/v4l2-subdev.h>
  31
  32/* Register 0x00 */
  33#define MAX9286_MSTLINKSEL_AUTO		(7 << 5)
  34#define MAX9286_MSTLINKSEL(n)		((n) << 5)
  35#define MAX9286_EN_VS_GEN		BIT(4)
  36#define MAX9286_LINKEN(n)		(1 << (n))
  37/* Register 0x01 */
  38#define MAX9286_FSYNCMODE_ECU		(3 << 6)
  39#define MAX9286_FSYNCMODE_EXT		(2 << 6)
  40#define MAX9286_FSYNCMODE_INT_OUT	(1 << 6)
  41#define MAX9286_FSYNCMODE_INT_HIZ	(0 << 6)
  42#define MAX9286_GPIEN			BIT(5)
  43#define MAX9286_ENLMO_RSTFSYNC		BIT(2)
  44#define MAX9286_FSYNCMETH_AUTO		(2 << 0)
  45#define MAX9286_FSYNCMETH_SEMI_AUTO	(1 << 0)
  46#define MAX9286_FSYNCMETH_MANUAL	(0 << 0)
  47#define MAX9286_REG_FSYNC_PERIOD_L	0x06
  48#define MAX9286_REG_FSYNC_PERIOD_M	0x07
  49#define MAX9286_REG_FSYNC_PERIOD_H	0x08
  50/* Register 0x0a */
  51#define MAX9286_FWDCCEN(n)		(1 << ((n) + 4))
  52#define MAX9286_REVCCEN(n)		(1 << (n))
  53/* Register 0x0c */
  54#define MAX9286_HVEN			BIT(7)
  55#define MAX9286_EDC_6BIT_HAMMING	(2 << 5)
  56#define MAX9286_EDC_6BIT_CRC		(1 << 5)
  57#define MAX9286_EDC_1BIT_PARITY		(0 << 5)
  58#define MAX9286_DESEL			BIT(4)
  59#define MAX9286_INVVS			BIT(3)
  60#define MAX9286_INVHS			BIT(2)
  61#define MAX9286_HVSRC_D0		(2 << 0)
  62#define MAX9286_HVSRC_D14		(1 << 0)
  63#define MAX9286_HVSRC_D18		(0 << 0)
  64/* Register 0x0f */
  65#define MAX9286_0X0F_RESERVED		BIT(3)
  66/* Register 0x12 */
  67#define MAX9286_CSILANECNT(n)		(((n) - 1) << 6)
  68#define MAX9286_CSIDBL			BIT(5)
  69#define MAX9286_DBL			BIT(4)
  70#define MAX9286_DATATYPE_USER_8BIT	(11 << 0)
  71#define MAX9286_DATATYPE_USER_YUV_12BIT	(10 << 0)
  72#define MAX9286_DATATYPE_USER_24BIT	(9 << 0)
  73#define MAX9286_DATATYPE_RAW14		(8 << 0)
  74#define MAX9286_DATATYPE_RAW12		(7 << 0)
  75#define MAX9286_DATATYPE_RAW10		(6 << 0)
  76#define MAX9286_DATATYPE_RAW8		(5 << 0)
  77#define MAX9286_DATATYPE_YUV422_10BIT	(4 << 0)
  78#define MAX9286_DATATYPE_YUV422_8BIT	(3 << 0)
  79#define MAX9286_DATATYPE_RGB555		(2 << 0)
  80#define MAX9286_DATATYPE_RGB565		(1 << 0)
  81#define MAX9286_DATATYPE_RGB888		(0 << 0)
  82/* Register 0x15 */
  83#define MAX9286_CSI_IMAGE_TYP		BIT(7)
  84#define MAX9286_VC(n)			((n) << 5)
  85#define MAX9286_VCTYPE			BIT(4)
  86#define MAX9286_CSIOUTEN		BIT(3)
  87#define MAX9286_SWP_ENDIAN		BIT(2)
  88#define MAX9286_EN_CCBSYB_CLK_STR	BIT(1)
  89#define MAX9286_EN_GPI_CCBSYB		BIT(0)
  90/* Register 0x1b */
  91#define MAX9286_SWITCHIN(n)		(1 << ((n) + 4))
  92#define MAX9286_ENEQ(n)			(1 << (n))
  93/* Register 0x1c */
  94#define MAX9286_HIGHIMM(n)		BIT((n) + 4)
  95#define MAX9286_I2CSEL			BIT(2)
  96#define MAX9286_HIBW			BIT(1)
  97#define MAX9286_BWS			BIT(0)
  98/* Register 0x27 */
  99#define MAX9286_LOCKED			BIT(7)
 100/* Register 0x31 */
 101#define MAX9286_FSYNC_LOCKED		BIT(6)
 102/* Register 0x34 */
 103#define MAX9286_I2CLOCACK		BIT(7)
 104#define MAX9286_I2CSLVSH_1046NS_469NS	(3 << 5)
 105#define MAX9286_I2CSLVSH_938NS_352NS	(2 << 5)
 106#define MAX9286_I2CSLVSH_469NS_234NS	(1 << 5)
 107#define MAX9286_I2CSLVSH_352NS_117NS	(0 << 5)
 108#define MAX9286_I2CMSTBT_837KBPS	(7 << 2)
 109#define MAX9286_I2CMSTBT_533KBPS	(6 << 2)
 110#define MAX9286_I2CMSTBT_339KBPS	(5 << 2)
 111#define MAX9286_I2CMSTBT_173KBPS	(4 << 2)
 112#define MAX9286_I2CMSTBT_105KBPS	(3 << 2)
 113#define MAX9286_I2CMSTBT_84KBPS		(2 << 2)
 114#define MAX9286_I2CMSTBT_28KBPS		(1 << 2)
 115#define MAX9286_I2CMSTBT_8KBPS		(0 << 2)
 116#define MAX9286_I2CSLVTO_NONE		(3 << 0)
 117#define MAX9286_I2CSLVTO_1024US		(2 << 0)
 118#define MAX9286_I2CSLVTO_256US		(1 << 0)
 119#define MAX9286_I2CSLVTO_64US		(0 << 0)
 120/* Register 0x3b */
 121#define MAX9286_REV_TRF(n)		((n) << 4)
 122#define MAX9286_REV_AMP(n)		((((n) - 30) / 10) << 1) /* in mV */
 123#define MAX9286_REV_AMP_X		BIT(0)
 124#define MAX9286_REV_AMP_HIGH		170
 125/* Register 0x3f */
 126#define MAX9286_EN_REV_CFG		BIT(6)
 127#define MAX9286_REV_FLEN(n)		((n) - 20)
 128/* Register 0x49 */
 129#define MAX9286_VIDEO_DETECT_MASK	0x0f
 130/* Register 0x69 */
 131#define MAX9286_LFLTBMONMASKED		BIT(7)
 132#define MAX9286_LOCKMONMASKED		BIT(6)
 133#define MAX9286_AUTOCOMBACKEN		BIT(5)
 134#define MAX9286_AUTOMASKEN		BIT(4)
 135#define MAX9286_MASKLINK(n)		((n) << 0)
 136
 137/*
 138 * The sink and source pads are created to match the OF graph port numbers so
 139 * that their indexes can be used interchangeably.
 140 */
 141#define MAX9286_NUM_GMSL		4
 142#define MAX9286_N_SINKS			4
 143#define MAX9286_N_PADS			5
 144#define MAX9286_SRC_PAD			4
 145
 146struct max9286_format_info {
 147	u32 code;
 148	u8 datatype;
 149};
 150
 151struct max9286_i2c_speed {
 152	u32 rate;
 153	u8 mstbt;
 154};
 155
 156struct max9286_source {
 157	struct v4l2_subdev *sd;
 158	struct fwnode_handle *fwnode;
 159	struct regulator *regulator;
 160};
 161
 162struct max9286_asd {
 163	struct v4l2_async_connection base;
 164	struct max9286_source *source;
 165};
 166
 167static inline struct max9286_asd *
 168to_max9286_asd(struct v4l2_async_connection *asd)
 169{
 170	return container_of(asd, struct max9286_asd, base);
 171}
 172
 173struct max9286_priv {
 174	struct i2c_client *client;
 175	struct gpio_desc *gpiod_pwdn;
 176	struct v4l2_subdev sd;
 177	struct media_pad pads[MAX9286_N_PADS];
 178	struct regulator *regulator;
 179
 180	struct gpio_chip gpio;
 181	u8 gpio_state;
 182
 183	struct i2c_mux_core *mux;
 184	unsigned int mux_channel;
 185	bool mux_open;
 186
 187	/* The initial reverse control channel amplitude. */
 188	u32 init_rev_chan_mv;
 189	u32 rev_chan_mv;
 190	u8 i2c_mstbt;
 191	u32 bus_width;
 192
 193	bool use_gpio_poc;
 194	u32 gpio_poc[2];
 195
 196	struct v4l2_ctrl_handler ctrls;
 197	struct v4l2_ctrl *pixelrate_ctrl;
 198	unsigned int pixelrate;
 199
 200	unsigned int nsources;
 201	unsigned int source_mask;
 202	unsigned int route_mask;
 203	unsigned int bound_sources;
 204	unsigned int csi2_data_lanes;
 205	struct max9286_source sources[MAX9286_NUM_GMSL];
 206	struct v4l2_async_notifier notifier;
 207};
 208
 209static struct max9286_source *next_source(struct max9286_priv *priv,
 210					  struct max9286_source *source)
 211{
 212	if (!source)
 213		source = &priv->sources[0];
 214	else
 215		source++;
 216
 217	for (; source < &priv->sources[MAX9286_NUM_GMSL]; source++) {
 218		if (source->fwnode)
 219			return source;
 220	}
 221
 222	return NULL;
 223}
 224
 225#define for_each_source(priv, source) \
 226	for ((source) = NULL; ((source) = next_source((priv), (source))); )
 227
 228#define to_index(priv, source) ((source) - &(priv)->sources[0])
 229
 230static inline struct max9286_priv *sd_to_max9286(struct v4l2_subdev *sd)
 231{
 232	return container_of(sd, struct max9286_priv, sd);
 233}
 234
 235static const struct max9286_format_info max9286_formats[] = {
 236	{
 237		.code = MEDIA_BUS_FMT_UYVY8_1X16,
 238		.datatype = MAX9286_DATATYPE_YUV422_8BIT,
 239	}, {
 240		.code = MEDIA_BUS_FMT_VYUY8_1X16,
 241		.datatype = MAX9286_DATATYPE_YUV422_8BIT,
 242	}, {
 243		.code = MEDIA_BUS_FMT_YUYV8_1X16,
 244		.datatype = MAX9286_DATATYPE_YUV422_8BIT,
 245	}, {
 246		.code = MEDIA_BUS_FMT_YVYU8_1X16,
 247		.datatype = MAX9286_DATATYPE_YUV422_8BIT,
 248	}, {
 249		.code = MEDIA_BUS_FMT_SBGGR12_1X12,
 250		.datatype = MAX9286_DATATYPE_RAW12,
 251	}, {
 252		.code = MEDIA_BUS_FMT_SGBRG12_1X12,
 253		.datatype = MAX9286_DATATYPE_RAW12,
 254	}, {
 255		.code = MEDIA_BUS_FMT_SGRBG12_1X12,
 256		.datatype = MAX9286_DATATYPE_RAW12,
 257	}, {
 258		.code = MEDIA_BUS_FMT_SRGGB12_1X12,
 259		.datatype = MAX9286_DATATYPE_RAW12,
 260	},
 261};
 262
 263static const struct max9286_i2c_speed max9286_i2c_speeds[] = {
 264	{ .rate =   8470, .mstbt = MAX9286_I2CMSTBT_8KBPS },
 265	{ .rate =  28300, .mstbt = MAX9286_I2CMSTBT_28KBPS },
 266	{ .rate =  84700, .mstbt = MAX9286_I2CMSTBT_84KBPS },
 267	{ .rate = 105000, .mstbt = MAX9286_I2CMSTBT_105KBPS },
 268	{ .rate = 173000, .mstbt = MAX9286_I2CMSTBT_173KBPS },
 269	{ .rate = 339000, .mstbt = MAX9286_I2CMSTBT_339KBPS },
 270	{ .rate = 533000, .mstbt = MAX9286_I2CMSTBT_533KBPS },
 271	{ .rate = 837000, .mstbt = MAX9286_I2CMSTBT_837KBPS },
 272};
 273
 274/* -----------------------------------------------------------------------------
 275 * I2C IO
 276 */
 277
 278static int max9286_read(struct max9286_priv *priv, u8 reg)
 279{
 280	int ret;
 281
 282	ret = i2c_smbus_read_byte_data(priv->client, reg);
 283	if (ret < 0)
 284		dev_err(&priv->client->dev,
 285			"%s: register 0x%02x read failed (%d)\n",
 286			__func__, reg, ret);
 287
 288	return ret;
 289}
 290
 291static int max9286_write(struct max9286_priv *priv, u8 reg, u8 val)
 292{
 293	int ret;
 294
 295	ret = i2c_smbus_write_byte_data(priv->client, reg, val);
 296	if (ret < 0)
 297		dev_err(&priv->client->dev,
 298			"%s: register 0x%02x write failed (%d)\n",
 299			__func__, reg, ret);
 300
 301	return ret;
 302}
 303
 304/* -----------------------------------------------------------------------------
 305 * I2C Multiplexer
 306 */
 307
 308static void max9286_i2c_mux_configure(struct max9286_priv *priv, u8 conf)
 309{
 310	max9286_write(priv, 0x0a, conf);
 311
 312	/*
 313	 * We must sleep after any change to the forward or reverse channel
 314	 * configuration.
 315	 */
 316	usleep_range(3000, 5000);
 317}
 318
 319static void max9286_i2c_mux_open(struct max9286_priv *priv)
 320{
 321	/* Open all channels on the MAX9286 */
 322	max9286_i2c_mux_configure(priv, 0xff);
 323
 324	priv->mux_open = true;
 325}
 326
 327static void max9286_i2c_mux_close(struct max9286_priv *priv)
 328{
 329	/*
 330	 * Ensure that both the forward and reverse channel are disabled on the
 331	 * mux, and that the channel ID is invalidated to ensure we reconfigure
 332	 * on the next max9286_i2c_mux_select() call.
 333	 */
 334	max9286_i2c_mux_configure(priv, 0x00);
 335
 336	priv->mux_open = false;
 337	priv->mux_channel = -1;
 338}
 339
 340static int max9286_i2c_mux_select(struct i2c_mux_core *muxc, u32 chan)
 341{
 342	struct max9286_priv *priv = i2c_mux_priv(muxc);
 343
 344	/* Channel select is disabled when configured in the opened state. */
 345	if (priv->mux_open)
 346		return 0;
 347
 348	if (priv->mux_channel == chan)
 349		return 0;
 350
 351	priv->mux_channel = chan;
 352
 353	max9286_i2c_mux_configure(priv, MAX9286_FWDCCEN(chan) |
 354					MAX9286_REVCCEN(chan));
 355
 356	return 0;
 357}
 358
 359static int max9286_i2c_mux_init(struct max9286_priv *priv)
 360{
 361	struct max9286_source *source;
 362	int ret;
 363
 364	if (!i2c_check_functionality(priv->client->adapter,
 365				     I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
 366		return -ENODEV;
 367
 368	priv->mux = i2c_mux_alloc(priv->client->adapter, &priv->client->dev,
 369				  priv->nsources, 0, I2C_MUX_LOCKED,
 370				  max9286_i2c_mux_select, NULL);
 371	if (!priv->mux)
 372		return -ENOMEM;
 373
 374	priv->mux->priv = priv;
 375
 376	for_each_source(priv, source) {
 377		unsigned int index = to_index(priv, source);
 378
 379		ret = i2c_mux_add_adapter(priv->mux, 0, index);
 380		if (ret < 0)
 381			goto error;
 382	}
 383
 384	return 0;
 385
 386error:
 387	i2c_mux_del_adapters(priv->mux);
 388	return ret;
 389}
 390
 391static void max9286_configure_i2c(struct max9286_priv *priv, bool localack)
 392{
 393	u8 config = MAX9286_I2CSLVSH_469NS_234NS | MAX9286_I2CSLVTO_1024US |
 394		    priv->i2c_mstbt;
 395
 396	if (localack)
 397		config |= MAX9286_I2CLOCACK;
 398
 399	max9286_write(priv, 0x34, config);
 400	usleep_range(3000, 5000);
 401}
 402
 403static void max9286_reverse_channel_setup(struct max9286_priv *priv,
 404					  unsigned int chan_amplitude)
 405{
 406	u8 chan_config;
 407
 408	if (priv->rev_chan_mv == chan_amplitude)
 409		return;
 410
 411	priv->rev_chan_mv = chan_amplitude;
 412
 413	/* Reverse channel transmission time: default to 1. */
 414	chan_config = MAX9286_REV_TRF(1);
 415
 416	/*
 417	 * Reverse channel setup.
 418	 *
 419	 * - Enable custom reverse channel configuration (through register 0x3f)
 420	 *   and set the first pulse length to 35 clock cycles.
 421	 * - Adjust reverse channel amplitude: values > 130 are programmed
 422	 *   using the additional +100mV REV_AMP_X boost flag
 423	 */
 424	max9286_write(priv, 0x3f, MAX9286_EN_REV_CFG | MAX9286_REV_FLEN(35));
 425
 426	if (chan_amplitude > 100) {
 427		/* It is not possible to express values (100 < x < 130) */
 428		chan_amplitude = max(30U, chan_amplitude - 100);
 429		chan_config |= MAX9286_REV_AMP_X;
 430	}
 431	max9286_write(priv, 0x3b, chan_config | MAX9286_REV_AMP(chan_amplitude));
 432	usleep_range(2000, 2500);
 433}
 434
 435/*
 436 * max9286_check_video_links() - Make sure video links are detected and locked
 437 *
 438 * Performs safety checks on video link status. Make sure they are detected
 439 * and all enabled links are locked.
 440 *
 441 * Returns 0 for success, -EIO for errors.
 442 */
 443static int max9286_check_video_links(struct max9286_priv *priv)
 444{
 445	unsigned int i;
 446	int ret;
 447
 448	/*
 449	 * Make sure valid video links are detected.
 450	 * The delay is not characterized in de-serializer manual, wait up
 451	 * to 5 ms.
 452	 */
 453	for (i = 0; i < 10; i++) {
 454		ret = max9286_read(priv, 0x49);
 455		if (ret < 0)
 456			return -EIO;
 457
 458		if ((ret & MAX9286_VIDEO_DETECT_MASK) == priv->source_mask)
 459			break;
 460
 461		usleep_range(350, 500);
 462	}
 463
 464	if (i == 10) {
 465		dev_err(&priv->client->dev,
 466			"Unable to detect video links: 0x%02x\n", ret);
 467		return -EIO;
 468	}
 469
 470	/* Make sure all enabled links are locked (4ms max). */
 471	for (i = 0; i < 10; i++) {
 472		ret = max9286_read(priv, 0x27);
 473		if (ret < 0)
 474			return -EIO;
 475
 476		if (ret & MAX9286_LOCKED)
 477			break;
 478
 479		usleep_range(350, 450);
 480	}
 481
 482	if (i == 10) {
 483		dev_err(&priv->client->dev, "Not all enabled links locked\n");
 484		return -EIO;
 485	}
 486
 487	return 0;
 488}
 489
 490/*
 491 * max9286_check_config_link() - Detect and wait for configuration links
 492 *
 493 * Determine if the configuration channel is up and settled for a link.
 494 *
 495 * Returns 0 for success, -EIO for errors.
 496 */
 497static int max9286_check_config_link(struct max9286_priv *priv,
 498				     unsigned int source_mask)
 499{
 500	unsigned int conflink_mask = (source_mask & 0x0f) << 4;
 501	unsigned int i;
 502	int ret;
 503
 504	/*
 505	 * Make sure requested configuration links are detected.
 506	 * The delay is not characterized in the chip manual: wait up
 507	 * to 5 milliseconds.
 508	 */
 509	for (i = 0; i < 10; i++) {
 510		ret = max9286_read(priv, 0x49);
 511		if (ret < 0)
 512			return -EIO;
 513
 514		ret &= 0xf0;
 515		if (ret == conflink_mask)
 516			break;
 517
 518		usleep_range(350, 500);
 519	}
 520
 521	if (ret != conflink_mask) {
 522		dev_err(&priv->client->dev,
 523			"Unable to detect configuration links: 0x%02x expected 0x%02x\n",
 524			ret, conflink_mask);
 525		return -EIO;
 526	}
 527
 528	dev_info(&priv->client->dev,
 529		 "Successfully detected configuration links after %u loops: 0x%02x\n",
 530		 i, conflink_mask);
 531
 532	return 0;
 533}
 534
 535static void max9286_set_video_format(struct max9286_priv *priv,
 536				     const struct v4l2_mbus_framefmt *format)
 537{
 538	const struct max9286_format_info *info = NULL;
 539	unsigned int i;
 540
 541	for (i = 0; i < ARRAY_SIZE(max9286_formats); ++i) {
 542		if (max9286_formats[i].code == format->code) {
 543			info = &max9286_formats[i];
 544			break;
 545		}
 546	}
 547
 548	if (WARN_ON(!info))
 549		return;
 550
 551	/*
 552	 * Video format setup: disable CSI output, set VC according to Link
 553	 * number, enable I2C clock stretching when CCBSY is low, enable CCBSY
 554	 * in external GPI-to-GPO mode.
 555	 */
 556	max9286_write(priv, 0x15, MAX9286_VCTYPE | MAX9286_EN_CCBSYB_CLK_STR |
 557		      MAX9286_EN_GPI_CCBSYB);
 558
 559	/* Enable CSI-2 Lane D0-D3 only, DBL mode. */
 560	max9286_write(priv, 0x12, MAX9286_CSIDBL | MAX9286_DBL |
 561		      MAX9286_CSILANECNT(priv->csi2_data_lanes) |
 562		      info->datatype);
 563
 564	/*
 565	 * Enable HS/VS encoding, use HS as line valid source, use D14/15 for
 566	 * HS/VS, invert VS.
 567	 */
 568	max9286_write(priv, 0x0c, MAX9286_HVEN | MAX9286_DESEL |
 569		      MAX9286_INVVS | MAX9286_HVSRC_D14);
 570}
 571
 572static void max9286_set_fsync_period(struct max9286_priv *priv,
 573				     struct v4l2_subdev_state *state)
 574{
 575	const struct v4l2_fract *interval;
 576	u32 fsync;
 577
 578	interval = v4l2_subdev_state_get_interval(state, MAX9286_SRC_PAD);
 579	if (!interval->numerator || !interval->denominator) {
 580		/*
 581		 * Special case, a null interval enables automatic FRAMESYNC
 582		 * mode. FRAMESYNC is taken from the slowest link.
 583		 */
 584		max9286_write(priv, 0x01, MAX9286_FSYNCMODE_INT_HIZ |
 585			      MAX9286_FSYNCMETH_AUTO);
 586		return;
 587	}
 588
 589	/*
 590	 * Manual FRAMESYNC
 591	 *
 592	 * The FRAMESYNC generator is configured with a period expressed as a
 593	 * number of PCLK periods.
 594	 */
 595	fsync = div_u64((u64)priv->pixelrate * interval->numerator,
 596			interval->denominator);
 597
 598	dev_dbg(&priv->client->dev, "fsync period %u (pclk %u)\n", fsync,
 599		priv->pixelrate);
 600
 601	max9286_write(priv, 0x01, MAX9286_FSYNCMODE_INT_OUT |
 602		      MAX9286_FSYNCMETH_MANUAL);
 603
 604	max9286_write(priv, 0x06, (fsync >> 0) & 0xff);
 605	max9286_write(priv, 0x07, (fsync >> 8) & 0xff);
 606	max9286_write(priv, 0x08, (fsync >> 16) & 0xff);
 607}
 608
 609/* -----------------------------------------------------------------------------
 610 * V4L2 Subdev
 611 */
 612
 613static int max9286_set_pixelrate(struct max9286_priv *priv)
 614{
 615	struct max9286_source *source = NULL;
 616	u64 pixelrate = 0;
 617
 618	for_each_source(priv, source) {
 619		struct v4l2_ctrl *ctrl;
 620		u64 source_rate = 0;
 621
 622		/* Pixel rate is mandatory to be reported by sources. */
 623		ctrl = v4l2_ctrl_find(source->sd->ctrl_handler,
 624				      V4L2_CID_PIXEL_RATE);
 625		if (!ctrl) {
 626			pixelrate = 0;
 627			break;
 628		}
 629
 630		/* All source must report the same pixel rate. */
 631		source_rate = v4l2_ctrl_g_ctrl_int64(ctrl);
 632		if (!pixelrate) {
 633			pixelrate = source_rate;
 634		} else if (pixelrate != source_rate) {
 635			dev_err(&priv->client->dev,
 636				"Unable to calculate pixel rate\n");
 637			return -EINVAL;
 638		}
 639	}
 640
 641	if (!pixelrate) {
 642		dev_err(&priv->client->dev,
 643			"No pixel rate control available in sources\n");
 644		return -EINVAL;
 645	}
 646
 647	priv->pixelrate = pixelrate;
 648
 649	/*
 650	 * The CSI-2 transmitter pixel rate is the single source rate multiplied
 651	 * by the number of available sources.
 652	 */
 653	return v4l2_ctrl_s_ctrl_int64(priv->pixelrate_ctrl,
 654				      pixelrate * priv->nsources);
 655}
 656
 657static int max9286_notify_bound(struct v4l2_async_notifier *notifier,
 658				struct v4l2_subdev *subdev,
 659				struct v4l2_async_connection *asd)
 660{
 661	struct max9286_priv *priv = sd_to_max9286(notifier->sd);
 662	struct max9286_source *source = to_max9286_asd(asd)->source;
 663	unsigned int index = to_index(priv, source);
 664	unsigned int src_pad;
 665	int ret;
 666
 667	ret = media_entity_get_fwnode_pad(&subdev->entity,
 668					  source->fwnode,
 669					  MEDIA_PAD_FL_SOURCE);
 670	if (ret < 0) {
 671		dev_err(&priv->client->dev,
 672			"Failed to find pad for %s\n", subdev->name);
 673		return ret;
 674	}
 675
 676	priv->bound_sources |= BIT(index);
 677	source->sd = subdev;
 678	src_pad = ret;
 679
 680	ret = media_create_pad_link(&source->sd->entity, src_pad,
 681				    &priv->sd.entity, index,
 682				    MEDIA_LNK_FL_ENABLED |
 683				    MEDIA_LNK_FL_IMMUTABLE);
 684	if (ret) {
 685		dev_err(&priv->client->dev,
 686			"Unable to link %s:%u -> %s:%u\n",
 687			source->sd->name, src_pad, priv->sd.name, index);
 688		return ret;
 689	}
 690
 691	dev_dbg(&priv->client->dev, "Bound %s pad: %u on index %u\n",
 692		subdev->name, src_pad, index);
 693
 694	/*
 695	 * As we register a subdev notifiers we won't get a .complete() callback
 696	 * here, so we have to use bound_sources to identify when all remote
 697	 * serializers have probed.
 698	 */
 699	if (priv->bound_sources != priv->source_mask)
 700		return 0;
 701
 702	/*
 703	 * All enabled sources have probed and enabled their reverse control
 704	 * channels:
 705	 *
 706	 * - Increase the reverse channel amplitude to compensate for the
 707	 *   remote ends high threshold
 708	 * - Verify all configuration links are properly detected
 709	 * - Disable auto-ack as communication on the control channel are now
 710	 *   stable.
 711	 */
 712	max9286_reverse_channel_setup(priv, MAX9286_REV_AMP_HIGH);
 713	max9286_check_config_link(priv, priv->source_mask);
 714	max9286_configure_i2c(priv, false);
 715
 716	return max9286_set_pixelrate(priv);
 717}
 718
 719static void max9286_notify_unbind(struct v4l2_async_notifier *notifier,
 720				  struct v4l2_subdev *subdev,
 721				  struct v4l2_async_connection *asd)
 722{
 723	struct max9286_priv *priv = sd_to_max9286(notifier->sd);
 724	struct max9286_source *source = to_max9286_asd(asd)->source;
 725	unsigned int index = to_index(priv, source);
 726
 727	source->sd = NULL;
 728	priv->bound_sources &= ~BIT(index);
 729}
 730
 731static const struct v4l2_async_notifier_operations max9286_notify_ops = {
 732	.bound = max9286_notify_bound,
 733	.unbind = max9286_notify_unbind,
 734};
 735
 736static int max9286_v4l2_notifier_register(struct max9286_priv *priv)
 737{
 738	struct device *dev = &priv->client->dev;
 739	struct max9286_source *source = NULL;
 740	int ret;
 741
 742	if (!priv->nsources)
 743		return 0;
 744
 745	v4l2_async_subdev_nf_init(&priv->notifier, &priv->sd);
 746
 747	for_each_source(priv, source) {
 748		unsigned int i = to_index(priv, source);
 749		struct max9286_asd *mas;
 750
 751		mas = v4l2_async_nf_add_fwnode(&priv->notifier, source->fwnode,
 752					       struct max9286_asd);
 753		if (IS_ERR(mas)) {
 754			dev_err(dev, "Failed to add subdev for source %u: %pe",
 755				i, mas);
 756			v4l2_async_nf_cleanup(&priv->notifier);
 757			return PTR_ERR(mas);
 758		}
 759
 760		mas->source = source;
 761	}
 762
 763	priv->notifier.ops = &max9286_notify_ops;
 764
 765	ret = v4l2_async_nf_register(&priv->notifier);
 766	if (ret) {
 767		dev_err(dev, "Failed to register subdev_notifier");
 768		v4l2_async_nf_cleanup(&priv->notifier);
 769		return ret;
 770	}
 771
 772	return 0;
 773}
 774
 775static void max9286_v4l2_notifier_unregister(struct max9286_priv *priv)
 776{
 777	if (!priv->nsources)
 778		return;
 779
 780	v4l2_async_nf_unregister(&priv->notifier);
 781	v4l2_async_nf_cleanup(&priv->notifier);
 782}
 783
 784static int max9286_s_stream(struct v4l2_subdev *sd, int enable)
 785{
 786	struct max9286_priv *priv = sd_to_max9286(sd);
 787	struct v4l2_subdev_state *state;
 788	struct max9286_source *source;
 789	unsigned int i;
 790	bool sync = false;
 791	int ret = 0;
 792
 793	state = v4l2_subdev_lock_and_get_active_state(sd);
 794
 795	if (enable) {
 796		const struct v4l2_mbus_framefmt *format;
 797
 798		/*
 799		 * Get the format from the source pad, as all formats must be
 800		 * identical.
 801		 */
 802		format = v4l2_subdev_state_get_format(state, MAX9286_SRC_PAD);
 803
 804		max9286_set_video_format(priv, format);
 805		max9286_set_fsync_period(priv, state);
 806
 807		/*
 808		 * The frame sync between cameras is transmitted across the
 809		 * reverse channel as GPIO. We must open all channels while
 810		 * streaming to allow this synchronisation signal to be shared.
 811		 */
 812		max9286_i2c_mux_open(priv);
 813
 814		/* Start all cameras. */
 815		for_each_source(priv, source) {
 816			ret = v4l2_subdev_call(source->sd, video, s_stream, 1);
 817			if (ret)
 818				goto unlock;
 819		}
 820
 821		ret = max9286_check_video_links(priv);
 822		if (ret)
 823			goto unlock;
 824
 825		/*
 826		 * Wait until frame synchronization is locked.
 827		 *
 828		 * Manual says frame sync locking should take ~6 VTS.
 829		 * From practical experience at least 8 are required. Give
 830		 * 12 complete frames time (~400ms at 30 fps) to achieve frame
 831		 * locking before returning error.
 832		 */
 833		for (i = 0; i < 40; i++) {
 834			if (max9286_read(priv, 0x31) & MAX9286_FSYNC_LOCKED) {
 835				sync = true;
 836				break;
 837			}
 838			usleep_range(9000, 11000);
 839		}
 840
 841		if (!sync) {
 842			dev_err(&priv->client->dev,
 843				"Failed to get frame synchronization\n");
 844			ret = -EXDEV; /* Invalid cross-device link */
 845			goto unlock;
 846		}
 847
 848		/*
 849		 * Configure the CSI-2 output to line interleaved mode (W x (N
 850		 * x H), as opposed to the (N x W) x H mode that outputs the
 851		 * images stitched side-by-side) and enable it.
 852		 */
 853		max9286_write(priv, 0x15, MAX9286_CSI_IMAGE_TYP | MAX9286_VCTYPE |
 854			      MAX9286_CSIOUTEN | MAX9286_EN_CCBSYB_CLK_STR |
 855			      MAX9286_EN_GPI_CCBSYB);
 856	} else {
 857		max9286_write(priv, 0x15, MAX9286_VCTYPE |
 858			      MAX9286_EN_CCBSYB_CLK_STR |
 859			      MAX9286_EN_GPI_CCBSYB);
 860
 861		/* Stop all cameras. */
 862		for_each_source(priv, source)
 863			v4l2_subdev_call(source->sd, video, s_stream, 0);
 864
 865		max9286_i2c_mux_close(priv);
 866	}
 867
 868unlock:
 869	v4l2_subdev_unlock_state(state);
 870
 871	return ret;
 872}
 873
 874static int max9286_get_frame_interval(struct v4l2_subdev *sd,
 875				      struct v4l2_subdev_state *sd_state,
 876				      struct v4l2_subdev_frame_interval *interval)
 877{
 878	if (interval->pad != MAX9286_SRC_PAD)
 879		return -EINVAL;
 880
 881	interval->interval = *v4l2_subdev_state_get_interval(sd_state,
 882							     interval->pad);
 883
 884	return 0;
 885}
 886
 887static int max9286_set_frame_interval(struct v4l2_subdev *sd,
 888				      struct v4l2_subdev_state *sd_state,
 889				      struct v4l2_subdev_frame_interval *interval)
 890{
 891	if (interval->pad != MAX9286_SRC_PAD)
 892		return -EINVAL;
 893
 894	*v4l2_subdev_state_get_interval(sd_state,
 895					interval->pad) = interval->interval;
 896
 897	return 0;
 898}
 899
 900static int max9286_enum_mbus_code(struct v4l2_subdev *sd,
 901				  struct v4l2_subdev_state *sd_state,
 902				  struct v4l2_subdev_mbus_code_enum *code)
 903{
 904	if (code->pad || code->index >= ARRAY_SIZE(max9286_formats))
 905		return -EINVAL;
 906
 907	code->code = max9286_formats[code->index].code;
 908
 909	return 0;
 910}
 911
 912static int max9286_set_fmt(struct v4l2_subdev *sd,
 913			   struct v4l2_subdev_state *state,
 914			   struct v4l2_subdev_format *format)
 915{
 916	struct max9286_priv *priv = sd_to_max9286(sd);
 917	struct max9286_source *source;
 918	unsigned int i;
 919
 920	/*
 921	 * Disable setting format on the source pad: format is propagated
 922	 * from the sinks.
 923	 */
 924	if (format->pad == MAX9286_SRC_PAD)
 925		return v4l2_subdev_get_fmt(sd, state, format);
 926
 927	/* Validate the format. */
 928	for (i = 0; i < ARRAY_SIZE(max9286_formats); ++i) {
 929		if (max9286_formats[i].code == format->format.code)
 930			break;
 931	}
 932
 933	if (i == ARRAY_SIZE(max9286_formats))
 934		format->format.code = max9286_formats[0].code;
 935
 936	/*
 937	 * Apply the same format on all the other pad as all links must have the
 938	 * same format.
 939	 */
 940	for_each_source(priv, source) {
 941		unsigned int index = to_index(priv, source);
 942
 943		*v4l2_subdev_state_get_format(state, index) = format->format;
 944	}
 945
 946	*v4l2_subdev_state_get_format(state, MAX9286_SRC_PAD) = format->format;
 947
 948	return 0;
 949}
 950
 951static const struct v4l2_subdev_video_ops max9286_video_ops = {
 952	.s_stream	= max9286_s_stream,
 953};
 954
 955static const struct v4l2_subdev_pad_ops max9286_pad_ops = {
 956	.enum_mbus_code = max9286_enum_mbus_code,
 957	.get_fmt	= v4l2_subdev_get_fmt,
 958	.set_fmt	= max9286_set_fmt,
 959	.get_frame_interval = max9286_get_frame_interval,
 960	.set_frame_interval = max9286_set_frame_interval,
 961};
 962
 963static const struct v4l2_subdev_ops max9286_subdev_ops = {
 964	.video		= &max9286_video_ops,
 965	.pad		= &max9286_pad_ops,
 966};
 967
 968static const struct v4l2_mbus_framefmt max9286_default_format = {
 969	.width		= 1280,
 970	.height		= 800,
 971	.code		= MEDIA_BUS_FMT_UYVY8_1X16,
 972	.colorspace	= V4L2_COLORSPACE_SRGB,
 973	.field		= V4L2_FIELD_NONE,
 974	.ycbcr_enc	= V4L2_YCBCR_ENC_DEFAULT,
 975	.quantization	= V4L2_QUANTIZATION_DEFAULT,
 976	.xfer_func	= V4L2_XFER_FUNC_DEFAULT,
 977};
 978
 979static int max9286_init_state(struct v4l2_subdev *sd,
 980			      struct v4l2_subdev_state *state)
 981{
 982	struct v4l2_fract *interval;
 983
 984	for (unsigned int i = 0; i < MAX9286_N_PADS; i++)
 985		*v4l2_subdev_state_get_format(state, i) = max9286_default_format;
 986
 987	/*
 988	 * Special case: a null interval enables automatic FRAMESYNC mode.
 989	 *
 990	 * FRAMESYNC is taken from the slowest link. See register 0x01
 991	 * configuration.
 992	 */
 993	interval = v4l2_subdev_state_get_interval(state, MAX9286_SRC_PAD);
 994	interval->numerator = 0;
 995	interval->denominator = 0;
 996
 997	return 0;
 998}
 999
1000static const struct v4l2_subdev_internal_ops max9286_subdev_internal_ops = {
1001	.init_state = max9286_init_state,
1002};
1003
1004static const struct media_entity_operations max9286_media_ops = {
1005	.link_validate = v4l2_subdev_link_validate
1006};
1007
1008static int max9286_s_ctrl(struct v4l2_ctrl *ctrl)
1009{
1010	switch (ctrl->id) {
1011	case V4L2_CID_PIXEL_RATE:
1012		return 0;
1013	default:
1014		return -EINVAL;
1015	}
1016}
1017
1018static const struct v4l2_ctrl_ops max9286_ctrl_ops = {
1019	.s_ctrl = max9286_s_ctrl,
1020};
1021
1022static int max9286_v4l2_register(struct max9286_priv *priv)
1023{
1024	struct device *dev = &priv->client->dev;
1025	int ret;
1026	int i;
1027
1028	/* Register v4l2 async notifiers for connected Camera subdevices */
1029	ret = max9286_v4l2_notifier_register(priv);
1030	if (ret) {
1031		dev_err(dev, "Unable to register V4L2 async notifiers\n");
1032		return ret;
1033	}
1034
1035	/* Configure V4L2 for the MAX9286 itself */
1036	v4l2_i2c_subdev_init(&priv->sd, priv->client, &max9286_subdev_ops);
1037	priv->sd.internal_ops = &max9286_subdev_internal_ops;
1038	priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1039
1040	v4l2_ctrl_handler_init(&priv->ctrls, 1);
1041	priv->pixelrate_ctrl = v4l2_ctrl_new_std(&priv->ctrls,
1042						 &max9286_ctrl_ops,
1043						 V4L2_CID_PIXEL_RATE,
1044						 1, INT_MAX, 1, 50000000);
1045
1046	priv->sd.ctrl_handler = &priv->ctrls;
1047	ret = priv->ctrls.error;
1048	if (ret)
1049		goto err_async;
1050
1051	priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
1052	priv->sd.entity.ops = &max9286_media_ops;
1053
1054	priv->pads[MAX9286_SRC_PAD].flags = MEDIA_PAD_FL_SOURCE;
1055	for (i = 0; i < MAX9286_SRC_PAD; i++)
1056		priv->pads[i].flags = MEDIA_PAD_FL_SINK;
1057	ret = media_entity_pads_init(&priv->sd.entity, MAX9286_N_PADS,
1058				     priv->pads);
1059	if (ret)
1060		goto err_async;
1061
1062	priv->sd.state_lock = priv->ctrls.lock;
1063	ret = v4l2_subdev_init_finalize(&priv->sd);
1064	if (ret)
1065		goto err_async;
1066
1067	ret = v4l2_async_register_subdev(&priv->sd);
1068	if (ret < 0) {
1069		dev_err(dev, "Unable to register subdevice\n");
1070		goto err_subdev;
1071	}
1072
1073	return 0;
1074
1075err_subdev:
1076	v4l2_subdev_cleanup(&priv->sd);
1077err_async:
1078	v4l2_ctrl_handler_free(&priv->ctrls);
1079	max9286_v4l2_notifier_unregister(priv);
1080
1081	return ret;
1082}
1083
1084static void max9286_v4l2_unregister(struct max9286_priv *priv)
1085{
1086	v4l2_subdev_cleanup(&priv->sd);
1087	v4l2_ctrl_handler_free(&priv->ctrls);
1088	v4l2_async_unregister_subdev(&priv->sd);
1089	max9286_v4l2_notifier_unregister(priv);
1090}
1091
1092/* -----------------------------------------------------------------------------
1093 * Probe/Remove
1094 */
1095
1096static int max9286_setup(struct max9286_priv *priv)
1097{
1098	/*
1099	 * Link ordering values for all enabled links combinations. Orders must
1100	 * be assigned sequentially from 0 to the number of enabled links
1101	 * without leaving any hole for disabled links. We thus assign orders to
1102	 * enabled links first, and use the remaining order values for disabled
1103	 * links are all links must have a different order value;
1104	 */
1105	static const u8 link_order[] = {
1106		(3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxxx */
1107		(3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxx0 */
1108		(3 << 6) | (2 << 4) | (0 << 2) | (1 << 0), /* xx0x */
1109		(3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xx10 */
1110		(3 << 6) | (0 << 4) | (2 << 2) | (1 << 0), /* x0xx */
1111		(3 << 6) | (1 << 4) | (2 << 2) | (0 << 0), /* x1x0 */
1112		(3 << 6) | (1 << 4) | (0 << 2) | (2 << 0), /* x10x */
1113		(3 << 6) | (1 << 4) | (1 << 2) | (0 << 0), /* x210 */
1114		(0 << 6) | (3 << 4) | (2 << 2) | (1 << 0), /* 0xxx */
1115		(1 << 6) | (3 << 4) | (2 << 2) | (0 << 0), /* 1xx0 */
1116		(1 << 6) | (3 << 4) | (0 << 2) | (2 << 0), /* 1x0x */
1117		(2 << 6) | (3 << 4) | (1 << 2) | (0 << 0), /* 2x10 */
1118		(1 << 6) | (0 << 4) | (3 << 2) | (2 << 0), /* 10xx */
1119		(2 << 6) | (1 << 4) | (3 << 2) | (0 << 0), /* 21x0 */
1120		(2 << 6) | (1 << 4) | (0 << 2) | (3 << 0), /* 210x */
1121		(3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* 3210 */
1122	};
1123	int cfg;
1124
1125	/*
1126	 * Set the I2C bus speed.
1127	 *
1128	 * Enable I2C Local Acknowledge during the probe sequences of the camera
1129	 * only. This should be disabled after the mux is initialised.
1130	 */
1131	max9286_configure_i2c(priv, true);
1132	max9286_reverse_channel_setup(priv, priv->init_rev_chan_mv);
1133
1134	/*
1135	 * Enable GMSL links, mask unused ones and autodetect link
1136	 * used as CSI clock source.
1137	 */
1138	max9286_write(priv, 0x00, MAX9286_MSTLINKSEL_AUTO | priv->route_mask);
1139	max9286_write(priv, 0x0b, link_order[priv->route_mask]);
1140	max9286_write(priv, 0x69, (0xf & ~priv->route_mask));
1141
1142	max9286_set_video_format(priv, &max9286_default_format);
1143
1144	cfg = max9286_read(priv, 0x1c);
1145	if (cfg < 0)
1146		return cfg;
1147
1148	dev_dbg(&priv->client->dev, "power-up config: %s immunity, %u-bit bus\n",
1149		cfg & MAX9286_HIGHIMM(0) ? "high" : "legacy",
1150		cfg & MAX9286_BWS ? 32 : cfg & MAX9286_HIBW ? 27 : 24);
1151
1152	if (priv->bus_width) {
1153		cfg &= ~(MAX9286_HIBW | MAX9286_BWS);
1154
1155		if (priv->bus_width == 27)
1156			cfg |= MAX9286_HIBW;
1157		else if (priv->bus_width == 32)
1158			cfg |= MAX9286_BWS;
1159
1160		max9286_write(priv, 0x1c, cfg);
1161	}
1162
1163	/*
1164	 * The overlap window seems to provide additional validation by tracking
1165	 * the delay between vsync and frame sync, generating an error if the
1166	 * delay is bigger than the programmed window, though it's not yet clear
1167	 * what value should be set.
1168	 *
1169	 * As it's an optional value and can be disabled, we do so by setting
1170	 * a 0 overlap value.
1171	 */
1172	max9286_write(priv, 0x63, 0);
1173	max9286_write(priv, 0x64, 0);
1174
1175	/*
1176	 * Wait for 2ms to allow the link to resynchronize after the
1177	 * configuration change.
1178	 */
1179	usleep_range(2000, 5000);
1180
1181	return 0;
1182}
1183
1184static int max9286_gpio_set(struct max9286_priv *priv, unsigned int offset,
1185			    int value)
1186{
1187	if (value)
1188		priv->gpio_state |= BIT(offset);
1189	else
1190		priv->gpio_state &= ~BIT(offset);
1191
1192	return max9286_write(priv, 0x0f,
1193			     MAX9286_0X0F_RESERVED | priv->gpio_state);
1194}
1195
1196static int max9286_gpiochip_set(struct gpio_chip *chip,
1197				unsigned int offset, int value)
1198{
1199	struct max9286_priv *priv = gpiochip_get_data(chip);
1200
1201	return max9286_gpio_set(priv, offset, value);
1202}
1203
1204static int max9286_gpiochip_get(struct gpio_chip *chip, unsigned int offset)
1205{
1206	struct max9286_priv *priv = gpiochip_get_data(chip);
1207
1208	return priv->gpio_state & BIT(offset);
1209}
1210
1211static int max9286_register_gpio(struct max9286_priv *priv)
1212{
1213	struct device *dev = &priv->client->dev;
1214	struct gpio_chip *gpio = &priv->gpio;
1215	int ret;
1216
1217	/* Configure the GPIO */
1218	gpio->label = dev_name(dev);
1219	gpio->parent = dev;
1220	gpio->owner = THIS_MODULE;
1221	gpio->ngpio = 2;
1222	gpio->base = -1;
1223	gpio->set = max9286_gpiochip_set;
1224	gpio->get = max9286_gpiochip_get;
1225	gpio->can_sleep = true;
1226
1227	ret = devm_gpiochip_add_data(dev, gpio, priv);
1228	if (ret)
1229		dev_err(dev, "Unable to create gpio_chip\n");
1230
1231	return ret;
1232}
1233
1234static int max9286_parse_gpios(struct max9286_priv *priv)
1235{
1236	struct device *dev = &priv->client->dev;
1237	int ret;
1238
1239	/*
1240	 * Parse the "gpio-poc" vendor property. If the property is not
1241	 * specified the camera power is controlled by a regulator.
1242	 */
1243	ret = of_property_read_u32_array(dev->of_node, "maxim,gpio-poc",
1244					 priv->gpio_poc, 2);
1245	if (ret == -EINVAL) {
1246		/*
1247		 * If gpio lines are not used for the camera power, register
1248		 * a gpio controller for consumers.
1249		 */
1250		return max9286_register_gpio(priv);
1251	}
1252
1253	/* If the property is specified make sure it is well formed. */
1254	if (ret || priv->gpio_poc[0] > 1 ||
1255	    (priv->gpio_poc[1] != GPIO_ACTIVE_HIGH &&
1256	     priv->gpio_poc[1] != GPIO_ACTIVE_LOW)) {
1257		dev_err(dev, "Invalid 'gpio-poc' property\n");
1258		return -EINVAL;
1259	}
1260
1261	priv->use_gpio_poc = true;
1262	return 0;
1263}
1264
1265static int max9286_poc_power_on(struct max9286_priv *priv)
1266{
1267	struct max9286_source *source;
1268	unsigned int enabled = 0;
1269	int ret;
1270
1271	/* Enable the global regulator if available. */
1272	if (priv->regulator)
1273		return regulator_enable(priv->regulator);
1274
1275	if (priv->use_gpio_poc)
1276		return max9286_gpio_set(priv, priv->gpio_poc[0],
1277					!priv->gpio_poc[1]);
1278
1279	/* Otherwise use the per-port regulators. */
1280	for_each_source(priv, source) {
1281		ret = regulator_enable(source->regulator);
1282		if (ret < 0)
1283			goto error;
1284
1285		enabled |= BIT(to_index(priv, source));
1286	}
1287
1288	return 0;
1289
1290error:
1291	for_each_source(priv, source) {
1292		if (enabled & BIT(to_index(priv, source)))
1293			regulator_disable(source->regulator);
1294	}
1295
1296	return ret;
1297}
1298
1299static int max9286_poc_power_off(struct max9286_priv *priv)
1300{
1301	struct max9286_source *source;
1302	int ret = 0;
1303
1304	if (priv->regulator)
1305		return regulator_disable(priv->regulator);
1306
1307	if (priv->use_gpio_poc)
1308		return max9286_gpio_set(priv, priv->gpio_poc[0],
1309					priv->gpio_poc[1]);
1310
1311	for_each_source(priv, source) {
1312		int err;
1313
1314		err = regulator_disable(source->regulator);
1315		if (!ret)
1316			ret = err;
1317	}
1318
1319	return ret;
1320}
1321
1322static int max9286_poc_enable(struct max9286_priv *priv, bool enable)
1323{
1324	int ret;
1325
1326	if (enable)
1327		ret = max9286_poc_power_on(priv);
1328	else
1329		ret = max9286_poc_power_off(priv);
1330
1331	if (ret < 0)
1332		dev_err(&priv->client->dev, "Unable to turn power %s\n",
1333			enable ? "on" : "off");
1334
1335	return ret;
1336}
1337
1338static int max9286_init(struct max9286_priv *priv)
1339{
1340	struct i2c_client *client = priv->client;
1341	int ret;
1342
1343	ret = max9286_poc_enable(priv, true);
1344	if (ret)
1345		return ret;
1346
1347	ret = max9286_setup(priv);
1348	if (ret) {
1349		dev_err(&client->dev, "Unable to setup max9286\n");
1350		goto err_poc_disable;
1351	}
1352
1353	/*
1354	 * Register all V4L2 interactions for the MAX9286 and notifiers for
1355	 * any subdevices connected.
1356	 */
1357	ret = max9286_v4l2_register(priv);
1358	if (ret) {
1359		dev_err(&client->dev, "Failed to register with V4L2\n");
1360		goto err_poc_disable;
1361	}
1362
1363	ret = max9286_i2c_mux_init(priv);
1364	if (ret) {
1365		dev_err(&client->dev, "Unable to initialize I2C multiplexer\n");
1366		goto err_v4l2_register;
1367	}
1368
1369	/* Leave the mux channels disabled until they are selected. */
1370	max9286_i2c_mux_close(priv);
1371
1372	return 0;
1373
1374err_v4l2_register:
1375	max9286_v4l2_unregister(priv);
1376err_poc_disable:
1377	max9286_poc_enable(priv, false);
1378
1379	return ret;
1380}
1381
1382static void max9286_cleanup_dt(struct max9286_priv *priv)
1383{
1384	struct max9286_source *source;
1385
1386	for_each_source(priv, source) {
1387		fwnode_handle_put(source->fwnode);
1388		source->fwnode = NULL;
1389	}
1390}
1391
1392static int max9286_parse_dt(struct max9286_priv *priv)
1393{
1394	struct device *dev = &priv->client->dev;
1395	struct device_node *i2c_mux;
1396	struct device_node *node = NULL;
1397	unsigned int i2c_mux_mask = 0;
1398	u32 reverse_channel_microvolt;
1399	u32 i2c_clk_freq = 105000;
1400	unsigned int i;
1401
1402	/* Balance the of_node_put() performed by of_find_node_by_name(). */
1403	of_node_get(dev->of_node);
1404	i2c_mux = of_find_node_by_name(dev->of_node, "i2c-mux");
1405	if (!i2c_mux) {
1406		dev_err(dev, "Failed to find i2c-mux node\n");
1407		return -EINVAL;
1408	}
1409
1410	/* Identify which i2c-mux channels are enabled */
1411	for_each_child_of_node(i2c_mux, node) {
1412		u32 id = 0;
1413
1414		of_property_read_u32(node, "reg", &id);
1415		if (id >= MAX9286_NUM_GMSL)
1416			continue;
1417
1418		if (!of_device_is_available(node)) {
1419			dev_dbg(dev, "Skipping disabled I2C bus port %u\n", id);
1420			continue;
1421		}
1422
1423		i2c_mux_mask |= BIT(id);
1424	}
1425	of_node_put(i2c_mux);
1426
1427	/* Parse the endpoints */
1428	for_each_endpoint_of_node(dev->of_node, node) {
1429		struct max9286_source *source;
1430		struct of_endpoint ep;
1431
1432		of_graph_parse_endpoint(node, &ep);
1433		dev_dbg(dev, "Endpoint %pOF on port %d",
1434			ep.local_node, ep.port);
1435
1436		if (ep.port > MAX9286_NUM_GMSL) {
1437			dev_err(dev, "Invalid endpoint %s on port %d",
1438				of_node_full_name(ep.local_node), ep.port);
1439			continue;
1440		}
1441
1442		/* For the source endpoint just parse the bus configuration. */
1443		if (ep.port == MAX9286_SRC_PAD) {
1444			struct v4l2_fwnode_endpoint vep = {
1445				.bus_type = V4L2_MBUS_CSI2_DPHY
1446			};
1447			int ret;
1448
1449			ret = v4l2_fwnode_endpoint_parse(
1450					of_fwnode_handle(node), &vep);
1451			if (ret) {
1452				of_node_put(node);
1453				return ret;
1454			}
1455
1456			priv->csi2_data_lanes =
1457				vep.bus.mipi_csi2.num_data_lanes;
1458
1459			continue;
1460		}
1461
1462		/* Skip if the corresponding GMSL link is unavailable. */
1463		if (!(i2c_mux_mask & BIT(ep.port)))
1464			continue;
1465
1466		if (priv->sources[ep.port].fwnode) {
1467			dev_err(dev,
1468				"Multiple port endpoints are not supported: %d",
1469				ep.port);
1470
1471			continue;
1472		}
1473
1474		source = &priv->sources[ep.port];
1475		source->fwnode = fwnode_graph_get_remote_endpoint(
1476						of_fwnode_handle(node));
1477		if (!source->fwnode) {
1478			dev_err(dev,
1479				"Endpoint %pOF has no remote endpoint connection\n",
1480				ep.local_node);
1481
1482			continue;
1483		}
1484
1485		priv->source_mask |= BIT(ep.port);
1486		priv->nsources++;
1487	}
1488
1489	of_property_read_u32(dev->of_node, "maxim,bus-width", &priv->bus_width);
1490	switch (priv->bus_width) {
1491	case 0:
1492		/*
1493		 * The property isn't specified in the device tree, the driver
1494		 * will keep the default value selected by the BWS pin.
1495		 */
1496	case 24:
1497	case 27:
1498	case 32:
1499		break;
1500	default:
1501		dev_err(dev, "Invalid %s value %u\n", "maxim,bus-width",
1502			priv->bus_width);
1503		return -EINVAL;
1504	}
1505
1506	of_property_read_u32(dev->of_node, "maxim,i2c-remote-bus-hz",
1507			     &i2c_clk_freq);
1508	for (i = 0; i < ARRAY_SIZE(max9286_i2c_speeds); ++i) {
1509		const struct max9286_i2c_speed *speed = &max9286_i2c_speeds[i];
1510
1511		if (speed->rate == i2c_clk_freq) {
1512			priv->i2c_mstbt = speed->mstbt;
1513			break;
1514		}
1515	}
1516
1517	if (i == ARRAY_SIZE(max9286_i2c_speeds)) {
1518		dev_err(dev, "Invalid %s value %u\n", "maxim,i2c-remote-bus-hz",
1519			i2c_clk_freq);
1520		return -EINVAL;
1521	}
1522
1523	/*
1524	 * Parse the initial value of the reverse channel amplitude from
1525	 * the firmware interface and convert it to millivolts.
1526	 *
1527	 * Default it to 170mV for backward compatibility with DTBs that do not
1528	 * provide the property.
1529	 */
1530	if (of_property_read_u32(dev->of_node,
1531				 "maxim,reverse-channel-microvolt",
1532				 &reverse_channel_microvolt))
1533		priv->init_rev_chan_mv = 170;
1534	else
1535		priv->init_rev_chan_mv = reverse_channel_microvolt / 1000U;
1536
1537	priv->route_mask = priv->source_mask;
1538
1539	return 0;
1540}
1541
1542static int max9286_get_poc_supplies(struct max9286_priv *priv)
1543{
1544	struct device *dev = &priv->client->dev;
1545	struct max9286_source *source;
1546	int ret;
1547
1548	/* Start by getting the global regulator. */
1549	priv->regulator = devm_regulator_get_optional(dev, "poc");
1550	if (!IS_ERR(priv->regulator))
1551		return 0;
1552
1553	if (PTR_ERR(priv->regulator) != -ENODEV)
1554		return dev_err_probe(dev, PTR_ERR(priv->regulator),
1555				     "Unable to get PoC regulator\n");
1556
1557	/* If there's no global regulator, get per-port regulators. */
1558	dev_dbg(dev,
1559		"No global PoC regulator, looking for per-port regulators\n");
1560	priv->regulator = NULL;
1561
1562	for_each_source(priv, source) {
1563		unsigned int index = to_index(priv, source);
1564		char name[10];
1565
1566		snprintf(name, sizeof(name), "port%u-poc", index);
1567		source->regulator = devm_regulator_get(dev, name);
1568		if (IS_ERR(source->regulator)) {
1569			ret = PTR_ERR(source->regulator);
1570			dev_err_probe(dev, ret,
1571				      "Unable to get port %u PoC regulator\n",
1572				      index);
1573			return ret;
1574		}
1575	}
1576
1577	return 0;
1578}
1579
1580static int max9286_probe(struct i2c_client *client)
1581{
1582	struct max9286_priv *priv;
1583	int ret;
1584
1585	priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
1586	if (!priv)
1587		return -ENOMEM;
1588
1589	priv->client = client;
1590
1591	/* GPIO values default to high */
1592	priv->gpio_state = BIT(0) | BIT(1);
1593
1594	ret = max9286_parse_dt(priv);
1595	if (ret)
1596		goto err_cleanup_dt;
1597
1598	priv->gpiod_pwdn = devm_gpiod_get_optional(&client->dev, "enable",
1599						   GPIOD_OUT_HIGH);
1600	if (IS_ERR(priv->gpiod_pwdn)) {
1601		ret = PTR_ERR(priv->gpiod_pwdn);
1602		goto err_cleanup_dt;
1603	}
1604
1605	gpiod_set_consumer_name(priv->gpiod_pwdn, "max9286-pwdn");
1606	gpiod_set_value_cansleep(priv->gpiod_pwdn, 1);
1607
1608	/* Wait at least 4ms before the I2C lines latch to the address */
1609	if (priv->gpiod_pwdn)
1610		usleep_range(4000, 5000);
1611
1612	/*
1613	 * The MAX9286 starts by default with all ports enabled, we disable all
1614	 * ports early to ensure that all channels are disabled if we error out
1615	 * and keep the bus consistent.
1616	 */
1617	max9286_i2c_mux_close(priv);
1618
1619	/*
1620	 * The MAX9286 initialises with auto-acknowledge enabled by default.
1621	 * This can be invasive to other transactions on the same bus, so
1622	 * disable it early. It will be enabled only as and when needed.
1623	 */
1624	max9286_configure_i2c(priv, false);
1625
1626	ret = max9286_parse_gpios(priv);
1627	if (ret)
1628		goto err_powerdown;
1629
1630	if (!priv->use_gpio_poc) {
1631		ret = max9286_get_poc_supplies(priv);
1632		if (ret)
1633			goto err_cleanup_dt;
1634	}
1635
1636	ret = max9286_init(priv);
1637	if (ret < 0)
1638		goto err_cleanup_dt;
1639
1640	return 0;
1641
1642err_powerdown:
1643	gpiod_set_value_cansleep(priv->gpiod_pwdn, 0);
1644err_cleanup_dt:
1645	max9286_cleanup_dt(priv);
1646
1647	return ret;
1648}
1649
1650static void max9286_remove(struct i2c_client *client)
1651{
1652	struct max9286_priv *priv = sd_to_max9286(i2c_get_clientdata(client));
1653
1654	i2c_mux_del_adapters(priv->mux);
1655
1656	max9286_v4l2_unregister(priv);
1657
1658	max9286_poc_enable(priv, false);
1659
1660	gpiod_set_value_cansleep(priv->gpiod_pwdn, 0);
1661
1662	max9286_cleanup_dt(priv);
1663}
1664
1665static const struct of_device_id max9286_dt_ids[] = {
1666	{ .compatible = "maxim,max9286" },
1667	{},
1668};
1669MODULE_DEVICE_TABLE(of, max9286_dt_ids);
1670
1671static struct i2c_driver max9286_i2c_driver = {
1672	.driver	= {
1673		.name		= "max9286",
1674		.of_match_table	= max9286_dt_ids,
1675	},
1676	.probe		= max9286_probe,
1677	.remove		= max9286_remove,
1678};
1679
1680module_i2c_driver(max9286_i2c_driver);
1681
1682MODULE_DESCRIPTION("Maxim MAX9286 GMSL Deserializer Driver");
1683MODULE_AUTHOR("Jacopo Mondi, Kieran Bingham, Laurent Pinchart, Niklas Söderlund, Vladimir Barinov");
1684MODULE_LICENSE("GPL");