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imx415.c
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linux-6.19.14/drivers/media/i2c/imx415.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Driver for the Sony IMX415 CMOS Image Sensor. 4 * 5 * Copyright (C) 2023 WolfVision GmbH. 6 */ 7 8#include <linux/clk.h> 9#include <linux/gpio/consumer.h> 10#include <linux/i2c.h> 11#include <linux/module.h> 12#include <linux/of.h> 13#include <linux/pm_runtime.h> 14#include <linux/regmap.h> 15#include <linux/regulator/consumer.h> 16#include <linux/slab.h> 17#include <linux/videodev2.h> 18 19#include <media/v4l2-cci.h> 20#include <media/v4l2-ctrls.h> 21#include <media/v4l2-fwnode.h> 22#include <media/v4l2-subdev.h> 23 24#define IMX415_PIXEL_ARRAY_TOP 0 25#define IMX415_PIXEL_ARRAY_LEFT 0 26#define IMX415_PIXEL_ARRAY_WIDTH 3864 27#define IMX415_PIXEL_ARRAY_HEIGHT 2192 28#define IMX415_PIXEL_ARRAY_VBLANK 58 29#define IMX415_EXPOSURE_OFFSET 8 30 31#define IMX415_PIXEL_RATE_74_25MHZ 891000000 32#define IMX415_PIXEL_RATE_72MHZ 864000000 33 34#define IMX415_NUM_CLK_PARAM_REGS 11 35 36#define IMX415_MODE CCI_REG8(0x3000) 37#define IMX415_MODE_OPERATING (0) 38#define IMX415_MODE_STANDBY BIT(0) 39#define IMX415_REGHOLD CCI_REG8(0x3001) 40#define IMX415_REGHOLD_INVALID (0) 41#define IMX415_REGHOLD_VALID BIT(0) 42#define IMX415_XMSTA CCI_REG8(0x3002) 43#define IMX415_XMSTA_START (0) 44#define IMX415_XMSTA_STOP BIT(0) 45#define IMX415_BCWAIT_TIME CCI_REG16_LE(0x3008) 46#define IMX415_CPWAIT_TIME CCI_REG16_LE(0x300a) 47#define IMX415_WINMODE CCI_REG8(0x301c) 48#define IMX415_ADDMODE CCI_REG8(0x3022) 49#define IMX415_REVERSE CCI_REG8(0x3030) 50#define IMX415_HREVERSE_SHIFT (0) 51#define IMX415_VREVERSE_SHIFT BIT(0) 52#define IMX415_ADBIT CCI_REG8(0x3031) 53#define IMX415_MDBIT CCI_REG8(0x3032) 54#define IMX415_SYS_MODE CCI_REG8(0x3033) 55#define IMX415_OUTSEL CCI_REG8(0x30c0) 56#define IMX415_DRV CCI_REG8(0x30c1) 57#define IMX415_VMAX CCI_REG24_LE(0x3024) 58#define IMX415_VMAX_MAX 0xfffff 59#define IMX415_HMAX CCI_REG16_LE(0x3028) 60#define IMX415_HMAX_MAX 0xffff 61#define IMX415_HMAX_MULTIPLIER 12 62#define IMX415_SHR0 CCI_REG24_LE(0x3050) 63#define IMX415_GAIN_PCG_0 CCI_REG16_LE(0x3090) 64#define IMX415_AGAIN_MIN 0 65#define IMX415_AGAIN_MAX 100 66#define IMX415_AGAIN_STEP 1 67#define IMX415_BLKLEVEL CCI_REG16_LE(0x30e2) 68#define IMX415_BLKLEVEL_DEFAULT 50 69#define IMX415_TPG_EN_DUOUT CCI_REG8(0x30e4) 70#define IMX415_TPG_PATSEL_DUOUT CCI_REG8(0x30e6) 71#define IMX415_TPG_COLORWIDTH CCI_REG8(0x30e8) 72#define IMX415_TESTCLKEN_MIPI CCI_REG8(0x3110) 73#define IMX415_INCKSEL1 CCI_REG8(0x3115) 74#define IMX415_INCKSEL2 CCI_REG8(0x3116) 75#define IMX415_INCKSEL3 CCI_REG16_LE(0x3118) 76#define IMX415_INCKSEL4 CCI_REG16_LE(0x311a) 77#define IMX415_INCKSEL5 CCI_REG8(0x311e) 78#define IMX415_DIG_CLP_MODE CCI_REG8(0x32c8) 79#define IMX415_WRJ_OPEN CCI_REG8(0x3390) 80#define IMX415_SENSOR_INFO CCI_REG16_LE(0x3f12) 81#define IMX415_SENSOR_INFO_MASK 0xfff 82#define IMX415_CHIP_ID 0x514 83#define IMX415_LANEMODE CCI_REG16_LE(0x4001) 84#define IMX415_LANEMODE_2 1 85#define IMX415_LANEMODE_4 3 86#define IMX415_TXCLKESC_FREQ CCI_REG16_LE(0x4004) 87#define IMX415_INCKSEL6 CCI_REG8(0x400c) 88#define IMX415_TCLKPOST CCI_REG16_LE(0x4018) 89#define IMX415_TCLKPREPARE CCI_REG16_LE(0x401a) 90#define IMX415_TCLKTRAIL CCI_REG16_LE(0x401c) 91#define IMX415_TCLKZERO CCI_REG16_LE(0x401e) 92#define IMX415_THSPREPARE CCI_REG16_LE(0x4020) 93#define IMX415_THSZERO CCI_REG16_LE(0x4022) 94#define IMX415_THSTRAIL CCI_REG16_LE(0x4024) 95#define IMX415_THSEXIT CCI_REG16_LE(0x4026) 96#define IMX415_TLPX CCI_REG16_LE(0x4028) 97#define IMX415_INCKSEL7 CCI_REG8(0x4074) 98 99static const char *const imx415_supply_names[] = { 100 "dvdd", 101 "ovdd", 102 "avdd", 103}; 104 105/* 106 * The IMX415 data sheet uses lane rates but v4l2 uses link frequency to 107 * describe MIPI CSI-2 speed. This driver uses lane rates wherever possible 108 * and converts them to link frequencies by a factor of two when needed. 109 */ 110static const s64 link_freq_menu_items[] = { 111 594000000 / 2, 720000000 / 2, 891000000 / 2, 112 1440000000 / 2, 1485000000 / 2, 113}; 114 115struct imx415_clk_params { 116 u64 lane_rate; 117 u64 inck; 118 struct cci_reg_sequence regs[IMX415_NUM_CLK_PARAM_REGS]; 119}; 120 121/* INCK Settings - includes all lane rate and INCK dependent registers */ 122static const struct imx415_clk_params imx415_clk_params[] = { 123 { 124 .lane_rate = 594000000UL, 125 .inck = 27000000, 126 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D }, 127 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 }, 128 .regs[2] = { IMX415_SYS_MODE, 0x7 }, 129 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 130 .regs[4] = { IMX415_INCKSEL2, 0x23 }, 131 .regs[5] = { IMX415_INCKSEL3, 0x084 }, 132 .regs[6] = { IMX415_INCKSEL4, 0x0E7 }, 133 .regs[7] = { IMX415_INCKSEL5, 0x23 }, 134 .regs[8] = { IMX415_INCKSEL6, 0x0 }, 135 .regs[9] = { IMX415_INCKSEL7, 0x1 }, 136 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 }, 137 }, 138 { 139 .lane_rate = 594000000UL, 140 .inck = 37125000, 141 .regs[0] = { IMX415_BCWAIT_TIME, 0x07F }, 142 .regs[1] = { IMX415_CPWAIT_TIME, 0x05B }, 143 .regs[2] = { IMX415_SYS_MODE, 0x7 }, 144 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 145 .regs[4] = { IMX415_INCKSEL2, 0x24 }, 146 .regs[5] = { IMX415_INCKSEL3, 0x080 }, 147 .regs[6] = { IMX415_INCKSEL4, 0x0E0 }, 148 .regs[7] = { IMX415_INCKSEL5, 0x24 }, 149 .regs[8] = { IMX415_INCKSEL6, 0x0 }, 150 .regs[9] = { IMX415_INCKSEL7, 0x1 }, 151 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0984 }, 152 }, 153 { 154 .lane_rate = 594000000UL, 155 .inck = 74250000, 156 .regs[0] = { IMX415_BCWAIT_TIME, 0x0FF }, 157 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 }, 158 .regs[2] = { IMX415_SYS_MODE, 0x7 }, 159 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 160 .regs[4] = { IMX415_INCKSEL2, 0x28 }, 161 .regs[5] = { IMX415_INCKSEL3, 0x080 }, 162 .regs[6] = { IMX415_INCKSEL4, 0x0E0 }, 163 .regs[7] = { IMX415_INCKSEL5, 0x28 }, 164 .regs[8] = { IMX415_INCKSEL6, 0x0 }, 165 .regs[9] = { IMX415_INCKSEL7, 0x1 }, 166 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 }, 167 }, 168 { 169 .lane_rate = 720000000UL, 170 .inck = 24000000, 171 .regs[0] = { IMX415_BCWAIT_TIME, 0x054 }, 172 .regs[1] = { IMX415_CPWAIT_TIME, 0x03B }, 173 .regs[2] = { IMX415_SYS_MODE, 0x9 }, 174 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 175 .regs[4] = { IMX415_INCKSEL2, 0x23 }, 176 .regs[5] = { IMX415_INCKSEL3, 0x0B4 }, 177 .regs[6] = { IMX415_INCKSEL4, 0x0FC }, 178 .regs[7] = { IMX415_INCKSEL5, 0x23 }, 179 .regs[8] = { IMX415_INCKSEL6, 0x0 }, 180 .regs[9] = { IMX415_INCKSEL7, 0x1 }, 181 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 }, 182 }, 183 { 184 .lane_rate = 720000000UL, 185 .inck = 72000000, 186 .regs[0] = { IMX415_BCWAIT_TIME, 0x0F8 }, 187 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B0 }, 188 .regs[2] = { IMX415_SYS_MODE, 0x9 }, 189 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 190 .regs[4] = { IMX415_INCKSEL2, 0x28 }, 191 .regs[5] = { IMX415_INCKSEL3, 0x0A0 }, 192 .regs[6] = { IMX415_INCKSEL4, 0x0E0 }, 193 .regs[7] = { IMX415_INCKSEL5, 0x28 }, 194 .regs[8] = { IMX415_INCKSEL6, 0x0 }, 195 .regs[9] = { IMX415_INCKSEL7, 0x1 }, 196 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1200 }, 197 }, 198 { 199 .lane_rate = 891000000UL, 200 .inck = 27000000, 201 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D }, 202 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 }, 203 .regs[2] = { IMX415_SYS_MODE, 0x5 }, 204 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 205 .regs[4] = { IMX415_INCKSEL2, 0x23 }, 206 .regs[5] = { IMX415_INCKSEL3, 0x0C6 }, 207 .regs[6] = { IMX415_INCKSEL4, 0x0E7 }, 208 .regs[7] = { IMX415_INCKSEL5, 0x23 }, 209 .regs[8] = { IMX415_INCKSEL6, 0x0 }, 210 .regs[9] = { IMX415_INCKSEL7, 0x1 }, 211 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 }, 212 }, 213 { 214 .lane_rate = 891000000UL, 215 .inck = 37125000, 216 .regs[0] = { IMX415_BCWAIT_TIME, 0x07F }, 217 .regs[1] = { IMX415_CPWAIT_TIME, 0x05B }, 218 .regs[2] = { IMX415_SYS_MODE, 0x5 }, 219 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 220 .regs[4] = { IMX415_INCKSEL2, 0x24 }, 221 .regs[5] = { IMX415_INCKSEL3, 0x0C0 }, 222 .regs[6] = { IMX415_INCKSEL4, 0x0E0 }, 223 .regs[7] = { IMX415_INCKSEL5, 0x24 }, 224 .regs[8] = { IMX415_INCKSEL6, 0x0 }, 225 .regs[9] = { IMX415_INCKSEL7, 0x1 }, 226 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 }, 227 }, 228 { 229 .lane_rate = 891000000UL, 230 .inck = 74250000, 231 .regs[0] = { IMX415_BCWAIT_TIME, 0x0FF }, 232 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 }, 233 .regs[2] = { IMX415_SYS_MODE, 0x5 }, 234 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 235 .regs[4] = { IMX415_INCKSEL2, 0x28 }, 236 .regs[5] = { IMX415_INCKSEL3, 0x0C0 }, 237 .regs[6] = { IMX415_INCKSEL4, 0x0E0 }, 238 .regs[7] = { IMX415_INCKSEL5, 0x28 }, 239 .regs[8] = { IMX415_INCKSEL6, 0x0 }, 240 .regs[9] = { IMX415_INCKSEL7, 0x1 }, 241 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 }, 242 }, 243 { 244 .lane_rate = 1440000000UL, 245 .inck = 24000000, 246 .regs[0] = { IMX415_BCWAIT_TIME, 0x054 }, 247 .regs[1] = { IMX415_CPWAIT_TIME, 0x03B }, 248 .regs[2] = { IMX415_SYS_MODE, 0x8 }, 249 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 250 .regs[4] = { IMX415_INCKSEL2, 0x23 }, 251 .regs[5] = { IMX415_INCKSEL3, 0x0B4 }, 252 .regs[6] = { IMX415_INCKSEL4, 0x0FC }, 253 .regs[7] = { IMX415_INCKSEL5, 0x23 }, 254 .regs[8] = { IMX415_INCKSEL6, 0x1 }, 255 .regs[9] = { IMX415_INCKSEL7, 0x0 }, 256 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 }, 257 }, 258 { 259 .lane_rate = 1440000000UL, 260 .inck = 72000000, 261 .regs[0] = { IMX415_BCWAIT_TIME, 0x0F8 }, 262 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B0 }, 263 .regs[2] = { IMX415_SYS_MODE, 0x8 }, 264 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 265 .regs[4] = { IMX415_INCKSEL2, 0x28 }, 266 .regs[5] = { IMX415_INCKSEL3, 0x0A0 }, 267 .regs[6] = { IMX415_INCKSEL4, 0x0E0 }, 268 .regs[7] = { IMX415_INCKSEL5, 0x28 }, 269 .regs[8] = { IMX415_INCKSEL6, 0x1 }, 270 .regs[9] = { IMX415_INCKSEL7, 0x0 }, 271 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1200 }, 272 }, 273 { 274 .lane_rate = 1485000000UL, 275 .inck = 27000000, 276 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D }, 277 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 }, 278 .regs[2] = { IMX415_SYS_MODE, 0x8 }, 279 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 280 .regs[4] = { IMX415_INCKSEL2, 0x23 }, 281 .regs[5] = { IMX415_INCKSEL3, 0x0A5 }, 282 .regs[6] = { IMX415_INCKSEL4, 0x0E7 }, 283 .regs[7] = { IMX415_INCKSEL5, 0x23 }, 284 .regs[8] = { IMX415_INCKSEL6, 0x1 }, 285 .regs[9] = { IMX415_INCKSEL7, 0x0 }, 286 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 }, 287 }, 288 { 289 .lane_rate = 1485000000UL, 290 .inck = 37125000, 291 .regs[0] = { IMX415_BCWAIT_TIME, 0x07F }, 292 .regs[1] = { IMX415_CPWAIT_TIME, 0x05B }, 293 .regs[2] = { IMX415_SYS_MODE, 0x8 }, 294 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 295 .regs[4] = { IMX415_INCKSEL2, 0x24 }, 296 .regs[5] = { IMX415_INCKSEL3, 0x0A0 }, 297 .regs[6] = { IMX415_INCKSEL4, 0x0E0 }, 298 .regs[7] = { IMX415_INCKSEL5, 0x24 }, 299 .regs[8] = { IMX415_INCKSEL6, 0x1 }, 300 .regs[9] = { IMX415_INCKSEL7, 0x0 }, 301 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 }, 302 }, 303 { 304 .lane_rate = 1485000000UL, 305 .inck = 74250000, 306 .regs[0] = { IMX415_BCWAIT_TIME, 0x0FF }, 307 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 }, 308 .regs[2] = { IMX415_SYS_MODE, 0x8 }, 309 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 310 .regs[4] = { IMX415_INCKSEL2, 0x28 }, 311 .regs[5] = { IMX415_INCKSEL3, 0x0A0 }, 312 .regs[6] = { IMX415_INCKSEL4, 0x0E0 }, 313 .regs[7] = { IMX415_INCKSEL5, 0x28 }, 314 .regs[8] = { IMX415_INCKSEL6, 0x1 }, 315 .regs[9] = { IMX415_INCKSEL7, 0x0 }, 316 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 }, 317 }, 318 { 319 .lane_rate = 1782000000UL, 320 .inck = 27000000, 321 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D }, 322 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 }, 323 .regs[2] = { IMX415_SYS_MODE, 0x4 }, 324 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 325 .regs[4] = { IMX415_INCKSEL2, 0x23 }, 326 .regs[5] = { IMX415_INCKSEL3, 0x0C6 }, 327 .regs[6] = { IMX415_INCKSEL4, 0x0E7 }, 328 .regs[7] = { IMX415_INCKSEL5, 0x23 }, 329 .regs[8] = { IMX415_INCKSEL6, 0x1 }, 330 .regs[9] = { IMX415_INCKSEL7, 0x0 }, 331 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 }, 332 }, 333 { 334 .lane_rate = 1782000000UL, 335 .inck = 37125000, 336 .regs[0] = { IMX415_BCWAIT_TIME, 0x07F }, 337 .regs[1] = { IMX415_CPWAIT_TIME, 0x05B }, 338 .regs[2] = { IMX415_SYS_MODE, 0x4 }, 339 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 340 .regs[4] = { IMX415_INCKSEL2, 0x24 }, 341 .regs[5] = { IMX415_INCKSEL3, 0x0C0 }, 342 .regs[6] = { IMX415_INCKSEL4, 0x0E0 }, 343 .regs[7] = { IMX415_INCKSEL5, 0x24 }, 344 .regs[8] = { IMX415_INCKSEL6, 0x1 }, 345 .regs[9] = { IMX415_INCKSEL7, 0x0 }, 346 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 }, 347 }, 348 { 349 .lane_rate = 1782000000UL, 350 .inck = 74250000, 351 .regs[0] = { IMX415_BCWAIT_TIME, 0x0FF }, 352 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 }, 353 .regs[2] = { IMX415_SYS_MODE, 0x4 }, 354 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 355 .regs[4] = { IMX415_INCKSEL2, 0x28 }, 356 .regs[5] = { IMX415_INCKSEL3, 0x0C0 }, 357 .regs[6] = { IMX415_INCKSEL4, 0x0E0 }, 358 .regs[7] = { IMX415_INCKSEL5, 0x28 }, 359 .regs[8] = { IMX415_INCKSEL6, 0x1 }, 360 .regs[9] = { IMX415_INCKSEL7, 0x0 }, 361 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 }, 362 }, 363 { 364 .lane_rate = 2079000000UL, 365 .inck = 27000000, 366 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D }, 367 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 }, 368 .regs[2] = { IMX415_SYS_MODE, 0x2 }, 369 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 370 .regs[4] = { IMX415_INCKSEL2, 0x23 }, 371 .regs[5] = { IMX415_INCKSEL3, 0x0E7 }, 372 .regs[6] = { IMX415_INCKSEL4, 0x0E7 }, 373 .regs[7] = { IMX415_INCKSEL5, 0x23 }, 374 .regs[8] = { IMX415_INCKSEL6, 0x1 }, 375 .regs[9] = { IMX415_INCKSEL7, 0x0 }, 376 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 }, 377 }, 378 { 379 .lane_rate = 2079000000UL, 380 .inck = 37125000, 381 .regs[0] = { IMX415_BCWAIT_TIME, 0x07F }, 382 .regs[1] = { IMX415_CPWAIT_TIME, 0x05B }, 383 .regs[2] = { IMX415_SYS_MODE, 0x2 }, 384 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 385 .regs[4] = { IMX415_INCKSEL2, 0x24 }, 386 .regs[5] = { IMX415_INCKSEL3, 0x0E0 }, 387 .regs[6] = { IMX415_INCKSEL4, 0x0E0 }, 388 .regs[7] = { IMX415_INCKSEL5, 0x24 }, 389 .regs[8] = { IMX415_INCKSEL6, 0x1 }, 390 .regs[9] = { IMX415_INCKSEL7, 0x0 }, 391 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 }, 392 }, 393 { 394 .lane_rate = 2079000000UL, 395 .inck = 74250000, 396 .regs[0] = { IMX415_BCWAIT_TIME, 0x0FF }, 397 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 }, 398 .regs[2] = { IMX415_SYS_MODE, 0x2 }, 399 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 400 .regs[4] = { IMX415_INCKSEL2, 0x28 }, 401 .regs[5] = { IMX415_INCKSEL3, 0x0E0 }, 402 .regs[6] = { IMX415_INCKSEL4, 0x0E0 }, 403 .regs[7] = { IMX415_INCKSEL5, 0x28 }, 404 .regs[8] = { IMX415_INCKSEL6, 0x1 }, 405 .regs[9] = { IMX415_INCKSEL7, 0x0 }, 406 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 }, 407 }, 408 { 409 .lane_rate = 2376000000UL, 410 .inck = 27000000, 411 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D }, 412 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 }, 413 .regs[2] = { IMX415_SYS_MODE, 0x0 }, 414 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 415 .regs[4] = { IMX415_INCKSEL2, 0x23 }, 416 .regs[5] = { IMX415_INCKSEL3, 0x108 }, 417 .regs[6] = { IMX415_INCKSEL4, 0x0E7 }, 418 .regs[7] = { IMX415_INCKSEL5, 0x23 }, 419 .regs[8] = { IMX415_INCKSEL6, 0x1 }, 420 .regs[9] = { IMX415_INCKSEL7, 0x0 }, 421 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 }, 422 }, 423 { 424 .lane_rate = 2376000000UL, 425 .inck = 37125000, 426 .regs[0] = { IMX415_BCWAIT_TIME, 0x07F }, 427 .regs[1] = { IMX415_CPWAIT_TIME, 0x05B }, 428 .regs[2] = { IMX415_SYS_MODE, 0x0 }, 429 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 430 .regs[4] = { IMX415_INCKSEL2, 0x24 }, 431 .regs[5] = { IMX415_INCKSEL3, 0x100 }, 432 .regs[6] = { IMX415_INCKSEL4, 0x0E0 }, 433 .regs[7] = { IMX415_INCKSEL5, 0x24 }, 434 .regs[8] = { IMX415_INCKSEL6, 0x1 }, 435 .regs[9] = { IMX415_INCKSEL7, 0x0 }, 436 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 }, 437 }, 438 { 439 .lane_rate = 2376000000UL, 440 .inck = 74250000, 441 .regs[0] = { IMX415_BCWAIT_TIME, 0x0FF }, 442 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 }, 443 .regs[2] = { IMX415_SYS_MODE, 0x0 }, 444 .regs[3] = { IMX415_INCKSEL1, 0x00 }, 445 .regs[4] = { IMX415_INCKSEL2, 0x28 }, 446 .regs[5] = { IMX415_INCKSEL3, 0x100 }, 447 .regs[6] = { IMX415_INCKSEL4, 0x0E0 }, 448 .regs[7] = { IMX415_INCKSEL5, 0x28 }, 449 .regs[8] = { IMX415_INCKSEL6, 0x1 }, 450 .regs[9] = { IMX415_INCKSEL7, 0x0 }, 451 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 }, 452 }, 453}; 454 455/* 720 Mbps CSI configuration */ 456static const struct cci_reg_sequence imx415_linkrate_720mbps[] = { 457 { IMX415_TCLKPOST, 0x006F }, 458 { IMX415_TCLKPREPARE, 0x002F }, 459 { IMX415_TCLKTRAIL, 0x002F }, 460 { IMX415_TCLKZERO, 0x00BF }, 461 { IMX415_THSPREPARE, 0x002F }, 462 { IMX415_THSZERO, 0x0057 }, 463 { IMX415_THSTRAIL, 0x002F }, 464 { IMX415_THSEXIT, 0x004F }, 465 { IMX415_TLPX, 0x0027 }, 466}; 467 468/* 1440 Mbps CSI configuration */ 469static const struct cci_reg_sequence imx415_linkrate_1440mbps[] = { 470 { IMX415_TCLKPOST, 0x009F }, 471 { IMX415_TCLKPREPARE, 0x0057 }, 472 { IMX415_TCLKTRAIL, 0x0057 }, 473 { IMX415_TCLKZERO, 0x0187 }, 474 { IMX415_THSPREPARE, 0x005F }, 475 { IMX415_THSZERO, 0x00A7 }, 476 { IMX415_THSTRAIL, 0x005F }, 477 { IMX415_THSEXIT, 0x0097 }, 478 { IMX415_TLPX, 0x004F }, 479}; 480 481/* 891 Mbps CSI configuration */ 482static const struct cci_reg_sequence imx415_linkrate_891mbps[] = { 483 { IMX415_TCLKPOST, 0x007F }, 484 { IMX415_TCLKPREPARE, 0x0037 }, 485 { IMX415_TCLKTRAIL, 0x0037 }, 486 { IMX415_TCLKZERO, 0x00F7 }, 487 { IMX415_THSPREPARE, 0x003F }, 488 { IMX415_THSZERO, 0x006F }, 489 { IMX415_THSTRAIL, 0x003F }, 490 { IMX415_THSEXIT, 0x005F }, 491 { IMX415_TLPX, 0x002F }, 492}; 493 494struct imx415_mode_reg_list { 495 u32 num_of_regs; 496 const struct cci_reg_sequence *regs; 497}; 498 499struct imx415_mode { 500 u64 lane_rate; 501 u32 hmax_min[2]; 502 struct imx415_mode_reg_list reg_list; 503}; 504 505/* mode configs */ 506static const struct imx415_mode supported_modes[] = { 507 { 508 .lane_rate = 720000000, 509 .hmax_min = { 2032, 1066 }, 510 .reg_list = { 511 .num_of_regs = ARRAY_SIZE(imx415_linkrate_720mbps), 512 .regs = imx415_linkrate_720mbps, 513 }, 514 }, 515 { 516 .lane_rate = 1440000000, 517 .hmax_min = { 1066, 533 }, 518 .reg_list = { 519 .num_of_regs = ARRAY_SIZE(imx415_linkrate_1440mbps), 520 .regs = imx415_linkrate_1440mbps, 521 }, 522 }, 523 { 524 .lane_rate = 891000000, 525 .hmax_min = { 2200, 1100 }, 526 .reg_list = { 527 .num_of_regs = ARRAY_SIZE(imx415_linkrate_891mbps), 528 .regs = imx415_linkrate_891mbps, 529 }, 530 }, 531}; 532 533static const char *const imx415_test_pattern_menu[] = { 534 "disabled", 535 "solid black", 536 "solid white", 537 "solid dark gray", 538 "solid light gray", 539 "stripes light/dark grey", 540 "stripes dark/light grey", 541 "stripes black/dark grey", 542 "stripes dark grey/black", 543 "stripes black/white", 544 "stripes white/black", 545 "horizontal color bar", 546 "vertical color bar", 547}; 548 549struct imx415 { 550 struct device *dev; 551 struct clk *clk; 552 unsigned long pixel_rate; 553 struct regulator_bulk_data supplies[ARRAY_SIZE(imx415_supply_names)]; 554 struct gpio_desc *reset; 555 struct regmap *regmap; 556 557 const struct imx415_clk_params *clk_params; 558 559 struct v4l2_subdev subdev; 560 struct media_pad pad; 561 562 struct v4l2_ctrl_handler ctrls; 563 struct v4l2_ctrl *vblank; 564 struct v4l2_ctrl *hblank; 565 struct v4l2_ctrl *hflip; 566 struct v4l2_ctrl *vflip; 567 struct v4l2_ctrl *exposure; 568 569 unsigned int cur_mode; 570 unsigned int num_data_lanes; 571}; 572 573/* 574 * This table includes fixed register settings and a bunch of undocumented 575 * registers that have to be set to another value than default. 576 */ 577static const struct cci_reg_sequence imx415_init_table[] = { 578 /* use all-pixel readout mode, no flip */ 579 { IMX415_WINMODE, 0x00 }, 580 { IMX415_ADDMODE, 0x00 }, 581 { IMX415_REVERSE, 0x00 }, 582 /* use RAW 10-bit mode */ 583 { IMX415_ADBIT, 0x00 }, 584 { IMX415_MDBIT, 0x00 }, 585 /* output VSYNC on XVS and low on XHS */ 586 { IMX415_OUTSEL, 0x22 }, 587 { IMX415_DRV, 0x00 }, 588 589 /* SONY magic registers */ 590 { CCI_REG8(0x32D4), 0x21 }, 591 { CCI_REG8(0x32EC), 0xA1 }, 592 { CCI_REG8(0x3452), 0x7F }, 593 { CCI_REG8(0x3453), 0x03 }, 594 { CCI_REG8(0x358A), 0x04 }, 595 { CCI_REG8(0x35A1), 0x02 }, 596 { CCI_REG8(0x36BC), 0x0C }, 597 { CCI_REG8(0x36CC), 0x53 }, 598 { CCI_REG8(0x36CD), 0x00 }, 599 { CCI_REG8(0x36CE), 0x3C }, 600 { CCI_REG8(0x36D0), 0x8C }, 601 { CCI_REG8(0x36D1), 0x00 }, 602 { CCI_REG8(0x36D2), 0x71 }, 603 { CCI_REG8(0x36D4), 0x3C }, 604 { CCI_REG8(0x36D6), 0x53 }, 605 { CCI_REG8(0x36D7), 0x00 }, 606 { CCI_REG8(0x36D8), 0x71 }, 607 { CCI_REG8(0x36DA), 0x8C }, 608 { CCI_REG8(0x36DB), 0x00 }, 609 { CCI_REG8(0x3724), 0x02 }, 610 { CCI_REG8(0x3726), 0x02 }, 611 { CCI_REG8(0x3732), 0x02 }, 612 { CCI_REG8(0x3734), 0x03 }, 613 { CCI_REG8(0x3736), 0x03 }, 614 { CCI_REG8(0x3742), 0x03 }, 615 { CCI_REG8(0x3862), 0xE0 }, 616 { CCI_REG8(0x38CC), 0x30 }, 617 { CCI_REG8(0x38CD), 0x2F }, 618 { CCI_REG8(0x395C), 0x0C }, 619 { CCI_REG8(0x3A42), 0xD1 }, 620 { CCI_REG8(0x3A4C), 0x77 }, 621 { CCI_REG8(0x3AE0), 0x02 }, 622 { CCI_REG8(0x3AEC), 0x0C }, 623 { CCI_REG8(0x3B00), 0x2E }, 624 { CCI_REG8(0x3B06), 0x29 }, 625 { CCI_REG8(0x3B98), 0x25 }, 626 { CCI_REG8(0x3B99), 0x21 }, 627 { CCI_REG8(0x3B9B), 0x13 }, 628 { CCI_REG8(0x3B9C), 0x13 }, 629 { CCI_REG8(0x3B9D), 0x13 }, 630 { CCI_REG8(0x3B9E), 0x13 }, 631 { CCI_REG8(0x3BA1), 0x00 }, 632 { CCI_REG8(0x3BA2), 0x06 }, 633 { CCI_REG8(0x3BA3), 0x0B }, 634 { CCI_REG8(0x3BA4), 0x10 }, 635 { CCI_REG8(0x3BA5), 0x14 }, 636 { CCI_REG8(0x3BA6), 0x18 }, 637 { CCI_REG8(0x3BA7), 0x1A }, 638 { CCI_REG8(0x3BA8), 0x1A }, 639 { CCI_REG8(0x3BA9), 0x1A }, 640 { CCI_REG8(0x3BAC), 0xED }, 641 { CCI_REG8(0x3BAD), 0x01 }, 642 { CCI_REG8(0x3BAE), 0xF6 }, 643 { CCI_REG8(0x3BAF), 0x02 }, 644 { CCI_REG8(0x3BB0), 0xA2 }, 645 { CCI_REG8(0x3BB1), 0x03 }, 646 { CCI_REG8(0x3BB2), 0xE0 }, 647 { CCI_REG8(0x3BB3), 0x03 }, 648 { CCI_REG8(0x3BB4), 0xE0 }, 649 { CCI_REG8(0x3BB5), 0x03 }, 650 { CCI_REG8(0x3BB6), 0xE0 }, 651 { CCI_REG8(0x3BB7), 0x03 }, 652 { CCI_REG8(0x3BB8), 0xE0 }, 653 { CCI_REG8(0x3BBA), 0xE0 }, 654 { CCI_REG8(0x3BBC), 0xDA }, 655 { CCI_REG8(0x3BBE), 0x88 }, 656 { CCI_REG8(0x3BC0), 0x44 }, 657 { CCI_REG8(0x3BC2), 0x7B }, 658 { CCI_REG8(0x3BC4), 0xA2 }, 659 { CCI_REG8(0x3BC8), 0xBD }, 660 { CCI_REG8(0x3BCA), 0xBD }, 661}; 662 663static inline struct imx415 *to_imx415(struct v4l2_subdev *sd) 664{ 665 return container_of(sd, struct imx415, subdev); 666} 667 668static int imx415_set_testpattern(struct imx415 *sensor, int val) 669{ 670 int ret = 0; 671 672 if (val) { 673 cci_write(sensor->regmap, IMX415_BLKLEVEL, 0x00, &ret); 674 cci_write(sensor->regmap, IMX415_TPG_EN_DUOUT, 0x01, &ret); 675 cci_write(sensor->regmap, IMX415_TPG_PATSEL_DUOUT, 676 val - 1, &ret); 677 cci_write(sensor->regmap, IMX415_TPG_COLORWIDTH, 0x01, &ret); 678 cci_write(sensor->regmap, IMX415_TESTCLKEN_MIPI, 0x20, &ret); 679 cci_write(sensor->regmap, IMX415_DIG_CLP_MODE, 0x00, &ret); 680 cci_write(sensor->regmap, IMX415_WRJ_OPEN, 0x00, &ret); 681 } else { 682 cci_write(sensor->regmap, IMX415_BLKLEVEL, 683 IMX415_BLKLEVEL_DEFAULT, &ret); 684 cci_write(sensor->regmap, IMX415_TPG_EN_DUOUT, 0x00, &ret); 685 cci_write(sensor->regmap, IMX415_TESTCLKEN_MIPI, 0x00, &ret); 686 cci_write(sensor->regmap, IMX415_DIG_CLP_MODE, 0x01, &ret); 687 cci_write(sensor->regmap, IMX415_WRJ_OPEN, 0x01, &ret); 688 } 689 return 0; 690} 691 692static int imx415_s_ctrl(struct v4l2_ctrl *ctrl) 693{ 694 struct imx415 *sensor = container_of(ctrl->handler, struct imx415, 695 ctrls); 696 const struct v4l2_mbus_framefmt *format; 697 struct v4l2_subdev_state *state; 698 u32 exposure_max; 699 unsigned int vmax; 700 unsigned int flip; 701 int ret; 702 703 state = v4l2_subdev_get_locked_active_state(&sensor->subdev); 704 format = v4l2_subdev_state_get_format(state, 0); 705 706 if (ctrl->id == V4L2_CID_VBLANK) { 707 exposure_max = format->height + ctrl->val - 708 IMX415_EXPOSURE_OFFSET; 709 __v4l2_ctrl_modify_range(sensor->exposure, 710 sensor->exposure->minimum, 711 exposure_max, sensor->exposure->step, 712 sensor->exposure->default_value); 713 } 714 715 if (!pm_runtime_get_if_in_use(sensor->dev)) 716 return 0; 717 718 switch (ctrl->id) { 719 case V4L2_CID_VBLANK: 720 ret = cci_write(sensor->regmap, IMX415_VMAX, 721 format->height + ctrl->val, NULL); 722 if (ret) 723 return ret; 724 /* 725 * Exposure is set based on VMAX which has just changed, so 726 * program exposure register as well 727 */ 728 ctrl = sensor->exposure; 729 fallthrough; 730 case V4L2_CID_EXPOSURE: 731 /* clamp the exposure value to VMAX. */ 732 vmax = format->height + sensor->vblank->cur.val; 733 ctrl->val = min_t(int, ctrl->val, vmax); 734 ret = cci_write(sensor->regmap, IMX415_SHR0, 735 vmax - ctrl->val, NULL); 736 break; 737 738 case V4L2_CID_ANALOGUE_GAIN: 739 /* analogue gain in 0.3 dB step size */ 740 ret = cci_write(sensor->regmap, IMX415_GAIN_PCG_0, 741 ctrl->val, NULL); 742 break; 743 744 case V4L2_CID_HFLIP: 745 case V4L2_CID_VFLIP: 746 flip = (sensor->hflip->val << IMX415_HREVERSE_SHIFT) | 747 (sensor->vflip->val << IMX415_VREVERSE_SHIFT); 748 ret = cci_write(sensor->regmap, IMX415_REVERSE, flip, NULL); 749 break; 750 751 case V4L2_CID_TEST_PATTERN: 752 ret = imx415_set_testpattern(sensor, ctrl->val); 753 break; 754 755 case V4L2_CID_HBLANK: 756 ret = cci_write(sensor->regmap, IMX415_HMAX, 757 (format->width + ctrl->val) / 758 IMX415_HMAX_MULTIPLIER, 759 NULL); 760 break; 761 762 default: 763 ret = -EINVAL; 764 break; 765 } 766 767 pm_runtime_put(sensor->dev); 768 769 return ret; 770} 771 772static const struct v4l2_ctrl_ops imx415_ctrl_ops = { 773 .s_ctrl = imx415_s_ctrl, 774}; 775 776static int imx415_ctrls_init(struct imx415 *sensor) 777{ 778 struct v4l2_fwnode_device_properties props; 779 struct v4l2_ctrl *ctrl; 780 const struct imx415_mode *cur_mode = &supported_modes[sensor->cur_mode]; 781 u64 lane_rate = cur_mode->lane_rate; 782 u32 exposure_max = IMX415_PIXEL_ARRAY_HEIGHT + 783 IMX415_PIXEL_ARRAY_VBLANK - 784 IMX415_EXPOSURE_OFFSET; 785 u32 hblank_min, hblank_max; 786 unsigned int i; 787 int ret; 788 789 ret = v4l2_fwnode_device_parse(sensor->dev, &props); 790 if (ret < 0) 791 return ret; 792 793 v4l2_ctrl_handler_init(&sensor->ctrls, 10); 794 795 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); ++i) { 796 if (lane_rate == link_freq_menu_items[i] * 2) 797 break; 798 } 799 if (i == ARRAY_SIZE(link_freq_menu_items)) { 800 return dev_err_probe(sensor->dev, -EINVAL, 801 "lane rate %llu not supported\n", 802 lane_rate); 803 } 804 805 ctrl = v4l2_ctrl_new_int_menu(&sensor->ctrls, &imx415_ctrl_ops, 806 V4L2_CID_LINK_FREQ, 807 ARRAY_SIZE(link_freq_menu_items) - 1, i, 808 link_freq_menu_items); 809 810 if (ctrl) 811 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; 812 813 sensor->exposure = v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops, 814 V4L2_CID_EXPOSURE, 4, 815 exposure_max, 1, exposure_max); 816 817 v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops, 818 V4L2_CID_ANALOGUE_GAIN, IMX415_AGAIN_MIN, 819 IMX415_AGAIN_MAX, IMX415_AGAIN_STEP, 820 IMX415_AGAIN_MIN); 821 822 hblank_min = (cur_mode->hmax_min[sensor->num_data_lanes == 2 ? 0 : 1] * 823 IMX415_HMAX_MULTIPLIER) - IMX415_PIXEL_ARRAY_WIDTH; 824 hblank_max = (IMX415_HMAX_MAX * IMX415_HMAX_MULTIPLIER) - 825 IMX415_PIXEL_ARRAY_WIDTH; 826 ctrl = v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops, 827 V4L2_CID_HBLANK, hblank_min, 828 hblank_max, IMX415_HMAX_MULTIPLIER, 829 hblank_min); 830 831 sensor->vblank = v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops, 832 V4L2_CID_VBLANK, 833 IMX415_PIXEL_ARRAY_VBLANK, 834 IMX415_VMAX_MAX - IMX415_PIXEL_ARRAY_HEIGHT, 835 1, IMX415_PIXEL_ARRAY_VBLANK); 836 837 v4l2_ctrl_new_std(&sensor->ctrls, NULL, V4L2_CID_PIXEL_RATE, 838 sensor->pixel_rate, sensor->pixel_rate, 1, 839 sensor->pixel_rate); 840 841 sensor->hflip = v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops, 842 V4L2_CID_HFLIP, 0, 1, 1, 0); 843 sensor->vflip = v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops, 844 V4L2_CID_VFLIP, 0, 1, 1, 0); 845 846 v4l2_ctrl_new_std_menu_items(&sensor->ctrls, &imx415_ctrl_ops, 847 V4L2_CID_TEST_PATTERN, 848 ARRAY_SIZE(imx415_test_pattern_menu) - 1, 849 0, 0, imx415_test_pattern_menu); 850 851 v4l2_ctrl_new_fwnode_properties(&sensor->ctrls, &imx415_ctrl_ops, 852 &props); 853 854 if (sensor->ctrls.error) { 855 dev_err_probe(sensor->dev, sensor->ctrls.error, 856 "failed to add controls\n"); 857 v4l2_ctrl_handler_free(&sensor->ctrls); 858 return sensor->ctrls.error; 859 } 860 sensor->subdev.ctrl_handler = &sensor->ctrls; 861 862 return 0; 863} 864 865static int imx415_set_mode(struct imx415 *sensor, int mode) 866{ 867 int ret = 0; 868 869 if (mode >= ARRAY_SIZE(supported_modes)) { 870 dev_err(sensor->dev, "Mode %d not supported\n", mode); 871 return -EINVAL; 872 } 873 874 cci_multi_reg_write(sensor->regmap, 875 supported_modes[mode].reg_list.regs, 876 supported_modes[mode].reg_list.num_of_regs, 877 &ret); 878 879 cci_multi_reg_write(sensor->regmap, 880 sensor->clk_params->regs, 881 IMX415_NUM_CLK_PARAM_REGS, 882 &ret); 883 884 ret = cci_write(sensor->regmap, IMX415_LANEMODE, 885 sensor->num_data_lanes == 2 ? IMX415_LANEMODE_2 : 886 IMX415_LANEMODE_4, 887 NULL); 888 889 return ret; 890} 891 892static int imx415_setup(struct imx415 *sensor, struct v4l2_subdev_state *state) 893{ 894 int ret; 895 896 ret = cci_multi_reg_write(sensor->regmap, 897 imx415_init_table, 898 ARRAY_SIZE(imx415_init_table), 899 NULL); 900 if (ret) 901 return ret; 902 903 return imx415_set_mode(sensor, sensor->cur_mode); 904} 905 906static int imx415_wakeup(struct imx415 *sensor) 907{ 908 int ret; 909 910 ret = cci_write(sensor->regmap, IMX415_MODE, 911 IMX415_MODE_OPERATING, NULL); 912 if (ret) 913 return ret; 914 915 /* 916 * According to the datasheet we have to wait at least 63 us after 917 * leaving standby mode. But this doesn't work even after 30 ms. 918 * So probably this should be 63 ms and therefore we wait for 80 ms. 919 */ 920 msleep(80); 921 922 return 0; 923} 924 925static int imx415_stream_on(struct imx415 *sensor) 926{ 927 int ret; 928 929 ret = imx415_wakeup(sensor); 930 return cci_write(sensor->regmap, IMX415_XMSTA, 931 IMX415_XMSTA_START, &ret); 932} 933 934static int imx415_stream_off(struct imx415 *sensor) 935{ 936 int ret; 937 938 ret = cci_write(sensor->regmap, IMX415_XMSTA, 939 IMX415_XMSTA_STOP, NULL); 940 return cci_write(sensor->regmap, IMX415_MODE, 941 IMX415_MODE_STANDBY, &ret); 942} 943 944static int imx415_s_stream(struct v4l2_subdev *sd, int enable) 945{ 946 struct imx415 *sensor = to_imx415(sd); 947 struct v4l2_subdev_state *state; 948 int ret; 949 950 state = v4l2_subdev_lock_and_get_active_state(sd); 951 952 if (!enable) { 953 ret = imx415_stream_off(sensor); 954 955 pm_runtime_put_autosuspend(sensor->dev); 956 957 goto unlock; 958 } 959 960 ret = pm_runtime_resume_and_get(sensor->dev); 961 if (ret < 0) 962 goto unlock; 963 964 ret = imx415_setup(sensor, state); 965 if (ret) 966 goto err_pm; 967 968 ret = __v4l2_ctrl_handler_setup(&sensor->ctrls); 969 if (ret < 0) 970 goto err_pm; 971 972 ret = imx415_stream_on(sensor); 973 if (ret) 974 goto err_pm; 975 976 ret = 0; 977 978unlock: 979 v4l2_subdev_unlock_state(state); 980 981 return ret; 982 983err_pm: 984 /* 985 * In case of error, turn the power off synchronously as the device 986 * likely has no other chance to recover. 987 */ 988 pm_runtime_put_sync(sensor->dev); 989 990 goto unlock; 991} 992 993static int imx415_enum_mbus_code(struct v4l2_subdev *sd, 994 struct v4l2_subdev_state *state, 995 struct v4l2_subdev_mbus_code_enum *code) 996{ 997 if (code->index != 0) 998 return -EINVAL; 999 1000 code->code = MEDIA_BUS_FMT_SGBRG10_1X10; 1001 1002 return 0; 1003} 1004 1005static int imx415_enum_frame_size(struct v4l2_subdev *sd, 1006 struct v4l2_subdev_state *state, 1007 struct v4l2_subdev_frame_size_enum *fse) 1008{ 1009 const struct v4l2_mbus_framefmt *format; 1010 1011 format = v4l2_subdev_state_get_format(state, fse->pad); 1012 1013 if (fse->index > 0 || fse->code != format->code) 1014 return -EINVAL; 1015 1016 fse->min_width = IMX415_PIXEL_ARRAY_WIDTH; 1017 fse->max_width = fse->min_width; 1018 fse->min_height = IMX415_PIXEL_ARRAY_HEIGHT; 1019 fse->max_height = fse->min_height; 1020 return 0; 1021} 1022 1023static int imx415_set_format(struct v4l2_subdev *sd, 1024 struct v4l2_subdev_state *state, 1025 struct v4l2_subdev_format *fmt) 1026{ 1027 struct v4l2_mbus_framefmt *format; 1028 1029 format = v4l2_subdev_state_get_format(state, fmt->pad); 1030 1031 format->width = fmt->format.width; 1032 format->height = fmt->format.height; 1033 format->code = MEDIA_BUS_FMT_SGBRG10_1X10; 1034 format->field = V4L2_FIELD_NONE; 1035 format->colorspace = V4L2_COLORSPACE_RAW; 1036 format->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 1037 format->quantization = V4L2_QUANTIZATION_DEFAULT; 1038 format->xfer_func = V4L2_XFER_FUNC_NONE; 1039 1040 fmt->format = *format; 1041 return 0; 1042} 1043 1044static int imx415_get_selection(struct v4l2_subdev *sd, 1045 struct v4l2_subdev_state *sd_state, 1046 struct v4l2_subdev_selection *sel) 1047{ 1048 switch (sel->target) { 1049 case V4L2_SEL_TGT_CROP: 1050 case V4L2_SEL_TGT_CROP_DEFAULT: 1051 case V4L2_SEL_TGT_CROP_BOUNDS: 1052 sel->r.top = IMX415_PIXEL_ARRAY_TOP; 1053 sel->r.left = IMX415_PIXEL_ARRAY_LEFT; 1054 sel->r.width = IMX415_PIXEL_ARRAY_WIDTH; 1055 sel->r.height = IMX415_PIXEL_ARRAY_HEIGHT; 1056 1057 return 0; 1058 } 1059 1060 return -EINVAL; 1061} 1062 1063static int imx415_init_state(struct v4l2_subdev *sd, 1064 struct v4l2_subdev_state *state) 1065{ 1066 struct v4l2_subdev_format format = { 1067 .format = { 1068 .width = IMX415_PIXEL_ARRAY_WIDTH, 1069 .height = IMX415_PIXEL_ARRAY_HEIGHT, 1070 }, 1071 }; 1072 1073 imx415_set_format(sd, state, &format); 1074 1075 return 0; 1076} 1077 1078static const struct v4l2_subdev_video_ops imx415_subdev_video_ops = { 1079 .s_stream = imx415_s_stream, 1080}; 1081 1082static const struct v4l2_subdev_pad_ops imx415_subdev_pad_ops = { 1083 .enum_mbus_code = imx415_enum_mbus_code, 1084 .enum_frame_size = imx415_enum_frame_size, 1085 .get_fmt = v4l2_subdev_get_fmt, 1086 .set_fmt = imx415_set_format, 1087 .get_selection = imx415_get_selection, 1088}; 1089 1090static const struct v4l2_subdev_ops imx415_subdev_ops = { 1091 .video = &imx415_subdev_video_ops, 1092 .pad = &imx415_subdev_pad_ops, 1093}; 1094 1095static const struct v4l2_subdev_internal_ops imx415_internal_ops = { 1096 .init_state = imx415_init_state, 1097}; 1098 1099static int imx415_subdev_init(struct imx415 *sensor) 1100{ 1101 struct i2c_client *client = to_i2c_client(sensor->dev); 1102 int ret; 1103 1104 v4l2_i2c_subdev_init(&sensor->subdev, client, &imx415_subdev_ops); 1105 sensor->subdev.internal_ops = &imx415_internal_ops; 1106 1107 ret = imx415_ctrls_init(sensor); 1108 if (ret) 1109 return ret; 1110 1111 sensor->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1112 sensor->pad.flags = MEDIA_PAD_FL_SOURCE; 1113 sensor->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1114 ret = media_entity_pads_init(&sensor->subdev.entity, 1, &sensor->pad); 1115 if (ret < 0) { 1116 v4l2_ctrl_handler_free(&sensor->ctrls); 1117 return ret; 1118 } 1119 1120 sensor->subdev.state_lock = sensor->subdev.ctrl_handler->lock; 1121 v4l2_subdev_init_finalize(&sensor->subdev); 1122 1123 return 0; 1124} 1125 1126static void imx415_subdev_cleanup(struct imx415 *sensor) 1127{ 1128 media_entity_cleanup(&sensor->subdev.entity); 1129 v4l2_ctrl_handler_free(&sensor->ctrls); 1130} 1131 1132static int imx415_power_on(struct imx415 *sensor) 1133{ 1134 int ret; 1135 1136 ret = regulator_bulk_enable(ARRAY_SIZE(sensor->supplies), 1137 sensor->supplies); 1138 if (ret < 0) 1139 return ret; 1140 1141 gpiod_set_value_cansleep(sensor->reset, 0); 1142 1143 udelay(1); 1144 1145 ret = clk_prepare_enable(sensor->clk); 1146 if (ret < 0) 1147 goto err_reset; 1148 1149 /* 1150 * Data sheet states that 20 us are required before communication start, 1151 * but this doesn't work in all cases. Use 100 us to be on the safe 1152 * side. 1153 */ 1154 usleep_range(100, 200); 1155 1156 return 0; 1157 1158err_reset: 1159 gpiod_set_value_cansleep(sensor->reset, 1); 1160 regulator_bulk_disable(ARRAY_SIZE(sensor->supplies), sensor->supplies); 1161 return ret; 1162} 1163 1164static void imx415_power_off(struct imx415 *sensor) 1165{ 1166 clk_disable_unprepare(sensor->clk); 1167 gpiod_set_value_cansleep(sensor->reset, 1); 1168 regulator_bulk_disable(ARRAY_SIZE(sensor->supplies), sensor->supplies); 1169} 1170 1171static int imx415_identify_model(struct imx415 *sensor) 1172{ 1173 int model, ret; 1174 u64 chip_id; 1175 1176 /* 1177 * While most registers can be read when the sensor is in standby, this 1178 * is not the case of the sensor info register :-( 1179 */ 1180 ret = imx415_wakeup(sensor); 1181 if (ret) 1182 return dev_err_probe(sensor->dev, ret, 1183 "failed to get sensor out of standby\n"); 1184 1185 ret = cci_read(sensor->regmap, IMX415_SENSOR_INFO, &chip_id, NULL); 1186 if (ret < 0) { 1187 dev_err_probe(sensor->dev, ret, 1188 "failed to read sensor information\n"); 1189 goto done; 1190 } 1191 1192 model = chip_id & IMX415_SENSOR_INFO_MASK; 1193 1194 switch (model) { 1195 case IMX415_CHIP_ID: 1196 dev_info(sensor->dev, "Detected IMX415 image sensor\n"); 1197 break; 1198 default: 1199 ret = dev_err_probe(sensor->dev, -ENODEV, 1200 "invalid device model 0x%04x\n", model); 1201 goto done; 1202 } 1203 1204 ret = 0; 1205 1206done: 1207 cci_write(sensor->regmap, IMX415_MODE, IMX415_MODE_STANDBY, &ret); 1208 return ret; 1209} 1210 1211static int imx415_check_inck(unsigned long inck, u64 link_frequency) 1212{ 1213 unsigned int i; 1214 1215 for (i = 0; i < ARRAY_SIZE(imx415_clk_params); ++i) { 1216 if ((imx415_clk_params[i].lane_rate == link_frequency * 2) && 1217 imx415_clk_params[i].inck == inck) 1218 break; 1219 } 1220 1221 if (i == ARRAY_SIZE(imx415_clk_params)) 1222 return -EINVAL; 1223 else 1224 return 0; 1225} 1226 1227static int imx415_parse_hw_config(struct imx415 *sensor) 1228{ 1229 struct v4l2_fwnode_endpoint bus_cfg = { 1230 .bus_type = V4L2_MBUS_CSI2_DPHY, 1231 }; 1232 struct fwnode_handle *ep; 1233 u64 lane_rate; 1234 unsigned long inck; 1235 unsigned int i, j; 1236 int ret; 1237 1238 for (i = 0; i < ARRAY_SIZE(sensor->supplies); ++i) 1239 sensor->supplies[i].supply = imx415_supply_names[i]; 1240 1241 ret = devm_regulator_bulk_get(sensor->dev, ARRAY_SIZE(sensor->supplies), 1242 sensor->supplies); 1243 if (ret) 1244 return dev_err_probe(sensor->dev, ret, 1245 "failed to get supplies\n"); 1246 1247 sensor->reset = devm_gpiod_get_optional(sensor->dev, "reset", 1248 GPIOD_OUT_HIGH); 1249 if (IS_ERR(sensor->reset)) 1250 return dev_err_probe(sensor->dev, PTR_ERR(sensor->reset), 1251 "failed to get reset GPIO\n"); 1252 1253 sensor->clk = devm_v4l2_sensor_clk_get(sensor->dev, NULL); 1254 if (IS_ERR(sensor->clk)) 1255 return dev_err_probe(sensor->dev, PTR_ERR(sensor->clk), 1256 "failed to get clock\n"); 1257 1258 ep = fwnode_graph_get_next_endpoint(dev_fwnode(sensor->dev), NULL); 1259 if (!ep) 1260 return -ENXIO; 1261 1262 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 1263 fwnode_handle_put(ep); 1264 if (ret) 1265 return ret; 1266 1267 switch (bus_cfg.bus.mipi_csi2.num_data_lanes) { 1268 case 2: 1269 case 4: 1270 sensor->num_data_lanes = bus_cfg.bus.mipi_csi2.num_data_lanes; 1271 break; 1272 default: 1273 ret = dev_err_probe(sensor->dev, -EINVAL, 1274 "invalid number of CSI2 data lanes %d\n", 1275 bus_cfg.bus.mipi_csi2.num_data_lanes); 1276 goto done_endpoint_free; 1277 } 1278 1279 if (!bus_cfg.nr_of_link_frequencies) { 1280 ret = dev_err_probe(sensor->dev, -EINVAL, 1281 "no link frequencies defined"); 1282 goto done_endpoint_free; 1283 } 1284 1285 /* 1286 * Check if there exists a sensor mode defined for current INCK, 1287 * number of lanes and given lane rates. 1288 */ 1289 inck = clk_get_rate(sensor->clk); 1290 for (i = 0; i < bus_cfg.nr_of_link_frequencies; ++i) { 1291 if (imx415_check_inck(inck, bus_cfg.link_frequencies[i])) { 1292 dev_dbg(sensor->dev, 1293 "INCK %lu Hz not supported for this link freq", 1294 inck); 1295 continue; 1296 } 1297 1298 for (j = 0; j < ARRAY_SIZE(supported_modes); ++j) { 1299 if (bus_cfg.link_frequencies[i] * 2 != 1300 supported_modes[j].lane_rate) 1301 continue; 1302 sensor->cur_mode = j; 1303 break; 1304 } 1305 if (j < ARRAY_SIZE(supported_modes)) 1306 break; 1307 } 1308 if (i == bus_cfg.nr_of_link_frequencies) { 1309 ret = dev_err_probe(sensor->dev, -EINVAL, 1310 "no valid sensor mode defined\n"); 1311 goto done_endpoint_free; 1312 } 1313 switch (inck) { 1314 case 27000000: 1315 case 37125000: 1316 case 74250000: 1317 sensor->pixel_rate = IMX415_PIXEL_RATE_74_25MHZ; 1318 break; 1319 case 24000000: 1320 case 72000000: 1321 sensor->pixel_rate = IMX415_PIXEL_RATE_72MHZ; 1322 break; 1323 } 1324 1325 lane_rate = supported_modes[sensor->cur_mode].lane_rate; 1326 for (i = 0; i < ARRAY_SIZE(imx415_clk_params); ++i) { 1327 if (lane_rate == imx415_clk_params[i].lane_rate && 1328 inck == imx415_clk_params[i].inck) { 1329 sensor->clk_params = &imx415_clk_params[i]; 1330 break; 1331 } 1332 } 1333 if (i == ARRAY_SIZE(imx415_clk_params)) { 1334 ret = dev_err_probe(sensor->dev, -EINVAL, 1335 "Mode %d not supported\n", 1336 sensor->cur_mode); 1337 goto done_endpoint_free; 1338 } 1339 1340 ret = 0; 1341 dev_dbg(sensor->dev, "clock: %lu Hz, lane_rate: %llu bps, lanes: %d\n", 1342 inck, lane_rate, sensor->num_data_lanes); 1343 1344done_endpoint_free: 1345 v4l2_fwnode_endpoint_free(&bus_cfg); 1346 1347 return ret; 1348} 1349 1350static int imx415_probe(struct i2c_client *client) 1351{ 1352 struct imx415 *sensor; 1353 int ret; 1354 1355 sensor = devm_kzalloc(&client->dev, sizeof(*sensor), GFP_KERNEL); 1356 if (!sensor) 1357 return -ENOMEM; 1358 1359 sensor->dev = &client->dev; 1360 1361 ret = imx415_parse_hw_config(sensor); 1362 if (ret) 1363 return ret; 1364 1365 sensor->regmap = devm_cci_regmap_init_i2c(client, 16); 1366 if (IS_ERR(sensor->regmap)) 1367 return PTR_ERR(sensor->regmap); 1368 1369 /* 1370 * Enable power management. The driver supports runtime PM, but needs to 1371 * work when runtime PM is disabled in the kernel. To that end, power 1372 * the sensor on manually here, identify it, and fully initialize it. 1373 */ 1374 ret = imx415_power_on(sensor); 1375 if (ret) 1376 return ret; 1377 1378 ret = imx415_identify_model(sensor); 1379 if (ret) 1380 goto err_power; 1381 1382 ret = imx415_subdev_init(sensor); 1383 if (ret) 1384 goto err_power; 1385 1386 /* 1387 * Enable runtime PM. As the device has been powered manually, mark it 1388 * as active, and increase the usage count without resuming the device. 1389 */ 1390 pm_runtime_set_active(sensor->dev); 1391 pm_runtime_get_noresume(sensor->dev); 1392 pm_runtime_enable(sensor->dev); 1393 1394 ret = v4l2_async_register_subdev_sensor(&sensor->subdev); 1395 if (ret < 0) 1396 goto err_pm; 1397 1398 /* 1399 * Finally, enable autosuspend and decrease the usage count. The device 1400 * will get suspended after the autosuspend delay, turning the power 1401 * off. 1402 */ 1403 pm_runtime_set_autosuspend_delay(sensor->dev, 1000); 1404 pm_runtime_use_autosuspend(sensor->dev); 1405 pm_runtime_put_autosuspend(sensor->dev); 1406 1407 return 0; 1408 1409err_pm: 1410 pm_runtime_disable(sensor->dev); 1411 pm_runtime_put_noidle(sensor->dev); 1412 imx415_subdev_cleanup(sensor); 1413err_power: 1414 imx415_power_off(sensor); 1415 return ret; 1416} 1417 1418static void imx415_remove(struct i2c_client *client) 1419{ 1420 struct v4l2_subdev *subdev = i2c_get_clientdata(client); 1421 struct imx415 *sensor = to_imx415(subdev); 1422 1423 v4l2_async_unregister_subdev(subdev); 1424 1425 imx415_subdev_cleanup(sensor); 1426 1427 /* 1428 * Disable runtime PM. In case runtime PM is disabled in the kernel, 1429 * make sure to turn power off manually. 1430 */ 1431 pm_runtime_disable(sensor->dev); 1432 if (!pm_runtime_status_suspended(sensor->dev)) 1433 imx415_power_off(sensor); 1434 pm_runtime_set_suspended(sensor->dev); 1435} 1436 1437static int imx415_runtime_resume(struct device *dev) 1438{ 1439 struct i2c_client *client = to_i2c_client(dev); 1440 struct v4l2_subdev *subdev = i2c_get_clientdata(client); 1441 struct imx415 *sensor = to_imx415(subdev); 1442 1443 return imx415_power_on(sensor); 1444} 1445 1446static int imx415_runtime_suspend(struct device *dev) 1447{ 1448 struct i2c_client *client = to_i2c_client(dev); 1449 struct v4l2_subdev *subdev = i2c_get_clientdata(client); 1450 struct imx415 *sensor = to_imx415(subdev); 1451 1452 imx415_power_off(sensor); 1453 1454 return 0; 1455} 1456 1457static DEFINE_RUNTIME_DEV_PM_OPS(imx415_pm_ops, imx415_runtime_suspend, 1458 imx415_runtime_resume, NULL); 1459 1460static const struct of_device_id imx415_of_match[] = { 1461 { .compatible = "sony,imx415" }, 1462 { /* sentinel */ } 1463}; 1464 1465MODULE_DEVICE_TABLE(of, imx415_of_match); 1466 1467static struct i2c_driver imx415_driver = { 1468 .probe = imx415_probe, 1469 .remove = imx415_remove, 1470 .driver = { 1471 .name = "imx415", 1472 .of_match_table = imx415_of_match, 1473 .pm = pm_ptr(&imx415_pm_ops), 1474 }, 1475}; 1476 1477module_i2c_driver(imx415_driver); 1478 1479MODULE_DESCRIPTION("Sony IMX415 image sensor driver"); 1480MODULE_AUTHOR("Gerald Loacker <gerald.loacker@wolfvision.net>"); 1481MODULE_AUTHOR("Michael Riesch <michael.riesch@wolfvision.net>"); 1482MODULE_LICENSE("GPL");
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