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imx290.c
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linux-6.19.14/drivers/media/i2c/imx290.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Sony IMX290 CMOS Image Sensor Driver 4 * 5 * Copyright (C) 2019 FRAMOS GmbH. 6 * 7 * Copyright (C) 2019 Linaro Ltd. 8 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 9 */ 10 11#include <linux/clk.h> 12#include <linux/delay.h> 13#include <linux/gpio/consumer.h> 14#include <linux/i2c.h> 15#include <linux/module.h> 16#include <linux/of.h> 17#include <linux/pm_runtime.h> 18#include <linux/regmap.h> 19#include <linux/regulator/consumer.h> 20 21#include <linux/unaligned.h> 22 23#include <media/media-entity.h> 24#include <media/v4l2-cci.h> 25#include <media/v4l2-ctrls.h> 26#include <media/v4l2-device.h> 27#include <media/v4l2-fwnode.h> 28#include <media/v4l2-subdev.h> 29 30#define IMX290_STANDBY CCI_REG8(0x3000) 31#define IMX290_REGHOLD CCI_REG8(0x3001) 32#define IMX290_XMSTA CCI_REG8(0x3002) 33#define IMX290_ADBIT CCI_REG8(0x3005) 34#define IMX290_ADBIT_10BIT (0 << 0) 35#define IMX290_ADBIT_12BIT (1 << 0) 36#define IMX290_CTRL_07 CCI_REG8(0x3007) 37#define IMX290_VREVERSE BIT(0) 38#define IMX290_HREVERSE BIT(1) 39#define IMX290_WINMODE_1080P (0 << 4) 40#define IMX290_WINMODE_720P (1 << 4) 41#define IMX290_WINMODE_CROP (4 << 4) 42#define IMX290_FR_FDG_SEL CCI_REG8(0x3009) 43#define IMX290_BLKLEVEL CCI_REG16_LE(0x300a) 44#define IMX290_GAIN CCI_REG8(0x3014) 45#define IMX290_VMAX CCI_REG24_LE(0x3018) 46#define IMX290_VMAX_MAX 0x3ffff 47#define IMX290_HMAX CCI_REG16_LE(0x301c) 48#define IMX290_HMAX_MAX 0xffff 49#define IMX290_SHS1 CCI_REG24_LE(0x3020) 50#define IMX290_WINWV_OB CCI_REG8(0x303a) 51#define IMX290_WINPV CCI_REG16_LE(0x303c) 52#define IMX290_WINWV CCI_REG16_LE(0x303e) 53#define IMX290_WINPH CCI_REG16_LE(0x3040) 54#define IMX290_WINWH CCI_REG16_LE(0x3042) 55#define IMX290_OUT_CTRL CCI_REG8(0x3046) 56#define IMX290_ODBIT_10BIT (0 << 0) 57#define IMX290_ODBIT_12BIT (1 << 0) 58#define IMX290_OPORTSEL_PARALLEL (0x0 << 4) 59#define IMX290_OPORTSEL_LVDS_2CH (0xd << 4) 60#define IMX290_OPORTSEL_LVDS_4CH (0xe << 4) 61#define IMX290_OPORTSEL_LVDS_8CH (0xf << 4) 62#define IMX290_XSOUTSEL CCI_REG8(0x304b) 63#define IMX290_XSOUTSEL_XVSOUTSEL_HIGH (0 << 0) 64#define IMX290_XSOUTSEL_XVSOUTSEL_VSYNC (2 << 0) 65#define IMX290_XSOUTSEL_XHSOUTSEL_HIGH (0 << 2) 66#define IMX290_XSOUTSEL_XHSOUTSEL_HSYNC (2 << 2) 67#define IMX290_INCKSEL1 CCI_REG8(0x305c) 68#define IMX290_INCKSEL2 CCI_REG8(0x305d) 69#define IMX290_INCKSEL3 CCI_REG8(0x305e) 70#define IMX290_INCKSEL4 CCI_REG8(0x305f) 71#define IMX290_PGCTRL CCI_REG8(0x308c) 72#define IMX290_ADBIT1 CCI_REG8(0x3129) 73#define IMX290_ADBIT1_10BIT 0x1d 74#define IMX290_ADBIT1_12BIT 0x00 75#define IMX290_INCKSEL5 CCI_REG8(0x315e) 76#define IMX290_INCKSEL6 CCI_REG8(0x3164) 77#define IMX290_ADBIT2 CCI_REG8(0x317c) 78#define IMX290_ADBIT2_10BIT 0x12 79#define IMX290_ADBIT2_12BIT 0x00 80#define IMX290_ADBIT3 CCI_REG8(0x31ec) 81#define IMX290_ADBIT3_10BIT 0x37 82#define IMX290_ADBIT3_12BIT 0x0e 83#define IMX290_REPETITION CCI_REG8(0x3405) 84#define IMX290_PHY_LANE_NUM CCI_REG8(0x3407) 85#define IMX290_OPB_SIZE_V CCI_REG8(0x3414) 86#define IMX290_Y_OUT_SIZE CCI_REG16_LE(0x3418) 87#define IMX290_CSI_DT_FMT CCI_REG16_LE(0x3441) 88#define IMX290_CSI_DT_FMT_RAW10 0x0a0a 89#define IMX290_CSI_DT_FMT_RAW12 0x0c0c 90#define IMX290_CSI_LANE_MODE CCI_REG8(0x3443) 91#define IMX290_EXTCK_FREQ CCI_REG16_LE(0x3444) 92#define IMX290_TCLKPOST CCI_REG16_LE(0x3446) 93#define IMX290_THSZERO CCI_REG16_LE(0x3448) 94#define IMX290_THSPREPARE CCI_REG16_LE(0x344a) 95#define IMX290_TCLKTRAIL CCI_REG16_LE(0x344c) 96#define IMX290_THSTRAIL CCI_REG16_LE(0x344e) 97#define IMX290_TCLKZERO CCI_REG16_LE(0x3450) 98#define IMX290_TCLKPREPARE CCI_REG16_LE(0x3452) 99#define IMX290_TLPX CCI_REG16_LE(0x3454) 100#define IMX290_X_OUT_SIZE CCI_REG16_LE(0x3472) 101#define IMX290_INCKSEL7 CCI_REG8(0x3480) 102 103#define IMX290_PGCTRL_REGEN BIT(0) 104#define IMX290_PGCTRL_THRU BIT(1) 105#define IMX290_PGCTRL_MODE(n) ((n) << 4) 106 107/* Number of lines by which exposure must be less than VMAX */ 108#define IMX290_EXPOSURE_OFFSET 2 109 110#define IMX290_PIXEL_RATE 148500000 111 112/* 113 * The IMX290 pixel array is organized as follows: 114 * 115 * +------------------------------------+ 116 * | Optical Black | } Vertical effective optical black (10) 117 * +---+------------------------------------+---+ 118 * | | | | } Effective top margin (8) 119 * | | +----------------------------+ | | \ 120 * | | | | | | | 121 * | | | | | | | 122 * | | | | | | | 123 * | | | Recording Pixel Area | | | | Recommended height (1080) 124 * | | | | | | | 125 * | | | | | | | 126 * | | | | | | | 127 * | | +----------------------------+ | | / 128 * | | | | } Effective bottom margin (9) 129 * +---+------------------------------------+---+ 130 * <-> <-> <--------------------------> <-> <-> 131 * \---- Ignored right margin (4) 132 * \-------- Effective right margin (9) 133 * \------------------------- Recommended width (1920) 134 * \----------------------------------------- Effective left margin (8) 135 * \--------------------------------------------- Ignored left margin (4) 136 * 137 * The optical black lines are output over CSI-2 with a separate data type. 138 * 139 * The pixel array is meant to have 1920x1080 usable pixels after image 140 * processing in an ISP. It has 8 (9) extra active pixels usable for color 141 * processing in the ISP on the top and left (bottom and right) sides of the 142 * image. In addition, 4 additional pixels are present on the left and right 143 * sides of the image, documented as "ignored area". 144 * 145 * As far as is understood, all pixels of the pixel array (ignored area, color 146 * processing margins and recording area) can be output by the sensor. 147 */ 148 149#define IMX290_PIXEL_ARRAY_WIDTH 1945 150#define IMX290_PIXEL_ARRAY_HEIGHT 1097 151#define IMX290_PIXEL_ARRAY_MARGIN_LEFT 12 152#define IMX290_PIXEL_ARRAY_MARGIN_RIGHT 13 153#define IMX290_PIXEL_ARRAY_MARGIN_TOP 8 154#define IMX290_PIXEL_ARRAY_MARGIN_BOTTOM 9 155#define IMX290_PIXEL_ARRAY_RECORDING_WIDTH 1920 156#define IMX290_PIXEL_ARRAY_RECORDING_HEIGHT 1080 157 158/* Equivalent value for 16bpp */ 159#define IMX290_BLACK_LEVEL_DEFAULT 3840 160 161#define IMX290_NUM_SUPPLIES 3 162 163enum imx290_colour_variant { 164 IMX290_VARIANT_COLOUR, 165 IMX290_VARIANT_MONO, 166 IMX290_VARIANT_MAX 167}; 168 169enum imx290_model { 170 IMX290_MODEL_IMX290LQR, 171 IMX290_MODEL_IMX290LLR, 172 IMX290_MODEL_IMX327LQR, 173 IMX290_MODEL_IMX462LQR, 174 IMX290_MODEL_IMX462LLR, 175}; 176 177struct imx290_model_info { 178 enum imx290_colour_variant colour_variant; 179 const struct cci_reg_sequence *init_regs; 180 size_t init_regs_num; 181 unsigned int max_analog_gain; 182 const char *name; 183}; 184 185enum imx290_clk_freq { 186 IMX290_CLK_37_125, 187 IMX290_CLK_74_25, 188 IMX290_NUM_CLK 189}; 190 191/* 192 * Clock configuration for registers INCKSEL1 to INCKSEL6. 193 */ 194struct imx290_clk_cfg { 195 u8 incksel1; 196 u8 incksel2; 197 u8 incksel3; 198 u8 incksel4; 199 u8 incksel5; 200 u8 incksel6; 201}; 202 203struct imx290_mode { 204 u32 width; 205 u32 height; 206 u32 hmax_min; 207 u32 vmax_min; 208 u8 link_freq_index; 209 u8 ctrl_07; 210 211 const struct cci_reg_sequence *data; 212 u32 data_size; 213 214 const struct imx290_clk_cfg *clk_cfg; 215}; 216 217struct imx290_csi_cfg { 218 u16 repetition; 219 u16 tclkpost; 220 u16 thszero; 221 u16 thsprepare; 222 u16 tclktrail; 223 u16 thstrail; 224 u16 tclkzero; 225 u16 tclkprepare; 226 u16 tlpx; 227}; 228 229struct imx290 { 230 struct device *dev; 231 struct clk *xclk; 232 struct regmap *regmap; 233 enum imx290_clk_freq xclk_idx; 234 u8 nlanes; 235 const struct imx290_model_info *model; 236 237 struct v4l2_subdev sd; 238 struct media_pad pad; 239 240 const struct imx290_mode *current_mode; 241 242 struct regulator_bulk_data supplies[IMX290_NUM_SUPPLIES]; 243 struct gpio_desc *rst_gpio; 244 245 struct v4l2_ctrl_handler ctrls; 246 struct v4l2_ctrl *link_freq; 247 struct v4l2_ctrl *hblank; 248 struct v4l2_ctrl *vblank; 249 struct v4l2_ctrl *exposure; 250 struct { 251 struct v4l2_ctrl *hflip; 252 struct v4l2_ctrl *vflip; 253 }; 254}; 255 256static inline struct imx290 *to_imx290(struct v4l2_subdev *_sd) 257{ 258 return container_of(_sd, struct imx290, sd); 259} 260 261/* ----------------------------------------------------------------------------- 262 * Modes and formats 263 */ 264 265static const struct cci_reg_sequence imx290_global_init_settings[] = { 266 { IMX290_WINWV_OB, 12 }, 267 { IMX290_WINPH, 0 }, 268 { IMX290_WINPV, 0 }, 269 { IMX290_WINWH, 1948 }, 270 { IMX290_WINWV, 1097 }, 271 { IMX290_XSOUTSEL, IMX290_XSOUTSEL_XVSOUTSEL_VSYNC | 272 IMX290_XSOUTSEL_XHSOUTSEL_HSYNC }, 273 { CCI_REG8(0x3012), 0x64 }, 274 { CCI_REG8(0x3013), 0x00 }, 275}; 276 277static const struct cci_reg_sequence imx290_global_init_settings_290[] = { 278 { CCI_REG8(0x300f), 0x00 }, 279 { CCI_REG8(0x3010), 0x21 }, 280 { CCI_REG8(0x3011), 0x00 }, 281 { CCI_REG8(0x3016), 0x09 }, 282 { CCI_REG8(0x3070), 0x02 }, 283 { CCI_REG8(0x3071), 0x11 }, 284 { CCI_REG8(0x309b), 0x10 }, 285 { CCI_REG8(0x309c), 0x22 }, 286 { CCI_REG8(0x30a2), 0x02 }, 287 { CCI_REG8(0x30a6), 0x20 }, 288 { CCI_REG8(0x30a8), 0x20 }, 289 { CCI_REG8(0x30aa), 0x20 }, 290 { CCI_REG8(0x30ac), 0x20 }, 291 { CCI_REG8(0x30b0), 0x43 }, 292 { CCI_REG8(0x3119), 0x9e }, 293 { CCI_REG8(0x311c), 0x1e }, 294 { CCI_REG8(0x311e), 0x08 }, 295 { CCI_REG8(0x3128), 0x05 }, 296 { CCI_REG8(0x313d), 0x83 }, 297 { CCI_REG8(0x3150), 0x03 }, 298 { CCI_REG8(0x317e), 0x00 }, 299 { CCI_REG8(0x32b8), 0x50 }, 300 { CCI_REG8(0x32b9), 0x10 }, 301 { CCI_REG8(0x32ba), 0x00 }, 302 { CCI_REG8(0x32bb), 0x04 }, 303 { CCI_REG8(0x32c8), 0x50 }, 304 { CCI_REG8(0x32c9), 0x10 }, 305 { CCI_REG8(0x32ca), 0x00 }, 306 { CCI_REG8(0x32cb), 0x04 }, 307 { CCI_REG8(0x332c), 0xd3 }, 308 { CCI_REG8(0x332d), 0x10 }, 309 { CCI_REG8(0x332e), 0x0d }, 310 { CCI_REG8(0x3358), 0x06 }, 311 { CCI_REG8(0x3359), 0xe1 }, 312 { CCI_REG8(0x335a), 0x11 }, 313 { CCI_REG8(0x3360), 0x1e }, 314 { CCI_REG8(0x3361), 0x61 }, 315 { CCI_REG8(0x3362), 0x10 }, 316 { CCI_REG8(0x33b0), 0x50 }, 317 { CCI_REG8(0x33b2), 0x1a }, 318 { CCI_REG8(0x33b3), 0x04 }, 319}; 320 321static const struct cci_reg_sequence imx290_global_init_settings_462[] = { 322 { CCI_REG8(0x300f), 0x00 }, 323 { CCI_REG8(0x3010), 0x21 }, 324 { CCI_REG8(0x3011), 0x02 }, 325 { CCI_REG8(0x3016), 0x09 }, 326 { CCI_REG8(0x3070), 0x02 }, 327 { CCI_REG8(0x3071), 0x11 }, 328 { CCI_REG8(0x309b), 0x10 }, 329 { CCI_REG8(0x309c), 0x22 }, 330 { CCI_REG8(0x30a2), 0x02 }, 331 { CCI_REG8(0x30a6), 0x20 }, 332 { CCI_REG8(0x30a8), 0x20 }, 333 { CCI_REG8(0x30aa), 0x20 }, 334 { CCI_REG8(0x30ac), 0x20 }, 335 { CCI_REG8(0x30b0), 0x43 }, 336 { CCI_REG8(0x3119), 0x9e }, 337 { CCI_REG8(0x311c), 0x1e }, 338 { CCI_REG8(0x311e), 0x08 }, 339 { CCI_REG8(0x3128), 0x05 }, 340 { CCI_REG8(0x313d), 0x83 }, 341 { CCI_REG8(0x3150), 0x03 }, 342 { CCI_REG8(0x317e), 0x00 }, 343 { CCI_REG8(0x32b8), 0x50 }, 344 { CCI_REG8(0x32b9), 0x10 }, 345 { CCI_REG8(0x32ba), 0x00 }, 346 { CCI_REG8(0x32bb), 0x04 }, 347 { CCI_REG8(0x32c8), 0x50 }, 348 { CCI_REG8(0x32c9), 0x10 }, 349 { CCI_REG8(0x32ca), 0x00 }, 350 { CCI_REG8(0x32cb), 0x04 }, 351 { CCI_REG8(0x332c), 0xd3 }, 352 { CCI_REG8(0x332d), 0x10 }, 353 { CCI_REG8(0x332e), 0x0d }, 354 { CCI_REG8(0x3358), 0x06 }, 355 { CCI_REG8(0x3359), 0xe1 }, 356 { CCI_REG8(0x335a), 0x11 }, 357 { CCI_REG8(0x3360), 0x1e }, 358 { CCI_REG8(0x3361), 0x61 }, 359 { CCI_REG8(0x3362), 0x10 }, 360 { CCI_REG8(0x33b0), 0x50 }, 361 { CCI_REG8(0x33b2), 0x1a }, 362 { CCI_REG8(0x33b3), 0x04 }, 363}; 364 365#define IMX290_NUM_CLK_REGS 2 366static const struct cci_reg_sequence xclk_regs[][IMX290_NUM_CLK_REGS] = { 367 [IMX290_CLK_37_125] = { 368 { IMX290_EXTCK_FREQ, (37125 * 256) / 1000 }, 369 { IMX290_INCKSEL7, 0x49 }, 370 }, 371 [IMX290_CLK_74_25] = { 372 { IMX290_EXTCK_FREQ, (74250 * 256) / 1000 }, 373 { IMX290_INCKSEL7, 0x92 }, 374 }, 375}; 376 377static const struct cci_reg_sequence imx290_global_init_settings_327[] = { 378 { CCI_REG8(0x3011), 0x02 }, 379 { CCI_REG8(0x309e), 0x4A }, 380 { CCI_REG8(0x309f), 0x4A }, 381 { CCI_REG8(0x313b), 0x61 }, 382}; 383 384static const struct cci_reg_sequence imx290_1080p_settings[] = { 385 /* mode settings */ 386 { IMX290_WINWV_OB, 12 }, 387 { IMX290_OPB_SIZE_V, 10 }, 388 { IMX290_X_OUT_SIZE, 1920 }, 389 { IMX290_Y_OUT_SIZE, 1080 }, 390}; 391 392static const struct cci_reg_sequence imx290_720p_settings[] = { 393 /* mode settings */ 394 { IMX290_WINWV_OB, 6 }, 395 { IMX290_OPB_SIZE_V, 4 }, 396 { IMX290_X_OUT_SIZE, 1280 }, 397 { IMX290_Y_OUT_SIZE, 720 }, 398}; 399 400static const struct cci_reg_sequence imx290_10bit_settings[] = { 401 { IMX290_ADBIT, IMX290_ADBIT_10BIT }, 402 { IMX290_OUT_CTRL, IMX290_ODBIT_10BIT }, 403 { IMX290_ADBIT1, IMX290_ADBIT1_10BIT }, 404 { IMX290_ADBIT2, IMX290_ADBIT2_10BIT }, 405 { IMX290_ADBIT3, IMX290_ADBIT3_10BIT }, 406 { IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW10 }, 407}; 408 409static const struct cci_reg_sequence imx290_12bit_settings[] = { 410 { IMX290_ADBIT, IMX290_ADBIT_12BIT }, 411 { IMX290_OUT_CTRL, IMX290_ODBIT_12BIT }, 412 { IMX290_ADBIT1, IMX290_ADBIT1_12BIT }, 413 { IMX290_ADBIT2, IMX290_ADBIT2_12BIT }, 414 { IMX290_ADBIT3, IMX290_ADBIT3_12BIT }, 415 { IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW12 }, 416}; 417 418static const struct imx290_csi_cfg imx290_csi_222_75mhz = { 419 /* 222.75MHz or 445.5Mbit/s per lane */ 420 .repetition = 0x10, 421 .tclkpost = 87, 422 .thszero = 55, 423 .thsprepare = 31, 424 .tclktrail = 31, 425 .thstrail = 31, 426 .tclkzero = 119, 427 .tclkprepare = 31, 428 .tlpx = 23, 429}; 430 431static const struct imx290_csi_cfg imx290_csi_445_5mhz = { 432 /* 445.5MHz or 891Mbit/s per lane */ 433 .repetition = 0x00, 434 .tclkpost = 119, 435 .thszero = 103, 436 .thsprepare = 71, 437 .tclktrail = 55, 438 .thstrail = 63, 439 .tclkzero = 255, 440 .tclkprepare = 63, 441 .tlpx = 55, 442}; 443 444static const struct imx290_csi_cfg imx290_csi_148_5mhz = { 445 /* 148.5MHz or 297Mbit/s per lane */ 446 .repetition = 0x10, 447 .tclkpost = 79, 448 .thszero = 47, 449 .thsprepare = 23, 450 .tclktrail = 23, 451 .thstrail = 23, 452 .tclkzero = 87, 453 .tclkprepare = 23, 454 .tlpx = 23, 455}; 456 457static const struct imx290_csi_cfg imx290_csi_297mhz = { 458 /* 297MHz or 594Mbit/s per lane */ 459 .repetition = 0x00, 460 .tclkpost = 103, 461 .thszero = 87, 462 .thsprepare = 47, 463 .tclktrail = 39, 464 .thstrail = 47, 465 .tclkzero = 191, 466 .tclkprepare = 47, 467 .tlpx = 39, 468}; 469 470/* supported link frequencies */ 471#define FREQ_INDEX_1080P 0 472#define FREQ_INDEX_720P 1 473static const s64 imx290_link_freq_2lanes[] = { 474 [FREQ_INDEX_1080P] = 445500000, 475 [FREQ_INDEX_720P] = 297000000, 476}; 477 478static const s64 imx290_link_freq_4lanes[] = { 479 [FREQ_INDEX_1080P] = 222750000, 480 [FREQ_INDEX_720P] = 148500000, 481}; 482 483/* 484 * In this function and in the similar ones below We rely on imx290_probe() 485 * to ensure that nlanes is either 2 or 4. 486 */ 487static inline const s64 *imx290_link_freqs_ptr(const struct imx290 *imx290) 488{ 489 if (imx290->nlanes == 2) 490 return imx290_link_freq_2lanes; 491 else 492 return imx290_link_freq_4lanes; 493} 494 495static inline int imx290_link_freqs_num(const struct imx290 *imx290) 496{ 497 if (imx290->nlanes == 2) 498 return ARRAY_SIZE(imx290_link_freq_2lanes); 499 else 500 return ARRAY_SIZE(imx290_link_freq_4lanes); 501} 502 503static const struct imx290_clk_cfg imx290_1080p_clock_config[] = { 504 [IMX290_CLK_37_125] = { 505 /* 37.125MHz clock config */ 506 .incksel1 = 0x18, 507 .incksel2 = 0x03, 508 .incksel3 = 0x20, 509 .incksel4 = 0x01, 510 .incksel5 = 0x1a, 511 .incksel6 = 0x1a, 512 }, 513 [IMX290_CLK_74_25] = { 514 /* 74.25MHz clock config */ 515 .incksel1 = 0x0c, 516 .incksel2 = 0x03, 517 .incksel3 = 0x10, 518 .incksel4 = 0x01, 519 .incksel5 = 0x1b, 520 .incksel6 = 0x1b, 521 }, 522}; 523 524static const struct imx290_clk_cfg imx290_720p_clock_config[] = { 525 [IMX290_CLK_37_125] = { 526 /* 37.125MHz clock config */ 527 .incksel1 = 0x20, 528 .incksel2 = 0x00, 529 .incksel3 = 0x20, 530 .incksel4 = 0x01, 531 .incksel5 = 0x1a, 532 .incksel6 = 0x1a, 533 }, 534 [IMX290_CLK_74_25] = { 535 /* 74.25MHz clock config */ 536 .incksel1 = 0x10, 537 .incksel2 = 0x00, 538 .incksel3 = 0x10, 539 .incksel4 = 0x01, 540 .incksel5 = 0x1b, 541 .incksel6 = 0x1b, 542 }, 543}; 544 545/* Mode configs */ 546static const struct imx290_mode imx290_modes_2lanes[] = { 547 { 548 .width = 1920, 549 .height = 1080, 550 .hmax_min = 2200, 551 .vmax_min = 1125, 552 .link_freq_index = FREQ_INDEX_1080P, 553 .ctrl_07 = IMX290_WINMODE_1080P, 554 .data = imx290_1080p_settings, 555 .data_size = ARRAY_SIZE(imx290_1080p_settings), 556 .clk_cfg = imx290_1080p_clock_config, 557 }, 558 { 559 .width = 1280, 560 .height = 720, 561 .hmax_min = 3300, 562 .vmax_min = 750, 563 .link_freq_index = FREQ_INDEX_720P, 564 .ctrl_07 = IMX290_WINMODE_720P, 565 .data = imx290_720p_settings, 566 .data_size = ARRAY_SIZE(imx290_720p_settings), 567 .clk_cfg = imx290_720p_clock_config, 568 }, 569}; 570 571static const struct imx290_mode imx290_modes_4lanes[] = { 572 { 573 .width = 1920, 574 .height = 1080, 575 .hmax_min = 2200, 576 .vmax_min = 1125, 577 .link_freq_index = FREQ_INDEX_1080P, 578 .ctrl_07 = IMX290_WINMODE_1080P, 579 .data = imx290_1080p_settings, 580 .data_size = ARRAY_SIZE(imx290_1080p_settings), 581 .clk_cfg = imx290_1080p_clock_config, 582 }, 583 { 584 .width = 1280, 585 .height = 720, 586 .hmax_min = 3300, 587 .vmax_min = 750, 588 .link_freq_index = FREQ_INDEX_720P, 589 .ctrl_07 = IMX290_WINMODE_720P, 590 .data = imx290_720p_settings, 591 .data_size = ARRAY_SIZE(imx290_720p_settings), 592 .clk_cfg = imx290_720p_clock_config, 593 }, 594}; 595 596static inline const struct imx290_mode *imx290_modes_ptr(const struct imx290 *imx290) 597{ 598 if (imx290->nlanes == 2) 599 return imx290_modes_2lanes; 600 else 601 return imx290_modes_4lanes; 602} 603 604static inline int imx290_modes_num(const struct imx290 *imx290) 605{ 606 if (imx290->nlanes == 2) 607 return ARRAY_SIZE(imx290_modes_2lanes); 608 else 609 return ARRAY_SIZE(imx290_modes_4lanes); 610} 611 612struct imx290_format_info { 613 u32 code[IMX290_VARIANT_MAX]; 614 u8 bpp; 615 const struct cci_reg_sequence *regs; 616 unsigned int num_regs; 617}; 618 619static const struct imx290_format_info imx290_formats[] = { 620 { 621 .code = { 622 [IMX290_VARIANT_COLOUR] = MEDIA_BUS_FMT_SRGGB10_1X10, 623 [IMX290_VARIANT_MONO] = MEDIA_BUS_FMT_Y10_1X10 624 }, 625 .bpp = 10, 626 .regs = imx290_10bit_settings, 627 .num_regs = ARRAY_SIZE(imx290_10bit_settings), 628 }, { 629 .code = { 630 [IMX290_VARIANT_COLOUR] = MEDIA_BUS_FMT_SRGGB12_1X12, 631 [IMX290_VARIANT_MONO] = MEDIA_BUS_FMT_Y12_1X12 632 }, 633 .bpp = 12, 634 .regs = imx290_12bit_settings, 635 .num_regs = ARRAY_SIZE(imx290_12bit_settings), 636 } 637}; 638 639static const struct imx290_format_info * 640imx290_format_info(const struct imx290 *imx290, u32 code) 641{ 642 unsigned int i; 643 644 for (i = 0; i < ARRAY_SIZE(imx290_formats); ++i) { 645 const struct imx290_format_info *info = &imx290_formats[i]; 646 647 if (info->code[imx290->model->colour_variant] == code) 648 return info; 649 } 650 651 return NULL; 652} 653 654static int imx290_set_register_array(struct imx290 *imx290, 655 const struct cci_reg_sequence *settings, 656 unsigned int num_settings) 657{ 658 int ret; 659 660 ret = cci_multi_reg_write(imx290->regmap, settings, num_settings, NULL); 661 if (ret < 0) 662 return ret; 663 664 /* Provide 10ms settle time */ 665 usleep_range(10000, 11000); 666 667 return 0; 668} 669 670static int imx290_set_clock(struct imx290 *imx290) 671{ 672 const struct imx290_mode *mode = imx290->current_mode; 673 enum imx290_clk_freq clk_idx = imx290->xclk_idx; 674 const struct imx290_clk_cfg *clk_cfg = &mode->clk_cfg[clk_idx]; 675 int ret; 676 677 ret = imx290_set_register_array(imx290, xclk_regs[clk_idx], 678 IMX290_NUM_CLK_REGS); 679 680 cci_write(imx290->regmap, IMX290_INCKSEL1, clk_cfg->incksel1, &ret); 681 cci_write(imx290->regmap, IMX290_INCKSEL2, clk_cfg->incksel2, &ret); 682 cci_write(imx290->regmap, IMX290_INCKSEL3, clk_cfg->incksel3, &ret); 683 cci_write(imx290->regmap, IMX290_INCKSEL4, clk_cfg->incksel4, &ret); 684 cci_write(imx290->regmap, IMX290_INCKSEL5, clk_cfg->incksel5, &ret); 685 cci_write(imx290->regmap, IMX290_INCKSEL6, clk_cfg->incksel6, &ret); 686 687 return ret; 688} 689 690static int imx290_set_data_lanes(struct imx290 *imx290) 691{ 692 int ret = 0; 693 694 cci_write(imx290->regmap, IMX290_PHY_LANE_NUM, imx290->nlanes - 1, 695 &ret); 696 cci_write(imx290->regmap, IMX290_CSI_LANE_MODE, imx290->nlanes - 1, 697 &ret); 698 cci_write(imx290->regmap, IMX290_FR_FDG_SEL, 0x01, &ret); 699 700 return ret; 701} 702 703static int imx290_set_black_level(struct imx290 *imx290, 704 const struct v4l2_mbus_framefmt *format, 705 unsigned int black_level, int *err) 706{ 707 unsigned int bpp = imx290_format_info(imx290, format->code)->bpp; 708 709 return cci_write(imx290->regmap, IMX290_BLKLEVEL, 710 black_level >> (16 - bpp), err); 711} 712 713static int imx290_set_csi_config(struct imx290 *imx290) 714{ 715 const s64 *link_freqs = imx290_link_freqs_ptr(imx290); 716 const struct imx290_csi_cfg *csi_cfg; 717 int ret = 0; 718 719 switch (link_freqs[imx290->current_mode->link_freq_index]) { 720 case 445500000: 721 csi_cfg = &imx290_csi_445_5mhz; 722 break; 723 case 297000000: 724 csi_cfg = &imx290_csi_297mhz; 725 break; 726 case 222750000: 727 csi_cfg = &imx290_csi_222_75mhz; 728 break; 729 case 148500000: 730 csi_cfg = &imx290_csi_148_5mhz; 731 break; 732 default: 733 return -EINVAL; 734 } 735 736 cci_write(imx290->regmap, IMX290_REPETITION, csi_cfg->repetition, &ret); 737 cci_write(imx290->regmap, IMX290_TCLKPOST, csi_cfg->tclkpost, &ret); 738 cci_write(imx290->regmap, IMX290_THSZERO, csi_cfg->thszero, &ret); 739 cci_write(imx290->regmap, IMX290_THSPREPARE, csi_cfg->thsprepare, &ret); 740 cci_write(imx290->regmap, IMX290_TCLKTRAIL, csi_cfg->tclktrail, &ret); 741 cci_write(imx290->regmap, IMX290_THSTRAIL, csi_cfg->thstrail, &ret); 742 cci_write(imx290->regmap, IMX290_TCLKZERO, csi_cfg->tclkzero, &ret); 743 cci_write(imx290->regmap, IMX290_TCLKPREPARE, csi_cfg->tclkprepare, 744 &ret); 745 cci_write(imx290->regmap, IMX290_TLPX, csi_cfg->tlpx, &ret); 746 747 return ret; 748} 749 750static int imx290_setup_format(struct imx290 *imx290, 751 const struct v4l2_mbus_framefmt *format) 752{ 753 const struct imx290_format_info *info; 754 int ret; 755 756 info = imx290_format_info(imx290, format->code); 757 758 ret = imx290_set_register_array(imx290, info->regs, info->num_regs); 759 if (ret < 0) { 760 dev_err(imx290->dev, "Could not set format registers\n"); 761 return ret; 762 } 763 764 return imx290_set_black_level(imx290, format, 765 IMX290_BLACK_LEVEL_DEFAULT, &ret); 766} 767 768/* ---------------------------------------------------------------------------- 769 * Controls 770 */ 771static void imx290_exposure_update(struct imx290 *imx290, 772 const struct imx290_mode *mode) 773{ 774 unsigned int exposure_max; 775 776 exposure_max = imx290->vblank->val + mode->height - 777 IMX290_EXPOSURE_OFFSET; 778 __v4l2_ctrl_modify_range(imx290->exposure, 1, exposure_max, 1, 779 exposure_max); 780} 781 782static int imx290_set_ctrl(struct v4l2_ctrl *ctrl) 783{ 784 struct imx290 *imx290 = container_of(ctrl->handler, 785 struct imx290, ctrls); 786 const struct v4l2_mbus_framefmt *format; 787 struct v4l2_subdev_state *state; 788 int ret = 0, vmax; 789 790 /* 791 * Return immediately for controls that don't need to be applied to the 792 * device. 793 */ 794 if (ctrl->flags & V4L2_CTRL_FLAG_READ_ONLY) 795 return 0; 796 797 if (ctrl->id == V4L2_CID_VBLANK) { 798 /* Changing vblank changes the allowed range for exposure. */ 799 imx290_exposure_update(imx290, imx290->current_mode); 800 } 801 802 /* V4L2 controls values will be applied only when power is already up */ 803 if (!pm_runtime_get_if_in_use(imx290->dev)) 804 return 0; 805 806 state = v4l2_subdev_get_locked_active_state(&imx290->sd); 807 format = v4l2_subdev_state_get_format(state, 0); 808 809 switch (ctrl->id) { 810 case V4L2_CID_ANALOGUE_GAIN: 811 ret = cci_write(imx290->regmap, IMX290_GAIN, ctrl->val, NULL); 812 break; 813 814 case V4L2_CID_VBLANK: 815 ret = cci_write(imx290->regmap, IMX290_VMAX, 816 ctrl->val + imx290->current_mode->height, NULL); 817 /* 818 * Due to the way that exposure is programmed in this sensor in 819 * relation to VMAX, we have to reprogramme it whenever VMAX is 820 * changed. 821 * Update ctrl so that the V4L2_CID_EXPOSURE case can refer to 822 * it. 823 */ 824 ctrl = imx290->exposure; 825 fallthrough; 826 case V4L2_CID_EXPOSURE: 827 vmax = imx290->vblank->val + imx290->current_mode->height; 828 ret = cci_write(imx290->regmap, IMX290_SHS1, 829 vmax - ctrl->val - 1, NULL); 830 break; 831 832 case V4L2_CID_TEST_PATTERN: 833 if (ctrl->val) { 834 imx290_set_black_level(imx290, format, 0, &ret); 835 usleep_range(10000, 11000); 836 cci_write(imx290->regmap, IMX290_PGCTRL, 837 (u8)(IMX290_PGCTRL_REGEN | 838 IMX290_PGCTRL_THRU | 839 IMX290_PGCTRL_MODE(ctrl->val)), &ret); 840 } else { 841 cci_write(imx290->regmap, IMX290_PGCTRL, 0x00, &ret); 842 usleep_range(10000, 11000); 843 imx290_set_black_level(imx290, format, 844 IMX290_BLACK_LEVEL_DEFAULT, &ret); 845 } 846 break; 847 848 case V4L2_CID_HBLANK: 849 ret = cci_write(imx290->regmap, IMX290_HMAX, 850 ctrl->val + imx290->current_mode->width, NULL); 851 break; 852 853 case V4L2_CID_HFLIP: 854 case V4L2_CID_VFLIP: 855 { 856 u32 reg; 857 858 reg = imx290->current_mode->ctrl_07; 859 if (imx290->hflip->val) 860 reg |= IMX290_HREVERSE; 861 if (imx290->vflip->val) 862 reg |= IMX290_VREVERSE; 863 ret = cci_write(imx290->regmap, IMX290_CTRL_07, reg, NULL); 864 break; 865 } 866 867 default: 868 ret = -EINVAL; 869 break; 870 } 871 872 pm_runtime_put_autosuspend(imx290->dev); 873 874 return ret; 875} 876 877static const struct v4l2_ctrl_ops imx290_ctrl_ops = { 878 .s_ctrl = imx290_set_ctrl, 879}; 880 881static const char * const imx290_test_pattern_menu[] = { 882 "Disabled", 883 "Sequence Pattern 1", 884 "Horizontal Color-bar Chart", 885 "Vertical Color-bar Chart", 886 "Sequence Pattern 2", 887 "Gradation Pattern 1", 888 "Gradation Pattern 2", 889 "000/555h Toggle Pattern", 890}; 891 892static void imx290_ctrl_update(struct imx290 *imx290, 893 const struct imx290_mode *mode) 894{ 895 unsigned int hblank_min = mode->hmax_min - mode->width; 896 unsigned int hblank_max = IMX290_HMAX_MAX - mode->width; 897 unsigned int vblank_min = mode->vmax_min - mode->height; 898 unsigned int vblank_max = IMX290_VMAX_MAX - mode->height; 899 900 __v4l2_ctrl_s_ctrl(imx290->link_freq, mode->link_freq_index); 901 902 __v4l2_ctrl_modify_range(imx290->hblank, hblank_min, hblank_max, 1, 903 hblank_min); 904 __v4l2_ctrl_modify_range(imx290->vblank, vblank_min, vblank_max, 1, 905 vblank_min); 906} 907 908static int imx290_ctrl_init(struct imx290 *imx290) 909{ 910 struct v4l2_fwnode_device_properties props; 911 int ret; 912 913 ret = v4l2_fwnode_device_parse(imx290->dev, &props); 914 if (ret < 0) 915 return ret; 916 917 v4l2_ctrl_handler_init(&imx290->ctrls, 11); 918 919 /* 920 * The sensor has an analog gain and a digital gain, both controlled 921 * through a single gain value, expressed in 0.3dB increments. Values 922 * from 0.0dB (0) to 30.0dB (100) apply analog gain only, higher values 923 * up to 72.0dB (240) add further digital gain. Limit the range to 924 * analog gain only, support for digital gain can be added separately 925 * if needed. 926 */ 927 v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 928 V4L2_CID_ANALOGUE_GAIN, 0, 929 imx290->model->max_analog_gain, 1, 0); 930 931 /* 932 * Correct range will be determined through imx290_ctrl_update setting 933 * V4L2_CID_VBLANK. 934 */ 935 imx290->exposure = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 936 V4L2_CID_EXPOSURE, 1, 65535, 1, 937 65535); 938 939 /* 940 * Set the link frequency, pixel rate, horizontal blanking and vertical 941 * blanking to hardcoded values, they will be updated by 942 * imx290_ctrl_update(). 943 */ 944 imx290->link_freq = 945 v4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops, 946 V4L2_CID_LINK_FREQ, 947 imx290_link_freqs_num(imx290) - 1, 0, 948 imx290_link_freqs_ptr(imx290)); 949 if (imx290->link_freq) 950 imx290->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 951 952 v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, V4L2_CID_PIXEL_RATE, 953 IMX290_PIXEL_RATE, IMX290_PIXEL_RATE, 1, 954 IMX290_PIXEL_RATE); 955 956 v4l2_ctrl_new_std_menu_items(&imx290->ctrls, &imx290_ctrl_ops, 957 V4L2_CID_TEST_PATTERN, 958 ARRAY_SIZE(imx290_test_pattern_menu) - 1, 959 0, 0, imx290_test_pattern_menu); 960 961 /* 962 * Actual range will be set from imx290_ctrl_update later in the probe. 963 */ 964 imx290->hblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 965 V4L2_CID_HBLANK, 1, 1, 1, 1); 966 967 imx290->vblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 968 V4L2_CID_VBLANK, 1, 1, 1, 1); 969 970 imx290->hflip = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 971 V4L2_CID_HFLIP, 0, 1, 1, 0); 972 imx290->vflip = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 973 V4L2_CID_VFLIP, 0, 1, 1, 0); 974 v4l2_ctrl_cluster(2, &imx290->hflip); 975 976 v4l2_ctrl_new_fwnode_properties(&imx290->ctrls, &imx290_ctrl_ops, 977 &props); 978 979 imx290->sd.ctrl_handler = &imx290->ctrls; 980 981 if (imx290->ctrls.error) { 982 ret = imx290->ctrls.error; 983 v4l2_ctrl_handler_free(&imx290->ctrls); 984 return ret; 985 } 986 987 return 0; 988} 989 990/* ---------------------------------------------------------------------------- 991 * Subdev operations 992 */ 993 994/* Start streaming */ 995static int imx290_start_streaming(struct imx290 *imx290, 996 struct v4l2_subdev_state *state) 997{ 998 const struct v4l2_mbus_framefmt *format; 999 int ret; 1000 1001 /* Set init register settings */ 1002 ret = imx290_set_register_array(imx290, imx290_global_init_settings, 1003 ARRAY_SIZE(imx290_global_init_settings)); 1004 if (ret < 0) { 1005 dev_err(imx290->dev, "Could not set init registers\n"); 1006 return ret; 1007 } 1008 1009 /* Set mdel specific init register settings */ 1010 ret = imx290_set_register_array(imx290, imx290->model->init_regs, 1011 imx290->model->init_regs_num); 1012 if (ret < 0) { 1013 dev_err(imx290->dev, "Could not set model specific init registers\n"); 1014 return ret; 1015 } 1016 1017 /* Set clock parameters based on mode and xclk */ 1018 ret = imx290_set_clock(imx290); 1019 if (ret < 0) { 1020 dev_err(imx290->dev, "Could not set clocks - %d\n", ret); 1021 return ret; 1022 } 1023 1024 /* Set data lane count */ 1025 ret = imx290_set_data_lanes(imx290); 1026 if (ret < 0) { 1027 dev_err(imx290->dev, "Could not set data lanes - %d\n", ret); 1028 return ret; 1029 } 1030 1031 ret = imx290_set_csi_config(imx290); 1032 if (ret < 0) { 1033 dev_err(imx290->dev, "Could not set csi cfg - %d\n", ret); 1034 return ret; 1035 } 1036 1037 /* Apply the register values related to current frame format */ 1038 format = v4l2_subdev_state_get_format(state, 0); 1039 ret = imx290_setup_format(imx290, format); 1040 if (ret < 0) { 1041 dev_err(imx290->dev, "Could not set frame format - %d\n", ret); 1042 return ret; 1043 } 1044 1045 /* Apply default values of current mode */ 1046 ret = imx290_set_register_array(imx290, imx290->current_mode->data, 1047 imx290->current_mode->data_size); 1048 if (ret < 0) { 1049 dev_err(imx290->dev, "Could not set current mode - %d\n", ret); 1050 return ret; 1051 } 1052 1053 /* Apply customized values from user */ 1054 ret = __v4l2_ctrl_handler_setup(imx290->sd.ctrl_handler); 1055 if (ret) { 1056 dev_err(imx290->dev, "Could not sync v4l2 controls - %d\n", ret); 1057 return ret; 1058 } 1059 1060 cci_write(imx290->regmap, IMX290_STANDBY, 0x00, &ret); 1061 1062 msleep(30); 1063 1064 /* Start streaming */ 1065 return cci_write(imx290->regmap, IMX290_XMSTA, 0x00, &ret); 1066} 1067 1068/* Stop streaming */ 1069static int imx290_stop_streaming(struct imx290 *imx290) 1070{ 1071 int ret = 0; 1072 1073 cci_write(imx290->regmap, IMX290_STANDBY, 0x01, &ret); 1074 1075 msleep(30); 1076 1077 return cci_write(imx290->regmap, IMX290_XMSTA, 0x01, &ret); 1078} 1079 1080static int imx290_set_stream(struct v4l2_subdev *sd, int enable) 1081{ 1082 struct imx290 *imx290 = to_imx290(sd); 1083 struct v4l2_subdev_state *state; 1084 int ret = 0; 1085 1086 state = v4l2_subdev_lock_and_get_active_state(sd); 1087 1088 if (enable) { 1089 ret = pm_runtime_resume_and_get(imx290->dev); 1090 if (ret < 0) 1091 goto unlock; 1092 1093 ret = imx290_start_streaming(imx290, state); 1094 if (ret) { 1095 dev_err(imx290->dev, "Start stream failed\n"); 1096 pm_runtime_put_sync(imx290->dev); 1097 goto unlock; 1098 } 1099 } else { 1100 imx290_stop_streaming(imx290); 1101 pm_runtime_put_autosuspend(imx290->dev); 1102 } 1103 1104 /* 1105 * vflip and hflip should not be changed during streaming as the sensor 1106 * will produce an invalid frame. 1107 */ 1108 __v4l2_ctrl_grab(imx290->vflip, enable); 1109 __v4l2_ctrl_grab(imx290->hflip, enable); 1110 1111unlock: 1112 v4l2_subdev_unlock_state(state); 1113 return ret; 1114} 1115 1116static int imx290_enum_mbus_code(struct v4l2_subdev *sd, 1117 struct v4l2_subdev_state *sd_state, 1118 struct v4l2_subdev_mbus_code_enum *code) 1119{ 1120 const struct imx290 *imx290 = to_imx290(sd); 1121 1122 if (code->index >= ARRAY_SIZE(imx290_formats)) 1123 return -EINVAL; 1124 1125 code->code = imx290_formats[code->index].code[imx290->model->colour_variant]; 1126 1127 return 0; 1128} 1129 1130static int imx290_enum_frame_size(struct v4l2_subdev *sd, 1131 struct v4l2_subdev_state *sd_state, 1132 struct v4l2_subdev_frame_size_enum *fse) 1133{ 1134 const struct imx290 *imx290 = to_imx290(sd); 1135 const struct imx290_mode *imx290_modes = imx290_modes_ptr(imx290); 1136 1137 if (!imx290_format_info(imx290, fse->code)) 1138 return -EINVAL; 1139 1140 if (fse->index >= imx290_modes_num(imx290)) 1141 return -EINVAL; 1142 1143 fse->min_width = imx290_modes[fse->index].width; 1144 fse->max_width = imx290_modes[fse->index].width; 1145 fse->min_height = imx290_modes[fse->index].height; 1146 fse->max_height = imx290_modes[fse->index].height; 1147 1148 return 0; 1149} 1150 1151static int imx290_set_fmt(struct v4l2_subdev *sd, 1152 struct v4l2_subdev_state *sd_state, 1153 struct v4l2_subdev_format *fmt) 1154{ 1155 struct imx290 *imx290 = to_imx290(sd); 1156 const struct imx290_mode *mode; 1157 struct v4l2_mbus_framefmt *format; 1158 1159 mode = v4l2_find_nearest_size(imx290_modes_ptr(imx290), 1160 imx290_modes_num(imx290), width, height, 1161 fmt->format.width, fmt->format.height); 1162 1163 fmt->format.width = mode->width; 1164 fmt->format.height = mode->height; 1165 1166 if (!imx290_format_info(imx290, fmt->format.code)) 1167 fmt->format.code = imx290_formats[0].code[imx290->model->colour_variant]; 1168 1169 fmt->format.field = V4L2_FIELD_NONE; 1170 fmt->format.colorspace = V4L2_COLORSPACE_RAW; 1171 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_601; 1172 fmt->format.quantization = V4L2_QUANTIZATION_FULL_RANGE; 1173 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE; 1174 1175 format = v4l2_subdev_state_get_format(sd_state, 0); 1176 1177 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 1178 imx290->current_mode = mode; 1179 1180 imx290_ctrl_update(imx290, mode); 1181 imx290_exposure_update(imx290, mode); 1182 } 1183 1184 *format = fmt->format; 1185 1186 return 0; 1187} 1188 1189static int imx290_get_selection(struct v4l2_subdev *sd, 1190 struct v4l2_subdev_state *sd_state, 1191 struct v4l2_subdev_selection *sel) 1192{ 1193 struct imx290 *imx290 = to_imx290(sd); 1194 struct v4l2_mbus_framefmt *format; 1195 1196 switch (sel->target) { 1197 case V4L2_SEL_TGT_CROP: { 1198 format = v4l2_subdev_state_get_format(sd_state, 0); 1199 1200 /* 1201 * The sensor moves the readout by 1 pixel based on flips to 1202 * keep the Bayer order the same. 1203 */ 1204 sel->r.top = IMX290_PIXEL_ARRAY_MARGIN_TOP 1205 + (IMX290_PIXEL_ARRAY_RECORDING_HEIGHT - format->height) / 2 1206 + imx290->vflip->val; 1207 sel->r.left = IMX290_PIXEL_ARRAY_MARGIN_LEFT 1208 + (IMX290_PIXEL_ARRAY_RECORDING_WIDTH - format->width) / 2 1209 + imx290->hflip->val; 1210 sel->r.width = format->width; 1211 sel->r.height = format->height; 1212 1213 return 0; 1214 } 1215 1216 case V4L2_SEL_TGT_NATIVE_SIZE: 1217 case V4L2_SEL_TGT_CROP_BOUNDS: 1218 sel->r.top = 0; 1219 sel->r.left = 0; 1220 sel->r.width = IMX290_PIXEL_ARRAY_WIDTH; 1221 sel->r.height = IMX290_PIXEL_ARRAY_HEIGHT; 1222 1223 return 0; 1224 1225 case V4L2_SEL_TGT_CROP_DEFAULT: 1226 sel->r.top = IMX290_PIXEL_ARRAY_MARGIN_TOP; 1227 sel->r.left = IMX290_PIXEL_ARRAY_MARGIN_LEFT; 1228 sel->r.width = IMX290_PIXEL_ARRAY_RECORDING_WIDTH; 1229 sel->r.height = IMX290_PIXEL_ARRAY_RECORDING_HEIGHT; 1230 1231 return 0; 1232 1233 default: 1234 return -EINVAL; 1235 } 1236} 1237 1238static int imx290_entity_init_state(struct v4l2_subdev *subdev, 1239 struct v4l2_subdev_state *sd_state) 1240{ 1241 struct v4l2_subdev_format fmt = { 1242 .which = V4L2_SUBDEV_FORMAT_TRY, 1243 .format = { 1244 .width = 1920, 1245 .height = 1080, 1246 }, 1247 }; 1248 1249 imx290_set_fmt(subdev, sd_state, &fmt); 1250 1251 return 0; 1252} 1253 1254static const struct v4l2_subdev_video_ops imx290_video_ops = { 1255 .s_stream = imx290_set_stream, 1256}; 1257 1258static const struct v4l2_subdev_pad_ops imx290_pad_ops = { 1259 .enum_mbus_code = imx290_enum_mbus_code, 1260 .enum_frame_size = imx290_enum_frame_size, 1261 .get_fmt = v4l2_subdev_get_fmt, 1262 .set_fmt = imx290_set_fmt, 1263 .get_selection = imx290_get_selection, 1264}; 1265 1266static const struct v4l2_subdev_ops imx290_subdev_ops = { 1267 .video = &imx290_video_ops, 1268 .pad = &imx290_pad_ops, 1269}; 1270 1271static const struct v4l2_subdev_internal_ops imx290_internal_ops = { 1272 .init_state = imx290_entity_init_state, 1273}; 1274 1275static const struct media_entity_operations imx290_subdev_entity_ops = { 1276 .link_validate = v4l2_subdev_link_validate, 1277}; 1278 1279static int imx290_subdev_init(struct imx290 *imx290) 1280{ 1281 struct i2c_client *client = to_i2c_client(imx290->dev); 1282 struct v4l2_subdev_state *state; 1283 int ret; 1284 1285 imx290->current_mode = &imx290_modes_ptr(imx290)[0]; 1286 1287 /* 1288 * After linking the subdev with the imx290 instance, we are allowed to 1289 * use the pm_runtime functions. Decrease the PM usage count. The device 1290 * will get suspended after the autosuspend delay, turning the power 1291 * off. However, the communication happening in imx290_ctrl_update() 1292 * will already be prevented even before the delay. 1293 */ 1294 v4l2_i2c_subdev_init(&imx290->sd, client, &imx290_subdev_ops); 1295 pm_runtime_put_autosuspend(imx290->dev); 1296 1297 imx290->sd.internal_ops = &imx290_internal_ops; 1298 imx290->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1299 imx290->sd.entity.ops = &imx290_subdev_entity_ops; 1300 imx290->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1301 1302 imx290->pad.flags = MEDIA_PAD_FL_SOURCE; 1303 ret = media_entity_pads_init(&imx290->sd.entity, 1, &imx290->pad); 1304 if (ret < 0) { 1305 dev_err(imx290->dev, "Could not register media entity\n"); 1306 return ret; 1307 } 1308 1309 ret = imx290_ctrl_init(imx290); 1310 if (ret < 0) { 1311 dev_err(imx290->dev, "Control initialization error %d\n", ret); 1312 goto err_media; 1313 } 1314 1315 imx290->sd.state_lock = imx290->ctrls.lock; 1316 1317 ret = v4l2_subdev_init_finalize(&imx290->sd); 1318 if (ret < 0) { 1319 dev_err(imx290->dev, "subdev initialization error %d\n", ret); 1320 goto err_ctrls; 1321 } 1322 1323 state = v4l2_subdev_lock_and_get_active_state(&imx290->sd); 1324 imx290_ctrl_update(imx290, imx290->current_mode); 1325 v4l2_subdev_unlock_state(state); 1326 1327 return 0; 1328 1329err_ctrls: 1330 v4l2_ctrl_handler_free(&imx290->ctrls); 1331err_media: 1332 media_entity_cleanup(&imx290->sd.entity); 1333 return ret; 1334} 1335 1336static void imx290_subdev_cleanup(struct imx290 *imx290) 1337{ 1338 v4l2_subdev_cleanup(&imx290->sd); 1339 media_entity_cleanup(&imx290->sd.entity); 1340 v4l2_ctrl_handler_free(&imx290->ctrls); 1341} 1342 1343/* ---------------------------------------------------------------------------- 1344 * Power management 1345 */ 1346 1347static int imx290_power_on(struct imx290 *imx290) 1348{ 1349 int ret; 1350 1351 ret = clk_prepare_enable(imx290->xclk); 1352 if (ret) { 1353 dev_err(imx290->dev, "Failed to enable clock\n"); 1354 return ret; 1355 } 1356 1357 ret = regulator_bulk_enable(ARRAY_SIZE(imx290->supplies), 1358 imx290->supplies); 1359 if (ret) { 1360 dev_err(imx290->dev, "Failed to enable regulators\n"); 1361 clk_disable_unprepare(imx290->xclk); 1362 return ret; 1363 } 1364 1365 usleep_range(1, 2); 1366 gpiod_set_value_cansleep(imx290->rst_gpio, 0); 1367 usleep_range(30000, 31000); 1368 1369 return 0; 1370} 1371 1372static void imx290_power_off(struct imx290 *imx290) 1373{ 1374 clk_disable_unprepare(imx290->xclk); 1375 gpiod_set_value_cansleep(imx290->rst_gpio, 1); 1376 regulator_bulk_disable(ARRAY_SIZE(imx290->supplies), imx290->supplies); 1377} 1378 1379static int imx290_runtime_resume(struct device *dev) 1380{ 1381 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1382 struct imx290 *imx290 = to_imx290(sd); 1383 1384 return imx290_power_on(imx290); 1385} 1386 1387static int imx290_runtime_suspend(struct device *dev) 1388{ 1389 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1390 struct imx290 *imx290 = to_imx290(sd); 1391 1392 imx290_power_off(imx290); 1393 1394 return 0; 1395} 1396 1397static const struct dev_pm_ops imx290_pm_ops = { 1398 RUNTIME_PM_OPS(imx290_runtime_suspend, imx290_runtime_resume, NULL) 1399}; 1400 1401/* ---------------------------------------------------------------------------- 1402 * Probe & remove 1403 */ 1404 1405static const char * const imx290_supply_name[IMX290_NUM_SUPPLIES] = { 1406 "vdda", 1407 "vddd", 1408 "vdddo", 1409}; 1410 1411static int imx290_get_regulators(struct device *dev, struct imx290 *imx290) 1412{ 1413 unsigned int i; 1414 1415 for (i = 0; i < ARRAY_SIZE(imx290->supplies); i++) 1416 imx290->supplies[i].supply = imx290_supply_name[i]; 1417 1418 return devm_regulator_bulk_get(dev, ARRAY_SIZE(imx290->supplies), 1419 imx290->supplies); 1420} 1421 1422static int imx290_init_clk(struct imx290 *imx290) 1423{ 1424 u32 xclk_freq; 1425 1426 imx290->xclk = devm_v4l2_sensor_clk_get_legacy(imx290->dev, "xclk", 1427 false, 0); 1428 if (IS_ERR(imx290->xclk)) 1429 return dev_err_probe(imx290->dev, PTR_ERR(imx290->xclk), 1430 "Could not get xclk\n"); 1431 1432 xclk_freq = clk_get_rate(imx290->xclk); 1433 1434 /* external clock must be 37.125 MHz or 74.25MHz */ 1435 switch (xclk_freq) { 1436 case 37125000: 1437 imx290->xclk_idx = IMX290_CLK_37_125; 1438 break; 1439 case 74250000: 1440 imx290->xclk_idx = IMX290_CLK_74_25; 1441 break; 1442 default: 1443 dev_err(imx290->dev, "External clock frequency %u is not supported\n", 1444 xclk_freq); 1445 return -EINVAL; 1446 } 1447 1448 return 0; 1449} 1450 1451/* 1452 * Returns 0 if all link frequencies used by the driver for the given number 1453 * of MIPI data lanes are mentioned in the device tree, or the value of the 1454 * first missing frequency otherwise. 1455 */ 1456static s64 imx290_check_link_freqs(const struct imx290 *imx290, 1457 const struct v4l2_fwnode_endpoint *ep) 1458{ 1459 int i, j; 1460 const s64 *freqs = imx290_link_freqs_ptr(imx290); 1461 int freqs_count = imx290_link_freqs_num(imx290); 1462 1463 for (i = 0; i < freqs_count; i++) { 1464 for (j = 0; j < ep->nr_of_link_frequencies; j++) 1465 if (freqs[i] == ep->link_frequencies[j]) 1466 break; 1467 if (j == ep->nr_of_link_frequencies) 1468 return freqs[i]; 1469 } 1470 return 0; 1471} 1472 1473static const struct imx290_model_info imx290_models[] = { 1474 [IMX290_MODEL_IMX290LQR] = { 1475 .colour_variant = IMX290_VARIANT_COLOUR, 1476 .init_regs = imx290_global_init_settings_290, 1477 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_290), 1478 .max_analog_gain = 100, 1479 .name = "imx290", 1480 }, 1481 [IMX290_MODEL_IMX290LLR] = { 1482 .colour_variant = IMX290_VARIANT_MONO, 1483 .init_regs = imx290_global_init_settings_290, 1484 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_290), 1485 .max_analog_gain = 100, 1486 .name = "imx290", 1487 }, 1488 [IMX290_MODEL_IMX327LQR] = { 1489 .colour_variant = IMX290_VARIANT_COLOUR, 1490 .init_regs = imx290_global_init_settings_327, 1491 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_327), 1492 .max_analog_gain = 98, 1493 .name = "imx327", 1494 }, 1495 [IMX290_MODEL_IMX462LQR] = { 1496 .colour_variant = IMX290_VARIANT_COLOUR, 1497 .init_regs = imx290_global_init_settings_462, 1498 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_462), 1499 .max_analog_gain = 98, 1500 .name = "imx462", 1501 }, 1502 [IMX290_MODEL_IMX462LLR] = { 1503 .colour_variant = IMX290_VARIANT_MONO, 1504 .init_regs = imx290_global_init_settings_462, 1505 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_462), 1506 .max_analog_gain = 98, 1507 .name = "imx462", 1508 }, 1509}; 1510 1511static int imx290_parse_dt(struct imx290 *imx290) 1512{ 1513 /* Only CSI2 is supported for now: */ 1514 struct v4l2_fwnode_endpoint ep = { 1515 .bus_type = V4L2_MBUS_CSI2_DPHY 1516 }; 1517 struct fwnode_handle *endpoint; 1518 int ret; 1519 s64 fq; 1520 1521 imx290->model = of_device_get_match_data(imx290->dev); 1522 1523 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(imx290->dev), NULL); 1524 if (!endpoint) { 1525 dev_err(imx290->dev, "Endpoint node not found\n"); 1526 return -EINVAL; 1527 } 1528 1529 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep); 1530 fwnode_handle_put(endpoint); 1531 if (ret == -ENXIO) { 1532 dev_err(imx290->dev, "Unsupported bus type, should be CSI2\n"); 1533 goto done; 1534 } else if (ret) { 1535 dev_err(imx290->dev, "Parsing endpoint node failed\n"); 1536 goto done; 1537 } 1538 1539 /* Get number of data lanes */ 1540 imx290->nlanes = ep.bus.mipi_csi2.num_data_lanes; 1541 if (imx290->nlanes != 2 && imx290->nlanes != 4) { 1542 dev_err(imx290->dev, "Invalid data lanes: %d\n", imx290->nlanes); 1543 ret = -EINVAL; 1544 goto done; 1545 } 1546 1547 dev_dbg(imx290->dev, "Using %u data lanes\n", imx290->nlanes); 1548 1549 if (!ep.nr_of_link_frequencies) { 1550 dev_err(imx290->dev, "link-frequency property not found in DT\n"); 1551 ret = -EINVAL; 1552 goto done; 1553 } 1554 1555 /* Check that link frequences for all the modes are in device tree */ 1556 fq = imx290_check_link_freqs(imx290, &ep); 1557 if (fq) { 1558 dev_err(imx290->dev, "Link frequency of %lld is not supported\n", 1559 fq); 1560 ret = -EINVAL; 1561 goto done; 1562 } 1563 1564 ret = 0; 1565 1566done: 1567 v4l2_fwnode_endpoint_free(&ep); 1568 return ret; 1569} 1570 1571static int imx290_probe(struct i2c_client *client) 1572{ 1573 struct device *dev = &client->dev; 1574 struct imx290 *imx290; 1575 int ret; 1576 1577 imx290 = devm_kzalloc(dev, sizeof(*imx290), GFP_KERNEL); 1578 if (!imx290) 1579 return -ENOMEM; 1580 1581 imx290->dev = dev; 1582 imx290->regmap = devm_cci_regmap_init_i2c(client, 16); 1583 if (IS_ERR(imx290->regmap)) { 1584 dev_err(dev, "Unable to initialize I2C\n"); 1585 return -ENODEV; 1586 } 1587 1588 ret = imx290_parse_dt(imx290); 1589 if (ret) 1590 return ret; 1591 1592 /* Acquire resources. */ 1593 ret = imx290_get_regulators(dev, imx290); 1594 if (ret < 0) 1595 return dev_err_probe(dev, ret, "Cannot get regulators\n"); 1596 1597 imx290->rst_gpio = devm_gpiod_get_optional(dev, "reset", 1598 GPIOD_OUT_HIGH); 1599 if (IS_ERR(imx290->rst_gpio)) 1600 return dev_err_probe(dev, PTR_ERR(imx290->rst_gpio), 1601 "Cannot get reset gpio\n"); 1602 1603 /* Initialize external clock. */ 1604 ret = imx290_init_clk(imx290); 1605 if (ret) 1606 return ret; 1607 1608 /* 1609 * Enable power management. The driver supports runtime PM, but needs to 1610 * work when runtime PM is disabled in the kernel. To that end, power 1611 * the sensor on manually here. 1612 */ 1613 ret = imx290_power_on(imx290); 1614 if (ret < 0) { 1615 dev_err(dev, "Could not power on the device\n"); 1616 return ret; 1617 } 1618 1619 /* 1620 * Enable runtime PM with autosuspend. As the device has been powered 1621 * manually, mark it as active, and increase the usage count without 1622 * resuming the device. 1623 */ 1624 pm_runtime_set_active(dev); 1625 pm_runtime_get_noresume(dev); 1626 pm_runtime_enable(dev); 1627 pm_runtime_set_autosuspend_delay(dev, 1000); 1628 pm_runtime_use_autosuspend(dev); 1629 1630 /* 1631 * Make sure the sensor is available, in STANDBY and not streaming 1632 * before the V4L2 subdev is initialized. 1633 */ 1634 ret = imx290_stop_streaming(imx290); 1635 if (ret) { 1636 ret = dev_err_probe(dev, ret, "Could not initialize device\n"); 1637 goto err_pm; 1638 } 1639 1640 /* Initialize the V4L2 subdev. */ 1641 ret = imx290_subdev_init(imx290); 1642 if (ret) 1643 goto err_pm; 1644 1645 v4l2_i2c_subdev_set_name(&imx290->sd, client, 1646 imx290->model->name, NULL); 1647 1648 /* 1649 * Finally, register the V4L2 subdev. This must be done after 1650 * initializing everything as the subdev can be used immediately after 1651 * being registered. 1652 */ 1653 ret = v4l2_async_register_subdev(&imx290->sd); 1654 if (ret < 0) { 1655 dev_err(dev, "Could not register v4l2 device\n"); 1656 goto err_subdev; 1657 } 1658 1659 return 0; 1660 1661err_subdev: 1662 imx290_subdev_cleanup(imx290); 1663err_pm: 1664 pm_runtime_disable(dev); 1665 pm_runtime_put_noidle(dev); 1666 imx290_power_off(imx290); 1667 return ret; 1668} 1669 1670static void imx290_remove(struct i2c_client *client) 1671{ 1672 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1673 struct imx290 *imx290 = to_imx290(sd); 1674 1675 v4l2_async_unregister_subdev(sd); 1676 imx290_subdev_cleanup(imx290); 1677 1678 /* 1679 * Disable runtime PM. In case runtime PM is disabled in the kernel, 1680 * make sure to turn power off manually. 1681 */ 1682 pm_runtime_disable(imx290->dev); 1683 if (!pm_runtime_status_suspended(imx290->dev)) 1684 imx290_power_off(imx290); 1685 pm_runtime_set_suspended(imx290->dev); 1686} 1687 1688static const struct of_device_id imx290_of_match[] = { 1689 { 1690 /* Deprecated - synonym for "sony,imx290lqr" */ 1691 .compatible = "sony,imx290", 1692 .data = &imx290_models[IMX290_MODEL_IMX290LQR], 1693 }, { 1694 .compatible = "sony,imx290lqr", 1695 .data = &imx290_models[IMX290_MODEL_IMX290LQR], 1696 }, { 1697 .compatible = "sony,imx290llr", 1698 .data = &imx290_models[IMX290_MODEL_IMX290LLR], 1699 }, { 1700 .compatible = "sony,imx327lqr", 1701 .data = &imx290_models[IMX290_MODEL_IMX327LQR], 1702 }, { 1703 .compatible = "sony,imx462lqr", 1704 .data = &imx290_models[IMX290_MODEL_IMX462LQR], 1705 }, { 1706 .compatible = "sony,imx462llr", 1707 .data = &imx290_models[IMX290_MODEL_IMX462LLR], 1708 }, 1709 { /* sentinel */ }, 1710}; 1711MODULE_DEVICE_TABLE(of, imx290_of_match); 1712 1713static struct i2c_driver imx290_i2c_driver = { 1714 .probe = imx290_probe, 1715 .remove = imx290_remove, 1716 .driver = { 1717 .name = "imx290", 1718 .pm = pm_ptr(&imx290_pm_ops), 1719 .of_match_table = imx290_of_match, 1720 }, 1721}; 1722 1723module_i2c_driver(imx290_i2c_driver); 1724 1725MODULE_DESCRIPTION("Sony IMX290 CMOS Image Sensor Driver"); 1726MODULE_AUTHOR("FRAMOS GmbH"); 1727MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 1728MODULE_LICENSE("GPL v2");
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