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imx283.c
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linux-6.19.14/drivers/media/i2c/imx283.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * V4L2 Support for the IMX283 4 * 5 * Diagonal 15.86 mm (Type 1) CMOS Image Sensor with Square Pixel for Color 6 * Cameras. 7 * 8 * Copyright (C) 2024 Ideas on Board Oy. 9 * 10 * Based on Sony IMX283 driver prepared by Will Whang 11 * 12 * Based on Sony imx477 camera driver 13 * Copyright (C) 2019-2020 Raspberry Pi (Trading) Ltd 14 */ 15 16#include <linux/array_size.h> 17#include <linux/bitops.h> 18#include <linux/container_of.h> 19#include <linux/clk.h> 20#include <linux/delay.h> 21#include <linux/err.h> 22#include <linux/gpio/consumer.h> 23#include <linux/i2c.h> 24#include <linux/minmax.h> 25#include <linux/module.h> 26#include <linux/mutex.h> 27#include <linux/pm_runtime.h> 28#include <linux/property.h> 29#include <linux/regulator/consumer.h> 30#include <linux/types.h> 31#include <linux/units.h> 32#include <media/v4l2-cci.h> 33#include <media/v4l2-ctrls.h> 34#include <media/v4l2-device.h> 35#include <media/v4l2-fwnode.h> 36#include <media/v4l2-mediabus.h> 37 38/* Chip ID */ 39#define IMX283_REG_CHIP_ID CCI_REG8(0x3000) 40#define IMX283_CHIP_ID 0x0b // Default power on state 41 42#define IMX283_REG_STANDBY CCI_REG8(0x3000) 43#define IMX283_ACTIVE 0 44#define IMX283_STANDBY BIT(0) 45#define IMX283_STBLOGIC BIT(1) 46#define IMX283_STBMIPI BIT(2) 47#define IMX283_STBDV BIT(3) 48#define IMX283_SLEEP BIT(4) 49 50#define IMX283_REG_CLAMP CCI_REG8(0x3001) 51#define IMX283_CLPSQRST BIT(4) 52 53#define IMX283_REG_PLSTMG08 CCI_REG8(0x3003) 54#define IMX283_PLSTMG08_VAL 0x77 55 56#define IMX283_REG_MDSEL1 CCI_REG8(0x3004) 57#define IMX283_REG_MDSEL2 CCI_REG8(0x3005) 58#define IMX283_REG_MDSEL3 CCI_REG8(0x3006) 59#define IMX283_MDSEL3_VCROP_EN BIT(5) 60#define IMX283_REG_MDSEL4 CCI_REG8(0x3007) 61#define IMX283_MDSEL4_VCROP_EN (BIT(4) | BIT(6)) 62 63#define IMX283_REG_SVR CCI_REG16_LE(0x3009) 64 65#define IMX283_REG_HTRIMMING CCI_REG8(0x300b) 66#define IMX283_MDVREV BIT(0) /* VFLIP */ 67#define IMX283_HTRIMMING_EN BIT(4) 68 69#define IMX283_REG_VWINPOS CCI_REG16_LE(0x300f) 70#define IMX283_REG_VWIDCUT CCI_REG16_LE(0x3011) 71 72#define IMX283_REG_MDSEL7 CCI_REG16_LE(0x3013) 73 74/* CSI Clock Configuration */ 75#define IMX283_REG_TCLKPOST CCI_REG8(0x3018) 76#define IMX283_REG_THSPREPARE CCI_REG8(0x301a) 77#define IMX283_REG_THSZERO CCI_REG8(0x301c) 78#define IMX283_REG_THSTRAIL CCI_REG8(0x301e) 79#define IMX283_REG_TCLKTRAIL CCI_REG8(0x3020) 80#define IMX283_REG_TCLKPREPARE CCI_REG8(0x3022) 81#define IMX283_REG_TCLKZERO CCI_REG16_LE(0x3024) 82#define IMX283_REG_TLPX CCI_REG8(0x3026) 83#define IMX283_REG_THSEXIT CCI_REG8(0x3028) 84#define IMX283_REG_TCLKPRE CCI_REG8(0x302a) 85#define IMX283_REG_SYSMODE CCI_REG8(0x3104) 86 87#define IMX283_REG_Y_OUT_SIZE CCI_REG16_LE(0x302f) 88#define IMX283_REG_WRITE_VSIZE CCI_REG16_LE(0x3031) 89#define IMX283_REG_OB_SIZE_V CCI_REG8(0x3033) 90 91/* HMAX internal HBLANK */ 92#define IMX283_REG_HMAX CCI_REG16_LE(0x3036) 93#define IMX283_HMAX_MAX (BIT(16) - 1) 94 95/* VMAX internal VBLANK */ 96#define IMX283_REG_VMAX CCI_REG24_LE(0x3038) 97#define IMX283_VMAX_MAX (BIT(16) - 1) 98 99/* SHR internal */ 100#define IMX283_REG_SHR CCI_REG16_LE(0x303b) 101#define IMX283_SHR_MIN 11 102 103/* 104 * Analog gain control 105 * Gain [dB] = -20log{(2048 - value [10:0]) /2048} 106 * Range: 0dB to approximately +27dB 107 */ 108#define IMX283_REG_ANALOG_GAIN CCI_REG16_LE(0x3042) 109#define IMX283_ANA_GAIN_MIN 0 110#define IMX283_ANA_GAIN_MAX 1957 111#define IMX283_ANA_GAIN_STEP 1 112#define IMX283_ANA_GAIN_DEFAULT 0x0 113 114/* 115 * Digital gain control 116 * Gain [dB] = value * 6 117 * Range: 0dB to +18db 118 */ 119#define IMX283_REG_DIGITAL_GAIN CCI_REG8(0x3044) 120#define IMX283_DGTL_GAIN_MIN 0 121#define IMX283_DGTL_GAIN_MAX 3 122#define IMX283_DGTL_GAIN_DEFAULT 0 123#define IMX283_DGTL_GAIN_STEP 1 124 125#define IMX283_REG_HTRIMMING_START CCI_REG16_LE(0x3058) 126#define IMX283_REG_HTRIMMING_END CCI_REG16_LE(0x305a) 127 128#define IMX283_REG_MDSEL18 CCI_REG16_LE(0x30f6) 129 130/* Master Mode Operation Control */ 131#define IMX283_REG_XMSTA CCI_REG8(0x3105) 132#define IMX283_XMSTA BIT(0) 133 134#define IMX283_REG_SYNCDRV CCI_REG8(0x3107) 135#define IMX283_SYNCDRV_XHS_XVS (0xa0 | 0x02) 136#define IMX283_SYNCDRV_HIZ (0xa0 | 0x03) 137 138/* PLL Standby */ 139#define IMX283_REG_STBPL CCI_REG8(0x320b) 140#define IMX283_STBPL_NORMAL 0x00 141#define IMX283_STBPL_STANDBY 0x03 142 143/* Input Frequency Setting */ 144#define IMX283_REG_PLRD1 CCI_REG8(0x36c1) 145#define IMX283_REG_PLRD2 CCI_REG16_LE(0x36c2) 146#define IMX283_REG_PLRD3 CCI_REG8(0x36f7) 147#define IMX283_REG_PLRD4 CCI_REG8(0x36f8) 148 149#define IMX283_REG_PLSTMG02 CCI_REG8(0x36aa) 150#define IMX283_PLSTMG02_VAL 0x00 151 152#define IMX283_REG_EBD_X_OUT_SIZE CCI_REG16_LE(0x3a54) 153 154/* Test pattern generator */ 155#define IMX283_REG_TPG_CTRL CCI_REG8(0x3156) 156#define IMX283_TPG_CTRL_CLKEN BIT(0) 157#define IMX283_TPG_CTRL_PATEN BIT(4) 158 159#define IMX283_REG_TPG_PAT CCI_REG8(0x3157) 160#define IMX283_TPG_PAT_ALL_000 0x00 161#define IMX283_TPG_PAT_ALL_FFF 0x01 162#define IMX283_TPG_PAT_ALL_555 0x02 163#define IMX283_TPG_PAT_ALL_AAA 0x03 164#define IMX283_TPG_PAT_H_COLOR_BARS 0x0a 165#define IMX283_TPG_PAT_V_COLOR_BARS 0x0b 166 167/* Exposure control */ 168#define IMX283_EXPOSURE_MIN 52 169#define IMX283_EXPOSURE_STEP 1 170#define IMX283_EXPOSURE_DEFAULT 1000 171#define IMX283_EXPOSURE_MAX 49865 172 173#define IMAGE_PAD 0 174 175#define IMX283_XCLR_MIN_DELAY_US (1 * USEC_PER_MSEC) 176#define IMX283_XCLR_DELAY_RANGE_US (1 * USEC_PER_MSEC) 177 178/* IMX283 native and active pixel array size. */ 179static const struct v4l2_rect imx283_native_area = { 180 .top = 0, 181 .left = 0, 182 .width = 5592, 183 .height = 3710, 184}; 185 186static const struct v4l2_rect imx283_active_area = { 187 .top = 40, 188 .left = 108, 189 .width = 5472, 190 .height = 3648, 191}; 192 193struct imx283_reg_list { 194 unsigned int num_of_regs; 195 const struct cci_reg_sequence *regs; 196}; 197 198/* Mode : resolution and related config values */ 199struct imx283_mode { 200 unsigned int mode; 201 202 /* Bits per pixel */ 203 unsigned int bpp; 204 205 /* Frame width */ 206 unsigned int width; 207 208 /* Frame height */ 209 unsigned int height; 210 211 /* 212 * Minimum horizontal timing in pixel-units 213 * 214 * Note that HMAX is written in 72MHz units, and the datasheet assumes a 215 * 720MHz link frequency. Convert datasheet values with the following: 216 * 217 * For 12 bpp modes (480Mbps) convert with: 218 * hmax = [hmax in 72MHz units] * 480 / 72 219 * 220 * For 10 bpp modes (576Mbps) convert with: 221 * hmax = [hmax in 72MHz units] * 576 / 72 222 */ 223 u32 min_hmax; 224 225 /* minimum V-timing in lines */ 226 u32 min_vmax; 227 228 /* default H-timing */ 229 u32 default_hmax; 230 231 /* default V-timing */ 232 u32 default_vmax; 233 234 /* minimum SHR */ 235 u32 min_shr; 236 237 /* 238 * Per-mode vertical crop constants used to calculate values 239 * of IMX283REG_WIDCUT and IMX283_REG_VWINPOS. 240 */ 241 u32 veff; 242 u32 vst; 243 u32 vct; 244 245 /* Horizontal and vertical binning ratio */ 246 u8 hbin_ratio; 247 u8 vbin_ratio; 248 249 /* Optical Blanking */ 250 u32 horizontal_ob; 251 u32 vertical_ob; 252 253 /* Analog crop rectangle. */ 254 struct v4l2_rect crop; 255}; 256 257struct imx283_input_frequency { 258 unsigned int mhz; 259 unsigned int reg_count; 260 struct cci_reg_sequence regs[4]; 261}; 262 263static const struct imx283_input_frequency imx283_frequencies[] = { 264 { 265 .mhz = 6 * HZ_PER_MHZ, 266 .reg_count = 4, 267 .regs = { 268 { IMX283_REG_PLRD1, 0x00 }, 269 { IMX283_REG_PLRD2, 0x00f0 }, 270 { IMX283_REG_PLRD3, 0x00 }, 271 { IMX283_REG_PLRD4, 0xc0 }, 272 }, 273 }, 274 { 275 .mhz = 12 * HZ_PER_MHZ, 276 .reg_count = 4, 277 .regs = { 278 { IMX283_REG_PLRD1, 0x01 }, 279 { IMX283_REG_PLRD2, 0x00f0 }, 280 { IMX283_REG_PLRD3, 0x01 }, 281 { IMX283_REG_PLRD4, 0xc0 }, 282 }, 283 }, 284 { 285 .mhz = 18 * HZ_PER_MHZ, 286 .reg_count = 4, 287 .regs = { 288 { IMX283_REG_PLRD1, 0x01 }, 289 { IMX283_REG_PLRD2, 0x00a0 }, 290 { IMX283_REG_PLRD3, 0x01 }, 291 { IMX283_REG_PLRD4, 0x80 }, 292 }, 293 }, 294 { 295 .mhz = 24 * HZ_PER_MHZ, 296 .reg_count = 4, 297 .regs = { 298 { IMX283_REG_PLRD1, 0x02 }, 299 { IMX283_REG_PLRD2, 0x00f0 }, 300 { IMX283_REG_PLRD3, 0x02 }, 301 { IMX283_REG_PLRD4, 0xc0 }, 302 }, 303 }, 304}; 305 306enum imx283_modes { 307 IMX283_MODE_0, 308 IMX283_MODE_1, 309 IMX283_MODE_1A, 310 IMX283_MODE_1S, 311 IMX283_MODE_2, 312 IMX283_MODE_2A, 313 IMX283_MODE_3, 314 IMX283_MODE_4, 315 IMX283_MODE_5, 316 IMX283_MODE_6, 317}; 318 319struct imx283_readout_mode { 320 u8 mdsel1; 321 u8 mdsel2; 322 u8 mdsel3; 323 u8 mdsel4; 324}; 325 326static const struct imx283_readout_mode imx283_readout_modes[] = { 327 /* All pixel scan modes */ 328 [IMX283_MODE_0] = { 0x04, 0x03, 0x10, 0x00 }, /* 12 bit */ 329 [IMX283_MODE_1] = { 0x04, 0x01, 0x00, 0x00 }, /* 10 bit */ 330 [IMX283_MODE_1A] = { 0x04, 0x01, 0x20, 0x50 }, /* 10 bit */ 331 [IMX283_MODE_1S] = { 0x04, 0x41, 0x20, 0x50 }, /* 10 bit */ 332 333 /* Horizontal / Vertical 2/2-line binning */ 334 [IMX283_MODE_2] = { 0x0d, 0x11, 0x50, 0x00 }, /* 12 bit */ 335 [IMX283_MODE_2A] = { 0x0d, 0x11, 0x70, 0x50 }, /* 12 bit */ 336 337 /* Horizontal / Vertical 3/3-line binning */ 338 [IMX283_MODE_3] = { 0x1e, 0x18, 0x10, 0x00 }, /* 12 bit */ 339 340 /* Vertical 2/9 subsampling, horizontal 3 binning cropping */ 341 [IMX283_MODE_4] = { 0x29, 0x18, 0x30, 0x50 }, /* 12 bit */ 342 343 /* Vertical 2/19 subsampling binning, horizontal 3 binning */ 344 [IMX283_MODE_5] = { 0x2d, 0x18, 0x10, 0x00 }, /* 12 bit */ 345 346 /* Vertical 2 binning horizontal 2/4, subsampling 16:9 cropping */ 347 [IMX283_MODE_6] = { 0x18, 0x21, 0x00, 0x09 }, /* 10 bit */ 348 349 /* 350 * New modes should make sure the offset period is complied. 351 * See imx283_exposure() for reference. 352 */ 353}; 354 355static const struct cci_reg_sequence mipi_data_rate_1440Mbps[] = { 356 /* The default register settings provide the 1440Mbps rate */ 357 { CCI_REG8(0x36c5), 0x00 }, /* Undocumented */ 358 { CCI_REG8(0x3ac4), 0x00 }, /* Undocumented */ 359 360 { IMX283_REG_STBPL, 0x00 }, 361 { IMX283_REG_TCLKPOST, 0xa7 }, 362 { IMX283_REG_THSPREPARE, 0x6f }, 363 { IMX283_REG_THSZERO, 0x9f }, 364 { IMX283_REG_THSTRAIL, 0x5f }, 365 { IMX283_REG_TCLKTRAIL, 0x5f }, 366 { IMX283_REG_TCLKPREPARE, 0x6f }, 367 { IMX283_REG_TCLKZERO, 0x017f }, 368 { IMX283_REG_TLPX, 0x4f }, 369 { IMX283_REG_THSEXIT, 0x47 }, 370 { IMX283_REG_TCLKPRE, 0x07 }, 371 { IMX283_REG_SYSMODE, 0x02 }, 372}; 373 374static const struct cci_reg_sequence mipi_data_rate_720Mbps[] = { 375 /* Undocumented Additions "For 720MBps" Setting */ 376 { CCI_REG8(0x36c5), 0x01 }, /* Undocumented */ 377 { CCI_REG8(0x3ac4), 0x01 }, /* Undocumented */ 378 379 { IMX283_REG_STBPL, 0x00 }, 380 { IMX283_REG_TCLKPOST, 0x77 }, 381 { IMX283_REG_THSPREPARE, 0x37 }, 382 { IMX283_REG_THSZERO, 0x67 }, 383 { IMX283_REG_THSTRAIL, 0x37 }, 384 { IMX283_REG_TCLKTRAIL, 0x37 }, 385 { IMX283_REG_TCLKPREPARE, 0x37 }, 386 { IMX283_REG_TCLKZERO, 0xdf }, 387 { IMX283_REG_TLPX, 0x2f }, 388 { IMX283_REG_THSEXIT, 0x47 }, 389 { IMX283_REG_TCLKPRE, 0x0f }, 390 { IMX283_REG_SYSMODE, 0x02 }, 391}; 392 393static const s64 link_frequencies[] = { 394 720 * HZ_PER_MHZ, /* 1440 Mbps lane data rate */ 395 360 * HZ_PER_MHZ, /* 720 Mbps data lane rate */ 396}; 397 398static const struct imx283_reg_list link_freq_reglist[] = { 399 { /* 720 MHz */ 400 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1440Mbps), 401 .regs = mipi_data_rate_1440Mbps, 402 }, 403 { /* 360 MHz */ 404 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720Mbps), 405 .regs = mipi_data_rate_720Mbps, 406 }, 407}; 408 409/* Mode configs */ 410static const struct imx283_mode supported_modes_12bit[] = { 411 { 412 /* 20MPix 21.40 fps readout mode 0 */ 413 .mode = IMX283_MODE_0, 414 .bpp = 12, 415 .width = 5472, 416 .height = 3648, 417 .min_hmax = 5914, /* 887 @ 480MHz/72MHz */ 418 .min_vmax = 3793, /* Lines */ 419 420 .veff = 3694, 421 .vst = 0, 422 .vct = 0, 423 424 .hbin_ratio = 1, 425 .vbin_ratio = 1, 426 427 /* 20.00 FPS */ 428 .default_hmax = 6000, /* 900 @ 480MHz/72MHz */ 429 .default_vmax = 4000, 430 431 .min_shr = 11, 432 .horizontal_ob = 96, 433 .vertical_ob = 16, 434 .crop = { 435 .top = 40, 436 .left = 108, 437 .width = 5472, 438 .height = 3648, 439 }, 440 }, 441 { 442 /* 443 * Readout mode 2 : 2/2 binned mode (2736x1824) 444 */ 445 .mode = IMX283_MODE_2, 446 .bpp = 12, 447 .width = 2736, 448 .height = 1824, 449 .min_hmax = 2414, /* Pixels (362 * 480MHz/72MHz + padding) */ 450 .min_vmax = 3840, /* Lines */ 451 452 /* 50.00 FPS */ 453 .default_hmax = 2500, /* 375 @ 480MHz/72Mhz */ 454 .default_vmax = 3840, 455 456 .veff = 1824, 457 .vst = 0, 458 .vct = 0, 459 460 .hbin_ratio = 2, 461 .vbin_ratio = 2, 462 463 .min_shr = 12, 464 .horizontal_ob = 48, 465 .vertical_ob = 4, 466 467 .crop = { 468 .top = 40, 469 .left = 108, 470 .width = 5472, 471 .height = 3648, 472 }, 473 }, 474 { 475 /* 476 * Readout mode 3 : 3/3 binned mode (1824x1216) 477 */ 478 .mode = IMX283_MODE_3, 479 .bpp = 12, 480 .width = 1824, 481 .height = 1216, 482 .min_hmax = 1894, /* Pixels (284 * 480MHz/72MHz + padding) */ 483 .min_vmax = 4200, /* Lines */ 484 485 /* 60.00 fps */ 486 .default_hmax = 1900, /* 285 @ 480MHz/72Mhz */ 487 .default_vmax = 4200, 488 489 .veff = 1234, 490 .vst = 0, 491 .vct = 0, 492 493 .hbin_ratio = 3, 494 .vbin_ratio = 3, 495 496 .min_shr = 16, 497 .horizontal_ob = 32, 498 .vertical_ob = 4, 499 500 .crop = { 501 .top = 40, 502 .left = 108, 503 .width = 5472, 504 .height = 3648, 505 }, 506 }, 507}; 508 509static const struct imx283_mode supported_modes_10bit[] = { 510 { 511 /* 20MPix 25.48 fps readout mode 1 */ 512 .mode = IMX283_MODE_1, 513 .bpp = 10, 514 .width = 5472, 515 .height = 3648, 516 .min_hmax = 5960, /* 745 @ 576MHz / 72MHz */ 517 .min_vmax = 3793, 518 519 /* 25.00 FPS */ 520 .default_hmax = 6000, /* 750 @ 576MHz / 72MHz */ 521 .default_vmax = 3840, 522 523 .min_shr = 10, 524 .horizontal_ob = 96, 525 .vertical_ob = 16, 526 .crop = { 527 .top = 40, 528 .left = 108, 529 .width = 5472, 530 .height = 3648, 531 }, 532 }, 533}; 534 535static const u32 imx283_mbus_codes[] = { 536 MEDIA_BUS_FMT_SRGGB12_1X12, 537 MEDIA_BUS_FMT_SRGGB10_1X10, 538}; 539 540/* regulator supplies */ 541static const char *const imx283_supply_name[] = { 542 "vadd", /* Analog (2.9V) supply */ 543 "vdd1", /* Supply Voltage 2 (1.8V) supply */ 544 "vdd2", /* Supply Voltage 3 (1.2V) supply */ 545}; 546 547struct imx283 { 548 struct device *dev; 549 struct regmap *cci; 550 551 const struct imx283_input_frequency *freq; 552 553 struct v4l2_subdev sd; 554 struct media_pad pad; 555 556 struct clk *xclk; 557 558 struct gpio_desc *reset_gpio; 559 struct regulator_bulk_data supplies[ARRAY_SIZE(imx283_supply_name)]; 560 561 /* V4L2 Controls */ 562 struct v4l2_ctrl_handler ctrl_handler; 563 struct v4l2_ctrl *exposure; 564 struct v4l2_ctrl *vblank; 565 struct v4l2_ctrl *hblank; 566 struct v4l2_ctrl *vflip; 567 568 unsigned long link_freq_bitmap; 569 570 u16 hmax; 571 u32 vmax; 572}; 573 574static inline struct imx283 *to_imx283(struct v4l2_subdev *sd) 575{ 576 return container_of_const(sd, struct imx283, sd); 577} 578 579static inline void get_mode_table(unsigned int code, 580 const struct imx283_mode **mode_list, 581 unsigned int *num_modes) 582{ 583 switch (code) { 584 case MEDIA_BUS_FMT_SRGGB12_1X12: 585 case MEDIA_BUS_FMT_SGRBG12_1X12: 586 case MEDIA_BUS_FMT_SGBRG12_1X12: 587 case MEDIA_BUS_FMT_SBGGR12_1X12: 588 *mode_list = supported_modes_12bit; 589 *num_modes = ARRAY_SIZE(supported_modes_12bit); 590 break; 591 592 case MEDIA_BUS_FMT_SRGGB10_1X10: 593 case MEDIA_BUS_FMT_SGRBG10_1X10: 594 case MEDIA_BUS_FMT_SGBRG10_1X10: 595 case MEDIA_BUS_FMT_SBGGR10_1X10: 596 *mode_list = supported_modes_10bit; 597 *num_modes = ARRAY_SIZE(supported_modes_10bit); 598 break; 599 default: 600 *mode_list = NULL; 601 *num_modes = 0; 602 break; 603 } 604} 605 606/* Calculate the Pixel Rate based on the current mode */ 607static u64 imx283_pixel_rate(struct imx283 *imx283, 608 const struct imx283_mode *mode) 609{ 610 u64 link_frequency = link_frequencies[__ffs(imx283->link_freq_bitmap)]; 611 unsigned int bpp = mode->bpp; 612 const unsigned int ddr = 2; /* Double Data Rate */ 613 const unsigned int lanes = 4; /* Only 4 lane support */ 614 u64 numerator = link_frequency * ddr * lanes; 615 616 do_div(numerator, bpp); 617 618 return numerator; 619} 620 621/* Convert from a variable pixel_rate to 72 MHz clock cycles */ 622static u64 imx283_internal_clock(unsigned int pixel_rate, unsigned int pixels) 623{ 624 /* 625 * Determine the following operation without overflow: 626 * pixels = 72 Mhz / pixel_rate 627 * 628 * The internal clock at 72MHz and Pixel Rate (between 240 and 576MHz) 629 * can easily overflow this calculation, so pre-divide to simplify. 630 */ 631 const u32 iclk_pre = 72; 632 const u32 pclk_pre = pixel_rate / HZ_PER_MHZ; 633 u64 numerator = pixels * iclk_pre; 634 635 do_div(numerator, pclk_pre); 636 637 return numerator; 638} 639 640/* Internal clock (72MHz) to Pixel Rate clock (Variable) */ 641static u64 imx283_iclk_to_pix(unsigned int pixel_rate, unsigned int cycles) 642{ 643 /* 644 * Determine the following operation without overflow: 645 * cycles * pixel_rate / 72 MHz 646 * 647 * The internal clock at 72MHz and Pixel Rate (between 240 and 576MHz) 648 * can easily overflow this calculation, so pre-divide to simplify. 649 */ 650 const u32 iclk_pre = 72; 651 const u32 pclk_pre = pixel_rate / HZ_PER_MHZ; 652 u64 numerator = cycles * pclk_pre; 653 654 do_div(numerator, iclk_pre); 655 656 return numerator; 657} 658 659/* Determine the exposure based on current hmax, vmax and a given SHR */ 660static u32 imx283_exposure(struct imx283 *imx283, 661 const struct imx283_mode *mode, u64 shr) 662{ 663 u32 svr = 0; /* SVR feature is not currently supported */ 664 u32 offset; 665 u64 numerator; 666 667 /* Number of clocks per internal offset period */ 668 offset = mode->mode == IMX283_MODE_0 ? 209 : 157; 669 numerator = (imx283->vmax * (svr + 1) - shr) * imx283->hmax + offset; 670 671 do_div(numerator, imx283->hmax); 672 673 return clamp(numerator, 0, U32_MAX); 674} 675 676static void imx283_exposure_limits(struct imx283 *imx283, 677 const struct imx283_mode *mode, 678 s64 *min_exposure, s64 *max_exposure) 679{ 680 u32 svr = 0; /* SVR feature is not currently supported */ 681 u64 min_shr = mode->min_shr; 682 /* Global Shutter is not supported */ 683 u64 max_shr = (svr + 1) * imx283->vmax - 4; 684 685 max_shr = min(max_shr, BIT(16) - 1); 686 687 *min_exposure = imx283_exposure(imx283, mode, max_shr); 688 *max_exposure = imx283_exposure(imx283, mode, min_shr); 689} 690 691/* 692 * Integration Time [s] = [ {VMAX x (SVR + 1) – (SHR)} x HMAX + offset ] 693 * / [ 72 x 10^6 ] 694 */ 695static u32 imx283_shr(struct imx283 *imx283, const struct imx283_mode *mode, 696 u32 exposure) 697{ 698 u32 svr = 0; /* SVR feature is not currently supported */ 699 u32 offset; 700 u64 temp; 701 702 /* Number of clocks per internal offset period */ 703 offset = mode->mode == IMX283_MODE_0 ? 209 : 157; 704 temp = ((u64)exposure * imx283->hmax - offset); 705 do_div(temp, imx283->hmax); 706 707 return (imx283->vmax * (svr + 1) - temp); 708} 709 710static const char * const imx283_tpg_menu[] = { 711 "Disabled", 712 "All 000h", 713 "All FFFh", 714 "All 555h", 715 "All AAAh", 716 "Horizontal color bars", 717 "Vertical color bars", 718}; 719 720static const int imx283_tpg_val[] = { 721 IMX283_TPG_PAT_ALL_000, 722 IMX283_TPG_PAT_ALL_000, 723 IMX283_TPG_PAT_ALL_FFF, 724 IMX283_TPG_PAT_ALL_555, 725 IMX283_TPG_PAT_ALL_AAA, 726 IMX283_TPG_PAT_H_COLOR_BARS, 727 IMX283_TPG_PAT_V_COLOR_BARS, 728}; 729 730static int imx283_update_test_pattern(struct imx283 *imx283, u32 pattern_index) 731{ 732 int ret; 733 734 if (pattern_index >= ARRAY_SIZE(imx283_tpg_val)) 735 return -EINVAL; 736 737 if (!pattern_index) 738 return cci_write(imx283->cci, IMX283_REG_TPG_CTRL, 0x00, NULL); 739 740 ret = cci_write(imx283->cci, IMX283_REG_TPG_PAT, 741 imx283_tpg_val[pattern_index], NULL); 742 if (ret) 743 return ret; 744 745 return cci_write(imx283->cci, IMX283_REG_TPG_CTRL, 746 IMX283_TPG_CTRL_CLKEN | IMX283_TPG_CTRL_PATEN, NULL); 747} 748 749static int imx283_set_ctrl(struct v4l2_ctrl *ctrl) 750{ 751 struct imx283 *imx283 = container_of(ctrl->handler, struct imx283, 752 ctrl_handler); 753 const struct imx283_mode *mode; 754 struct v4l2_mbus_framefmt *fmt; 755 const struct imx283_mode *mode_list; 756 struct v4l2_subdev_state *state; 757 unsigned int num_modes; 758 u64 shr, pixel_rate; 759 int ret = 0; 760 761 state = v4l2_subdev_get_locked_active_state(&imx283->sd); 762 fmt = v4l2_subdev_state_get_format(state, 0); 763 764 get_mode_table(fmt->code, &mode_list, &num_modes); 765 mode = v4l2_find_nearest_size(mode_list, num_modes, width, height, 766 fmt->width, fmt->height); 767 768 /* 769 * The VBLANK control may change the limits of usable exposure, so check 770 * and adjust if necessary. 771 */ 772 if (ctrl->id == V4L2_CID_VBLANK) { 773 /* Honour the VBLANK limits when setting exposure. */ 774 s64 current_exposure, max_exposure, min_exposure; 775 776 imx283->vmax = mode->height + ctrl->val; 777 778 imx283_exposure_limits(imx283, mode, 779 &min_exposure, &max_exposure); 780 781 current_exposure = imx283->exposure->val; 782 current_exposure = clamp(current_exposure, min_exposure, 783 max_exposure); 784 785 __v4l2_ctrl_modify_range(imx283->exposure, min_exposure, 786 max_exposure, 1, current_exposure); 787 } 788 789 /* 790 * Applying V4L2 control value only happens 791 * when power is up for streaming 792 */ 793 if (!pm_runtime_get_if_active(imx283->dev)) 794 return 0; 795 796 switch (ctrl->id) { 797 case V4L2_CID_EXPOSURE: 798 shr = imx283_shr(imx283, mode, ctrl->val); 799 dev_dbg(imx283->dev, "V4L2_CID_EXPOSURE : %d - SHR: %lld\n", 800 ctrl->val, shr); 801 ret = cci_write(imx283->cci, IMX283_REG_SHR, shr, NULL); 802 break; 803 804 case V4L2_CID_HBLANK: 805 pixel_rate = imx283_pixel_rate(imx283, mode); 806 imx283->hmax = imx283_internal_clock(pixel_rate, mode->width + ctrl->val); 807 dev_dbg(imx283->dev, "V4L2_CID_HBLANK : %d HMAX : %u\n", 808 ctrl->val, imx283->hmax); 809 ret = cci_write(imx283->cci, IMX283_REG_HMAX, imx283->hmax, NULL); 810 break; 811 812 case V4L2_CID_VBLANK: 813 imx283->vmax = mode->height + ctrl->val; 814 dev_dbg(imx283->dev, "V4L2_CID_VBLANK : %d VMAX : %u\n", 815 ctrl->val, imx283->vmax); 816 ret = cci_write(imx283->cci, IMX283_REG_VMAX, imx283->vmax, NULL); 817 break; 818 819 case V4L2_CID_ANALOGUE_GAIN: 820 ret = cci_write(imx283->cci, IMX283_REG_ANALOG_GAIN, ctrl->val, NULL); 821 break; 822 823 case V4L2_CID_DIGITAL_GAIN: 824 ret = cci_write(imx283->cci, IMX283_REG_DIGITAL_GAIN, ctrl->val, NULL); 825 break; 826 827 case V4L2_CID_VFLIP: 828 /* 829 * VFLIP is managed by BIT(0) of IMX283_REG_HTRIMMING address, hence 830 * both need to be set simultaneously. 831 */ 832 if (ctrl->val) { 833 cci_write(imx283->cci, IMX283_REG_HTRIMMING, 834 IMX283_HTRIMMING_EN | IMX283_MDVREV, &ret); 835 } else { 836 cci_write(imx283->cci, IMX283_REG_HTRIMMING, 837 IMX283_HTRIMMING_EN, &ret); 838 } 839 break; 840 841 case V4L2_CID_TEST_PATTERN: 842 ret = imx283_update_test_pattern(imx283, ctrl->val); 843 break; 844 845 default: 846 dev_err(imx283->dev, "ctrl(id:0x%x, val:0x%x) is not handled\n", 847 ctrl->id, ctrl->val); 848 break; 849 } 850 851 pm_runtime_put(imx283->dev); 852 853 return ret; 854} 855 856static const struct v4l2_ctrl_ops imx283_ctrl_ops = { 857 .s_ctrl = imx283_set_ctrl, 858}; 859 860static int imx283_enum_mbus_code(struct v4l2_subdev *sd, 861 struct v4l2_subdev_state *sd_state, 862 struct v4l2_subdev_mbus_code_enum *code) 863{ 864 if (code->index >= ARRAY_SIZE(imx283_mbus_codes)) 865 return -EINVAL; 866 867 code->code = imx283_mbus_codes[code->index]; 868 869 return 0; 870} 871 872static int imx283_enum_frame_size(struct v4l2_subdev *sd, 873 struct v4l2_subdev_state *sd_state, 874 struct v4l2_subdev_frame_size_enum *fse) 875{ 876 const struct imx283_mode *mode_list; 877 unsigned int num_modes; 878 879 get_mode_table(fse->code, &mode_list, &num_modes); 880 881 if (fse->index >= num_modes) 882 return -EINVAL; 883 884 fse->min_width = mode_list[fse->index].width; 885 fse->max_width = fse->min_width; 886 fse->min_height = mode_list[fse->index].height; 887 fse->max_height = fse->min_height; 888 889 return 0; 890} 891 892static void imx283_update_image_pad_format(struct imx283 *imx283, 893 const struct imx283_mode *mode, 894 struct v4l2_mbus_framefmt *format) 895{ 896 format->width = mode->width; 897 format->height = mode->height; 898 format->field = V4L2_FIELD_NONE; 899 format->colorspace = V4L2_COLORSPACE_RAW; 900 format->ycbcr_enc = V4L2_YCBCR_ENC_601; 901 format->quantization = V4L2_QUANTIZATION_FULL_RANGE; 902 format->xfer_func = V4L2_XFER_FUNC_NONE; 903} 904 905static int imx283_init_state(struct v4l2_subdev *sd, 906 struct v4l2_subdev_state *state) 907{ 908 struct imx283 *imx283 = to_imx283(sd); 909 struct v4l2_mbus_framefmt *format; 910 const struct imx283_mode *mode; 911 struct v4l2_rect *crop; 912 913 /* Initialize try_fmt */ 914 format = v4l2_subdev_state_get_format(state, IMAGE_PAD); 915 916 mode = &supported_modes_12bit[0]; 917 format->code = MEDIA_BUS_FMT_SRGGB12_1X12; 918 imx283_update_image_pad_format(imx283, mode, format); 919 920 /* Initialize crop rectangle to mode default */ 921 crop = v4l2_subdev_state_get_crop(state, IMAGE_PAD); 922 *crop = mode->crop; 923 924 return 0; 925} 926 927static void imx283_set_framing_limits(struct imx283 *imx283, 928 const struct imx283_mode *mode) 929{ 930 u64 pixel_rate = imx283_pixel_rate(imx283, mode); 931 u64 min_hblank, max_hblank, def_hblank; 932 933 /* Initialise hmax and vmax for exposure calculations */ 934 imx283->hmax = imx283_internal_clock(pixel_rate, mode->default_hmax); 935 imx283->vmax = mode->default_vmax; 936 937 /* 938 * Horizontal Blanking 939 * Convert the HMAX_MAX (72MHz) to Pixel rate values for HBLANK_MAX 940 */ 941 min_hblank = mode->min_hmax - mode->width; 942 max_hblank = imx283_iclk_to_pix(pixel_rate, IMX283_HMAX_MAX) - mode->width; 943 def_hblank = mode->default_hmax - mode->width; 944 __v4l2_ctrl_modify_range(imx283->hblank, min_hblank, max_hblank, 1, 945 def_hblank); 946 __v4l2_ctrl_s_ctrl(imx283->hblank, def_hblank); 947 948 /* Vertical Blanking */ 949 __v4l2_ctrl_modify_range(imx283->vblank, mode->min_vmax - mode->height, 950 IMX283_VMAX_MAX - mode->height, 1, 951 mode->default_vmax - mode->height); 952 __v4l2_ctrl_s_ctrl(imx283->vblank, mode->default_vmax - mode->height); 953} 954 955static int imx283_set_pad_format(struct v4l2_subdev *sd, 956 struct v4l2_subdev_state *sd_state, 957 struct v4l2_subdev_format *fmt) 958{ 959 struct v4l2_mbus_framefmt *format; 960 const struct imx283_mode *mode; 961 struct imx283 *imx283 = to_imx283(sd); 962 const struct imx283_mode *mode_list; 963 unsigned int num_modes; 964 965 get_mode_table(fmt->format.code, &mode_list, &num_modes); 966 967 mode = v4l2_find_nearest_size(mode_list, num_modes, width, height, 968 fmt->format.width, fmt->format.height); 969 970 fmt->format.width = mode->width; 971 fmt->format.height = mode->height; 972 fmt->format.field = V4L2_FIELD_NONE; 973 fmt->format.colorspace = V4L2_COLORSPACE_RAW; 974 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_601; 975 fmt->format.quantization = V4L2_QUANTIZATION_FULL_RANGE; 976 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE; 977 978 format = v4l2_subdev_state_get_format(sd_state, 0); 979 980 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) 981 imx283_set_framing_limits(imx283, mode); 982 983 *format = fmt->format; 984 985 return 0; 986} 987 988static int imx283_standby_cancel(struct imx283 *imx283) 989{ 990 unsigned int link_freq_idx; 991 int ret = 0; 992 993 cci_write(imx283->cci, IMX283_REG_STANDBY, 994 IMX283_STBLOGIC | IMX283_STBDV, &ret); 995 996 /* Configure PLL clocks based on the xclk */ 997 cci_multi_reg_write(imx283->cci, imx283->freq->regs, 998 imx283->freq->reg_count, &ret); 999 1000 dev_dbg(imx283->dev, "Using clk freq %ld MHz", 1001 imx283->freq->mhz / HZ_PER_MHZ); 1002 1003 /* Initialise communication */ 1004 cci_write(imx283->cci, IMX283_REG_PLSTMG08, IMX283_PLSTMG08_VAL, &ret); 1005 cci_write(imx283->cci, IMX283_REG_PLSTMG02, IMX283_PLSTMG02_VAL, &ret); 1006 1007 /* Enable PLL */ 1008 cci_write(imx283->cci, IMX283_REG_STBPL, IMX283_STBPL_NORMAL, &ret); 1009 1010 /* Configure the MIPI link speed */ 1011 link_freq_idx = __ffs(imx283->link_freq_bitmap); 1012 cci_multi_reg_write(imx283->cci, link_freq_reglist[link_freq_idx].regs, 1013 link_freq_reglist[link_freq_idx].num_of_regs, 1014 &ret); 1015 1016 /* 1st Stabilisation period of 1 ms or more */ 1017 usleep_range(1000, 2000); 1018 1019 /* Activate */ 1020 cci_write(imx283->cci, IMX283_REG_STANDBY, IMX283_ACTIVE, &ret); 1021 1022 /* 2nd Stabilisation period of 19ms or more */ 1023 usleep_range(19000, 20000); 1024 1025 cci_write(imx283->cci, IMX283_REG_CLAMP, IMX283_CLPSQRST, &ret); 1026 cci_write(imx283->cci, IMX283_REG_XMSTA, 0, &ret); 1027 cci_write(imx283->cci, IMX283_REG_SYNCDRV, IMX283_SYNCDRV_XHS_XVS, &ret); 1028 1029 return ret; 1030} 1031 1032/* Start streaming */ 1033static int imx283_start_streaming(struct imx283 *imx283, 1034 struct v4l2_subdev_state *state) 1035{ 1036 const struct imx283_readout_mode *readout; 1037 const struct imx283_mode *mode; 1038 const struct v4l2_mbus_framefmt *fmt; 1039 const struct imx283_mode *mode_list; 1040 unsigned int num_modes; 1041 u32 v_widcut; 1042 s32 v_pos; 1043 u32 write_v_size; 1044 u32 y_out_size; 1045 int ret = 0; 1046 1047 fmt = v4l2_subdev_state_get_format(state, 0); 1048 get_mode_table(fmt->code, &mode_list, &num_modes); 1049 mode = v4l2_find_nearest_size(mode_list, num_modes, width, height, 1050 fmt->width, fmt->height); 1051 1052 ret = imx283_standby_cancel(imx283); 1053 if (ret) { 1054 dev_err(imx283->dev, "failed to cancel standby\n"); 1055 return ret; 1056 } 1057 1058 /* 1059 * Set the readout mode registers. 1060 * MDSEL3 and MDSEL4 are updated to enable Arbitrary Vertical Cropping. 1061 */ 1062 readout = &imx283_readout_modes[mode->mode]; 1063 cci_write(imx283->cci, IMX283_REG_MDSEL1, readout->mdsel1, &ret); 1064 cci_write(imx283->cci, IMX283_REG_MDSEL2, readout->mdsel2, &ret); 1065 cci_write(imx283->cci, IMX283_REG_MDSEL3, 1066 readout->mdsel3 | IMX283_MDSEL3_VCROP_EN, &ret); 1067 cci_write(imx283->cci, IMX283_REG_MDSEL4, 1068 readout->mdsel4 | IMX283_MDSEL4_VCROP_EN, &ret); 1069 1070 /* Mode 1S specific entries from the Readout Drive Mode Tables */ 1071 if (mode->mode == IMX283_MODE_1S) { 1072 cci_write(imx283->cci, IMX283_REG_MDSEL7, 0x01, &ret); 1073 cci_write(imx283->cci, IMX283_REG_MDSEL18, 0x1098, &ret); 1074 } 1075 1076 if (ret) { 1077 dev_err(imx283->dev, "failed to set readout\n"); 1078 return ret; 1079 } 1080 1081 /* Initialise SVR. Unsupported for now - Always 0 */ 1082 cci_write(imx283->cci, IMX283_REG_SVR, 0x00, &ret); 1083 1084 dev_dbg(imx283->dev, "Mode: Size %d x %d\n", mode->width, mode->height); 1085 dev_dbg(imx283->dev, "Analogue Crop (in the mode) (%d,%d)/%ux%u\n", 1086 mode->crop.left, 1087 mode->crop.top, 1088 mode->crop.width, 1089 mode->crop.height); 1090 1091 y_out_size = mode->crop.height / mode->vbin_ratio; 1092 write_v_size = y_out_size + mode->vertical_ob; 1093 /* 1094 * cropping start position = (VWINPOS – Vst) × 2 1095 * cropping width = Veff – (VWIDCUT – Vct) × 2 1096 */ 1097 v_pos = imx283->vflip->val ? 1098 ((-mode->crop.top / mode->vbin_ratio) / 2) + mode->vst : 1099 ((mode->crop.top / mode->vbin_ratio) / 2) + mode->vst; 1100 v_widcut = ((mode->veff - y_out_size) / 2) + mode->vct; 1101 1102 cci_write(imx283->cci, IMX283_REG_Y_OUT_SIZE, y_out_size, &ret); 1103 cci_write(imx283->cci, IMX283_REG_WRITE_VSIZE, write_v_size, &ret); 1104 cci_write(imx283->cci, IMX283_REG_VWIDCUT, v_widcut, &ret); 1105 cci_write(imx283->cci, IMX283_REG_VWINPOS, v_pos, &ret); 1106 1107 cci_write(imx283->cci, IMX283_REG_OB_SIZE_V, mode->vertical_ob, &ret); 1108 1109 /* TODO: Validate mode->crop is fully contained within imx283_native_area */ 1110 cci_write(imx283->cci, IMX283_REG_HTRIMMING_START, mode->crop.left, &ret); 1111 cci_write(imx283->cci, IMX283_REG_HTRIMMING_END, 1112 mode->crop.left + mode->crop.width, &ret); 1113 1114 /* Disable embedded data */ 1115 cci_write(imx283->cci, IMX283_REG_EBD_X_OUT_SIZE, 0, &ret); 1116 1117 /* Apply customized values from controls (HMAX/VMAX/SHR) */ 1118 ret = __v4l2_ctrl_handler_setup(imx283->sd.ctrl_handler); 1119 1120 return ret; 1121} 1122 1123static int imx283_enable_streams(struct v4l2_subdev *sd, 1124 struct v4l2_subdev_state *state, u32 pad, 1125 u64 streams_mask) 1126{ 1127 struct imx283 *imx283 = to_imx283(sd); 1128 int ret; 1129 1130 if (pad != IMAGE_PAD) 1131 return -EINVAL; 1132 1133 ret = pm_runtime_get_sync(imx283->dev); 1134 if (ret < 0) { 1135 pm_runtime_put_noidle(imx283->dev); 1136 return ret; 1137 } 1138 1139 ret = imx283_start_streaming(imx283, state); 1140 if (ret) 1141 goto err_rpm_put; 1142 1143 return 0; 1144 1145err_rpm_put: 1146 pm_runtime_put_autosuspend(imx283->dev); 1147 1148 return ret; 1149} 1150 1151static int imx283_disable_streams(struct v4l2_subdev *sd, 1152 struct v4l2_subdev_state *state, u32 pad, 1153 u64 streams_mask) 1154{ 1155 struct imx283 *imx283 = to_imx283(sd); 1156 int ret; 1157 1158 if (pad != IMAGE_PAD) 1159 return -EINVAL; 1160 1161 ret = cci_write(imx283->cci, IMX283_REG_STANDBY, IMX283_STBLOGIC, NULL); 1162 if (ret) 1163 dev_err(imx283->dev, "Failed to stop stream\n"); 1164 1165 pm_runtime_put_autosuspend(imx283->dev); 1166 1167 return ret; 1168} 1169 1170/* Power/clock management functions */ 1171static int imx283_power_on(struct device *dev) 1172{ 1173 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1174 struct imx283 *imx283 = to_imx283(sd); 1175 int ret; 1176 1177 ret = regulator_bulk_enable(ARRAY_SIZE(imx283_supply_name), 1178 imx283->supplies); 1179 if (ret) { 1180 dev_err(imx283->dev, "failed to enable regulators\n"); 1181 return ret; 1182 } 1183 1184 ret = clk_prepare_enable(imx283->xclk); 1185 if (ret) { 1186 dev_err(imx283->dev, "failed to enable clock\n"); 1187 goto reg_off; 1188 } 1189 1190 gpiod_set_value_cansleep(imx283->reset_gpio, 0); 1191 1192 usleep_range(IMX283_XCLR_MIN_DELAY_US, 1193 IMX283_XCLR_MIN_DELAY_US + IMX283_XCLR_DELAY_RANGE_US); 1194 1195 return 0; 1196 1197reg_off: 1198 regulator_bulk_disable(ARRAY_SIZE(imx283_supply_name), imx283->supplies); 1199 return ret; 1200} 1201 1202static int imx283_power_off(struct device *dev) 1203{ 1204 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1205 struct imx283 *imx283 = to_imx283(sd); 1206 1207 gpiod_set_value_cansleep(imx283->reset_gpio, 1); 1208 regulator_bulk_disable(ARRAY_SIZE(imx283_supply_name), imx283->supplies); 1209 clk_disable_unprepare(imx283->xclk); 1210 1211 return 0; 1212} 1213 1214static int imx283_get_regulators(struct imx283 *imx283) 1215{ 1216 unsigned int i; 1217 1218 for (i = 0; i < ARRAY_SIZE(imx283_supply_name); i++) 1219 imx283->supplies[i].supply = imx283_supply_name[i]; 1220 1221 return devm_regulator_bulk_get(imx283->dev, 1222 ARRAY_SIZE(imx283_supply_name), 1223 imx283->supplies); 1224} 1225 1226/* Verify chip ID */ 1227static int imx283_identify_module(struct imx283 *imx283) 1228{ 1229 int ret; 1230 u64 val; 1231 1232 ret = cci_read(imx283->cci, IMX283_REG_CHIP_ID, &val, NULL); 1233 if (ret) { 1234 dev_err(imx283->dev, "failed to read chip id %x, with error %d\n", 1235 IMX283_CHIP_ID, ret); 1236 return ret; 1237 } 1238 1239 if (val != IMX283_CHIP_ID) { 1240 dev_err(imx283->dev, "chip id mismatch: %x!=%llx\n", 1241 IMX283_CHIP_ID, val); 1242 return -EIO; 1243 } 1244 1245 return 0; 1246} 1247 1248static int imx283_get_selection(struct v4l2_subdev *sd, 1249 struct v4l2_subdev_state *sd_state, 1250 struct v4l2_subdev_selection *sel) 1251{ 1252 switch (sel->target) { 1253 case V4L2_SEL_TGT_CROP: { 1254 sel->r = *v4l2_subdev_state_get_crop(sd_state, 0); 1255 return 0; 1256 } 1257 1258 case V4L2_SEL_TGT_NATIVE_SIZE: 1259 sel->r = imx283_native_area; 1260 return 0; 1261 1262 case V4L2_SEL_TGT_CROP_DEFAULT: 1263 case V4L2_SEL_TGT_CROP_BOUNDS: 1264 sel->r = imx283_active_area; 1265 return 0; 1266 default: 1267 return -EINVAL; 1268 } 1269} 1270 1271static const struct v4l2_subdev_video_ops imx283_video_ops = { 1272 .s_stream = v4l2_subdev_s_stream_helper, 1273}; 1274 1275static const struct v4l2_subdev_pad_ops imx283_pad_ops = { 1276 .enum_mbus_code = imx283_enum_mbus_code, 1277 .get_fmt = v4l2_subdev_get_fmt, 1278 .set_fmt = imx283_set_pad_format, 1279 .get_selection = imx283_get_selection, 1280 .enum_frame_size = imx283_enum_frame_size, 1281 .enable_streams = imx283_enable_streams, 1282 .disable_streams = imx283_disable_streams, 1283}; 1284 1285static const struct v4l2_subdev_internal_ops imx283_internal_ops = { 1286 .init_state = imx283_init_state, 1287}; 1288 1289static const struct v4l2_subdev_ops imx283_subdev_ops = { 1290 .video = &imx283_video_ops, 1291 .pad = &imx283_pad_ops, 1292}; 1293 1294/* Initialize control handlers */ 1295static int imx283_init_controls(struct imx283 *imx283) 1296{ 1297 struct v4l2_ctrl_handler *ctrl_hdlr; 1298 struct v4l2_fwnode_device_properties props; 1299 struct v4l2_ctrl *link_freq; 1300 const struct imx283_mode *mode = &supported_modes_12bit[0]; 1301 u64 min_hblank, max_hblank, def_hblank; 1302 u64 pixel_rate; 1303 int ret; 1304 1305 ctrl_hdlr = &imx283->ctrl_handler; 1306 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 16); 1307 if (ret) 1308 return ret; 1309 1310 /* 1311 * Create the controls here, but mode specific limits are setup 1312 * in the imx283_set_framing_limits() call below. 1313 */ 1314 1315 /* By default, PIXEL_RATE is read only */ 1316 pixel_rate = imx283_pixel_rate(imx283, mode); 1317 v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, 1318 V4L2_CID_PIXEL_RATE, pixel_rate, 1319 pixel_rate, 1, pixel_rate); 1320 1321 link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &imx283_ctrl_ops, 1322 V4L2_CID_LINK_FREQ, 1323 __fls(imx283->link_freq_bitmap), 1324 __ffs(imx283->link_freq_bitmap), 1325 link_frequencies); 1326 if (link_freq) 1327 link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1328 1329 /* Initialise vblank/hblank/exposure based on the current mode. */ 1330 imx283->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, 1331 V4L2_CID_VBLANK, 1332 mode->min_vmax - mode->height, 1333 IMX283_VMAX_MAX, 1, 1334 mode->default_vmax - mode->height); 1335 1336 min_hblank = mode->min_hmax - mode->width; 1337 max_hblank = imx283_iclk_to_pix(pixel_rate, IMX283_HMAX_MAX) - mode->width; 1338 def_hblank = mode->default_hmax - mode->width; 1339 imx283->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, 1340 V4L2_CID_HBLANK, min_hblank, max_hblank, 1341 1, def_hblank); 1342 1343 imx283->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, 1344 V4L2_CID_EXPOSURE, 1345 IMX283_EXPOSURE_MIN, 1346 IMX283_EXPOSURE_MAX, 1347 IMX283_EXPOSURE_STEP, 1348 IMX283_EXPOSURE_DEFAULT); 1349 1350 v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 1351 IMX283_ANA_GAIN_MIN, IMX283_ANA_GAIN_MAX, 1352 IMX283_ANA_GAIN_STEP, IMX283_ANA_GAIN_DEFAULT); 1353 1354 v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 1355 IMX283_DGTL_GAIN_MIN, IMX283_DGTL_GAIN_MAX, 1356 IMX283_DGTL_GAIN_STEP, IMX283_DGTL_GAIN_DEFAULT); 1357 1358 imx283->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, V4L2_CID_VFLIP, 1359 0, 1, 1, 0); 1360 if (imx283->vflip) 1361 imx283->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 1362 1363 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx283_ctrl_ops, 1364 V4L2_CID_TEST_PATTERN, 1365 ARRAY_SIZE(imx283_tpg_menu) - 1, 1366 0, 0, imx283_tpg_menu); 1367 1368 if (ctrl_hdlr->error) { 1369 ret = ctrl_hdlr->error; 1370 dev_err(imx283->dev, "control init failed (%d)\n", ret); 1371 goto error; 1372 } 1373 1374 ret = v4l2_fwnode_device_parse(imx283->dev, &props); 1375 if (ret) 1376 goto error; 1377 1378 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx283_ctrl_ops, 1379 &props); 1380 if (ret) 1381 goto error; 1382 1383 imx283->sd.ctrl_handler = ctrl_hdlr; 1384 1385 mutex_lock(imx283->ctrl_handler.lock); 1386 1387 /* Setup exposure and frame/line length limits. */ 1388 imx283_set_framing_limits(imx283, mode); 1389 1390 mutex_unlock(imx283->ctrl_handler.lock); 1391 1392 return 0; 1393 1394error: 1395 v4l2_ctrl_handler_free(ctrl_hdlr); 1396 1397 return ret; 1398} 1399 1400static int imx283_parse_endpoint(struct imx283 *imx283) 1401{ 1402 struct fwnode_handle *fwnode; 1403 struct v4l2_fwnode_endpoint bus_cfg = { 1404 .bus_type = V4L2_MBUS_CSI2_DPHY 1405 }; 1406 struct fwnode_handle *ep; 1407 int ret; 1408 1409 fwnode = dev_fwnode(imx283->dev); 1410 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 1411 if (!ep) { 1412 dev_err(imx283->dev, "Failed to get next endpoint\n"); 1413 return -ENXIO; 1414 } 1415 1416 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 1417 fwnode_handle_put(ep); 1418 if (ret) 1419 return ret; 1420 1421 if (bus_cfg.bus.mipi_csi2.num_data_lanes != 4) { 1422 dev_err(imx283->dev, 1423 "number of CSI2 data lanes %d is not supported\n", 1424 bus_cfg.bus.mipi_csi2.num_data_lanes); 1425 ret = -EINVAL; 1426 goto done_endpoint_free; 1427 } 1428 1429 ret = v4l2_link_freq_to_bitmap(imx283->dev, bus_cfg.link_frequencies, 1430 bus_cfg.nr_of_link_frequencies, 1431 link_frequencies, ARRAY_SIZE(link_frequencies), 1432 &imx283->link_freq_bitmap); 1433 1434done_endpoint_free: 1435 v4l2_fwnode_endpoint_free(&bus_cfg); 1436 1437 return ret; 1438}; 1439 1440static int imx283_probe(struct i2c_client *client) 1441{ 1442 struct imx283 *imx283; 1443 unsigned int i; 1444 unsigned int xclk_freq; 1445 int ret; 1446 1447 imx283 = devm_kzalloc(&client->dev, sizeof(*imx283), GFP_KERNEL); 1448 if (!imx283) 1449 return -ENOMEM; 1450 1451 imx283->dev = &client->dev; 1452 1453 v4l2_i2c_subdev_init(&imx283->sd, client, &imx283_subdev_ops); 1454 1455 imx283->cci = devm_cci_regmap_init_i2c(client, 16); 1456 if (IS_ERR(imx283->cci)) { 1457 ret = PTR_ERR(imx283->cci); 1458 dev_err(imx283->dev, "failed to initialize CCI: %d\n", ret); 1459 return ret; 1460 } 1461 1462 /* Get system clock (xclk) */ 1463 imx283->xclk = devm_v4l2_sensor_clk_get(imx283->dev, NULL); 1464 if (IS_ERR(imx283->xclk)) 1465 return dev_err_probe(imx283->dev, PTR_ERR(imx283->xclk), 1466 "failed to get xclk\n"); 1467 1468 xclk_freq = clk_get_rate(imx283->xclk); 1469 for (i = 0; i < ARRAY_SIZE(imx283_frequencies); i++) { 1470 if (xclk_freq == imx283_frequencies[i].mhz) { 1471 imx283->freq = &imx283_frequencies[i]; 1472 break; 1473 } 1474 } 1475 if (!imx283->freq) { 1476 dev_err(imx283->dev, "xclk frequency unsupported: %d Hz\n", xclk_freq); 1477 return -EINVAL; 1478 } 1479 1480 ret = imx283_get_regulators(imx283); 1481 if (ret) { 1482 return dev_err_probe(imx283->dev, ret, 1483 "failed to get regulators\n"); 1484 } 1485 1486 ret = imx283_parse_endpoint(imx283); 1487 if (ret) { 1488 dev_err(imx283->dev, "failed to parse endpoint configuration\n"); 1489 return ret; 1490 } 1491 1492 /* Request optional enable pin */ 1493 imx283->reset_gpio = devm_gpiod_get_optional(imx283->dev, "reset", 1494 GPIOD_OUT_LOW); 1495 if (IS_ERR(imx283->reset_gpio)) 1496 return dev_err_probe(imx283->dev, PTR_ERR(imx283->reset_gpio), 1497 "failed to get reset GPIO\n"); 1498 1499 /* 1500 * The sensor must be powered for imx283_identify_module() 1501 * to be able to read the CHIP_ID register 1502 */ 1503 ret = imx283_power_on(imx283->dev); 1504 if (ret) 1505 return ret; 1506 1507 ret = imx283_identify_module(imx283); 1508 if (ret) 1509 goto error_power_off; 1510 1511 /* 1512 * Enable runtime PM with autosuspend. As the device has been powered 1513 * manually, mark it as active, and increase the usage count without 1514 * resuming the device. 1515 */ 1516 pm_runtime_set_active(imx283->dev); 1517 pm_runtime_get_noresume(imx283->dev); 1518 pm_runtime_enable(imx283->dev); 1519 pm_runtime_set_autosuspend_delay(imx283->dev, 1000); 1520 pm_runtime_use_autosuspend(imx283->dev); 1521 1522 /* This needs the pm runtime to be registered. */ 1523 ret = imx283_init_controls(imx283); 1524 if (ret) 1525 goto error_pm; 1526 1527 /* Initialize subdev */ 1528 imx283->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1529 imx283->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1530 imx283->sd.internal_ops = &imx283_internal_ops; 1531 1532 /* Initialize source pads */ 1533 imx283->pad.flags = MEDIA_PAD_FL_SOURCE; 1534 1535 ret = media_entity_pads_init(&imx283->sd.entity, 1, &imx283->pad); 1536 if (ret) { 1537 dev_err(imx283->dev, "failed to init entity pads: %d\n", ret); 1538 goto error_handler_free; 1539 } 1540 1541 imx283->sd.state_lock = imx283->ctrl_handler.lock; 1542 ret = v4l2_subdev_init_finalize(&imx283->sd); 1543 if (ret < 0) { 1544 dev_err(imx283->dev, "subdev init error: %d\n", ret); 1545 goto error_media_entity; 1546 } 1547 1548 ret = v4l2_async_register_subdev_sensor(&imx283->sd); 1549 if (ret < 0) { 1550 dev_err(imx283->dev, "failed to register sensor sub-device: %d\n", ret); 1551 goto error_subdev_cleanup; 1552 } 1553 1554 /* 1555 * Decrease the PM usage count. The device will get suspended after the 1556 * autosuspend delay, turning the power off. 1557 */ 1558 pm_runtime_put_autosuspend(imx283->dev); 1559 1560 return 0; 1561 1562error_subdev_cleanup: 1563 v4l2_subdev_cleanup(&imx283->sd); 1564 1565error_media_entity: 1566 media_entity_cleanup(&imx283->sd.entity); 1567 1568error_handler_free: 1569 v4l2_ctrl_handler_free(imx283->sd.ctrl_handler); 1570 1571error_pm: 1572 pm_runtime_disable(imx283->dev); 1573 pm_runtime_set_suspended(imx283->dev); 1574error_power_off: 1575 imx283_power_off(imx283->dev); 1576 1577 return ret; 1578} 1579 1580static void imx283_remove(struct i2c_client *client) 1581{ 1582 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1583 struct imx283 *imx283 = to_imx283(sd); 1584 1585 v4l2_async_unregister_subdev(sd); 1586 v4l2_subdev_cleanup(&imx283->sd); 1587 media_entity_cleanup(&sd->entity); 1588 v4l2_ctrl_handler_free(imx283->sd.ctrl_handler); 1589 1590 pm_runtime_disable(imx283->dev); 1591 if (!pm_runtime_status_suspended(imx283->dev)) 1592 imx283_power_off(imx283->dev); 1593 pm_runtime_set_suspended(imx283->dev); 1594} 1595 1596static DEFINE_RUNTIME_DEV_PM_OPS(imx283_pm_ops, imx283_power_off, 1597 imx283_power_on, NULL); 1598 1599static const struct of_device_id imx283_dt_ids[] = { 1600 { .compatible = "sony,imx283" }, 1601 { /* sentinel */ } 1602}; 1603MODULE_DEVICE_TABLE(of, imx283_dt_ids); 1604 1605static struct i2c_driver imx283_i2c_driver = { 1606 .driver = { 1607 .name = "imx283", 1608 .pm = pm_ptr(&imx283_pm_ops), 1609 .of_match_table = imx283_dt_ids, 1610 }, 1611 .probe = imx283_probe, 1612 .remove = imx283_remove, 1613}; 1614module_i2c_driver(imx283_i2c_driver); 1615 1616MODULE_AUTHOR("Will Whang <will@willwhang.com>"); 1617MODULE_AUTHOR("Kieran Bingham <kieran.bingham@ideasonboard.com>"); 1618MODULE_AUTHOR("Umang Jain <umang.jain@ideasonboard.com>"); 1619MODULE_DESCRIPTION("Sony IMX283 Sensor Driver"); 1620MODULE_LICENSE("GPL");
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