imx258.c

   1// SPDX-License-Identifier: GPL-2.0
   2// Copyright (C) 2018 Intel Corporation
   3
   4#include <linux/acpi.h>
   5#include <linux/clk.h>
   6#include <linux/delay.h>
   7#include <linux/i2c.h>
   8#include <linux/module.h>
   9#include <linux/pm_runtime.h>
  10#include <linux/regulator/consumer.h>
  11#include <linux/unaligned.h>
  12
  13#include <media/v4l2-cci.h>
  14#include <media/v4l2-ctrls.h>
  15#include <media/v4l2-device.h>
  16#include <media/v4l2-fwnode.h>
  17
  18#define IMX258_REG_MODE_SELECT		CCI_REG8(0x0100)
  19#define IMX258_MODE_STANDBY		0x00
  20#define IMX258_MODE_STREAMING		0x01
  21
  22#define IMX258_REG_RESET		CCI_REG8(0x0103)
  23
  24/* Chip ID */
  25#define IMX258_REG_CHIP_ID		CCI_REG16(0x0016)
  26#define IMX258_CHIP_ID			0x0258
  27
  28/* V_TIMING internal */
  29#define IMX258_VTS_30FPS		0x0c50
  30#define IMX258_VTS_30FPS_2K		0x0638
  31#define IMX258_VTS_30FPS_VGA		0x034c
  32#define IMX258_VTS_MAX			65525
  33
  34/* HBLANK control - read only */
  35#define IMX258_PPL_DEFAULT		5352
  36
  37/* Exposure control */
  38#define IMX258_REG_EXPOSURE		CCI_REG16(0x0202)
  39#define IMX258_EXPOSURE_OFFSET		10
  40#define IMX258_EXPOSURE_MIN		4
  41#define IMX258_EXPOSURE_STEP		1
  42#define IMX258_EXPOSURE_DEFAULT		0x640
  43#define IMX258_EXPOSURE_MAX		(IMX258_VTS_MAX - IMX258_EXPOSURE_OFFSET)
  44
  45/* Analog gain control */
  46#define IMX258_REG_ANALOG_GAIN		CCI_REG16(0x0204)
  47#define IMX258_ANA_GAIN_MIN		0
  48#define IMX258_ANA_GAIN_MAX		480
  49#define IMX258_ANA_GAIN_STEP		1
  50#define IMX258_ANA_GAIN_DEFAULT		0x0
  51
  52/* Digital gain control */
  53#define IMX258_REG_GR_DIGITAL_GAIN	CCI_REG16(0x020e)
  54#define IMX258_REG_R_DIGITAL_GAIN	CCI_REG16(0x0210)
  55#define IMX258_REG_B_DIGITAL_GAIN	CCI_REG16(0x0212)
  56#define IMX258_REG_GB_DIGITAL_GAIN	CCI_REG16(0x0214)
  57#define IMX258_DGTL_GAIN_MIN		0
  58#define IMX258_DGTL_GAIN_MAX		4096	/* Max = 0xFFF */
  59#define IMX258_DGTL_GAIN_DEFAULT	1024
  60#define IMX258_DGTL_GAIN_STEP		1
  61
  62/* HDR control */
  63#define IMX258_REG_HDR			CCI_REG8(0x0220)
  64#define IMX258_HDR_ON			BIT(0)
  65#define IMX258_REG_HDR_RATIO		CCI_REG8(0x0222)
  66#define IMX258_HDR_RATIO_MIN		0
  67#define IMX258_HDR_RATIO_MAX		5
  68#define IMX258_HDR_RATIO_STEP		1
  69#define IMX258_HDR_RATIO_DEFAULT	0x0
  70
  71/* Test Pattern Control */
  72#define IMX258_REG_TEST_PATTERN		CCI_REG16(0x0600)
  73
  74#define IMX258_CLK_BLANK_STOP		CCI_REG8(0x4040)
  75
  76/* Orientation */
  77#define REG_MIRROR_FLIP_CONTROL		CCI_REG8(0x0101)
  78#define REG_CONFIG_MIRROR_HFLIP		0x01
  79#define REG_CONFIG_MIRROR_VFLIP		0x02
  80
  81/* IMX258 native and active pixel array size. */
  82#define IMX258_NATIVE_WIDTH		4224U
  83#define IMX258_NATIVE_HEIGHT		3192U
  84#define IMX258_PIXEL_ARRAY_LEFT		8U
  85#define IMX258_PIXEL_ARRAY_TOP		16U
  86#define IMX258_PIXEL_ARRAY_WIDTH	4208U
  87#define IMX258_PIXEL_ARRAY_HEIGHT	3120U
  88
  89/* regs */
  90#define IMX258_REG_PLL_MULT_DRIV                  CCI_REG8(0x0310)
  91#define IMX258_REG_IVTPXCK_DIV                    CCI_REG8(0x0301)
  92#define IMX258_REG_IVTSYCK_DIV                    CCI_REG8(0x0303)
  93#define IMX258_REG_PREPLLCK_VT_DIV                CCI_REG8(0x0305)
  94#define IMX258_REG_IOPPXCK_DIV                    CCI_REG8(0x0309)
  95#define IMX258_REG_IOPSYCK_DIV                    CCI_REG8(0x030b)
  96#define IMX258_REG_PREPLLCK_OP_DIV                CCI_REG8(0x030d)
  97#define IMX258_REG_PHASE_PIX_OUTEN                CCI_REG8(0x3030)
  98#define IMX258_REG_PDPIX_DATA_RATE                CCI_REG8(0x3032)
  99#define IMX258_REG_SCALE_MODE                     CCI_REG8(0x0401)
 100#define IMX258_REG_SCALE_MODE_EXT                 CCI_REG8(0x3038)
 101#define IMX258_REG_AF_WINDOW_MODE                 CCI_REG8(0x7bcd)
 102#define IMX258_REG_FRM_LENGTH_CTL                 CCI_REG8(0x0350)
 103#define IMX258_REG_CSI_LANE_MODE                  CCI_REG8(0x0114)
 104#define IMX258_REG_X_EVN_INC                      CCI_REG8(0x0381)
 105#define IMX258_REG_X_ODD_INC                      CCI_REG8(0x0383)
 106#define IMX258_REG_Y_EVN_INC                      CCI_REG8(0x0385)
 107#define IMX258_REG_Y_ODD_INC                      CCI_REG8(0x0387)
 108#define IMX258_REG_BINNING_MODE                   CCI_REG8(0x0900)
 109#define IMX258_REG_BINNING_TYPE_V                 CCI_REG8(0x0901)
 110#define IMX258_REG_FORCE_FD_SUM                   CCI_REG8(0x300d)
 111#define IMX258_REG_DIG_CROP_X_OFFSET              CCI_REG16(0x0408)
 112#define IMX258_REG_DIG_CROP_Y_OFFSET              CCI_REG16(0x040a)
 113#define IMX258_REG_DIG_CROP_IMAGE_WIDTH           CCI_REG16(0x040c)
 114#define IMX258_REG_DIG_CROP_IMAGE_HEIGHT          CCI_REG16(0x040e)
 115#define IMX258_REG_SCALE_M                        CCI_REG16(0x0404)
 116#define IMX258_REG_X_OUT_SIZE                     CCI_REG16(0x034c)
 117#define IMX258_REG_Y_OUT_SIZE                     CCI_REG16(0x034e)
 118#define IMX258_REG_X_ADD_STA                      CCI_REG16(0x0344)
 119#define IMX258_REG_Y_ADD_STA                      CCI_REG16(0x0346)
 120#define IMX258_REG_X_ADD_END                      CCI_REG16(0x0348)
 121#define IMX258_REG_Y_ADD_END                      CCI_REG16(0x034a)
 122#define IMX258_REG_EXCK_FREQ                      CCI_REG16(0x0136)
 123#define IMX258_REG_CSI_DT_FMT                     CCI_REG16(0x0112)
 124#define IMX258_REG_LINE_LENGTH_PCK                CCI_REG16(0x0342)
 125#define IMX258_REG_SCALE_M_EXT                    CCI_REG16(0x303a)
 126#define IMX258_REG_FRM_LENGTH_LINES               CCI_REG16(0x0340)
 127#define IMX258_REG_FINE_INTEG_TIME                CCI_REG8(0x0200)
 128#define IMX258_REG_PLL_IVT_MPY                    CCI_REG16(0x0306)
 129#define IMX258_REG_PLL_IOP_MPY                    CCI_REG16(0x030e)
 130#define IMX258_REG_REQ_LINK_BIT_RATE_MBPS_H       CCI_REG16(0x0820)
 131#define IMX258_REG_REQ_LINK_BIT_RATE_MBPS_L       CCI_REG16(0x0822)
 132
 133struct imx258_reg_list {
 134	u32 num_of_regs;
 135	const struct cci_reg_sequence *regs;
 136};
 137
 138struct imx258_link_cfg {
 139	unsigned int lf_to_pix_rate_factor;
 140	struct imx258_reg_list reg_list;
 141};
 142
 143enum {
 144	IMX258_2_LANE_MODE,
 145	IMX258_4_LANE_MODE,
 146	IMX258_LANE_CONFIGS,
 147};
 148
 149/* Link frequency config */
 150struct imx258_link_freq_config {
 151	u32 pixels_per_line;
 152
 153	/* Configuration for this link frequency / num lanes selection */
 154	struct imx258_link_cfg link_cfg[IMX258_LANE_CONFIGS];
 155};
 156
 157/* Mode : resolution and related config&values */
 158struct imx258_mode {
 159	/* Frame width */
 160	u32 width;
 161	/* Frame height */
 162	u32 height;
 163
 164	/* V-timing */
 165	u32 vts_def;
 166	u32 vts_min;
 167
 168	/* Index of Link frequency config to be used */
 169	u32 link_freq_index;
 170	/* Default register values */
 171	struct imx258_reg_list reg_list;
 172
 173	/* Analog crop rectangle */
 174	struct v4l2_rect crop;
 175};
 176
 177/*
 178 * 4208x3120 @ 30 fps needs 1267Mbps/lane, 4 lanes.
 179 * To avoid further computation of clock settings, adopt the same per
 180 * lane data rate when using 2 lanes, thus allowing a maximum of 15fps.
 181 */
 182static const struct cci_reg_sequence mipi_1267mbps_19_2mhz_2l[] = {
 183	{ IMX258_REG_EXCK_FREQ, 0x1333 },
 184	{ IMX258_REG_IVTPXCK_DIV, 10 },
 185	{ IMX258_REG_IVTSYCK_DIV, 2 },
 186	{ IMX258_REG_PREPLLCK_VT_DIV, 3 },
 187	{ IMX258_REG_PLL_IVT_MPY, 198 },
 188	{ IMX258_REG_IOPPXCK_DIV, 10 },
 189	{ IMX258_REG_IOPSYCK_DIV, 1 },
 190	{ IMX258_REG_PREPLLCK_OP_DIV, 2 },
 191	{ IMX258_REG_PLL_IOP_MPY, 216 },
 192	{ IMX258_REG_PLL_MULT_DRIV, 0 },
 193
 194	{ IMX258_REG_CSI_LANE_MODE, 1 },
 195	{ IMX258_REG_REQ_LINK_BIT_RATE_MBPS_H, 1267 * 2 },
 196	{ IMX258_REG_REQ_LINK_BIT_RATE_MBPS_L, 0 },
 197};
 198
 199static const struct cci_reg_sequence mipi_1267mbps_19_2mhz_4l[] = {
 200	{ IMX258_REG_EXCK_FREQ, 0x1333 },
 201	{ IMX258_REG_IVTPXCK_DIV, 5 },
 202	{ IMX258_REG_IVTSYCK_DIV, 2 },
 203	{ IMX258_REG_PREPLLCK_VT_DIV, 3 },
 204	{ IMX258_REG_PLL_IVT_MPY, 198 },
 205	{ IMX258_REG_IOPPXCK_DIV, 10 },
 206	{ IMX258_REG_IOPSYCK_DIV, 1 },
 207	{ IMX258_REG_PREPLLCK_OP_DIV, 2 },
 208	{ IMX258_REG_PLL_IOP_MPY, 216 },
 209	{ IMX258_REG_PLL_MULT_DRIV, 0 },
 210
 211	{ IMX258_REG_CSI_LANE_MODE, 3 },
 212	{ IMX258_REG_REQ_LINK_BIT_RATE_MBPS_H, 1267 * 4 },
 213	{ IMX258_REG_REQ_LINK_BIT_RATE_MBPS_L, 0 },
 214};
 215
 216static const struct cci_reg_sequence mipi_1272mbps_24mhz_2l[] = {
 217	{ IMX258_REG_EXCK_FREQ, 0x1800 },
 218	{ IMX258_REG_IVTPXCK_DIV, 10 },
 219	{ IMX258_REG_IVTSYCK_DIV, 2 },
 220	{ IMX258_REG_PREPLLCK_VT_DIV, 4 },
 221	{ IMX258_REG_PLL_IVT_MPY, 212 },
 222	{ IMX258_REG_IOPPXCK_DIV, 10 },
 223	{ IMX258_REG_IOPSYCK_DIV, 1 },
 224	{ IMX258_REG_PREPLLCK_OP_DIV, 2 },
 225	{ IMX258_REG_PLL_IOP_MPY, 216 },
 226	{ IMX258_REG_PLL_MULT_DRIV, 0 },
 227
 228	{ IMX258_REG_CSI_LANE_MODE, 1 },
 229	{ IMX258_REG_REQ_LINK_BIT_RATE_MBPS_H, 1272 * 2 },
 230	{ IMX258_REG_REQ_LINK_BIT_RATE_MBPS_L, 0 },
 231};
 232
 233static const struct cci_reg_sequence mipi_1272mbps_24mhz_4l[] = {
 234	{ IMX258_REG_EXCK_FREQ, 0x1800 },
 235	{ IMX258_REG_IVTPXCK_DIV, 5 },
 236	{ IMX258_REG_IVTSYCK_DIV, 2 },
 237	{ IMX258_REG_PREPLLCK_VT_DIV, 4 },
 238	{ IMX258_REG_PLL_IVT_MPY, 212 },
 239	{ IMX258_REG_IOPPXCK_DIV, 10 },
 240	{ IMX258_REG_IOPSYCK_DIV, 1 },
 241	{ IMX258_REG_PREPLLCK_OP_DIV, 2 },
 242	{ IMX258_REG_PLL_IOP_MPY, 216 },
 243	{ IMX258_REG_PLL_MULT_DRIV, 0 },
 244
 245	{ IMX258_REG_CSI_LANE_MODE, 3 },
 246	{ IMX258_REG_REQ_LINK_BIT_RATE_MBPS_H, 1272 * 4 },
 247	{ IMX258_REG_REQ_LINK_BIT_RATE_MBPS_L, 0 },
 248};
 249
 250static const struct cci_reg_sequence mipi_640mbps_19_2mhz_2l[] = {
 251	{ IMX258_REG_EXCK_FREQ, 0x1333 },
 252	{ IMX258_REG_IVTPXCK_DIV, 5 },
 253	{ IMX258_REG_IVTSYCK_DIV, 2 },
 254	{ IMX258_REG_PREPLLCK_VT_DIV, 3 },
 255	{ IMX258_REG_PLL_IVT_MPY, 100 },
 256	{ IMX258_REG_IOPPXCK_DIV, 10 },
 257	{ IMX258_REG_IOPSYCK_DIV, 1 },
 258	{ IMX258_REG_PREPLLCK_OP_DIV, 2 },
 259	{ IMX258_REG_PLL_IOP_MPY, 216 },
 260	{ IMX258_REG_PLL_MULT_DRIV, 0 },
 261
 262	{ IMX258_REG_CSI_LANE_MODE, 1 },
 263	{ IMX258_REG_REQ_LINK_BIT_RATE_MBPS_H, 640 * 2 },
 264	{ IMX258_REG_REQ_LINK_BIT_RATE_MBPS_L, 0 },
 265};
 266
 267static const struct cci_reg_sequence mipi_640mbps_19_2mhz_4l[] = {
 268	{ IMX258_REG_EXCK_FREQ, 0x1333 },
 269	{ IMX258_REG_IVTPXCK_DIV, 5 },
 270	{ IMX258_REG_IVTSYCK_DIV, 2 },
 271	{ IMX258_REG_PREPLLCK_VT_DIV, 3 },
 272	{ IMX258_REG_PLL_IVT_MPY, 100 },
 273	{ IMX258_REG_IOPPXCK_DIV, 10 },
 274	{ IMX258_REG_IOPSYCK_DIV, 1 },
 275	{ IMX258_REG_PREPLLCK_OP_DIV, 2 },
 276	{ IMX258_REG_PLL_IOP_MPY, 216 },
 277	{ IMX258_REG_PLL_MULT_DRIV, 0 },
 278
 279	{ IMX258_REG_CSI_LANE_MODE, 3 },
 280	{ IMX258_REG_REQ_LINK_BIT_RATE_MBPS_H, 640 * 4 },
 281	{ IMX258_REG_REQ_LINK_BIT_RATE_MBPS_L, 0 },
 282};
 283
 284static const struct cci_reg_sequence mipi_642mbps_24mhz_2l[] = {
 285	{ IMX258_REG_EXCK_FREQ, 0x1800 },
 286	{ IMX258_REG_IVTPXCK_DIV, 5 },
 287	{ IMX258_REG_IVTSYCK_DIV, 2 },
 288	{ IMX258_REG_PREPLLCK_VT_DIV, 4 },
 289	{ IMX258_REG_PLL_IVT_MPY, 107 },
 290	{ IMX258_REG_IOPPXCK_DIV, 10 },
 291	{ IMX258_REG_IOPSYCK_DIV, 1 },
 292	{ IMX258_REG_PREPLLCK_OP_DIV, 2 },
 293	{ IMX258_REG_PLL_IOP_MPY, 216 },
 294	{ IMX258_REG_PLL_MULT_DRIV, 0 },
 295
 296	{ IMX258_REG_CSI_LANE_MODE, 1 },
 297	{ IMX258_REG_REQ_LINK_BIT_RATE_MBPS_H, 642 * 2 },
 298	{ IMX258_REG_REQ_LINK_BIT_RATE_MBPS_L, 0 },
 299};
 300
 301static const struct cci_reg_sequence mipi_642mbps_24mhz_4l[] = {
 302	{ IMX258_REG_EXCK_FREQ, 0x1800 },
 303	{ IMX258_REG_IVTPXCK_DIV, 5 },
 304	{ IMX258_REG_IVTSYCK_DIV, 2 },
 305	{ IMX258_REG_PREPLLCK_VT_DIV, 4 },
 306	{ IMX258_REG_PLL_IVT_MPY, 107 },
 307	{ IMX258_REG_IOPPXCK_DIV, 10 },
 308	{ IMX258_REG_IOPSYCK_DIV, 1 },
 309	{ IMX258_REG_PREPLLCK_OP_DIV, 2 },
 310	{ IMX258_REG_PLL_IOP_MPY, 216 },
 311	{ IMX258_REG_PLL_MULT_DRIV, 0 },
 312
 313	{ IMX258_REG_CSI_LANE_MODE, 3 },
 314	{ IMX258_REG_REQ_LINK_BIT_RATE_MBPS_H, 642 * 4 },
 315	{ IMX258_REG_REQ_LINK_BIT_RATE_MBPS_L, 0 },
 316};
 317
 318static const struct cci_reg_sequence mode_common_regs[] = {
 319	{ CCI_REG8(0x3051), 0x00 },
 320	{ CCI_REG8(0x6B11), 0xCF },
 321	{ CCI_REG8(0x7FF0), 0x08 },
 322	{ CCI_REG8(0x7FF1), 0x0F },
 323	{ CCI_REG8(0x7FF2), 0x08 },
 324	{ CCI_REG8(0x7FF3), 0x1B },
 325	{ CCI_REG8(0x7FF4), 0x23 },
 326	{ CCI_REG8(0x7FF5), 0x60 },
 327	{ CCI_REG8(0x7FF6), 0x00 },
 328	{ CCI_REG8(0x7FF7), 0x01 },
 329	{ CCI_REG8(0x7FF8), 0x00 },
 330	{ CCI_REG8(0x7FF9), 0x78 },
 331	{ CCI_REG8(0x7FFA), 0x00 },
 332	{ CCI_REG8(0x7FFB), 0x00 },
 333	{ CCI_REG8(0x7FFC), 0x00 },
 334	{ CCI_REG8(0x7FFD), 0x00 },
 335	{ CCI_REG8(0x7FFE), 0x00 },
 336	{ CCI_REG8(0x7FFF), 0x03 },
 337	{ CCI_REG8(0x7F76), 0x03 },
 338	{ CCI_REG8(0x7F77), 0xFE },
 339	{ CCI_REG8(0x7FA8), 0x03 },
 340	{ CCI_REG8(0x7FA9), 0xFE },
 341	{ CCI_REG8(0x7B24), 0x81 },
 342	{ CCI_REG8(0x6564), 0x07 },
 343	{ CCI_REG8(0x6B0D), 0x41 },
 344	{ CCI_REG8(0x653D), 0x04 },
 345	{ CCI_REG8(0x6B05), 0x8C },
 346	{ CCI_REG8(0x6B06), 0xF9 },
 347	{ CCI_REG8(0x6B08), 0x65 },
 348	{ CCI_REG8(0x6B09), 0xFC },
 349	{ CCI_REG8(0x6B0A), 0xCF },
 350	{ CCI_REG8(0x6B0B), 0xD2 },
 351	{ CCI_REG8(0x6700), 0x0E },
 352	{ CCI_REG8(0x6707), 0x0E },
 353	{ CCI_REG8(0x9104), 0x00 },
 354	{ CCI_REG8(0x4648), 0x7F },
 355	{ CCI_REG8(0x7420), 0x00 },
 356	{ CCI_REG8(0x7421), 0x1C },
 357	{ CCI_REG8(0x7422), 0x00 },
 358	{ CCI_REG8(0x7423), 0xD7 },
 359	{ CCI_REG8(0x5F04), 0x00 },
 360	{ CCI_REG8(0x5F05), 0xED },
 361	{IMX258_REG_CSI_DT_FMT, 0x0a0a},
 362	{IMX258_REG_LINE_LENGTH_PCK, 5352},
 363	{IMX258_REG_X_ADD_STA, 0},
 364	{IMX258_REG_Y_ADD_STA, 0},
 365	{IMX258_REG_X_ADD_END, 4207},
 366	{IMX258_REG_Y_ADD_END, 3119},
 367	{IMX258_REG_X_EVN_INC, 1},
 368	{IMX258_REG_X_ODD_INC, 1},
 369	{IMX258_REG_Y_EVN_INC, 1},
 370	{IMX258_REG_Y_ODD_INC, 1},
 371	{IMX258_REG_DIG_CROP_X_OFFSET, 0},
 372	{IMX258_REG_DIG_CROP_Y_OFFSET, 0},
 373	{IMX258_REG_DIG_CROP_IMAGE_WIDTH, 4208},
 374	{IMX258_REG_SCALE_MODE_EXT, 0},
 375	{IMX258_REG_SCALE_M_EXT, 16},
 376	{IMX258_REG_FORCE_FD_SUM, 0},
 377	{IMX258_REG_FRM_LENGTH_CTL, 0},
 378	{IMX258_REG_ANALOG_GAIN, 0},
 379	{IMX258_REG_GR_DIGITAL_GAIN, 256},
 380	{IMX258_REG_R_DIGITAL_GAIN, 256},
 381	{IMX258_REG_B_DIGITAL_GAIN, 256},
 382	{IMX258_REG_GB_DIGITAL_GAIN, 256},
 383	{IMX258_REG_AF_WINDOW_MODE, 0},
 384	{ CCI_REG8(0x94DC), 0x20 },
 385	{ CCI_REG8(0x94DD), 0x20 },
 386	{ CCI_REG8(0x94DE), 0x20 },
 387	{ CCI_REG8(0x95DC), 0x20 },
 388	{ CCI_REG8(0x95DD), 0x20 },
 389	{ CCI_REG8(0x95DE), 0x20 },
 390	{ CCI_REG8(0x7FB0), 0x00 },
 391	{ CCI_REG8(0x9010), 0x3E },
 392	{ CCI_REG8(0x9419), 0x50 },
 393	{ CCI_REG8(0x941B), 0x50 },
 394	{ CCI_REG8(0x9519), 0x50 },
 395	{ CCI_REG8(0x951B), 0x50 },
 396	{IMX258_REG_PHASE_PIX_OUTEN, 0},
 397	{IMX258_REG_PDPIX_DATA_RATE, 0},
 398	{IMX258_REG_HDR, 0},
 399};
 400
 401static const struct cci_reg_sequence mode_4208x3120_regs[] = {
 402	{IMX258_REG_BINNING_MODE, 0},
 403	{IMX258_REG_BINNING_TYPE_V, 0x11},
 404	{IMX258_REG_SCALE_MODE, 0},
 405	{IMX258_REG_SCALE_M, 16},
 406	{IMX258_REG_DIG_CROP_IMAGE_HEIGHT, 3120},
 407	{IMX258_REG_X_OUT_SIZE, 4208},
 408	{IMX258_REG_Y_OUT_SIZE, 3120},
 409};
 410
 411static const struct cci_reg_sequence mode_2104_1560_regs[] = {
 412	{IMX258_REG_BINNING_MODE, 1},
 413	{IMX258_REG_BINNING_TYPE_V, 0x12},
 414	{IMX258_REG_SCALE_MODE, 1},
 415	{IMX258_REG_SCALE_M, 32},
 416	{IMX258_REG_DIG_CROP_IMAGE_HEIGHT, 1560},
 417	{IMX258_REG_X_OUT_SIZE, 2104},
 418	{IMX258_REG_Y_OUT_SIZE, 1560},
 419};
 420
 421static const struct cci_reg_sequence mode_1048_780_regs[] = {
 422	{IMX258_REG_BINNING_MODE, 1},
 423	{IMX258_REG_BINNING_TYPE_V, 0x14},
 424	{IMX258_REG_SCALE_MODE, 1},
 425	{IMX258_REG_SCALE_M, 64},
 426	{IMX258_REG_DIG_CROP_IMAGE_HEIGHT, 780},
 427	{IMX258_REG_X_OUT_SIZE, 1048},
 428	{IMX258_REG_Y_OUT_SIZE, 780},
 429};
 430
 431struct imx258_variant_cfg {
 432	const struct cci_reg_sequence *regs;
 433	unsigned int num_regs;
 434};
 435
 436static const struct cci_reg_sequence imx258_cfg_regs[] = {
 437	{ CCI_REG8(0x3052), 0x00 },
 438	{ CCI_REG8(0x4E21), 0x14 },
 439	{ CCI_REG8(0x7B25), 0x00 },
 440};
 441
 442static const struct imx258_variant_cfg imx258_cfg = {
 443	.regs = imx258_cfg_regs,
 444	.num_regs = ARRAY_SIZE(imx258_cfg_regs),
 445};
 446
 447static const struct cci_reg_sequence imx258_pdaf_cfg_regs[] = {
 448	{ CCI_REG8(0x3052), 0x01 },
 449	{ CCI_REG8(0x4E21), 0x10 },
 450	{ CCI_REG8(0x7B25), 0x01 },
 451};
 452
 453static const struct imx258_variant_cfg imx258_pdaf_cfg = {
 454	.regs = imx258_pdaf_cfg_regs,
 455	.num_regs = ARRAY_SIZE(imx258_pdaf_cfg_regs),
 456};
 457
 458/*
 459 * The supported formats.
 460 * This table MUST contain 4 entries per format, to cover the various flip
 461 * combinations in the order
 462 * - no flip
 463 * - h flip
 464 * - v flip
 465 * - h&v flips
 466 */
 467static const u32 codes[] = {
 468	/* 10-bit modes. */
 469	MEDIA_BUS_FMT_SRGGB10_1X10,
 470	MEDIA_BUS_FMT_SGRBG10_1X10,
 471	MEDIA_BUS_FMT_SGBRG10_1X10,
 472	MEDIA_BUS_FMT_SBGGR10_1X10
 473};
 474
 475static const char * const imx258_test_pattern_menu[] = {
 476	"Disabled",
 477	"Solid Colour",
 478	"Eight Vertical Colour Bars",
 479	"Colour Bars With Fade to Grey",
 480	"Pseudorandom Sequence (PN9)",
 481};
 482
 483/* regulator supplies */
 484static const char * const imx258_supply_name[] = {
 485	/* Supplies can be enabled in any order */
 486	"vana",  /* Analog (2.8V) supply */
 487	"vdig",  /* Digital Core (1.2V) supply */
 488	"vif",  /* IF (1.8V) supply */
 489};
 490
 491#define IMX258_NUM_SUPPLIES ARRAY_SIZE(imx258_supply_name)
 492
 493enum {
 494	IMX258_LINK_FREQ_1267MBPS,
 495	IMX258_LINK_FREQ_640MBPS,
 496};
 497
 498/*
 499 * Pixel rate does not necessarily relate to link frequency on this sensor as
 500 * there is a FIFO between the pixel array pipeline and the MIPI serializer.
 501 * The recommendation from Sony is that the pixel array is always run with a
 502 * line length of 5352 pixels, which means that there is a large amount of
 503 * blanking time for the 1048x780 mode. There is no need to replicate this
 504 * blanking on the CSI2 bus, and the configuration of register 0x0301 allows the
 505 * divider to be altered.
 506 *
 507 * The actual factor between link frequency and pixel rate is in the
 508 * imx258_link_cfg, so use this to convert between the two.
 509 * bits per pixel being 10, and D-PHY being DDR is assumed by this function, so
 510 * the value is only the combination of number of lanes and pixel clock divider.
 511 */
 512static u64 link_freq_to_pixel_rate(u64 f, const struct imx258_link_cfg *link_cfg)
 513{
 514	f *= 2 * link_cfg->lf_to_pix_rate_factor;
 515	do_div(f, 10);
 516
 517	return f;
 518}
 519
 520/* Menu items for LINK_FREQ V4L2 control */
 521/* Configurations for supported link frequencies */
 522static const s64 link_freq_menu_items_19_2[] = {
 523	633600000ULL,
 524	320000000ULL,
 525};
 526
 527static const s64 link_freq_menu_items_24[] = {
 528	636000000ULL,
 529	321000000ULL,
 530};
 531
 532#define REGS(_list) { .num_of_regs = ARRAY_SIZE(_list), .regs = _list, }
 533
 534/* Link frequency configs */
 535static const struct imx258_link_freq_config link_freq_configs_19_2[] = {
 536	[IMX258_LINK_FREQ_1267MBPS] = {
 537		.pixels_per_line = IMX258_PPL_DEFAULT,
 538		.link_cfg = {
 539			[IMX258_2_LANE_MODE] = {
 540				.lf_to_pix_rate_factor = 2 * 2,
 541				.reg_list = REGS(mipi_1267mbps_19_2mhz_2l),
 542			},
 543			[IMX258_4_LANE_MODE] = {
 544				.lf_to_pix_rate_factor = 4,
 545				.reg_list = REGS(mipi_1267mbps_19_2mhz_4l),
 546			},
 547		}
 548	},
 549	[IMX258_LINK_FREQ_640MBPS] = {
 550		.pixels_per_line = IMX258_PPL_DEFAULT,
 551		.link_cfg = {
 552			[IMX258_2_LANE_MODE] = {
 553				.lf_to_pix_rate_factor = 2,
 554				.reg_list = REGS(mipi_640mbps_19_2mhz_2l),
 555			},
 556			[IMX258_4_LANE_MODE] = {
 557				.lf_to_pix_rate_factor = 4,
 558				.reg_list = REGS(mipi_640mbps_19_2mhz_4l),
 559			},
 560		}
 561	},
 562};
 563
 564static const struct imx258_link_freq_config link_freq_configs_24[] = {
 565	[IMX258_LINK_FREQ_1267MBPS] = {
 566		.pixels_per_line = IMX258_PPL_DEFAULT,
 567		.link_cfg = {
 568			[IMX258_2_LANE_MODE] = {
 569				.lf_to_pix_rate_factor = 2,
 570				.reg_list = REGS(mipi_1272mbps_24mhz_2l),
 571			},
 572			[IMX258_4_LANE_MODE] = {
 573				.lf_to_pix_rate_factor = 4,
 574				.reg_list = REGS(mipi_1272mbps_24mhz_4l),
 575			},
 576		}
 577	},
 578	[IMX258_LINK_FREQ_640MBPS] = {
 579		.pixels_per_line = IMX258_PPL_DEFAULT,
 580		.link_cfg = {
 581			[IMX258_2_LANE_MODE] = {
 582				.lf_to_pix_rate_factor = 2 * 2,
 583				.reg_list = REGS(mipi_642mbps_24mhz_2l),
 584			},
 585			[IMX258_4_LANE_MODE] = {
 586				.lf_to_pix_rate_factor = 4,
 587				.reg_list = REGS(mipi_642mbps_24mhz_4l),
 588			},
 589		}
 590	},
 591};
 592
 593/* Mode configs */
 594static const struct imx258_mode supported_modes[] = {
 595	{
 596		.width = 4208,
 597		.height = 3120,
 598		.vts_def = IMX258_VTS_30FPS,
 599		.vts_min = IMX258_VTS_30FPS,
 600		.reg_list = {
 601			.num_of_regs = ARRAY_SIZE(mode_4208x3120_regs),
 602			.regs = mode_4208x3120_regs,
 603		},
 604		.link_freq_index = IMX258_LINK_FREQ_1267MBPS,
 605		.crop = {
 606			.left = IMX258_PIXEL_ARRAY_LEFT,
 607			.top = IMX258_PIXEL_ARRAY_TOP,
 608			.width = 4208,
 609			.height = 3120,
 610		},
 611	},
 612	{
 613		.width = 2104,
 614		.height = 1560,
 615		.vts_def = IMX258_VTS_30FPS_2K,
 616		.vts_min = IMX258_VTS_30FPS_2K,
 617		.reg_list = {
 618			.num_of_regs = ARRAY_SIZE(mode_2104_1560_regs),
 619			.regs = mode_2104_1560_regs,
 620		},
 621		.link_freq_index = IMX258_LINK_FREQ_640MBPS,
 622		.crop = {
 623			.left = IMX258_PIXEL_ARRAY_LEFT,
 624			.top = IMX258_PIXEL_ARRAY_TOP,
 625			.width = 4208,
 626			.height = 3120,
 627		},
 628	},
 629	{
 630		.width = 1048,
 631		.height = 780,
 632		.vts_def = IMX258_VTS_30FPS_VGA,
 633		.vts_min = IMX258_VTS_30FPS_VGA,
 634		.reg_list = {
 635			.num_of_regs = ARRAY_SIZE(mode_1048_780_regs),
 636			.regs = mode_1048_780_regs,
 637		},
 638		.link_freq_index = IMX258_LINK_FREQ_640MBPS,
 639		.crop = {
 640			.left = IMX258_PIXEL_ARRAY_LEFT,
 641			.top = IMX258_PIXEL_ARRAY_TOP,
 642			.width = 4208,
 643			.height = 3120,
 644		},
 645	},
 646};
 647
 648struct imx258 {
 649	struct device *dev;
 650
 651	struct v4l2_subdev sd;
 652	struct media_pad pad;
 653	struct regmap *regmap;
 654
 655	const struct imx258_variant_cfg *variant_cfg;
 656
 657	struct v4l2_ctrl_handler ctrl_handler;
 658	/* V4L2 Controls */
 659	struct v4l2_ctrl *link_freq;
 660	struct v4l2_ctrl *pixel_rate;
 661	struct v4l2_ctrl *vblank;
 662	struct v4l2_ctrl *hblank;
 663	struct v4l2_ctrl *exposure;
 664	struct v4l2_ctrl *hflip;
 665	struct v4l2_ctrl *vflip;
 666
 667	/* Current mode */
 668	const struct imx258_mode *cur_mode;
 669
 670	unsigned long link_freq_bitmap;
 671	const struct imx258_link_freq_config *link_freq_configs;
 672	const s64 *link_freq_menu_items;
 673	unsigned int lane_mode_idx;
 674	unsigned int csi2_flags;
 675
 676	/*
 677	 * Mutex for serialized access:
 678	 * Protect sensor module set pad format and start/stop streaming safely.
 679	 */
 680	struct mutex mutex;
 681
 682	struct clk *clk;
 683	struct regulator_bulk_data supplies[IMX258_NUM_SUPPLIES];
 684};
 685
 686static inline struct imx258 *to_imx258(struct v4l2_subdev *_sd)
 687{
 688	return container_of(_sd, struct imx258, sd);
 689}
 690
 691/* Get bayer order based on flip setting. */
 692static u32 imx258_get_format_code(const struct imx258 *imx258)
 693{
 694	unsigned int i;
 695
 696	lockdep_assert_held(&imx258->mutex);
 697
 698	i = (imx258->vflip->val ? 2 : 0) |
 699	    (imx258->hflip->val ? 1 : 0);
 700
 701	return codes[i];
 702}
 703
 704/* Open sub-device */
 705static int imx258_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
 706{
 707	struct imx258 *imx258 = to_imx258(sd);
 708	struct v4l2_mbus_framefmt *try_fmt =
 709		v4l2_subdev_state_get_format(fh->state, 0);
 710	struct v4l2_rect *try_crop;
 711
 712	/* Initialize try_fmt */
 713	try_fmt->width = supported_modes[0].width;
 714	try_fmt->height = supported_modes[0].height;
 715	try_fmt->code = imx258_get_format_code(imx258);
 716	try_fmt->field = V4L2_FIELD_NONE;
 717
 718	/* Initialize try_crop */
 719	try_crop = v4l2_subdev_state_get_crop(fh->state, 0);
 720	try_crop->left = IMX258_PIXEL_ARRAY_LEFT;
 721	try_crop->top = IMX258_PIXEL_ARRAY_TOP;
 722	try_crop->width = IMX258_PIXEL_ARRAY_WIDTH;
 723	try_crop->height = IMX258_PIXEL_ARRAY_HEIGHT;
 724
 725	return 0;
 726}
 727
 728static int imx258_update_digital_gain(struct imx258 *imx258, u32 val)
 729{
 730	int ret = 0;
 731
 732	cci_write(imx258->regmap, IMX258_REG_GR_DIGITAL_GAIN, val, &ret);
 733	cci_write(imx258->regmap, IMX258_REG_GB_DIGITAL_GAIN, val, &ret);
 734	cci_write(imx258->regmap, IMX258_REG_R_DIGITAL_GAIN, val, &ret);
 735	cci_write(imx258->regmap, IMX258_REG_B_DIGITAL_GAIN, val, &ret);
 736
 737	return ret;
 738}
 739
 740static void imx258_adjust_exposure_range(struct imx258 *imx258)
 741{
 742	int exposure_max, exposure_def;
 743
 744	/* Honour the VBLANK limits when setting exposure. */
 745	exposure_max = imx258->cur_mode->height + imx258->vblank->val -
 746		       IMX258_EXPOSURE_OFFSET;
 747	exposure_def = min(exposure_max, imx258->exposure->val);
 748	__v4l2_ctrl_modify_range(imx258->exposure, imx258->exposure->minimum,
 749				 exposure_max, imx258->exposure->step,
 750				 exposure_def);
 751}
 752
 753static int imx258_set_ctrl(struct v4l2_ctrl *ctrl)
 754{
 755	struct imx258 *imx258 =
 756		container_of(ctrl->handler, struct imx258, ctrl_handler);
 757	int ret = 0;
 758
 759	/*
 760	 * The VBLANK control may change the limits of usable exposure, so check
 761	 * and adjust if necessary.
 762	 */
 763	if (ctrl->id == V4L2_CID_VBLANK)
 764		imx258_adjust_exposure_range(imx258);
 765
 766	/*
 767	 * Applying V4L2 control value only happens
 768	 * when power is up for streaming
 769	 */
 770	if (pm_runtime_get_if_in_use(imx258->dev) == 0)
 771		return 0;
 772
 773	switch (ctrl->id) {
 774	case V4L2_CID_ANALOGUE_GAIN:
 775		ret = cci_write(imx258->regmap, IMX258_REG_ANALOG_GAIN,
 776				ctrl->val, NULL);
 777		break;
 778	case V4L2_CID_EXPOSURE:
 779		ret = cci_write(imx258->regmap, IMX258_REG_EXPOSURE,
 780				ctrl->val, NULL);
 781		break;
 782	case V4L2_CID_DIGITAL_GAIN:
 783		ret = imx258_update_digital_gain(imx258, ctrl->val);
 784		break;
 785	case V4L2_CID_TEST_PATTERN:
 786		ret = cci_write(imx258->regmap, IMX258_REG_TEST_PATTERN,
 787				ctrl->val, NULL);
 788		break;
 789	case V4L2_CID_WIDE_DYNAMIC_RANGE:
 790		if (!ctrl->val) {
 791			ret = cci_write(imx258->regmap, IMX258_REG_HDR,
 792					IMX258_HDR_RATIO_MIN, NULL);
 793		} else {
 794			ret = cci_write(imx258->regmap, IMX258_REG_HDR,
 795					IMX258_HDR_ON, NULL);
 796			if (ret)
 797				break;
 798			ret = cci_write(imx258->regmap, IMX258_REG_HDR_RATIO,
 799					BIT(IMX258_HDR_RATIO_MAX), NULL);
 800		}
 801		break;
 802	case V4L2_CID_VBLANK:
 803		ret = cci_write(imx258->regmap, IMX258_REG_FRM_LENGTH_LINES,
 804				imx258->cur_mode->height + ctrl->val, NULL);
 805		break;
 806	case V4L2_CID_VFLIP:
 807	case V4L2_CID_HFLIP:
 808		ret = cci_write(imx258->regmap, REG_MIRROR_FLIP_CONTROL,
 809				(imx258->hflip->val ?
 810				 REG_CONFIG_MIRROR_HFLIP : 0) |
 811				(imx258->vflip->val ?
 812				 REG_CONFIG_MIRROR_VFLIP : 0),
 813				NULL);
 814		break;
 815	default:
 816		dev_info(imx258->dev,
 817			 "ctrl(id:0x%x,val:0x%x) is not handled\n",
 818			 ctrl->id, ctrl->val);
 819		ret = -EINVAL;
 820		break;
 821	}
 822
 823	pm_runtime_put(imx258->dev);
 824
 825	return ret;
 826}
 827
 828static const struct v4l2_ctrl_ops imx258_ctrl_ops = {
 829	.s_ctrl = imx258_set_ctrl,
 830};
 831
 832static int imx258_enum_mbus_code(struct v4l2_subdev *sd,
 833				  struct v4l2_subdev_state *sd_state,
 834				  struct v4l2_subdev_mbus_code_enum *code)
 835{
 836	struct imx258 *imx258 = to_imx258(sd);
 837
 838	/* Only one bayer format (10 bit) is supported */
 839	if (code->index > 0)
 840		return -EINVAL;
 841
 842	code->code = imx258_get_format_code(imx258);
 843
 844	return 0;
 845}
 846
 847static int imx258_enum_frame_size(struct v4l2_subdev *sd,
 848				  struct v4l2_subdev_state *sd_state,
 849				  struct v4l2_subdev_frame_size_enum *fse)
 850{
 851	struct imx258 *imx258 = to_imx258(sd);
 852	if (fse->index >= ARRAY_SIZE(supported_modes))
 853		return -EINVAL;
 854
 855	if (fse->code != imx258_get_format_code(imx258))
 856		return -EINVAL;
 857
 858	fse->min_width = supported_modes[fse->index].width;
 859	fse->max_width = fse->min_width;
 860	fse->min_height = supported_modes[fse->index].height;
 861	fse->max_height = fse->min_height;
 862
 863	return 0;
 864}
 865
 866static void imx258_update_pad_format(struct imx258 *imx258,
 867				     const struct imx258_mode *mode,
 868				     struct v4l2_subdev_format *fmt)
 869{
 870	fmt->format.width = mode->width;
 871	fmt->format.height = mode->height;
 872	fmt->format.code = imx258_get_format_code(imx258);
 873	fmt->format.field = V4L2_FIELD_NONE;
 874}
 875
 876static int __imx258_get_pad_format(struct imx258 *imx258,
 877				   struct v4l2_subdev_state *sd_state,
 878				   struct v4l2_subdev_format *fmt)
 879{
 880	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
 881		fmt->format = *v4l2_subdev_state_get_format(sd_state,
 882							    fmt->pad);
 883	else
 884		imx258_update_pad_format(imx258, imx258->cur_mode, fmt);
 885
 886	return 0;
 887}
 888
 889static int imx258_get_pad_format(struct v4l2_subdev *sd,
 890				 struct v4l2_subdev_state *sd_state,
 891				 struct v4l2_subdev_format *fmt)
 892{
 893	struct imx258 *imx258 = to_imx258(sd);
 894	int ret;
 895
 896	mutex_lock(&imx258->mutex);
 897	ret = __imx258_get_pad_format(imx258, sd_state, fmt);
 898	mutex_unlock(&imx258->mutex);
 899
 900	return ret;
 901}
 902
 903static int imx258_set_pad_format(struct v4l2_subdev *sd,
 904				 struct v4l2_subdev_state *sd_state,
 905				 struct v4l2_subdev_format *fmt)
 906{
 907	struct imx258 *imx258 = to_imx258(sd);
 908	const struct imx258_link_freq_config *link_freq_cfgs;
 909	const struct imx258_link_cfg *link_cfg;
 910	struct v4l2_mbus_framefmt *framefmt;
 911	const struct imx258_mode *mode;
 912	s32 vblank_def;
 913	s32 vblank_min;
 914	s64 h_blank;
 915	s64 pixel_rate;
 916	s64 link_freq;
 917
 918	mutex_lock(&imx258->mutex);
 919
 920	fmt->format.code = imx258_get_format_code(imx258);
 921
 922	mode = v4l2_find_nearest_size(supported_modes,
 923		ARRAY_SIZE(supported_modes), width, height,
 924		fmt->format.width, fmt->format.height);
 925	imx258_update_pad_format(imx258, mode, fmt);
 926	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
 927		framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad);
 928		*framefmt = fmt->format;
 929	} else {
 930		imx258->cur_mode = mode;
 931		__v4l2_ctrl_s_ctrl(imx258->link_freq, mode->link_freq_index);
 932
 933		link_freq = imx258->link_freq_menu_items[mode->link_freq_index];
 934		link_freq_cfgs =
 935			&imx258->link_freq_configs[mode->link_freq_index];
 936
 937		link_cfg = &link_freq_cfgs->link_cfg[imx258->lane_mode_idx];
 938		pixel_rate = link_freq_to_pixel_rate(link_freq, link_cfg);
 939		__v4l2_ctrl_modify_range(imx258->pixel_rate, pixel_rate,
 940					 pixel_rate, 1, pixel_rate);
 941		/* Update limits and set FPS to default */
 942		vblank_def = imx258->cur_mode->vts_def -
 943			     imx258->cur_mode->height;
 944		vblank_min = imx258->cur_mode->vts_min -
 945			     imx258->cur_mode->height;
 946		__v4l2_ctrl_modify_range(
 947			imx258->vblank, vblank_min,
 948			IMX258_VTS_MAX - imx258->cur_mode->height, 1,
 949			vblank_def);
 950		__v4l2_ctrl_s_ctrl(imx258->vblank, vblank_def);
 951		h_blank =
 952			imx258->link_freq_configs[mode->link_freq_index].pixels_per_line
 953			 - imx258->cur_mode->width;
 954		__v4l2_ctrl_modify_range(imx258->hblank, h_blank,
 955					 h_blank, 1, h_blank);
 956	}
 957
 958	mutex_unlock(&imx258->mutex);
 959
 960	return 0;
 961}
 962
 963static const struct v4l2_rect *
 964__imx258_get_pad_crop(struct imx258 *imx258,
 965		      struct v4l2_subdev_state *sd_state,
 966		      unsigned int pad, enum v4l2_subdev_format_whence which)
 967{
 968	switch (which) {
 969	case V4L2_SUBDEV_FORMAT_TRY:
 970		return v4l2_subdev_state_get_crop(sd_state, pad);
 971	case V4L2_SUBDEV_FORMAT_ACTIVE:
 972		return &imx258->cur_mode->crop;
 973	}
 974
 975	return NULL;
 976}
 977
 978static int imx258_get_selection(struct v4l2_subdev *sd,
 979				struct v4l2_subdev_state *sd_state,
 980				struct v4l2_subdev_selection *sel)
 981{
 982	switch (sel->target) {
 983	case V4L2_SEL_TGT_CROP: {
 984		struct imx258 *imx258 = to_imx258(sd);
 985
 986		mutex_lock(&imx258->mutex);
 987		sel->r = *__imx258_get_pad_crop(imx258, sd_state, sel->pad,
 988						sel->which);
 989		mutex_unlock(&imx258->mutex);
 990
 991		return 0;
 992	}
 993
 994	case V4L2_SEL_TGT_NATIVE_SIZE:
 995		sel->r.left = 0;
 996		sel->r.top = 0;
 997		sel->r.width = IMX258_NATIVE_WIDTH;
 998		sel->r.height = IMX258_NATIVE_HEIGHT;
 999
1000		return 0;
1001
1002	case V4L2_SEL_TGT_CROP_DEFAULT:
1003	case V4L2_SEL_TGT_CROP_BOUNDS:
1004		sel->r.left = IMX258_PIXEL_ARRAY_LEFT;
1005		sel->r.top = IMX258_PIXEL_ARRAY_TOP;
1006		sel->r.width = IMX258_PIXEL_ARRAY_WIDTH;
1007		sel->r.height = IMX258_PIXEL_ARRAY_HEIGHT;
1008
1009		return 0;
1010	}
1011
1012	return -EINVAL;
1013}
1014
1015/* Start streaming */
1016static int imx258_start_streaming(struct imx258 *imx258)
1017{
1018	const struct imx258_reg_list *reg_list;
1019	const struct imx258_link_freq_config *link_freq_cfg;
1020	int ret, link_freq_index;
1021
1022	ret = cci_write(imx258->regmap, IMX258_REG_RESET, 0x01, NULL);
1023	if (ret) {
1024		dev_err(imx258->dev, "%s failed to reset sensor\n", __func__);
1025		return ret;
1026	}
1027
1028	/* 12ms is required from poweron to standby */
1029	fsleep(12000);
1030
1031	/* Setup PLL */
1032	link_freq_index = imx258->cur_mode->link_freq_index;
1033	link_freq_cfg = &imx258->link_freq_configs[link_freq_index];
1034
1035	reg_list = &link_freq_cfg->link_cfg[imx258->lane_mode_idx].reg_list;
1036	ret = cci_multi_reg_write(imx258->regmap, reg_list->regs, reg_list->num_of_regs, NULL);
1037	if (ret) {
1038		dev_err(imx258->dev, "%s failed to set plls\n", __func__);
1039		return ret;
1040	}
1041
1042	ret = cci_multi_reg_write(imx258->regmap, mode_common_regs,
1043				  ARRAY_SIZE(mode_common_regs), NULL);
1044	if (ret) {
1045		dev_err(imx258->dev, "%s failed to set common regs\n", __func__);
1046		return ret;
1047	}
1048
1049	ret = cci_multi_reg_write(imx258->regmap, imx258->variant_cfg->regs,
1050				  imx258->variant_cfg->num_regs, NULL);
1051	if (ret) {
1052		dev_err(imx258->dev, "%s failed to set variant config\n",
1053			__func__);
1054		return ret;
1055	}
1056
1057	ret = cci_write(imx258->regmap, IMX258_CLK_BLANK_STOP,
1058			!!(imx258->csi2_flags & V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK),
1059			NULL);
1060	if (ret) {
1061		dev_err(imx258->dev, "%s failed to set clock lane mode\n", __func__);
1062		return ret;
1063	}
1064
1065	/* Apply default values of current mode */
1066	reg_list = &imx258->cur_mode->reg_list;
1067	ret = cci_multi_reg_write(imx258->regmap, reg_list->regs, reg_list->num_of_regs, NULL);
1068	if (ret) {
1069		dev_err(imx258->dev, "%s failed to set mode\n", __func__);
1070		return ret;
1071	}
1072
1073	/* Apply customized values from user */
1074	ret =  __v4l2_ctrl_handler_setup(imx258->sd.ctrl_handler);
1075	if (ret)
1076		return ret;
1077
1078	/* set stream on register */
1079	return cci_write(imx258->regmap, IMX258_REG_MODE_SELECT,
1080			 IMX258_MODE_STREAMING, NULL);
1081}
1082
1083/* Stop streaming */
1084static int imx258_stop_streaming(struct imx258 *imx258)
1085{
1086	int ret;
1087
1088	/* set stream off register */
1089	ret = cci_write(imx258->regmap, IMX258_REG_MODE_SELECT,
1090			IMX258_MODE_STANDBY, NULL);
1091	if (ret)
1092		dev_err(imx258->dev, "%s failed to set stream\n", __func__);
1093
1094	/*
1095	 * Return success even if it was an error, as there is nothing the
1096	 * caller can do about it.
1097	 */
1098	return 0;
1099}
1100
1101static int imx258_power_on(struct device *dev)
1102{
1103	struct v4l2_subdev *sd = dev_get_drvdata(dev);
1104	struct imx258 *imx258 = to_imx258(sd);
1105	int ret;
1106
1107	ret = regulator_bulk_enable(IMX258_NUM_SUPPLIES,
1108				    imx258->supplies);
1109	if (ret) {
1110		dev_err(dev, "%s: failed to enable regulators\n",
1111			__func__);
1112		return ret;
1113	}
1114
1115	ret = clk_prepare_enable(imx258->clk);
1116	if (ret) {
1117		dev_err(dev, "failed to enable clock\n");
1118		regulator_bulk_disable(IMX258_NUM_SUPPLIES, imx258->supplies);
1119	}
1120
1121	return ret;
1122}
1123
1124static int imx258_power_off(struct device *dev)
1125{
1126	struct v4l2_subdev *sd = dev_get_drvdata(dev);
1127	struct imx258 *imx258 = to_imx258(sd);
1128
1129	clk_disable_unprepare(imx258->clk);
1130	regulator_bulk_disable(IMX258_NUM_SUPPLIES, imx258->supplies);
1131
1132	return 0;
1133}
1134
1135static int imx258_set_stream(struct v4l2_subdev *sd, int enable)
1136{
1137	struct imx258 *imx258 = to_imx258(sd);
1138	int ret = 0;
1139
1140	mutex_lock(&imx258->mutex);
1141
1142	if (enable) {
1143		ret = pm_runtime_resume_and_get(imx258->dev);
1144		if (ret < 0)
1145			goto err_unlock;
1146
1147		/*
1148		 * Apply default & customized values
1149		 * and then start streaming.
1150		 */
1151		ret = imx258_start_streaming(imx258);
1152		if (ret)
1153			goto err_rpm_put;
1154	} else {
1155		imx258_stop_streaming(imx258);
1156		pm_runtime_put(imx258->dev);
1157	}
1158
1159	mutex_unlock(&imx258->mutex);
1160
1161	return ret;
1162
1163err_rpm_put:
1164	pm_runtime_put(imx258->dev);
1165err_unlock:
1166	mutex_unlock(&imx258->mutex);
1167
1168	return ret;
1169}
1170
1171/* Verify chip ID */
1172static int imx258_identify_module(struct imx258 *imx258)
1173{
1174	int ret;
1175	u64 val;
1176
1177	ret = cci_read(imx258->regmap, IMX258_REG_CHIP_ID,
1178		       &val, NULL);
1179	if (ret) {
1180		dev_err(imx258->dev, "failed to read chip id %x\n",
1181			IMX258_CHIP_ID);
1182		return ret;
1183	}
1184
1185	if (val != IMX258_CHIP_ID) {
1186		dev_err(imx258->dev, "chip id mismatch: %x!=%llx\n",
1187			IMX258_CHIP_ID, val);
1188		return -EIO;
1189	}
1190
1191	return 0;
1192}
1193
1194static const struct v4l2_subdev_video_ops imx258_video_ops = {
1195	.s_stream = imx258_set_stream,
1196};
1197
1198static const struct v4l2_subdev_pad_ops imx258_pad_ops = {
1199	.enum_mbus_code = imx258_enum_mbus_code,
1200	.get_fmt = imx258_get_pad_format,
1201	.set_fmt = imx258_set_pad_format,
1202	.enum_frame_size = imx258_enum_frame_size,
1203	.get_selection = imx258_get_selection,
1204};
1205
1206static const struct v4l2_subdev_ops imx258_subdev_ops = {
1207	.video = &imx258_video_ops,
1208	.pad = &imx258_pad_ops,
1209};
1210
1211static const struct v4l2_subdev_internal_ops imx258_internal_ops = {
1212	.open = imx258_open,
1213};
1214
1215/* Initialize control handlers */
1216static int imx258_init_controls(struct imx258 *imx258)
1217{
1218	const struct imx258_link_freq_config *link_freq_cfgs;
1219	struct v4l2_fwnode_device_properties props;
1220	struct v4l2_ctrl_handler *ctrl_hdlr;
1221	const struct imx258_link_cfg *link_cfg;
1222	s64 vblank_def;
1223	s64 vblank_min;
1224	s64 pixel_rate;
1225	int ret;
1226
1227	ctrl_hdlr = &imx258->ctrl_handler;
1228	ret = v4l2_ctrl_handler_init(ctrl_hdlr, 13);
1229	if (ret)
1230		return ret;
1231
1232	mutex_init(&imx258->mutex);
1233	ctrl_hdlr->lock = &imx258->mutex;
1234	imx258->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
1235				&imx258_ctrl_ops,
1236				V4L2_CID_LINK_FREQ,
1237				ARRAY_SIZE(link_freq_menu_items_19_2) - 1,
1238				0,
1239				imx258->link_freq_menu_items);
1240
1241	if (imx258->link_freq)
1242		imx258->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1243
1244	imx258->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx258_ctrl_ops,
1245					  V4L2_CID_HFLIP, 0, 1, 1, 1);
1246	if (imx258->hflip)
1247		imx258->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
1248
1249	imx258->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx258_ctrl_ops,
1250					  V4L2_CID_VFLIP, 0, 1, 1, 1);
1251	if (imx258->vflip)
1252		imx258->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
1253
1254	link_freq_cfgs = &imx258->link_freq_configs[0];
1255	link_cfg = link_freq_cfgs[imx258->lane_mode_idx].link_cfg;
1256	pixel_rate = link_freq_to_pixel_rate(imx258->link_freq_menu_items[0],
1257					     link_cfg);
1258
1259	/* By default, PIXEL_RATE is read only */
1260	imx258->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &imx258_ctrl_ops,
1261				V4L2_CID_PIXEL_RATE,
1262				pixel_rate, pixel_rate,
1263				1, pixel_rate);
1264
1265	vblank_def = imx258->cur_mode->vts_def - imx258->cur_mode->height;
1266	vblank_min = imx258->cur_mode->vts_min - imx258->cur_mode->height;
1267	imx258->vblank = v4l2_ctrl_new_std(
1268				ctrl_hdlr, &imx258_ctrl_ops, V4L2_CID_VBLANK,
1269				vblank_min,
1270				IMX258_VTS_MAX - imx258->cur_mode->height, 1,
1271				vblank_def);
1272
1273	imx258->hblank = v4l2_ctrl_new_std(
1274				ctrl_hdlr, &imx258_ctrl_ops, V4L2_CID_HBLANK,
1275				IMX258_PPL_DEFAULT - imx258->cur_mode->width,
1276				IMX258_PPL_DEFAULT - imx258->cur_mode->width,
1277				1,
1278				IMX258_PPL_DEFAULT - imx258->cur_mode->width);
1279
1280	if (imx258->hblank)
1281		imx258->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1282
1283	imx258->exposure = v4l2_ctrl_new_std(
1284				ctrl_hdlr, &imx258_ctrl_ops,
1285				V4L2_CID_EXPOSURE, IMX258_EXPOSURE_MIN,
1286				IMX258_EXPOSURE_MAX, IMX258_EXPOSURE_STEP,
1287				IMX258_EXPOSURE_DEFAULT);
1288
1289	v4l2_ctrl_new_std(ctrl_hdlr, &imx258_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1290				IMX258_ANA_GAIN_MIN, IMX258_ANA_GAIN_MAX,
1291				IMX258_ANA_GAIN_STEP, IMX258_ANA_GAIN_DEFAULT);
1292
1293	v4l2_ctrl_new_std(ctrl_hdlr, &imx258_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1294				IMX258_DGTL_GAIN_MIN, IMX258_DGTL_GAIN_MAX,
1295				IMX258_DGTL_GAIN_STEP,
1296				IMX258_DGTL_GAIN_DEFAULT);
1297
1298	v4l2_ctrl_new_std(ctrl_hdlr, &imx258_ctrl_ops, V4L2_CID_WIDE_DYNAMIC_RANGE,
1299				0, 1, 1, IMX258_HDR_RATIO_DEFAULT);
1300
1301	v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx258_ctrl_ops,
1302				V4L2_CID_TEST_PATTERN,
1303				ARRAY_SIZE(imx258_test_pattern_menu) - 1,
1304				0, 0, imx258_test_pattern_menu);
1305
1306	if (ctrl_hdlr->error) {
1307		ret = ctrl_hdlr->error;
1308		dev_err(imx258->dev, "%s control init failed (%d)\n",
1309				__func__, ret);
1310		goto error;
1311	}
1312
1313	ret = v4l2_fwnode_device_parse(imx258->dev, &props);
1314	if (ret)
1315		goto error;
1316
1317	ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx258_ctrl_ops,
1318					      &props);
1319	if (ret)
1320		goto error;
1321
1322	imx258->sd.ctrl_handler = ctrl_hdlr;
1323
1324	return 0;
1325
1326error:
1327	v4l2_ctrl_handler_free(ctrl_hdlr);
1328	mutex_destroy(&imx258->mutex);
1329
1330	return ret;
1331}
1332
1333static void imx258_free_controls(struct imx258 *imx258)
1334{
1335	v4l2_ctrl_handler_free(imx258->sd.ctrl_handler);
1336	mutex_destroy(&imx258->mutex);
1337}
1338
1339static int imx258_get_regulators(struct imx258 *imx258)
1340{
1341	unsigned int i;
1342
1343	for (i = 0; i < IMX258_NUM_SUPPLIES; i++)
1344		imx258->supplies[i].supply = imx258_supply_name[i];
1345
1346	return devm_regulator_bulk_get(imx258->dev,
1347				    IMX258_NUM_SUPPLIES, imx258->supplies);
1348}
1349
1350static int imx258_probe(struct i2c_client *client)
1351{
1352	struct imx258 *imx258;
1353	struct fwnode_handle *endpoint;
1354	struct v4l2_fwnode_endpoint ep = {
1355		.bus_type = V4L2_MBUS_CSI2_DPHY
1356	};
1357	int ret;
1358	u32 val = 0;
1359
1360	imx258 = devm_kzalloc(&client->dev, sizeof(*imx258), GFP_KERNEL);
1361	if (!imx258)
1362		return -ENOMEM;
1363
1364	imx258->dev = &client->dev;
1365
1366	imx258->regmap = devm_cci_regmap_init_i2c(client, 16);
1367	if (IS_ERR(imx258->regmap)) {
1368		ret = PTR_ERR(imx258->regmap);
1369		dev_err(imx258->dev, "failed to initialize CCI: %d\n", ret);
1370		return ret;
1371	}
1372
1373	ret = imx258_get_regulators(imx258);
1374	if (ret)
1375		return dev_err_probe(imx258->dev, ret,
1376				     "failed to get regulators\n");
1377
1378	imx258->clk = devm_v4l2_sensor_clk_get_legacy(imx258->dev, NULL, false,
1379						      0);
1380	if (IS_ERR(imx258->clk))
1381		return dev_err_probe(imx258->dev, PTR_ERR(imx258->clk),
1382				     "error getting clock\n");
1383
1384	val = clk_get_rate(imx258->clk);
1385
1386	switch (val) {
1387	case 19200000:
1388		imx258->link_freq_configs = link_freq_configs_19_2;
1389		imx258->link_freq_menu_items = link_freq_menu_items_19_2;
1390		break;
1391	case 24000000:
1392		imx258->link_freq_configs = link_freq_configs_24;
1393		imx258->link_freq_menu_items = link_freq_menu_items_24;
1394		break;
1395	default:
1396		dev_err(imx258->dev, "input clock frequency of %u not supported\n",
1397			val);
1398		return -EINVAL;
1399	}
1400
1401	endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(imx258->dev), NULL);
1402	if (!endpoint) {
1403		dev_err(imx258->dev, "Endpoint node not found\n");
1404		return -EINVAL;
1405	}
1406
1407	ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep);
1408	fwnode_handle_put(endpoint);
1409	if (ret) {
1410		dev_err(imx258->dev, "Parsing endpoint node failed\n");
1411		return ret;
1412	}
1413
1414	ret = v4l2_link_freq_to_bitmap(imx258->dev,
1415				       ep.link_frequencies,
1416				       ep.nr_of_link_frequencies,
1417				       imx258->link_freq_menu_items,
1418				       ARRAY_SIZE(link_freq_menu_items_19_2),
1419				       &imx258->link_freq_bitmap);
1420	if (ret) {
1421		dev_err(imx258->dev, "Link frequency not supported\n");
1422		goto error_endpoint_free;
1423	}
1424
1425	/* Get number of data lanes */
1426	switch (ep.bus.mipi_csi2.num_data_lanes) {
1427	case 2:
1428		imx258->lane_mode_idx = IMX258_2_LANE_MODE;
1429		break;
1430	case 4:
1431		imx258->lane_mode_idx = IMX258_4_LANE_MODE;
1432		break;
1433	default:
1434		dev_err(imx258->dev, "Invalid data lanes: %u\n",
1435			ep.bus.mipi_csi2.num_data_lanes);
1436		ret = -EINVAL;
1437		goto error_endpoint_free;
1438	}
1439
1440	imx258->csi2_flags = ep.bus.mipi_csi2.flags;
1441
1442	imx258->variant_cfg = device_get_match_data(imx258->dev);
1443	if (!imx258->variant_cfg)
1444		imx258->variant_cfg = &imx258_cfg;
1445
1446	/* Initialize subdev */
1447	v4l2_i2c_subdev_init(&imx258->sd, client, &imx258_subdev_ops);
1448
1449	/* Will be powered off via pm_runtime_idle */
1450	ret = imx258_power_on(imx258->dev);
1451	if (ret)
1452		goto error_endpoint_free;
1453
1454	/* Check module identity */
1455	ret = imx258_identify_module(imx258);
1456	if (ret)
1457		goto error_identify;
1458
1459	/* Set default mode to max resolution */
1460	imx258->cur_mode = &supported_modes[0];
1461
1462	ret = imx258_init_controls(imx258);
1463	if (ret)
1464		goto error_identify;
1465
1466	/* Initialize subdev */
1467	imx258->sd.internal_ops = &imx258_internal_ops;
1468	imx258->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1469	imx258->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1470
1471	/* Initialize source pad */
1472	imx258->pad.flags = MEDIA_PAD_FL_SOURCE;
1473
1474	ret = media_entity_pads_init(&imx258->sd.entity, 1, &imx258->pad);
1475	if (ret)
1476		goto error_handler_free;
1477
1478	ret = v4l2_async_register_subdev_sensor(&imx258->sd);
1479	if (ret < 0)
1480		goto error_media_entity;
1481
1482	pm_runtime_set_active(imx258->dev);
1483	pm_runtime_enable(imx258->dev);
1484	pm_runtime_idle(imx258->dev);
1485	v4l2_fwnode_endpoint_free(&ep);
1486
1487	return 0;
1488
1489error_media_entity:
1490	media_entity_cleanup(&imx258->sd.entity);
1491
1492error_handler_free:
1493	imx258_free_controls(imx258);
1494
1495error_identify:
1496	imx258_power_off(imx258->dev);
1497
1498error_endpoint_free:
1499	v4l2_fwnode_endpoint_free(&ep);
1500
1501	return ret;
1502}
1503
1504static void imx258_remove(struct i2c_client *client)
1505{
1506	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1507	struct imx258 *imx258 = to_imx258(sd);
1508
1509	v4l2_async_unregister_subdev(sd);
1510	media_entity_cleanup(&sd->entity);
1511	imx258_free_controls(imx258);
1512
1513	pm_runtime_disable(imx258->dev);
1514	if (!pm_runtime_status_suspended(imx258->dev))
1515		imx258_power_off(imx258->dev);
1516	pm_runtime_set_suspended(imx258->dev);
1517}
1518
1519static const struct dev_pm_ops imx258_pm_ops = {
1520	SET_RUNTIME_PM_OPS(imx258_power_off, imx258_power_on, NULL)
1521};
1522
1523#ifdef CONFIG_ACPI
1524static const struct acpi_device_id imx258_acpi_ids[] = {
1525	{ "SONY258A" },
1526	{ /* sentinel */ }
1527};
1528
1529MODULE_DEVICE_TABLE(acpi, imx258_acpi_ids);
1530#endif
1531
1532static const struct of_device_id imx258_dt_ids[] = {
1533	{ .compatible = "sony,imx258", .data = &imx258_cfg },
1534	{ .compatible = "sony,imx258-pdaf", .data = &imx258_pdaf_cfg },
1535	{ /* sentinel */ }
1536};
1537MODULE_DEVICE_TABLE(of, imx258_dt_ids);
1538
1539static struct i2c_driver imx258_i2c_driver = {
1540	.driver = {
1541		.name = "imx258",
1542		.pm = &imx258_pm_ops,
1543		.acpi_match_table = ACPI_PTR(imx258_acpi_ids),
1544		.of_match_table	= imx258_dt_ids,
1545	},
1546	.probe = imx258_probe,
1547	.remove = imx258_remove,
1548};
1549
1550module_i2c_driver(imx258_i2c_driver);
1551
1552MODULE_AUTHOR("Yeh, Andy <andy.yeh@intel.com>");
1553MODULE_AUTHOR("Chiang, Alan");
1554MODULE_AUTHOR("Chen, Jason");
1555MODULE_DESCRIPTION("Sony IMX258 sensor driver");
1556MODULE_LICENSE("GPL v2");