gc0308.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Driver for the GalaxyCore GC0308 camera sensor.
   4 *
   5 * Copyright (c) 2023 Sebastian Reichel <sre@kernel.org>
   6 */
   7
   8#include <linux/clk.h>
   9#include <linux/device.h>
  10#include <linux/gpio/consumer.h>
  11#include <linux/i2c.h>
  12#include <linux/module.h>
  13#include <linux/mod_devicetable.h>
  14#include <linux/pm_runtime.h>
  15#include <linux/regmap.h>
  16#include <linux/regulator/consumer.h>
  17
  18#include <media/v4l2-cci.h>
  19#include <media/v4l2-ctrls.h>
  20#include <media/v4l2-device.h>
  21#include <media/v4l2-fwnode.h>
  22#include <media/v4l2-subdev.h>
  23
  24/* Analog & CISCTL*/
  25#define GC0308_CHIP_ID			CCI_REG8(0x000)
  26#define GC0308_HBLANK			CCI_REG8(0x001)
  27#define GC0308_VBLANK			CCI_REG8(0x002)
  28#define GC0308_EXP			CCI_REG16(0x003)
  29#define GC0308_ROW_START		CCI_REG16(0x005)
  30#define GC0308_COL_START		CCI_REG16(0x007)
  31#define GC0308_WIN_HEIGHT		CCI_REG16(0x009)
  32#define GC0308_WIN_WIDTH		CCI_REG16(0x00b)
  33#define GC0308_VS_START_TIME		CCI_REG8(0x00d) /* in rows */
  34#define GC0308_VS_END_TIME		CCI_REG8(0x00e) /* in rows */
  35#define GC0308_VB_HB			CCI_REG8(0x00f)
  36#define GC0308_RSH_WIDTH		CCI_REG8(0x010)
  37#define GC0308_TSP_WIDTH		CCI_REG8(0x011)
  38#define GC0308_SAMPLE_HOLD_DELAY	CCI_REG8(0x012)
  39#define GC0308_ROW_TAIL_WIDTH		CCI_REG8(0x013)
  40#define GC0308_CISCTL_MODE1		CCI_REG8(0x014)
  41#define GC0308_CISCTL_MODE2		CCI_REG8(0x015)
  42#define GC0308_CISCTL_MODE3		CCI_REG8(0x016)
  43#define GC0308_CISCTL_MODE4		CCI_REG8(0x017)
  44#define GC0308_ANALOG_MODE1		CCI_REG8(0x01a)
  45#define GC0308_ANALOG_MODE2		CCI_REG8(0x01b)
  46#define GC0308_HRST_RSG_V18		CCI_REG8(0x01c)
  47#define GC0308_VREF_V25			CCI_REG8(0x01d)
  48#define GC0308_ADC_R			CCI_REG8(0x01e)
  49#define GC0308_PAD_DRV			CCI_REG8(0x01f)
  50#define GC0308_SOFT_RESET		CCI_REG8(0x0fe)
  51
  52/* ISP */
  53#define GC0308_BLOCK_EN1		CCI_REG8(0x020)
  54#define GC0308_BLOCK_EN2		CCI_REG8(0x021)
  55#define GC0308_AAAA_EN			CCI_REG8(0x022)
  56#define GC0308_SPECIAL_EFFECT		CCI_REG8(0x023)
  57#define GC0308_OUT_FORMAT		CCI_REG8(0x024)
  58#define GC0308_OUT_EN			CCI_REG8(0x025)
  59#define GC0308_SYNC_MODE		CCI_REG8(0x026)
  60#define GC0308_CLK_DIV_MODE		CCI_REG8(0x028)
  61#define GC0308_BYPASS_MODE		CCI_REG8(0x029)
  62#define GC0308_CLK_GATING		CCI_REG8(0x02a)
  63#define GC0308_DITHER_MODE		CCI_REG8(0x02b)
  64#define GC0308_DITHER_BIT		CCI_REG8(0x02c)
  65#define GC0308_DEBUG_MODE1		CCI_REG8(0x02d)
  66#define GC0308_DEBUG_MODE2		CCI_REG8(0x02e)
  67#define GC0308_DEBUG_MODE3		CCI_REG8(0x02f)
  68#define GC0308_CROP_WIN_MODE		CCI_REG8(0x046)
  69#define GC0308_CROP_WIN_Y1		CCI_REG8(0x047)
  70#define GC0308_CROP_WIN_X1		CCI_REG8(0x048)
  71#define GC0308_CROP_WIN_HEIGHT		CCI_REG16(0x049)
  72#define GC0308_CROP_WIN_WIDTH		CCI_REG16(0x04b)
  73
  74/* BLK */
  75#define GC0308_BLK_MODE			CCI_REG8(0x030)
  76#define GC0308_BLK_LIMIT_VAL		CCI_REG8(0x031)
  77#define GC0308_GLOBAL_OFF		CCI_REG8(0x032)
  78#define GC0308_CURRENT_R_OFF		CCI_REG8(0x033)
  79#define GC0308_CURRENT_G_OFF		CCI_REG8(0x034)
  80#define GC0308_CURRENT_B_OFF		CCI_REG8(0x035)
  81#define GC0308_CURRENT_R_DARK_CURRENT	CCI_REG8(0x036)
  82#define GC0308_CURRENT_G_DARK_CURRENT	CCI_REG8(0x037)
  83#define GC0308_CURRENT_B_DARK_CURRENT	CCI_REG8(0x038)
  84#define GC0308_EXP_RATE_DARKC		CCI_REG8(0x039)
  85#define GC0308_OFF_SUBMODE		CCI_REG8(0x03a)
  86#define GC0308_DARKC_SUBMODE		CCI_REG8(0x03b)
  87#define GC0308_MANUAL_G1_OFF		CCI_REG8(0x03c)
  88#define GC0308_MANUAL_R1_OFF		CCI_REG8(0x03d)
  89#define GC0308_MANUAL_B2_OFF		CCI_REG8(0x03e)
  90#define GC0308_MANUAL_G2_OFF		CCI_REG8(0x03f)
  91
  92/* PREGAIN */
  93#define GC0308_GLOBAL_GAIN		CCI_REG8(0x050)
  94#define GC0308_AUTO_PREGAIN		CCI_REG8(0x051)
  95#define GC0308_AUTO_POSTGAIN		CCI_REG8(0x052)
  96#define GC0308_CHANNEL_GAIN_G1		CCI_REG8(0x053)
  97#define GC0308_CHANNEL_GAIN_R		CCI_REG8(0x054)
  98#define GC0308_CHANNEL_GAIN_B		CCI_REG8(0x055)
  99#define GC0308_CHANNEL_GAIN_G2		CCI_REG8(0x056)
 100#define GC0308_R_RATIO			CCI_REG8(0x057)
 101#define GC0308_G_RATIO			CCI_REG8(0x058)
 102#define GC0308_B_RATIO			CCI_REG8(0x059)
 103#define GC0308_AWB_R_GAIN		CCI_REG8(0x05a)
 104#define GC0308_AWB_G_GAIN		CCI_REG8(0x05b)
 105#define GC0308_AWB_B_GAIN		CCI_REG8(0x05c)
 106#define GC0308_LSC_DEC_LVL1		CCI_REG8(0x05d)
 107#define GC0308_LSC_DEC_LVL2		CCI_REG8(0x05e)
 108#define GC0308_LSC_DEC_LVL3		CCI_REG8(0x05f)
 109
 110/* DNDD */
 111#define GC0308_DN_MODE_EN		CCI_REG8(0x060)
 112#define GC0308_DN_MODE_RATIO		CCI_REG8(0x061)
 113#define GC0308_DN_BILAT_B_BASE		CCI_REG8(0x062)
 114#define GC0308_DN_B_INCR		CCI_REG8(0x063)
 115#define GC0308_DN_BILAT_N_BASE		CCI_REG8(0x064)
 116#define GC0308_DN_N_INCR		CCI_REG8(0x065)
 117#define GC0308_DD_DARK_BRIGHT_TH	CCI_REG8(0x066)
 118#define GC0308_DD_FLAT_TH		CCI_REG8(0x067)
 119#define GC0308_DD_LIMIT			CCI_REG8(0x068)
 120
 121/* ASDE - Auto Saturation De-noise and Edge-Enhancement */
 122#define GC0308_ASDE_GAIN_TRESH		CCI_REG8(0x069)
 123#define GC0308_ASDE_GAIN_MODE		CCI_REG8(0x06a)
 124#define GC0308_ASDE_DN_SLOPE		CCI_REG8(0x06b)
 125#define GC0308_ASDE_DD_BRIGHT		CCI_REG8(0x06c)
 126#define GC0308_ASDE_DD_LIMIT		CCI_REG8(0x06d)
 127#define GC0308_ASDE_AUTO_EE1		CCI_REG8(0x06e)
 128#define GC0308_ASDE_AUTO_EE2		CCI_REG8(0x06f)
 129#define GC0308_ASDE_AUTO_SAT_DEC_SLOPE	CCI_REG8(0x070)
 130#define GC0308_ASDE_AUTO_SAT_LOW_LIMIT	CCI_REG8(0x071)
 131
 132/* INTPEE - Interpolation and Edge-Enhancement */
 133#define GC0308_EEINTP_MODE_1		CCI_REG8(0x072)
 134#define GC0308_EEINTP_MODE_2		CCI_REG8(0x073)
 135#define GC0308_DIRECTION_TH1		CCI_REG8(0x074)
 136#define GC0308_DIRECTION_TH2		CCI_REG8(0x075)
 137#define GC0308_DIFF_HV_TI_TH		CCI_REG8(0x076)
 138#define GC0308_EDGE12_EFFECT		CCI_REG8(0x077)
 139#define GC0308_EDGE_POS_RATIO		CCI_REG8(0x078)
 140#define GC0308_EDGE1_MINMAX		CCI_REG8(0x079)
 141#define GC0308_EDGE2_MINMAX		CCI_REG8(0x07a)
 142#define GC0308_EDGE12_TH		CCI_REG8(0x07b)
 143#define GC0308_EDGE_MAX			CCI_REG8(0x07c)
 144
 145/* ABB - Auto Black Balance */
 146#define GC0308_ABB_MODE			CCI_REG8(0x080)
 147#define GC0308_ABB_TARGET_AVGH		CCI_REG8(0x081)
 148#define GC0308_ABB_TARGET_AVGL		CCI_REG8(0x082)
 149#define GC0308_ABB_LIMIT_VAL		CCI_REG8(0x083)
 150#define GC0308_ABB_SPEED		CCI_REG8(0x084)
 151#define GC0308_CURR_R_BLACK_LVL		CCI_REG8(0x085)
 152#define GC0308_CURR_G_BLACK_LVL		CCI_REG8(0x086)
 153#define GC0308_CURR_B_BLACK_LVL		CCI_REG8(0x087)
 154#define GC0308_CURR_R_BLACK_FACTOR	CCI_REG8(0x088)
 155#define GC0308_CURR_G_BLACK_FACTOR	CCI_REG8(0x089)
 156#define GC0308_CURR_B_BLACK_FACTOR	CCI_REG8(0x08a)
 157
 158/* LSC - Lens Shading Correction */
 159#define GC0308_LSC_RED_B2		CCI_REG8(0x08b)
 160#define GC0308_LSC_GREEN_B2		CCI_REG8(0x08c)
 161#define GC0308_LSC_BLUE_B2		CCI_REG8(0x08d)
 162#define GC0308_LSC_RED_B4		CCI_REG8(0x08e)
 163#define GC0308_LSC_GREEN_B4		CCI_REG8(0x08f)
 164#define GC0308_LSC_BLUE_B4		CCI_REG8(0x090)
 165#define GC0308_LSC_ROW_CENTER		CCI_REG8(0x091)
 166#define GC0308_LSC_COL_CENTER		CCI_REG8(0x092)
 167
 168/* CC - Channel Coefficient */
 169#define GC0308_CC_MATRIX_C11		CCI_REG8(0x093)
 170#define GC0308_CC_MATRIX_C12		CCI_REG8(0x094)
 171#define GC0308_CC_MATRIX_C13		CCI_REG8(0x095)
 172#define GC0308_CC_MATRIX_C21		CCI_REG8(0x096)
 173#define GC0308_CC_MATRIX_C22		CCI_REG8(0x097)
 174#define GC0308_CC_MATRIX_C23		CCI_REG8(0x098)
 175#define GC0308_CC_MATRIX_C41		CCI_REG8(0x09c)
 176#define GC0308_CC_MATRIX_C42		CCI_REG8(0x09d)
 177#define GC0308_CC_MATRIX_C43		CCI_REG8(0x09e)
 178
 179/* GAMMA */
 180#define GC0308_GAMMA_OUT0		CCI_REG8(0x09f)
 181#define GC0308_GAMMA_OUT1		CCI_REG8(0x0a0)
 182#define GC0308_GAMMA_OUT2		CCI_REG8(0x0a1)
 183#define GC0308_GAMMA_OUT3		CCI_REG8(0x0a2)
 184#define GC0308_GAMMA_OUT4		CCI_REG8(0x0a3)
 185#define GC0308_GAMMA_OUT5		CCI_REG8(0x0a4)
 186#define GC0308_GAMMA_OUT6		CCI_REG8(0x0a5)
 187#define GC0308_GAMMA_OUT7		CCI_REG8(0x0a6)
 188#define GC0308_GAMMA_OUT8		CCI_REG8(0x0a7)
 189#define GC0308_GAMMA_OUT9		CCI_REG8(0x0a8)
 190#define GC0308_GAMMA_OUT10		CCI_REG8(0x0a9)
 191#define GC0308_GAMMA_OUT11		CCI_REG8(0x0aa)
 192#define GC0308_GAMMA_OUT12		CCI_REG8(0x0ab)
 193#define GC0308_GAMMA_OUT13		CCI_REG8(0x0ac)
 194#define GC0308_GAMMA_OUT14		CCI_REG8(0x0ad)
 195#define GC0308_GAMMA_OUT15		CCI_REG8(0x0ae)
 196#define GC0308_GAMMA_OUT16		CCI_REG8(0x0af)
 197
 198/* YCP */
 199#define GC0308_GLOBAL_SATURATION	CCI_REG8(0x0b0)
 200#define GC0308_SATURATION_CB		CCI_REG8(0x0b1)
 201#define GC0308_SATURATION_CR		CCI_REG8(0x0b2)
 202#define GC0308_LUMA_CONTRAST		CCI_REG8(0x0b3)
 203#define GC0308_CONTRAST_CENTER		CCI_REG8(0x0b4)
 204#define GC0308_LUMA_OFFSET		CCI_REG8(0x0b5)
 205#define GC0308_SKIN_CB_CENTER		CCI_REG8(0x0b6)
 206#define GC0308_SKIN_CR_CENTER		CCI_REG8(0x0b7)
 207#define GC0308_SKIN_RADIUS_SQUARE	CCI_REG8(0x0b8)
 208#define GC0308_SKIN_BRIGHTNESS		CCI_REG8(0x0b9)
 209#define GC0308_FIXED_CB			CCI_REG8(0x0ba)
 210#define GC0308_FIXED_CR			CCI_REG8(0x0bb)
 211#define GC0308_EDGE_DEC_SA		CCI_REG8(0x0bd)
 212#define GC0308_AUTO_GRAY_MODE		CCI_REG8(0x0be)
 213#define GC0308_SATURATION_SUB_STRENGTH	CCI_REG8(0x0bf)
 214#define GC0308_Y_GAMMA_OUT0		CCI_REG8(0x0c0)
 215#define GC0308_Y_GAMMA_OUT1		CCI_REG8(0x0c1)
 216#define GC0308_Y_GAMMA_OUT2		CCI_REG8(0x0c2)
 217#define GC0308_Y_GAMMA_OUT3		CCI_REG8(0x0c3)
 218#define GC0308_Y_GAMMA_OUT4		CCI_REG8(0x0c4)
 219#define GC0308_Y_GAMMA_OUT5		CCI_REG8(0x0c5)
 220#define GC0308_Y_GAMMA_OUT6		CCI_REG8(0x0c6)
 221#define GC0308_Y_GAMMA_OUT7		CCI_REG8(0x0c7)
 222#define GC0308_Y_GAMMA_OUT8		CCI_REG8(0x0c8)
 223#define GC0308_Y_GAMMA_OUT9		CCI_REG8(0x0c9)
 224#define GC0308_Y_GAMMA_OUT10		CCI_REG8(0x0ca)
 225#define GC0308_Y_GAMMA_OUT11		CCI_REG8(0x0cb)
 226#define GC0308_Y_GAMMA_OUT12		CCI_REG8(0x0cc)
 227
 228/* AEC - Automatic Exposure Control */
 229#define GC0308_AEC_MODE1		CCI_REG8(0x0d0)
 230#define GC0308_AEC_MODE2		CCI_REG8(0x0d1)
 231#define GC0308_AEC_MODE3		CCI_REG8(0x0d2)
 232#define GC0308_AEC_TARGET_Y		CCI_REG8(0x0d3)
 233#define GC0308_Y_AVG			CCI_REG8(0x0d4)
 234#define GC0308_AEC_HIGH_LOW_RANGE	CCI_REG8(0x0d5)
 235#define GC0308_AEC_IGNORE		CCI_REG8(0x0d6)
 236#define GC0308_AEC_LIMIT_HIGH_RANGE	CCI_REG8(0x0d7)
 237#define GC0308_AEC_R_OFFSET		CCI_REG8(0x0d9)
 238#define GC0308_AEC_GB_OFFSET		CCI_REG8(0x0da)
 239#define GC0308_AEC_SLOW_MARGIN		CCI_REG8(0x0db)
 240#define GC0308_AEC_FAST_MARGIN		CCI_REG8(0x0dc)
 241#define GC0308_AEC_EXP_CHANGE_GAIN	CCI_REG8(0x0dd)
 242#define GC0308_AEC_STEP2_SUNLIGHT	CCI_REG8(0x0de)
 243#define GC0308_AEC_I_FRAMES		CCI_REG8(0x0df)
 244#define GC0308_AEC_I_STOP_L_MARGIN	CCI_REG8(0x0e0)
 245#define GC0308_AEC_I_STOP_MARGIN	CCI_REG8(0x0e1)
 246#define GC0308_ANTI_FLICKER_STEP	CCI_REG16(0x0e2)
 247#define GC0308_EXP_LVL_1		CCI_REG16(0x0e4)
 248#define GC0308_EXP_LVL_2		CCI_REG16(0x0e6)
 249#define GC0308_EXP_LVL_3		CCI_REG16(0x0e8)
 250#define GC0308_EXP_LVL_4		CCI_REG16(0x0ea)
 251#define GC0308_MAX_EXP_LVL		CCI_REG8(0x0ec)
 252#define GC0308_EXP_MIN_L		CCI_REG8(0x0ed)
 253#define GC0308_MAX_POST_DF_GAIN		CCI_REG8(0x0ee)
 254#define GC0308_MAX_PRE_DG_GAIN		CCI_REG8(0x0ef)
 255
 256/* ABS */
 257#define GC0308_ABS_RANGE_COMP		CCI_REG8(0x0f0)
 258#define GC0308_ABS_STOP_MARGIN		CCI_REG8(0x0f1)
 259#define GC0308_Y_S_COMP			CCI_REG8(0x0f2)
 260#define GC0308_Y_STRETCH_LIMIT		CCI_REG8(0x0f3)
 261#define GC0308_Y_TILT			CCI_REG8(0x0f4)
 262#define GC0308_Y_STRETCH		CCI_REG8(0x0f5)
 263
 264/* Measure Window */
 265#define GC0308_BIG_WIN_X0		CCI_REG8(0x0f7)
 266#define GC0308_BIG_WIN_Y0		CCI_REG8(0x0f8)
 267#define GC0308_BIG_WIN_X1		CCI_REG8(0x0f9)
 268#define GC0308_BIG_WIN_Y1		CCI_REG8(0x0fa)
 269#define GC0308_DIFF_Y_BIG_THD		CCI_REG8(0x0fb)
 270
 271/* OUT Module (P1) */
 272#define GC0308_CLOSE_FRAME_EN		CCI_REG8(0x150)
 273#define GC0308_CLOSE_FRAME_NUM1		CCI_REG8(0x151)
 274#define GC0308_CLOSE_FRAME_NUM2		CCI_REG8(0x152)
 275#define GC0308_BAYER_MODE		CCI_REG8(0x153)
 276#define GC0308_SUBSAMPLE		CCI_REG8(0x154)
 277#define GC0308_SUBMODE			CCI_REG8(0x155)
 278#define GC0308_SUB_ROW_N1		CCI_REG8(0x156)
 279#define GC0308_SUB_ROW_N2		CCI_REG8(0x157)
 280#define GC0308_SUB_COL_N1		CCI_REG8(0x158)
 281#define GC0308_SUB_COL_N2		CCI_REG8(0x159)
 282
 283/* AWB (P1) - Auto White Balance */
 284#define GC0308_AWB_RGB_HIGH_LOW		CCI_REG8(0x100)
 285#define GC0308_AWB_Y_TO_C_DIFF2		CCI_REG8(0x102)
 286#define GC0308_AWB_C_MAX		CCI_REG8(0x104)
 287#define GC0308_AWB_C_INTER		CCI_REG8(0x105)
 288#define GC0308_AWB_C_INTER2		CCI_REG8(0x106)
 289#define GC0308_AWB_C_MAX_BIG		CCI_REG8(0x108)
 290#define GC0308_AWB_Y_HIGH		CCI_REG8(0x109)
 291#define GC0308_AWB_NUMBER_LIMIT		CCI_REG8(0x10a)
 292#define GC0308_KWIN_RATIO		CCI_REG8(0x10b)
 293#define GC0308_KWIN_THD			CCI_REG8(0x10c)
 294#define GC0308_LIGHT_GAIN_RANGE		CCI_REG8(0x10d)
 295#define GC0308_SMALL_WIN_WIDTH_STEP	CCI_REG8(0x10e)
 296#define GC0308_SMALL_WIN_HEIGHT_STEP	CCI_REG8(0x10f)
 297#define GC0308_AWB_YELLOW_TH		CCI_REG8(0x110)
 298#define GC0308_AWB_MODE			CCI_REG8(0x111)
 299#define GC0308_AWB_ADJUST_SPEED		CCI_REG8(0x112)
 300#define GC0308_AWB_EVERY_N		CCI_REG8(0x113)
 301#define GC0308_R_AVG_USE		CCI_REG8(0x1d0)
 302#define GC0308_G_AVG_USE		CCI_REG8(0x1d1)
 303#define GC0308_B_AVG_USE		CCI_REG8(0x1d2)
 304
 305#define GC0308_HBLANK_MIN		0x021
 306#define GC0308_HBLANK_MAX		0xfff
 307#define GC0308_HBLANK_DEF		0x040
 308
 309#define GC0308_VBLANK_MIN		0x000
 310#define GC0308_VBLANK_MAX		0xfff
 311#define GC0308_VBLANK_DEF		0x020
 312
 313#define GC0308_PIXEL_RATE		24000000
 314
 315/*
 316 * frame_time = (BT + height + 8) * row_time
 317 * width = 640 (driver does not change window size)
 318 * height = 480 (driver does not change window size)
 319 * row_time = HBLANK + SAMPLE_HOLD_DELAY + width + 8 + 4
 320 *
 321 * When EXP_TIME > (BT + height):
 322 *     BT = EXP_TIME - height - 8 - VS_START_TIME + VS_END_TIME
 323 * else:
 324 *     BT = VBLANK + VS_START_TIME + VS_END_TIME
 325 *
 326 * max is 30 FPS
 327 *
 328 * In my tests frame rate mostly depends on exposure time. Unfortuantely
 329 * it's unclear how this is calculated exactly. Also since we enable AEC,
 330 * the frame times vary depending on ambient light conditions.
 331 */
 332#define GC0308_FRAME_RATE_MAX		30
 333
 334enum gc0308_exp_val {
 335	GC0308_EXP_M4 = 0,
 336	GC0308_EXP_M3,
 337	GC0308_EXP_M2,
 338	GC0308_EXP_M1,
 339	GC0308_EXP_0,
 340	GC0308_EXP_P1,
 341	GC0308_EXP_P2,
 342	GC0308_EXP_P3,
 343	GC0308_EXP_P4,
 344};
 345
 346static const s64 gc0308_exposure_menu[] = {
 347	-4, -3, -2, -1, 0, 1, 2, 3, 4
 348};
 349
 350struct gc0308_exposure {
 351	u8 luma_offset;
 352	u8 aec_target_y;
 353};
 354
 355#define GC0308_EXPOSURE(luma_offset_reg, aec_target_y_reg) \
 356	{ .luma_offset = luma_offset_reg, .aec_target_y = aec_target_y_reg }
 357
 358static const struct gc0308_exposure gc0308_exposure_values[] = {
 359	[GC0308_EXP_M4] = GC0308_EXPOSURE(0xc0, 0x30),
 360	[GC0308_EXP_M3] = GC0308_EXPOSURE(0xd0, 0x38),
 361	[GC0308_EXP_M2] = GC0308_EXPOSURE(0xe0, 0x40),
 362	[GC0308_EXP_M1] = GC0308_EXPOSURE(0xf0, 0x48),
 363	[GC0308_EXP_0]  = GC0308_EXPOSURE(0x08, 0x50),
 364	[GC0308_EXP_P1] = GC0308_EXPOSURE(0x10, 0x5c),
 365	[GC0308_EXP_P2] = GC0308_EXPOSURE(0x20, 0x60),
 366	[GC0308_EXP_P3] = GC0308_EXPOSURE(0x30, 0x68),
 367	[GC0308_EXP_P4] = GC0308_EXPOSURE(0x40, 0x70),
 368};
 369
 370struct gc0308_awb_gains {
 371	u8 r;
 372	u8 g;
 373	u8 b;
 374};
 375
 376#define GC0308_AWB_GAINS(red, green, blue) \
 377	{ .r = red, .g = green, .b = blue }
 378
 379static const struct gc0308_awb_gains gc0308_awb_gains[] = {
 380	[V4L2_WHITE_BALANCE_AUTO]         = GC0308_AWB_GAINS(0x56, 0x40, 0x4a),
 381	[V4L2_WHITE_BALANCE_CLOUDY]       = GC0308_AWB_GAINS(0x8c, 0x50, 0x40),
 382	[V4L2_WHITE_BALANCE_DAYLIGHT]     = GC0308_AWB_GAINS(0x74, 0x52, 0x40),
 383	[V4L2_WHITE_BALANCE_INCANDESCENT] = GC0308_AWB_GAINS(0x48, 0x40, 0x5c),
 384	[V4L2_WHITE_BALANCE_FLUORESCENT]  = GC0308_AWB_GAINS(0x40, 0x42, 0x50),
 385};
 386
 387struct gc0308_format {
 388	u32 code;
 389	u8 regval;
 390};
 391
 392#define GC0308_FORMAT(v4l2_code, gc0308_regval) \
 393	{ .code = v4l2_code, .regval = gc0308_regval }
 394
 395static const struct gc0308_format gc0308_formats[] = {
 396	GC0308_FORMAT(MEDIA_BUS_FMT_UYVY8_2X8, 0x00),
 397	GC0308_FORMAT(MEDIA_BUS_FMT_VYUY8_2X8, 0x01),
 398	GC0308_FORMAT(MEDIA_BUS_FMT_YUYV8_2X8, 0x02),
 399	GC0308_FORMAT(MEDIA_BUS_FMT_YVYU8_2X8, 0x03),
 400	GC0308_FORMAT(MEDIA_BUS_FMT_RGB565_2X8_BE, 0x06),
 401	GC0308_FORMAT(MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, 0x07),
 402	GC0308_FORMAT(MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE, 0x09),
 403};
 404
 405struct gc0308_frame_size {
 406	u8 subsample;
 407	u32 width;
 408	u32 height;
 409};
 410
 411#define GC0308_FRAME_SIZE(s, w, h) \
 412	{ .subsample = s, .width = w, .height = h }
 413
 414static const struct gc0308_frame_size gc0308_frame_sizes[] = {
 415	GC0308_FRAME_SIZE(0x11, 640, 480),
 416	GC0308_FRAME_SIZE(0x22, 320, 240),
 417	GC0308_FRAME_SIZE(0x44, 160, 120),
 418};
 419
 420struct gc0308_mode_registers {
 421	u8 out_format;
 422	u8 subsample;
 423	u16 width;
 424	u16 height;
 425};
 426
 427struct gc0308 {
 428	struct v4l2_subdev sd;
 429	struct v4l2_ctrl_handler hdl;
 430	struct media_pad pad;
 431	struct device *dev;
 432	struct clk *clk;
 433	struct regmap *regmap;
 434	struct regulator *vdd;
 435	struct gpio_desc *pwdn_gpio;
 436	struct gpio_desc *reset_gpio;
 437	unsigned int mbus_config;
 438	struct gc0308_mode_registers mode;
 439	struct {
 440		/* mirror cluster */
 441		struct v4l2_ctrl *hflip;
 442		struct v4l2_ctrl *vflip;
 443	};
 444	struct {
 445		/* blanking cluster */
 446		struct v4l2_ctrl *hblank;
 447		struct v4l2_ctrl *vblank;
 448	};
 449};
 450
 451static inline struct gc0308 *to_gc0308(struct v4l2_subdev *sd)
 452{
 453	return container_of(sd, struct gc0308, sd);
 454}
 455
 456static const struct regmap_range_cfg gc0308_ranges[] = {
 457	{
 458		.range_min	= 0x0000,
 459		.range_max	= 0x01ff,
 460		.selector_reg	= 0xfe,
 461		.selector_mask	= 0x01,
 462		.selector_shift	= 0x00,
 463		.window_start	= 0x00,
 464		.window_len	= 0x100,
 465	},
 466};
 467
 468static const struct regmap_config gc0308_regmap_config = {
 469	.reg_bits = 8,
 470	.val_bits = 8,
 471	.reg_format_endian = REGMAP_ENDIAN_BIG,
 472	.max_register = 0x1ff,
 473	.ranges = gc0308_ranges,
 474	.num_ranges = ARRAY_SIZE(gc0308_ranges),
 475	.disable_locking = true,
 476};
 477
 478static const struct cci_reg_sequence sensor_default_regs[] = {
 479	{GC0308_VB_HB, 0x00},
 480	{GC0308_HBLANK, 0x40},
 481	{GC0308_VBLANK, 0x20},
 482	{GC0308_EXP, 0x0258},
 483	{GC0308_AWB_R_GAIN, 0x56},
 484	{GC0308_AWB_G_GAIN, 0x40},
 485	{GC0308_AWB_B_GAIN, 0x4a},
 486	{GC0308_ANTI_FLICKER_STEP, 0x0078},
 487	{GC0308_EXP_LVL_1, 0x0258},
 488	{GC0308_EXP_LVL_2, 0x0258},
 489	{GC0308_EXP_LVL_3, 0x0258},
 490	{GC0308_EXP_LVL_4, 0x0ea6},
 491	{GC0308_MAX_EXP_LVL, 0x20},
 492	{GC0308_ROW_START, 0x0000},
 493	{GC0308_COL_START, 0x0000},
 494	{GC0308_WIN_HEIGHT, 488},
 495	{GC0308_WIN_WIDTH, 648},
 496	{GC0308_VS_START_TIME, 0x02},
 497	{GC0308_VS_END_TIME, 0x02},
 498	{GC0308_RSH_WIDTH, 0x22},
 499	{GC0308_TSP_WIDTH, 0x0d},
 500	{GC0308_SAMPLE_HOLD_DELAY, 0x50},
 501	{GC0308_ROW_TAIL_WIDTH, 0x0f},
 502	{GC0308_CISCTL_MODE1, 0x10},
 503	{GC0308_CISCTL_MODE2, 0x0a},
 504	{GC0308_CISCTL_MODE3, 0x05},
 505	{GC0308_CISCTL_MODE4, 0x01},
 506	{CCI_REG8(0x018), 0x44}, /* undocumented */
 507	{CCI_REG8(0x019), 0x44}, /* undocumented */
 508	{GC0308_ANALOG_MODE1, 0x2a},
 509	{GC0308_ANALOG_MODE2, 0x00},
 510	{GC0308_HRST_RSG_V18, 0x49},
 511	{GC0308_VREF_V25, 0x9a},
 512	{GC0308_ADC_R, 0x61},
 513	{GC0308_PAD_DRV, 0x01}, /* drv strength: pclk=4mA */
 514	{GC0308_BLOCK_EN1, 0x7f},
 515	{GC0308_BLOCK_EN2, 0xfa},
 516	{GC0308_AAAA_EN, 0x57},
 517	{GC0308_OUT_FORMAT, 0xa2}, /* YCbYCr */
 518	{GC0308_OUT_EN, 0x0f},
 519	{GC0308_SYNC_MODE, 0x03},
 520	{GC0308_CLK_DIV_MODE, 0x00},
 521	{GC0308_DEBUG_MODE1, 0x0a},
 522	{GC0308_DEBUG_MODE2, 0x00},
 523	{GC0308_DEBUG_MODE3, 0x01},
 524	{GC0308_BLK_MODE, 0xf7},
 525	{GC0308_BLK_LIMIT_VAL, 0x50},
 526	{GC0308_GLOBAL_OFF, 0x00},
 527	{GC0308_CURRENT_R_OFF, 0x28},
 528	{GC0308_CURRENT_G_OFF, 0x2a},
 529	{GC0308_CURRENT_B_OFF, 0x28},
 530	{GC0308_EXP_RATE_DARKC, 0x04},
 531	{GC0308_OFF_SUBMODE, 0x20},
 532	{GC0308_DARKC_SUBMODE, 0x20},
 533	{GC0308_MANUAL_G1_OFF, 0x00},
 534	{GC0308_MANUAL_R1_OFF, 0x00},
 535	{GC0308_MANUAL_B2_OFF, 0x00},
 536	{GC0308_MANUAL_G2_OFF, 0x00},
 537	{GC0308_GLOBAL_GAIN, 0x14},
 538	{GC0308_AUTO_POSTGAIN, 0x41},
 539	{GC0308_CHANNEL_GAIN_G1, 0x80},
 540	{GC0308_CHANNEL_GAIN_R, 0x80},
 541	{GC0308_CHANNEL_GAIN_B, 0x80},
 542	{GC0308_CHANNEL_GAIN_G2, 0x80},
 543	{GC0308_LSC_RED_B2, 0x20},
 544	{GC0308_LSC_GREEN_B2, 0x20},
 545	{GC0308_LSC_BLUE_B2, 0x20},
 546	{GC0308_LSC_RED_B4, 0x14},
 547	{GC0308_LSC_GREEN_B4, 0x10},
 548	{GC0308_LSC_BLUE_B4, 0x14},
 549	{GC0308_LSC_ROW_CENTER, 0x3c},
 550	{GC0308_LSC_COL_CENTER, 0x50},
 551	{GC0308_LSC_DEC_LVL1, 0x12},
 552	{GC0308_LSC_DEC_LVL2, 0x1a},
 553	{GC0308_LSC_DEC_LVL3, 0x24},
 554	{GC0308_DN_MODE_EN, 0x07},
 555	{GC0308_DN_MODE_RATIO, 0x15},
 556	{GC0308_DN_BILAT_B_BASE, 0x08},
 557	{GC0308_DN_BILAT_N_BASE, 0x03},
 558	{GC0308_DD_DARK_BRIGHT_TH, 0xe8},
 559	{GC0308_DD_FLAT_TH, 0x86},
 560	{GC0308_DD_LIMIT, 0x82},
 561	{GC0308_ASDE_GAIN_TRESH, 0x18},
 562	{GC0308_ASDE_GAIN_MODE, 0x0f},
 563	{GC0308_ASDE_DN_SLOPE, 0x00},
 564	{GC0308_ASDE_DD_BRIGHT, 0x5f},
 565	{GC0308_ASDE_DD_LIMIT, 0x8f},
 566	{GC0308_ASDE_AUTO_EE1, 0x55},
 567	{GC0308_ASDE_AUTO_EE2, 0x38},
 568	{GC0308_ASDE_AUTO_SAT_DEC_SLOPE, 0x15},
 569	{GC0308_ASDE_AUTO_SAT_LOW_LIMIT, 0x33},
 570	{GC0308_EEINTP_MODE_1, 0xdc},
 571	{GC0308_EEINTP_MODE_2, 0x00},
 572	{GC0308_DIRECTION_TH1, 0x02},
 573	{GC0308_DIRECTION_TH2, 0x3f},
 574	{GC0308_DIFF_HV_TI_TH, 0x02},
 575	{GC0308_EDGE12_EFFECT, 0x38},
 576	{GC0308_EDGE_POS_RATIO, 0x88},
 577	{GC0308_EDGE1_MINMAX, 0x81},
 578	{GC0308_EDGE2_MINMAX, 0x81},
 579	{GC0308_EDGE12_TH, 0x22},
 580	{GC0308_EDGE_MAX, 0xff},
 581	{GC0308_CC_MATRIX_C11, 0x48},
 582	{GC0308_CC_MATRIX_C12, 0x02},
 583	{GC0308_CC_MATRIX_C13, 0x07},
 584	{GC0308_CC_MATRIX_C21, 0xe0},
 585	{GC0308_CC_MATRIX_C22, 0x40},
 586	{GC0308_CC_MATRIX_C23, 0xf0},
 587	{GC0308_SATURATION_CB, 0x40},
 588	{GC0308_SATURATION_CR, 0x40},
 589	{GC0308_LUMA_CONTRAST, 0x40},
 590	{GC0308_SKIN_CB_CENTER, 0xe0},
 591	{GC0308_EDGE_DEC_SA, 0x38},
 592	{GC0308_AUTO_GRAY_MODE, 0x36},
 593	{GC0308_AEC_MODE1, 0xcb},
 594	{GC0308_AEC_MODE2, 0x10},
 595	{GC0308_AEC_MODE3, 0x90},
 596	{GC0308_AEC_TARGET_Y, 0x48},
 597	{GC0308_AEC_HIGH_LOW_RANGE, 0xf2},
 598	{GC0308_AEC_IGNORE, 0x16},
 599	{GC0308_AEC_SLOW_MARGIN, 0x92},
 600	{GC0308_AEC_FAST_MARGIN, 0xa5},
 601	{GC0308_AEC_I_FRAMES, 0x23},
 602	{GC0308_AEC_R_OFFSET, 0x00},
 603	{GC0308_AEC_GB_OFFSET, 0x00},
 604	{GC0308_AEC_I_STOP_L_MARGIN, 0x09},
 605	{GC0308_EXP_MIN_L, 0x04},
 606	{GC0308_MAX_POST_DF_GAIN, 0xa0},
 607	{GC0308_MAX_PRE_DG_GAIN, 0x40},
 608	{GC0308_ABB_MODE, 0x03},
 609	{GC0308_GAMMA_OUT0, 0x10},
 610	{GC0308_GAMMA_OUT1, 0x20},
 611	{GC0308_GAMMA_OUT2, 0x38},
 612	{GC0308_GAMMA_OUT3, 0x4e},
 613	{GC0308_GAMMA_OUT4, 0x63},
 614	{GC0308_GAMMA_OUT5, 0x76},
 615	{GC0308_GAMMA_OUT6, 0x87},
 616	{GC0308_GAMMA_OUT7, 0xa2},
 617	{GC0308_GAMMA_OUT8, 0xb8},
 618	{GC0308_GAMMA_OUT9, 0xca},
 619	{GC0308_GAMMA_OUT10, 0xd8},
 620	{GC0308_GAMMA_OUT11, 0xe3},
 621	{GC0308_GAMMA_OUT12, 0xeb},
 622	{GC0308_GAMMA_OUT13, 0xf0},
 623	{GC0308_GAMMA_OUT14, 0xf8},
 624	{GC0308_GAMMA_OUT15, 0xfd},
 625	{GC0308_GAMMA_OUT16, 0xff},
 626	{GC0308_Y_GAMMA_OUT0, 0x00},
 627	{GC0308_Y_GAMMA_OUT1, 0x10},
 628	{GC0308_Y_GAMMA_OUT2, 0x1c},
 629	{GC0308_Y_GAMMA_OUT3, 0x30},
 630	{GC0308_Y_GAMMA_OUT4, 0x43},
 631	{GC0308_Y_GAMMA_OUT5, 0x54},
 632	{GC0308_Y_GAMMA_OUT6, 0x65},
 633	{GC0308_Y_GAMMA_OUT7, 0x75},
 634	{GC0308_Y_GAMMA_OUT8, 0x93},
 635	{GC0308_Y_GAMMA_OUT9, 0xb0},
 636	{GC0308_Y_GAMMA_OUT10, 0xcb},
 637	{GC0308_Y_GAMMA_OUT11, 0xe6},
 638	{GC0308_Y_GAMMA_OUT12, 0xff},
 639	{GC0308_ABS_RANGE_COMP, 0x02},
 640	{GC0308_ABS_STOP_MARGIN, 0x01},
 641	{GC0308_Y_S_COMP, 0x02},
 642	{GC0308_Y_STRETCH_LIMIT, 0x30},
 643	{GC0308_BIG_WIN_X0, 0x12},
 644	{GC0308_BIG_WIN_Y0, 0x0a},
 645	{GC0308_BIG_WIN_X1, 0x9f},
 646	{GC0308_BIG_WIN_Y1, 0x78},
 647	{GC0308_AWB_RGB_HIGH_LOW, 0xf5},
 648	{GC0308_AWB_Y_TO_C_DIFF2, 0x20},
 649	{GC0308_AWB_C_MAX, 0x10},
 650	{GC0308_AWB_C_INTER, 0x08},
 651	{GC0308_AWB_C_INTER2, 0x20},
 652	{GC0308_AWB_C_MAX_BIG, 0x0a},
 653	{GC0308_AWB_NUMBER_LIMIT, 0xa0},
 654	{GC0308_KWIN_RATIO, 0x60},
 655	{GC0308_KWIN_THD, 0x08},
 656	{GC0308_SMALL_WIN_WIDTH_STEP, 0x44},
 657	{GC0308_SMALL_WIN_HEIGHT_STEP, 0x32},
 658	{GC0308_AWB_YELLOW_TH, 0x41},
 659	{GC0308_AWB_MODE, 0x37},
 660	{GC0308_AWB_ADJUST_SPEED, 0x22},
 661	{GC0308_AWB_EVERY_N, 0x19},
 662	{CCI_REG8(0x114), 0x44}, /* AWB set1 */
 663	{CCI_REG8(0x115), 0x44}, /* AWB set1 */
 664	{CCI_REG8(0x116), 0xc2}, /* AWB set1 */
 665	{CCI_REG8(0x117), 0xa8}, /* AWB set1 */
 666	{CCI_REG8(0x118), 0x18}, /* AWB set1 */
 667	{CCI_REG8(0x119), 0x50}, /* AWB set1 */
 668	{CCI_REG8(0x11a), 0xd8}, /* AWB set1 */
 669	{CCI_REG8(0x11b), 0xf5}, /* AWB set1 */
 670	{CCI_REG8(0x170), 0x40}, /* AWB set2 */
 671	{CCI_REG8(0x171), 0x58}, /* AWB set2 */
 672	{CCI_REG8(0x172), 0x30}, /* AWB set2 */
 673	{CCI_REG8(0x173), 0x48}, /* AWB set2 */
 674	{CCI_REG8(0x174), 0x20}, /* AWB set2 */
 675	{CCI_REG8(0x175), 0x60}, /* AWB set2 */
 676	{CCI_REG8(0x177), 0x20}, /* AWB set2 */
 677	{CCI_REG8(0x178), 0x32}, /* AWB set2 */
 678	{CCI_REG8(0x130), 0x03}, /* undocumented */
 679	{CCI_REG8(0x131), 0x40}, /* undocumented */
 680	{CCI_REG8(0x132), 0x10}, /* undocumented */
 681	{CCI_REG8(0x133), 0xe0}, /* undocumented */
 682	{CCI_REG8(0x134), 0xe0}, /* undocumented */
 683	{CCI_REG8(0x135), 0x00}, /* undocumented */
 684	{CCI_REG8(0x136), 0x80}, /* undocumented */
 685	{CCI_REG8(0x137), 0x00}, /* undocumented */
 686	{CCI_REG8(0x138), 0x04}, /* undocumented */
 687	{CCI_REG8(0x139), 0x09}, /* undocumented */
 688	{CCI_REG8(0x13a), 0x12}, /* undocumented */
 689	{CCI_REG8(0x13b), 0x1c}, /* undocumented */
 690	{CCI_REG8(0x13c), 0x28}, /* undocumented */
 691	{CCI_REG8(0x13d), 0x31}, /* undocumented */
 692	{CCI_REG8(0x13e), 0x44}, /* undocumented */
 693	{CCI_REG8(0x13f), 0x57}, /* undocumented */
 694	{CCI_REG8(0x140), 0x6c}, /* undocumented */
 695	{CCI_REG8(0x141), 0x81}, /* undocumented */
 696	{CCI_REG8(0x142), 0x94}, /* undocumented */
 697	{CCI_REG8(0x143), 0xa7}, /* undocumented */
 698	{CCI_REG8(0x144), 0xb8}, /* undocumented */
 699	{CCI_REG8(0x145), 0xd6}, /* undocumented */
 700	{CCI_REG8(0x146), 0xee}, /* undocumented */
 701	{CCI_REG8(0x147), 0x0d}, /* undocumented */
 702	{CCI_REG8(0x162), 0xf7}, /* undocumented */
 703	{CCI_REG8(0x163), 0x68}, /* undocumented */
 704	{CCI_REG8(0x164), 0xd3}, /* undocumented */
 705	{CCI_REG8(0x165), 0xd3}, /* undocumented */
 706	{CCI_REG8(0x166), 0x60}, /* undocumented */
 707};
 708
 709struct gc0308_colormode {
 710	u8 special_effect;
 711	u8 dbg_mode1;
 712	u8 block_en1;
 713	u8 aec_mode3;
 714	u8 eeintp_mode_2;
 715	u8 edge12_effect;
 716	u8 luma_contrast;
 717	u8 contrast_center;
 718	u8 fixed_cb;
 719	u8 fixed_cr;
 720};
 721
 722#define GC0308_COLOR_FX(reg_special_effect, reg_dbg_mode1, reg_block_en1, \
 723			reg_aec_mode3, reg_eeintp_mode_2, reg_edge12_effect, \
 724			reg_luma_contrast, reg_contrast_center, \
 725			reg_fixed_cb, reg_fixed_cr) \
 726	{ \
 727		.special_effect = reg_special_effect, \
 728		.dbg_mode1 = reg_dbg_mode1, \
 729		.block_en1 = reg_block_en1, \
 730		.aec_mode3 = reg_aec_mode3, \
 731		.eeintp_mode_2 = reg_eeintp_mode_2, \
 732		.edge12_effect = reg_edge12_effect, \
 733		.luma_contrast = reg_luma_contrast, \
 734		.contrast_center = reg_contrast_center, \
 735		.fixed_cb = reg_fixed_cb, \
 736		.fixed_cr = reg_fixed_cr, \
 737	}
 738
 739static const struct gc0308_colormode gc0308_colormodes[] = {
 740	[V4L2_COLORFX_NONE] =
 741		GC0308_COLOR_FX(0x00, 0x0a, 0xff, 0x90, 0x00,
 742				0x54, 0x3c, 0x80, 0x00, 0x00),
 743	[V4L2_COLORFX_BW] =
 744		GC0308_COLOR_FX(0x02, 0x0a, 0xff, 0x90, 0x00,
 745				0x54, 0x40, 0x80, 0x00, 0x00),
 746	[V4L2_COLORFX_SEPIA] =
 747		GC0308_COLOR_FX(0x02, 0x0a, 0xff, 0x90, 0x00,
 748				0x38, 0x40, 0x80, 0xd0, 0x28),
 749	[V4L2_COLORFX_NEGATIVE] =
 750		GC0308_COLOR_FX(0x01, 0x0a, 0xff, 0x90, 0x00,
 751				0x38, 0x40, 0x80, 0x00, 0x00),
 752	[V4L2_COLORFX_EMBOSS] =
 753		GC0308_COLOR_FX(0x02, 0x0a, 0xbf, 0x10, 0x01,
 754				0x38, 0x40, 0x80, 0x00, 0x00),
 755	[V4L2_COLORFX_SKETCH] =
 756		GC0308_COLOR_FX(0x02, 0x0a, 0xff, 0x10, 0x80,
 757				0x38, 0x80, 0x90, 0x00, 0x00),
 758	[V4L2_COLORFX_SKY_BLUE] =
 759		GC0308_COLOR_FX(0x02, 0x0a, 0xff, 0x90, 0x00,
 760				0x38, 0x40, 0x80, 0x50, 0xe0),
 761	[V4L2_COLORFX_GRASS_GREEN] =
 762		GC0308_COLOR_FX(0x02, 0x0a, 0xff, 0x90, 0x01,
 763				0x38, 0x40, 0x80, 0xc0, 0xc0),
 764	[V4L2_COLORFX_SKIN_WHITEN] =
 765		GC0308_COLOR_FX(0x02, 0x0a, 0xbf, 0x10, 0x01,
 766				0x38, 0x60, 0x40, 0x00, 0x00),
 767};
 768
 769static int gc0308_power_on(struct device *dev)
 770{
 771	struct gc0308 *gc0308 = dev_get_drvdata(dev);
 772	int ret;
 773
 774	ret = regulator_enable(gc0308->vdd);
 775	if (ret)
 776		return ret;
 777
 778	ret = clk_prepare_enable(gc0308->clk);
 779	if (ret)
 780		goto clk_fail;
 781
 782	gpiod_set_value_cansleep(gc0308->pwdn_gpio, 0);
 783	usleep_range(10000, 20000);
 784
 785	gpiod_set_value_cansleep(gc0308->reset_gpio, 1);
 786	usleep_range(10000, 20000);
 787	gpiod_set_value_cansleep(gc0308->reset_gpio, 0);
 788	msleep(30);
 789
 790	return 0;
 791
 792clk_fail:
 793	regulator_disable(gc0308->vdd);
 794	return ret;
 795}
 796
 797static int gc0308_power_off(struct device *dev)
 798{
 799	struct gc0308 *gc0308 = dev_get_drvdata(dev);
 800
 801	gpiod_set_value_cansleep(gc0308->pwdn_gpio, 1);
 802	clk_disable_unprepare(gc0308->clk);
 803	regulator_disable(gc0308->vdd);
 804
 805	return 0;
 806}
 807
 808#ifdef CONFIG_VIDEO_ADV_DEBUG
 809static int gc0308_g_register(struct v4l2_subdev *sd,
 810			     struct v4l2_dbg_register *reg)
 811{
 812	struct gc0308 *gc0308 = to_gc0308(sd);
 813
 814	return cci_read(gc0308->regmap, CCI_REG8(reg->reg), &reg->val, NULL);
 815}
 816
 817static int gc0308_s_register(struct v4l2_subdev *sd,
 818			     const struct v4l2_dbg_register *reg)
 819{
 820	struct gc0308 *gc0308 = to_gc0308(sd);
 821
 822	return cci_write(gc0308->regmap, CCI_REG8(reg->reg), reg->val, NULL);
 823}
 824#endif
 825
 826static int gc0308_set_exposure(struct gc0308 *gc0308, enum gc0308_exp_val exp)
 827{
 828	const struct gc0308_exposure *regs = &gc0308_exposure_values[exp];
 829	struct cci_reg_sequence exposure_reg_seq[] = {
 830		{GC0308_LUMA_OFFSET, regs->luma_offset},
 831		{GC0308_AEC_TARGET_Y, regs->aec_target_y},
 832	};
 833
 834	return cci_multi_reg_write(gc0308->regmap, exposure_reg_seq,
 835				   ARRAY_SIZE(exposure_reg_seq), NULL);
 836}
 837
 838static int gc0308_set_awb_mode(struct gc0308 *gc0308,
 839			       enum v4l2_auto_n_preset_white_balance val)
 840{
 841	const struct gc0308_awb_gains *regs = &gc0308_awb_gains[val];
 842	struct cci_reg_sequence awb_reg_seq[] = {
 843		{GC0308_AWB_R_GAIN, regs->r},
 844		{GC0308_AWB_G_GAIN, regs->g},
 845		{GC0308_AWB_B_GAIN, regs->b},
 846	};
 847	int ret;
 848
 849	ret = cci_update_bits(gc0308->regmap, GC0308_AAAA_EN,
 850			      BIT(1), val == V4L2_WHITE_BALANCE_AUTO, NULL);
 851	ret = cci_multi_reg_write(gc0308->regmap, awb_reg_seq,
 852				  ARRAY_SIZE(awb_reg_seq), &ret);
 853
 854	return ret;
 855}
 856
 857static int gc0308_set_colormode(struct gc0308 *gc0308, enum v4l2_colorfx mode)
 858{
 859	const struct gc0308_colormode *regs = &gc0308_colormodes[mode];
 860	struct cci_reg_sequence colormode_reg_seq[] = {
 861		{GC0308_SPECIAL_EFFECT, regs->special_effect},
 862		{GC0308_DEBUG_MODE1, regs->dbg_mode1},
 863		{GC0308_BLOCK_EN1, regs->block_en1},
 864		{GC0308_AEC_MODE3, regs->aec_mode3},
 865		{GC0308_EEINTP_MODE_2, regs->eeintp_mode_2},
 866		{GC0308_EDGE12_EFFECT, regs->edge12_effect},
 867		{GC0308_LUMA_CONTRAST, regs->luma_contrast},
 868		{GC0308_CONTRAST_CENTER, regs->contrast_center},
 869		{GC0308_FIXED_CB, regs->fixed_cb},
 870		{GC0308_FIXED_CR, regs->fixed_cr},
 871	};
 872
 873	return cci_multi_reg_write(gc0308->regmap, colormode_reg_seq,
 874				   ARRAY_SIZE(colormode_reg_seq), NULL);
 875}
 876
 877static int gc0308_set_power_line_freq(struct gc0308 *gc0308, int frequency)
 878{
 879	static const struct cci_reg_sequence pwr_line_50hz[] = {
 880		{GC0308_ANTI_FLICKER_STEP, 0x0078},
 881		{GC0308_EXP_LVL_1, 0x0258},
 882		{GC0308_EXP_LVL_2, 0x0348},
 883		{GC0308_EXP_LVL_3, 0x04b0},
 884		{GC0308_EXP_LVL_4, 0x05a0},
 885	};
 886	static const struct cci_reg_sequence pwr_line_60hz[] = {
 887		{GC0308_ANTI_FLICKER_STEP, 0x0064},
 888		{GC0308_EXP_LVL_1, 0x0258},
 889		{GC0308_EXP_LVL_2, 0x0384},
 890		{GC0308_EXP_LVL_3, 0x04b0},
 891		{GC0308_EXP_LVL_4, 0x05dc},
 892	};
 893
 894	switch (frequency) {
 895	case V4L2_CID_POWER_LINE_FREQUENCY_60HZ:
 896		return cci_multi_reg_write(gc0308->regmap, pwr_line_60hz,
 897					   ARRAY_SIZE(pwr_line_60hz), NULL);
 898	case V4L2_CID_POWER_LINE_FREQUENCY_50HZ:
 899		return cci_multi_reg_write(gc0308->regmap, pwr_line_50hz,
 900					   ARRAY_SIZE(pwr_line_50hz), NULL);
 901	}
 902
 903	return -EINVAL;
 904}
 905
 906static int gc0308_update_mirror(struct gc0308 *gc0308)
 907{
 908	u8 regval = 0x00;
 909
 910	if (gc0308->vflip->val)
 911		regval |= BIT(1);
 912
 913	if (gc0308->hflip->val)
 914		regval |= BIT(0);
 915
 916	return cci_update_bits(gc0308->regmap, GC0308_CISCTL_MODE1,
 917			       GENMASK(1, 0), regval, NULL);
 918}
 919
 920static int gc0308_update_blanking(struct gc0308 *gc0308)
 921{
 922	u16 vblank = gc0308->vblank->val;
 923	u16 hblank = gc0308->hblank->val;
 924	u8 vbhb = ((vblank >> 4) & 0xf0) | ((hblank >> 8) & 0x0f);
 925	int ret = 0;
 926
 927	cci_write(gc0308->regmap, GC0308_VB_HB, vbhb, &ret);
 928	cci_write(gc0308->regmap, GC0308_HBLANK, hblank & 0xff, &ret);
 929	cci_write(gc0308->regmap, GC0308_VBLANK, vblank & 0xff, &ret);
 930
 931	return ret;
 932}
 933
 934static int _gc0308_s_ctrl(struct v4l2_ctrl *ctrl)
 935{
 936	struct gc0308 *gc0308 = container_of(ctrl->handler, struct gc0308, hdl);
 937	u8 flipval = ctrl->val ? 0xff : 0x00;
 938
 939	switch (ctrl->id) {
 940	case V4L2_CID_HBLANK:
 941	case V4L2_CID_VBLANK:
 942		return gc0308_update_blanking(gc0308);
 943	case V4L2_CID_VFLIP:
 944	case V4L2_CID_HFLIP:
 945		return gc0308_update_mirror(gc0308);
 946	case V4L2_CID_AUTO_WHITE_BALANCE:
 947		return cci_update_bits(gc0308->regmap, GC0308_AAAA_EN,
 948				       BIT(1), flipval, NULL);
 949	case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
 950		return gc0308_set_awb_mode(gc0308, ctrl->val);
 951	case V4L2_CID_POWER_LINE_FREQUENCY:
 952		return gc0308_set_power_line_freq(gc0308, ctrl->val);
 953	case V4L2_CID_COLORFX:
 954		return gc0308_set_colormode(gc0308, ctrl->val);
 955	case V4L2_CID_TEST_PATTERN:
 956		return cci_update_bits(gc0308->regmap, GC0308_DEBUG_MODE2,
 957				       GENMASK(1, 0), ctrl->val, NULL);
 958	case V4L2_CID_AUTO_EXPOSURE_BIAS:
 959		return gc0308_set_exposure(gc0308, ctrl->val);
 960	}
 961
 962	return -EINVAL;
 963}
 964
 965static int gc0308_s_ctrl(struct v4l2_ctrl *ctrl)
 966{
 967	struct gc0308 *gc0308 = container_of(ctrl->handler, struct gc0308, hdl);
 968	int ret;
 969
 970	if (!pm_runtime_get_if_in_use(gc0308->dev))
 971		return 0;
 972
 973	ret = _gc0308_s_ctrl(ctrl);
 974	if (ret)
 975		dev_err(gc0308->dev, "failed to set control: %d\n", ret);
 976
 977	pm_runtime_put_autosuspend(gc0308->dev);
 978
 979	return ret;
 980}
 981
 982static const struct v4l2_ctrl_ops gc0308_ctrl_ops = {
 983	.s_ctrl = gc0308_s_ctrl,
 984};
 985
 986static const struct v4l2_subdev_core_ops gc0308_core_ops = {
 987	.log_status = v4l2_ctrl_subdev_log_status,
 988#ifdef CONFIG_VIDEO_ADV_DEBUG
 989	.g_register	= gc0308_g_register,
 990	.s_register	= gc0308_s_register,
 991#endif
 992};
 993
 994static int gc0308_enum_mbus_code(struct v4l2_subdev *sd,
 995				 struct v4l2_subdev_state *sd_state,
 996				 struct v4l2_subdev_mbus_code_enum *code)
 997{
 998	if (code->index >= ARRAY_SIZE(gc0308_formats))
 999		return -EINVAL;
1000
1001	code->code = gc0308_formats[code->index].code;
1002
1003	return 0;
1004}
1005
1006static int gc0308_get_format_idx(u32 code)
1007{
1008	int i;
1009
1010	for (i = 0; i < ARRAY_SIZE(gc0308_formats); i++) {
1011		if (gc0308_formats[i].code == code)
1012			return i;
1013	}
1014
1015	return -1;
1016}
1017
1018static int gc0308_enum_frame_size(struct v4l2_subdev *subdev,
1019				  struct v4l2_subdev_state *sd_state,
1020				  struct v4l2_subdev_frame_size_enum *fse)
1021{
1022	if (fse->index >= ARRAY_SIZE(gc0308_frame_sizes))
1023		return -EINVAL;
1024
1025	if (gc0308_get_format_idx(fse->code) < 0)
1026		return -EINVAL;
1027
1028	fse->min_width = gc0308_frame_sizes[fse->index].width;
1029	fse->max_width = gc0308_frame_sizes[fse->index].width;
1030	fse->min_height = gc0308_frame_sizes[fse->index].height;
1031	fse->max_height = gc0308_frame_sizes[fse->index].height;
1032
1033	return 0;
1034}
1035
1036static void gc0308_update_pad_format(const struct gc0308_frame_size *mode,
1037				     struct v4l2_mbus_framefmt *fmt, u32 code)
1038{
1039	fmt->width = mode->width;
1040	fmt->height = mode->height;
1041	fmt->code = code;
1042	fmt->field = V4L2_FIELD_NONE;
1043	fmt->colorspace = V4L2_COLORSPACE_SRGB;
1044}
1045
1046static int gc0308_set_format(struct v4l2_subdev *sd,
1047			     struct v4l2_subdev_state *sd_state,
1048			     struct v4l2_subdev_format *fmt)
1049{
1050	struct gc0308 *gc0308 = to_gc0308(sd);
1051	const struct gc0308_frame_size *mode;
1052	int i = gc0308_get_format_idx(fmt->format.code);
1053
1054	if (i < 0)
1055		i = 0;
1056
1057	mode = v4l2_find_nearest_size(gc0308_frame_sizes,
1058				      ARRAY_SIZE(gc0308_frame_sizes), width,
1059				      height, fmt->format.width,
1060				      fmt->format.height);
1061
1062	gc0308_update_pad_format(mode, &fmt->format, gc0308_formats[i].code);
1063	*v4l2_subdev_state_get_format(sd_state, 0) = fmt->format;
1064
1065	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
1066		return 0;
1067
1068	gc0308->mode.out_format = gc0308_formats[i].regval;
1069	gc0308->mode.subsample = mode->subsample;
1070	gc0308->mode.width = mode->width;
1071	gc0308->mode.height = mode->height;
1072
1073	return 0;
1074}
1075
1076static int gc0308_init_state(struct v4l2_subdev *sd,
1077			     struct v4l2_subdev_state *sd_state)
1078{
1079	struct v4l2_mbus_framefmt *format =
1080		v4l2_subdev_state_get_format(sd_state, 0);
1081
1082	format->width		= 640;
1083	format->height		= 480;
1084	format->code		= gc0308_formats[0].code;
1085	format->colorspace	= V4L2_COLORSPACE_SRGB;
1086	format->field		= V4L2_FIELD_NONE;
1087	format->ycbcr_enc	= V4L2_YCBCR_ENC_DEFAULT;
1088	format->quantization	= V4L2_QUANTIZATION_DEFAULT;
1089	format->xfer_func	= V4L2_XFER_FUNC_DEFAULT;
1090
1091	return 0;
1092}
1093
1094static const struct v4l2_subdev_pad_ops gc0308_pad_ops = {
1095	.enum_mbus_code = gc0308_enum_mbus_code,
1096	.enum_frame_size = gc0308_enum_frame_size,
1097	.get_fmt = v4l2_subdev_get_fmt,
1098	.set_fmt = gc0308_set_format,
1099};
1100
1101static int gc0308_set_resolution(struct gc0308 *gc0308, int *ret)
1102{
1103	struct cci_reg_sequence resolution_regs[] = {
1104		{GC0308_SUBSAMPLE, gc0308->mode.subsample},
1105		{GC0308_SUBMODE, 0x03},
1106		{GC0308_SUB_ROW_N1, 0x00},
1107		{GC0308_SUB_ROW_N2, 0x00},
1108		{GC0308_SUB_COL_N1, 0x00},
1109		{GC0308_SUB_COL_N2, 0x00},
1110		{GC0308_CROP_WIN_MODE, 0x80},
1111		{GC0308_CROP_WIN_Y1, 0x00},
1112		{GC0308_CROP_WIN_X1, 0x00},
1113		{GC0308_CROP_WIN_HEIGHT, gc0308->mode.height},
1114		{GC0308_CROP_WIN_WIDTH, gc0308->mode.width},
1115	};
1116
1117	return cci_multi_reg_write(gc0308->regmap, resolution_regs,
1118				   ARRAY_SIZE(resolution_regs), ret);
1119}
1120
1121static int gc0308_start_stream(struct gc0308 *gc0308)
1122{
1123	int ret, sync_mode;
1124
1125	ret = pm_runtime_resume_and_get(gc0308->dev);
1126	if (ret < 0)
1127		return ret;
1128
1129	cci_multi_reg_write(gc0308->regmap, sensor_default_regs,
1130			    ARRAY_SIZE(sensor_default_regs), &ret);
1131	cci_update_bits(gc0308->regmap, GC0308_OUT_FORMAT,
1132			GENMASK(4, 0), gc0308->mode.out_format, &ret);
1133	gc0308_set_resolution(gc0308, &ret);
1134
1135	if (ret) {
1136		dev_err(gc0308->dev, "failed to update registers: %d\n", ret);
1137		goto disable_pm;
1138	}
1139
1140	ret = __v4l2_ctrl_handler_setup(&gc0308->hdl);
1141	if (ret) {
1142		dev_err(gc0308->dev, "failed to setup controls\n");
1143		goto disable_pm;
1144	}
1145
1146	/* HSYNC/VSYNC polarity */
1147	sync_mode = 0x3;
1148	if (gc0308->mbus_config & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1149		sync_mode &= ~BIT(0);
1150	if (gc0308->mbus_config & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1151		sync_mode &= ~BIT(1);
1152	ret = cci_write(gc0308->regmap, GC0308_SYNC_MODE, sync_mode, NULL);
1153	if (ret)
1154		goto disable_pm;
1155
1156	return 0;
1157
1158disable_pm:
1159	pm_runtime_put_autosuspend(gc0308->dev);
1160	return ret;
1161}
1162
1163static int gc0308_stop_stream(struct gc0308 *gc0308)
1164{
1165	pm_runtime_put_autosuspend(gc0308->dev);
1166	return 0;
1167}
1168
1169static int gc0308_s_stream(struct v4l2_subdev *sd, int enable)
1170{
1171	struct gc0308 *gc0308 = to_gc0308(sd);
1172	struct v4l2_subdev_state *sd_state;
1173	int ret;
1174
1175	sd_state = v4l2_subdev_lock_and_get_active_state(sd);
1176
1177	if (enable)
1178		ret = gc0308_start_stream(gc0308);
1179	else
1180		ret = gc0308_stop_stream(gc0308);
1181
1182	v4l2_subdev_unlock_state(sd_state);
1183	return ret;
1184}
1185
1186static const struct v4l2_subdev_video_ops gc0308_video_ops = {
1187	.s_stream		= gc0308_s_stream,
1188};
1189
1190static const struct v4l2_subdev_ops gc0308_subdev_ops = {
1191	.core	= &gc0308_core_ops,
1192	.pad	= &gc0308_pad_ops,
1193	.video	= &gc0308_video_ops,
1194};
1195
1196static const struct v4l2_subdev_internal_ops gc0308_internal_ops = {
1197	.init_state = gc0308_init_state,
1198};
1199
1200static int gc0308_bus_config(struct gc0308 *gc0308)
1201{
1202	struct device *dev = gc0308->dev;
1203	struct v4l2_fwnode_endpoint bus_cfg = {
1204		.bus_type = V4L2_MBUS_PARALLEL
1205	};
1206	struct fwnode_handle *ep;
1207	int ret;
1208
1209	ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0, 0);
1210	if (!ep)
1211		return -EINVAL;
1212
1213	ret = v4l2_fwnode_endpoint_parse(ep, &bus_cfg);
1214	fwnode_handle_put(ep);
1215	if (ret)
1216		return ret;
1217
1218	gc0308->mbus_config = bus_cfg.bus.parallel.flags;
1219
1220	return 0;
1221}
1222
1223static const char * const gc0308_test_pattern_menu[] = {
1224	"Disabled",
1225	"Test Image 1",
1226	"Test Image 2",
1227};
1228
1229static int gc0308_init_controls(struct gc0308 *gc0308)
1230{
1231	int ret;
1232
1233	v4l2_ctrl_handler_init(&gc0308->hdl, 11);
1234	gc0308->hblank = v4l2_ctrl_new_std(&gc0308->hdl, &gc0308_ctrl_ops,
1235					   V4L2_CID_HBLANK, GC0308_HBLANK_MIN,
1236					   GC0308_HBLANK_MAX, 1,
1237					   GC0308_HBLANK_DEF);
1238	gc0308->vblank = v4l2_ctrl_new_std(&gc0308->hdl, &gc0308_ctrl_ops,
1239					   V4L2_CID_VBLANK, GC0308_VBLANK_MIN,
1240					   GC0308_VBLANK_MAX, 1,
1241					   GC0308_VBLANK_DEF);
1242	gc0308->hflip = v4l2_ctrl_new_std(&gc0308->hdl, &gc0308_ctrl_ops,
1243					  V4L2_CID_HFLIP, 0, 1, 1, 0);
1244	gc0308->vflip = v4l2_ctrl_new_std(&gc0308->hdl, &gc0308_ctrl_ops,
1245					  V4L2_CID_VFLIP, 0, 1, 1, 0);
1246	v4l2_ctrl_new_std(&gc0308->hdl, &gc0308_ctrl_ops, V4L2_CID_PIXEL_RATE,
1247			  GC0308_PIXEL_RATE, GC0308_PIXEL_RATE, 1,
1248			  GC0308_PIXEL_RATE);
1249	v4l2_ctrl_new_std(&gc0308->hdl, &gc0308_ctrl_ops,
1250			  V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1251	v4l2_ctrl_new_std_menu_items(&gc0308->hdl, &gc0308_ctrl_ops,
1252				     V4L2_CID_TEST_PATTERN,
1253				     ARRAY_SIZE(gc0308_test_pattern_menu) - 1,
1254				     0, 0, gc0308_test_pattern_menu);
1255	v4l2_ctrl_new_std_menu(&gc0308->hdl, &gc0308_ctrl_ops,
1256			       V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,
1257			       8, ~0x14e, V4L2_WHITE_BALANCE_AUTO);
1258	v4l2_ctrl_new_std_menu(&gc0308->hdl, &gc0308_ctrl_ops,
1259			       V4L2_CID_COLORFX, 8, 0, V4L2_COLORFX_NONE);
1260	v4l2_ctrl_new_std_menu(&gc0308->hdl, &gc0308_ctrl_ops,
1261			       V4L2_CID_POWER_LINE_FREQUENCY,
1262			       V4L2_CID_POWER_LINE_FREQUENCY_60HZ,
1263			       ~0x6, V4L2_CID_POWER_LINE_FREQUENCY_50HZ);
1264	v4l2_ctrl_new_int_menu(&gc0308->hdl, &gc0308_ctrl_ops,
1265			       V4L2_CID_AUTO_EXPOSURE_BIAS,
1266			       ARRAY_SIZE(gc0308_exposure_menu) - 1,
1267			       ARRAY_SIZE(gc0308_exposure_menu) / 2,
1268			       gc0308_exposure_menu);
1269
1270	gc0308->sd.ctrl_handler = &gc0308->hdl;
1271	if (gc0308->hdl.error) {
1272		ret = gc0308->hdl.error;
1273		v4l2_ctrl_handler_free(&gc0308->hdl);
1274		return ret;
1275	}
1276
1277	v4l2_ctrl_cluster(2, &gc0308->hflip);
1278	v4l2_ctrl_cluster(2, &gc0308->hblank);
1279
1280	return 0;
1281}
1282
1283static int gc0308_probe(struct i2c_client *client)
1284{
1285	struct device *dev = &client->dev;
1286	struct gc0308 *gc0308;
1287	unsigned long clkrate;
1288	u64 regval;
1289	int ret;
1290
1291	gc0308 = devm_kzalloc(dev, sizeof(*gc0308), GFP_KERNEL);
1292	if (!gc0308)
1293		return -ENOMEM;
1294
1295	gc0308->dev = dev;
1296	dev_set_drvdata(dev, gc0308);
1297
1298	ret = gc0308_bus_config(gc0308);
1299	if (ret)
1300		return dev_err_probe(dev, ret, "failed to get bus config\n");
1301
1302	gc0308->clk = devm_clk_get_optional(dev, NULL);
1303	if (IS_ERR(gc0308->clk))
1304		return dev_err_probe(dev, PTR_ERR(gc0308->clk),
1305				     "could not get clk\n");
1306
1307	gc0308->vdd = devm_regulator_get(dev, "vdd28");
1308	if (IS_ERR(gc0308->vdd))
1309		return dev_err_probe(dev, PTR_ERR(gc0308->vdd),
1310				     "failed to get vdd28 regulator\n");
1311
1312	gc0308->pwdn_gpio = devm_gpiod_get(dev, "powerdown", GPIOD_OUT_LOW);
1313	if (IS_ERR(gc0308->pwdn_gpio))
1314		return dev_err_probe(dev, PTR_ERR(gc0308->pwdn_gpio),
1315				     "failed to get powerdown gpio\n");
1316
1317	gc0308->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1318	if (IS_ERR(gc0308->reset_gpio))
1319		return dev_err_probe(dev, PTR_ERR(gc0308->reset_gpio),
1320				     "failed to get reset gpio\n");
1321
1322	/*
1323	 * This is not using devm_cci_regmap_init_i2c(), because the driver
1324	 * makes use of regmap's pagination feature. The chosen settings are
1325	 * compatible with the CCI helpers.
1326	 */
1327	gc0308->regmap = devm_regmap_init_i2c(client, &gc0308_regmap_config);
1328	if (IS_ERR(gc0308->regmap))
1329		return dev_err_probe(dev, PTR_ERR(gc0308->regmap),
1330				     "failed to init regmap\n");
1331
1332	v4l2_i2c_subdev_init(&gc0308->sd, client, &gc0308_subdev_ops);
1333	gc0308->sd.internal_ops = &gc0308_internal_ops;
1334	gc0308->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1335
1336	ret = gc0308_init_controls(gc0308);
1337	if (ret)
1338		return dev_err_probe(dev, ret, "failed to init controls\n");
1339
1340	gc0308->sd.state_lock = gc0308->hdl.lock;
1341	gc0308->pad.flags = MEDIA_PAD_FL_SOURCE;
1342	gc0308->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1343	ret = media_entity_pads_init(&gc0308->sd.entity, 1, &gc0308->pad);
1344	if (ret < 0)
1345		goto fail_ctrl_hdl_cleanup;
1346
1347	ret = v4l2_subdev_init_finalize(&gc0308->sd);
1348	if (ret)
1349		goto fail_media_entity_cleanup;
1350
1351	ret = gc0308_power_on(dev);
1352	if (ret)
1353		goto fail_subdev_cleanup;
1354
1355	if (gc0308->clk) {
1356		clkrate = clk_get_rate(gc0308->clk);
1357		if (clkrate != 24000000)
1358			dev_warn(dev, "unexpected clock rate: %lu\n", clkrate);
1359	}
1360
1361	ret = cci_read(gc0308->regmap, GC0308_CHIP_ID, &regval, NULL);
1362	if (ret < 0) {
1363		dev_err_probe(dev, ret, "failed to read chip ID\n");
1364		goto fail_power_off;
1365	}
1366
1367	if (regval != 0x9b) {
1368		ret = -EINVAL;
1369		dev_err_probe(dev, ret, "invalid chip ID (%02llx)\n", regval);
1370		goto fail_power_off;
1371	}
1372
1373	/*
1374	 * Enable runtime PM with autosuspend. As the device has been powered
1375	 * manually, mark it as active, and increase the usage count without
1376	 * resuming the device.
1377	 */
1378	pm_runtime_set_active(dev);
1379	pm_runtime_get_noresume(dev);
1380	pm_runtime_enable(dev);
1381	pm_runtime_set_autosuspend_delay(dev, 1000);
1382	pm_runtime_use_autosuspend(dev);
1383
1384	ret = v4l2_async_register_subdev(&gc0308->sd);
1385	if (ret) {
1386		dev_err_probe(dev, ret, "failed to register v4l subdev\n");
1387		goto fail_rpm;
1388	}
1389
1390	return 0;
1391
1392fail_rpm:
1393	pm_runtime_disable(dev);
1394	pm_runtime_put_noidle(dev);
1395fail_power_off:
1396	gc0308_power_off(dev);
1397fail_subdev_cleanup:
1398	v4l2_subdev_cleanup(&gc0308->sd);
1399fail_media_entity_cleanup:
1400	media_entity_cleanup(&gc0308->sd.entity);
1401fail_ctrl_hdl_cleanup:
1402	v4l2_ctrl_handler_free(&gc0308->hdl);
1403	return ret;
1404}
1405
1406static void gc0308_remove(struct i2c_client *client)
1407{
1408	struct gc0308 *gc0308 = i2c_get_clientdata(client);
1409	struct device *dev = &client->dev;
1410
1411	v4l2_async_unregister_subdev(&gc0308->sd);
1412	v4l2_ctrl_handler_free(&gc0308->hdl);
1413	media_entity_cleanup(&gc0308->sd.entity);
1414
1415	pm_runtime_disable(dev);
1416	if (!pm_runtime_status_suspended(dev))
1417		gc0308_power_off(dev);
1418	pm_runtime_set_suspended(dev);
1419}
1420
1421static const struct dev_pm_ops gc0308_pm_ops = {
1422	SET_RUNTIME_PM_OPS(gc0308_power_off, gc0308_power_on, NULL)
1423};
1424
1425static const struct of_device_id gc0308_of_match[] = {
1426	{ .compatible = "galaxycore,gc0308" },
1427	{ /* sentinel */ }
1428};
1429MODULE_DEVICE_TABLE(of, gc0308_of_match);
1430
1431static struct i2c_driver gc0308_i2c_driver = {
1432	.driver = {
1433		.name  = "gc0308",
1434		.pm = &gc0308_pm_ops,
1435		.of_match_table = gc0308_of_match,
1436	},
1437	.probe  = gc0308_probe,
1438	.remove = gc0308_remove,
1439};
1440module_i2c_driver(gc0308_i2c_driver);
1441
1442MODULE_DESCRIPTION("GalaxyCore GC0308 Camera Driver");
1443MODULE_AUTHOR("Sebastian Reichel <sre@kernel.org>");
1444MODULE_LICENSE("GPL");