et8ek8_mode.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * et8ek8_mode.c
  4 *
  5 * Copyright (C) 2008 Nokia Corporation
  6 *
  7 * Contact: Sakari Ailus <sakari.ailus@iki.fi>
  8 *          Tuukka Toivonen <tuukkat76@gmail.com>
  9 */
 10
 11#include "et8ek8_reg.h"
 12
 13/*
 14 * Stingray sensor mode settings for Scooby
 15 */
 16
 17/* Mode1_poweron_Mode2_16VGA_2592x1968_12.07fps */
 18static struct et8ek8_reglist mode1_poweron_mode2_16vga_2592x1968_12_07fps = {
 19/* (without the +1)
 20 * SPCK       = 80 MHz
 21 * CCP2       = 640 MHz
 22 * VCO        = 640 MHz
 23 * VCOUNT     = 84 (2016)
 24 * HCOUNT     = 137 (3288)
 25 * CKREF_DIV  = 2
 26 * CKVAR_DIV  = 200
 27 * VCO_DIV    = 0
 28 * SPCK_DIV   = 7
 29 * MRCK_DIV   = 7
 30 * LVDSCK_DIV = 0
 31 */
 32	.type = ET8EK8_REGLIST_POWERON,
 33	.mode = {
 34		.sensor_width = 2592,
 35		.sensor_height = 1968,
 36		.sensor_window_origin_x = 0,
 37		.sensor_window_origin_y = 0,
 38		.sensor_window_width = 2592,
 39		.sensor_window_height = 1968,
 40		.width = 3288,
 41		.height = 2016,
 42		.window_origin_x = 0,
 43		.window_origin_y = 0,
 44		.window_width = 2592,
 45		.window_height = 1968,
 46		.pixel_clock = 80000000,
 47		.timeperframe = {
 48			.numerator = 100,
 49			.denominator = 1207
 50		},
 51		.max_exp = 2012,
 52		/* .max_gain = 0, */
 53		.bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
 54		.sensitivity = 65536
 55	},
 56	.regs = {
 57		/* Need to set firstly */
 58		{ ET8EK8_REG_8BIT, 0x126C, 0xCC },
 59		/* Strobe and Data of CCP2 delay are minimized. */
 60		{ ET8EK8_REG_8BIT, 0x1269, 0x00 },
 61		/* Refined value of Min H_COUNT  */
 62		{ ET8EK8_REG_8BIT, 0x1220, 0x89 },
 63		/* Frequency of SPCK setting (SPCK=MRCK) */
 64		{ ET8EK8_REG_8BIT, 0x123A, 0x07 },
 65		{ ET8EK8_REG_8BIT, 0x1241, 0x94 },
 66		{ ET8EK8_REG_8BIT, 0x1242, 0x02 },
 67		{ ET8EK8_REG_8BIT, 0x124B, 0x00 },
 68		{ ET8EK8_REG_8BIT, 0x1255, 0xFF },
 69		{ ET8EK8_REG_8BIT, 0x1256, 0x9F },
 70		{ ET8EK8_REG_8BIT, 0x1258, 0x00 },
 71		/* From parallel out to serial out */
 72		{ ET8EK8_REG_8BIT, 0x125D, 0x88 },
 73		/* From w/ embedded data to w/o embedded data */
 74		{ ET8EK8_REG_8BIT, 0x125E, 0xC0 },
 75		/* CCP2 out is from STOP to ACTIVE */
 76		{ ET8EK8_REG_8BIT, 0x1263, 0x98 },
 77		{ ET8EK8_REG_8BIT, 0x1268, 0xC6 },
 78		{ ET8EK8_REG_8BIT, 0x1434, 0x00 },
 79		{ ET8EK8_REG_8BIT, 0x1163, 0x44 },
 80		{ ET8EK8_REG_8BIT, 0x1166, 0x29 },
 81		{ ET8EK8_REG_8BIT, 0x1140, 0x02 },
 82		{ ET8EK8_REG_8BIT, 0x1011, 0x24 },
 83		{ ET8EK8_REG_8BIT, 0x1151, 0x80 },
 84		{ ET8EK8_REG_8BIT, 0x1152, 0x23 },
 85		/* Initial setting for improvement2 of lower frequency noise */
 86		{ ET8EK8_REG_8BIT, 0x1014, 0x05 },
 87		{ ET8EK8_REG_8BIT, 0x1033, 0x06 },
 88		{ ET8EK8_REG_8BIT, 0x1034, 0x79 },
 89		{ ET8EK8_REG_8BIT, 0x1423, 0x3F },
 90		{ ET8EK8_REG_8BIT, 0x1424, 0x3F },
 91		{ ET8EK8_REG_8BIT, 0x1426, 0x00 },
 92		/* Switch of Preset-White-balance (0d:disable / 1d:enable) */
 93		{ ET8EK8_REG_8BIT, 0x1439, 0x00 },
 94		/* Switch of blemish correction (0d:disable / 1d:enable) */
 95		{ ET8EK8_REG_8BIT, 0x161F, 0x60 },
 96		/* Switch of auto noise correction (0d:disable / 1d:enable) */
 97		{ ET8EK8_REG_8BIT, 0x1634, 0x00 },
 98		{ ET8EK8_REG_8BIT, 0x1646, 0x00 },
 99		{ ET8EK8_REG_8BIT, 0x1648, 0x00 },
100		{ ET8EK8_REG_8BIT, 0x113E, 0x01 },
101		{ ET8EK8_REG_8BIT, 0x113F, 0x22 },
102		{ ET8EK8_REG_8BIT, 0x1239, 0x64 },
103		{ ET8EK8_REG_8BIT, 0x1238, 0x02 },
104		{ ET8EK8_REG_8BIT, 0x123B, 0x70 },
105		{ ET8EK8_REG_8BIT, 0x123A, 0x07 },
106		{ ET8EK8_REG_8BIT, 0x121B, 0x64 },
107		{ ET8EK8_REG_8BIT, 0x121D, 0x64 },
108		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
109		{ ET8EK8_REG_8BIT, 0x1220, 0x89 },
110		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
111		{ ET8EK8_REG_8BIT, 0x1222, 0x54 },
112		{ ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/  */
113		{ ET8EK8_REG_TERM, 0, 0}
114	}
115};
116
117/* Mode1_16VGA_2592x1968_13.12fps_DPCM10-8 */
118static struct et8ek8_reglist mode1_16vga_2592x1968_13_12fps_dpcm10_8 = {
119/* (without the +1)
120 * SPCK       = 80 MHz
121 * CCP2       = 560 MHz
122 * VCO        = 560 MHz
123 * VCOUNT     = 84 (2016)
124 * HCOUNT     = 128 (3072)
125 * CKREF_DIV  = 2
126 * CKVAR_DIV  = 175
127 * VCO_DIV    = 0
128 * SPCK_DIV   = 6
129 * MRCK_DIV   = 7
130 * LVDSCK_DIV = 0
131 */
132	.type = ET8EK8_REGLIST_MODE,
133	.mode = {
134		.sensor_width = 2592,
135		.sensor_height = 1968,
136		.sensor_window_origin_x = 0,
137		.sensor_window_origin_y = 0,
138		.sensor_window_width = 2592,
139		.sensor_window_height = 1968,
140		.width = 3072,
141		.height = 2016,
142		.window_origin_x = 0,
143		.window_origin_y = 0,
144		.window_width = 2592,
145		.window_height = 1968,
146		.pixel_clock = 80000000,
147		.timeperframe = {
148			.numerator = 100,
149			.denominator = 1292
150		},
151		.max_exp = 2012,
152		/* .max_gain = 0, */
153		.bus_format = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
154		.sensitivity = 65536
155	},
156	.regs = {
157		{ ET8EK8_REG_8BIT, 0x1239, 0x57 },
158		{ ET8EK8_REG_8BIT, 0x1238, 0x82 },
159		{ ET8EK8_REG_8BIT, 0x123B, 0x70 },
160		{ ET8EK8_REG_8BIT, 0x123A, 0x06 },
161		{ ET8EK8_REG_8BIT, 0x121B, 0x64 },
162		{ ET8EK8_REG_8BIT, 0x121D, 0x64 },
163		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
164		{ ET8EK8_REG_8BIT, 0x1220, 0x80 }, /* <-changed to v14 7E->80 */
165		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
166		{ ET8EK8_REG_8BIT, 0x1222, 0x54 },
167		{ ET8EK8_REG_8BIT, 0x125D, 0x83 }, /* CCP_LVDS_MODE/  */
168		{ ET8EK8_REG_TERM, 0, 0}
169	}
170};
171
172/* Mode3_4VGA_1296x984_29.99fps_DPCM10-8 */
173static struct et8ek8_reglist mode3_4vga_1296x984_29_99fps_dpcm10_8 = {
174/* (without the +1)
175 * SPCK       = 96.5333333333333 MHz
176 * CCP2       = 579.2 MHz
177 * VCO        = 579.2 MHz
178 * VCOUNT     = 84 (2016)
179 * HCOUNT     = 133 (3192)
180 * CKREF_DIV  = 2
181 * CKVAR_DIV  = 181
182 * VCO_DIV    = 0
183 * SPCK_DIV   = 5
184 * MRCK_DIV   = 7
185 * LVDSCK_DIV = 0
186 */
187	.type = ET8EK8_REGLIST_MODE,
188	.mode = {
189		.sensor_width = 2592,
190		.sensor_height = 1968,
191		.sensor_window_origin_x = 0,
192		.sensor_window_origin_y = 0,
193		.sensor_window_width = 2592,
194		.sensor_window_height = 1968,
195		.width = 3192,
196		.height = 1008,
197		.window_origin_x = 0,
198		.window_origin_y = 0,
199		.window_width = 1296,
200		.window_height = 984,
201		.pixel_clock = 96533333,
202		.timeperframe = {
203			.numerator = 100,
204			.denominator = 3000
205		},
206		.max_exp = 1004,
207		/* .max_gain = 0, */
208		.bus_format = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
209		.sensitivity = 65536
210	},
211	.regs = {
212		{ ET8EK8_REG_8BIT, 0x1239, 0x5A },
213		{ ET8EK8_REG_8BIT, 0x1238, 0x82 },
214		{ ET8EK8_REG_8BIT, 0x123B, 0x70 },
215		{ ET8EK8_REG_8BIT, 0x123A, 0x05 },
216		{ ET8EK8_REG_8BIT, 0x121B, 0x63 },
217		{ ET8EK8_REG_8BIT, 0x1220, 0x85 },
218		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
219		{ ET8EK8_REG_8BIT, 0x1222, 0x54 },
220		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
221		{ ET8EK8_REG_8BIT, 0x121D, 0x63 },
222		{ ET8EK8_REG_8BIT, 0x125D, 0x83 }, /* CCP_LVDS_MODE/  */
223		{ ET8EK8_REG_TERM, 0, 0}
224	}
225};
226
227/* Mode4_SVGA_864x656_29.88fps */
228static struct et8ek8_reglist mode4_svga_864x656_29_88fps = {
229/* (without the +1)
230 * SPCK       = 80 MHz
231 * CCP2       = 320 MHz
232 * VCO        = 640 MHz
233 * VCOUNT     = 84 (2016)
234 * HCOUNT     = 166 (3984)
235 * CKREF_DIV  = 2
236 * CKVAR_DIV  = 200
237 * VCO_DIV    = 0
238 * SPCK_DIV   = 7
239 * MRCK_DIV   = 7
240 * LVDSCK_DIV = 1
241 */
242	.type = ET8EK8_REGLIST_MODE,
243	.mode = {
244		.sensor_width = 2592,
245		.sensor_height = 1968,
246		.sensor_window_origin_x = 0,
247		.sensor_window_origin_y = 0,
248		.sensor_window_width = 2592,
249		.sensor_window_height = 1968,
250		.width = 3984,
251		.height = 672,
252		.window_origin_x = 0,
253		.window_origin_y = 0,
254		.window_width = 864,
255		.window_height = 656,
256		.pixel_clock = 80000000,
257		.timeperframe = {
258			.numerator = 100,
259			.denominator = 2988
260		},
261		.max_exp = 668,
262		/* .max_gain = 0, */
263		.bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
264		.sensitivity = 65536
265	},
266	.regs = {
267		{ ET8EK8_REG_8BIT, 0x1239, 0x64 },
268		{ ET8EK8_REG_8BIT, 0x1238, 0x02 },
269		{ ET8EK8_REG_8BIT, 0x123B, 0x71 },
270		{ ET8EK8_REG_8BIT, 0x123A, 0x07 },
271		{ ET8EK8_REG_8BIT, 0x121B, 0x62 },
272		{ ET8EK8_REG_8BIT, 0x121D, 0x62 },
273		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
274		{ ET8EK8_REG_8BIT, 0x1220, 0xA6 },
275		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
276		{ ET8EK8_REG_8BIT, 0x1222, 0x54 },
277		{ ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/  */
278		{ ET8EK8_REG_TERM, 0, 0}
279	}
280};
281
282/* Mode5_VGA_648x492_29.93fps */
283static struct et8ek8_reglist mode5_vga_648x492_29_93fps = {
284/* (without the +1)
285 * SPCK       = 80 MHz
286 * CCP2       = 320 MHz
287 * VCO        = 640 MHz
288 * VCOUNT     = 84 (2016)
289 * HCOUNT     = 221 (5304)
290 * CKREF_DIV  = 2
291 * CKVAR_DIV  = 200
292 * VCO_DIV    = 0
293 * SPCK_DIV   = 7
294 * MRCK_DIV   = 7
295 * LVDSCK_DIV = 1
296 */
297	.type = ET8EK8_REGLIST_MODE,
298	.mode = {
299		.sensor_width = 2592,
300		.sensor_height = 1968,
301		.sensor_window_origin_x = 0,
302		.sensor_window_origin_y = 0,
303		.sensor_window_width = 2592,
304		.sensor_window_height = 1968,
305		.width = 5304,
306		.height = 504,
307		.window_origin_x = 0,
308		.window_origin_y = 0,
309		.window_width = 648,
310		.window_height = 492,
311		.pixel_clock = 80000000,
312		.timeperframe = {
313			.numerator = 100,
314			.denominator = 2993
315		},
316		.max_exp = 500,
317		/* .max_gain = 0, */
318		.bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
319		.sensitivity = 65536
320	},
321	.regs = {
322		{ ET8EK8_REG_8BIT, 0x1239, 0x64 },
323		{ ET8EK8_REG_8BIT, 0x1238, 0x02 },
324		{ ET8EK8_REG_8BIT, 0x123B, 0x71 },
325		{ ET8EK8_REG_8BIT, 0x123A, 0x07 },
326		{ ET8EK8_REG_8BIT, 0x121B, 0x61 },
327		{ ET8EK8_REG_8BIT, 0x121D, 0x61 },
328		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
329		{ ET8EK8_REG_8BIT, 0x1220, 0xDD },
330		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
331		{ ET8EK8_REG_8BIT, 0x1222, 0x54 },
332		{ ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/  */
333		{ ET8EK8_REG_TERM, 0, 0}
334	}
335};
336
337/* Mode2_16VGA_2592x1968_3.99fps */
338static struct et8ek8_reglist mode2_16vga_2592x1968_3_99fps = {
339/* (without the +1)
340 * SPCK       = 80 MHz
341 * CCP2       = 640 MHz
342 * VCO        = 640 MHz
343 * VCOUNT     = 254 (6096)
344 * HCOUNT     = 137 (3288)
345 * CKREF_DIV  = 2
346 * CKVAR_DIV  = 200
347 * VCO_DIV    = 0
348 * SPCK_DIV   = 7
349 * MRCK_DIV   = 7
350 * LVDSCK_DIV = 0
351 */
352	.type = ET8EK8_REGLIST_MODE,
353	.mode = {
354		.sensor_width = 2592,
355		.sensor_height = 1968,
356		.sensor_window_origin_x = 0,
357		.sensor_window_origin_y = 0,
358		.sensor_window_width = 2592,
359		.sensor_window_height = 1968,
360		.width = 3288,
361		.height = 6096,
362		.window_origin_x = 0,
363		.window_origin_y = 0,
364		.window_width = 2592,
365		.window_height = 1968,
366		.pixel_clock = 80000000,
367		.timeperframe = {
368			.numerator = 100,
369			.denominator = 399
370		},
371		.max_exp = 6092,
372		/* .max_gain = 0, */
373		.bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
374		.sensitivity = 65536
375	},
376	.regs = {
377		{ ET8EK8_REG_8BIT, 0x1239, 0x64 },
378		{ ET8EK8_REG_8BIT, 0x1238, 0x02 },
379		{ ET8EK8_REG_8BIT, 0x123B, 0x70 },
380		{ ET8EK8_REG_8BIT, 0x123A, 0x07 },
381		{ ET8EK8_REG_8BIT, 0x121B, 0x64 },
382		{ ET8EK8_REG_8BIT, 0x121D, 0x64 },
383		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
384		{ ET8EK8_REG_8BIT, 0x1220, 0x89 },
385		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
386		{ ET8EK8_REG_8BIT, 0x1222, 0xFE },
387		{ ET8EK8_REG_TERM, 0, 0}
388	}
389};
390
391/* Mode_648x492_5fps */
392static struct et8ek8_reglist mode_648x492_5fps = {
393/* (without the +1)
394 * SPCK       = 13.3333333333333 MHz
395 * CCP2       = 53.3333333333333 MHz
396 * VCO        = 640 MHz
397 * VCOUNT     = 84 (2016)
398 * HCOUNT     = 221 (5304)
399 * CKREF_DIV  = 2
400 * CKVAR_DIV  = 200
401 * VCO_DIV    = 5
402 * SPCK_DIV   = 7
403 * MRCK_DIV   = 7
404 * LVDSCK_DIV = 1
405 */
406	.type = ET8EK8_REGLIST_MODE,
407	.mode = {
408		.sensor_width = 2592,
409		.sensor_height = 1968,
410		.sensor_window_origin_x = 0,
411		.sensor_window_origin_y = 0,
412		.sensor_window_width = 2592,
413		.sensor_window_height = 1968,
414		.width = 5304,
415		.height = 504,
416		.window_origin_x = 0,
417		.window_origin_y = 0,
418		.window_width = 648,
419		.window_height = 492,
420		.pixel_clock = 13333333,
421		.timeperframe = {
422			.numerator = 100,
423			.denominator = 499
424		},
425		.max_exp = 500,
426		/* .max_gain = 0, */
427		.bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
428		.sensitivity = 65536
429	},
430	.regs = {
431		{ ET8EK8_REG_8BIT, 0x1239, 0x64 },
432		{ ET8EK8_REG_8BIT, 0x1238, 0x02 },
433		{ ET8EK8_REG_8BIT, 0x123B, 0x71 },
434		{ ET8EK8_REG_8BIT, 0x123A, 0x57 },
435		{ ET8EK8_REG_8BIT, 0x121B, 0x61 },
436		{ ET8EK8_REG_8BIT, 0x121D, 0x61 },
437		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
438		{ ET8EK8_REG_8BIT, 0x1220, 0xDD },
439		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
440		{ ET8EK8_REG_8BIT, 0x1222, 0x54 },
441		{ ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/  */
442		{ ET8EK8_REG_TERM, 0, 0}
443	}
444};
445
446/* Mode3_4VGA_1296x984_5fps */
447static struct et8ek8_reglist mode3_4vga_1296x984_5fps = {
448/* (without the +1)
449 * SPCK       = 49.4 MHz
450 * CCP2       = 395.2 MHz
451 * VCO        = 790.4 MHz
452 * VCOUNT     = 250 (6000)
453 * HCOUNT     = 137 (3288)
454 * CKREF_DIV  = 2
455 * CKVAR_DIV  = 247
456 * VCO_DIV    = 1
457 * SPCK_DIV   = 7
458 * MRCK_DIV   = 7
459 * LVDSCK_DIV = 0
460 */
461	.type = ET8EK8_REGLIST_MODE,
462	.mode = {
463		.sensor_width = 2592,
464		.sensor_height = 1968,
465		.sensor_window_origin_x = 0,
466		.sensor_window_origin_y = 0,
467		.sensor_window_width = 2592,
468		.sensor_window_height = 1968,
469		.width = 3288,
470		.height = 3000,
471		.window_origin_x = 0,
472		.window_origin_y = 0,
473		.window_width = 1296,
474		.window_height = 984,
475		.pixel_clock = 49400000,
476		.timeperframe = {
477			.numerator = 100,
478			.denominator = 501
479		},
480		.max_exp = 2996,
481		/* .max_gain = 0, */
482		.bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
483		.sensitivity = 65536
484	},
485	.regs = {
486		{ ET8EK8_REG_8BIT, 0x1239, 0x7B },
487		{ ET8EK8_REG_8BIT, 0x1238, 0x82 },
488		{ ET8EK8_REG_8BIT, 0x123B, 0x70 },
489		{ ET8EK8_REG_8BIT, 0x123A, 0x17 },
490		{ ET8EK8_REG_8BIT, 0x121B, 0x63 },
491		{ ET8EK8_REG_8BIT, 0x121D, 0x63 },
492		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
493		{ ET8EK8_REG_8BIT, 0x1220, 0x89 },
494		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
495		{ ET8EK8_REG_8BIT, 0x1222, 0xFA },
496		{ ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/  */
497		{ ET8EK8_REG_TERM, 0, 0}
498	}
499};
500
501/* Mode_4VGA_1296x984_25fps_DPCM10-8 */
502static struct et8ek8_reglist mode_4vga_1296x984_25fps_dpcm10_8 = {
503/* (without the +1)
504 * SPCK       = 84.2666666666667 MHz
505 * CCP2       = 505.6 MHz
506 * VCO        = 505.6 MHz
507 * VCOUNT     = 88 (2112)
508 * HCOUNT     = 133 (3192)
509 * CKREF_DIV  = 2
510 * CKVAR_DIV  = 158
511 * VCO_DIV    = 0
512 * SPCK_DIV   = 5
513 * MRCK_DIV   = 7
514 * LVDSCK_DIV = 0
515 */
516	.type = ET8EK8_REGLIST_MODE,
517	.mode = {
518		.sensor_width = 2592,
519		.sensor_height = 1968,
520		.sensor_window_origin_x = 0,
521		.sensor_window_origin_y = 0,
522		.sensor_window_width = 2592,
523		.sensor_window_height = 1968,
524		.width = 3192,
525		.height = 1056,
526		.window_origin_x = 0,
527		.window_origin_y = 0,
528		.window_width = 1296,
529		.window_height = 984,
530		.pixel_clock = 84266667,
531		.timeperframe = {
532			.numerator = 100,
533			.denominator = 2500
534		},
535		.max_exp = 1052,
536		/* .max_gain = 0, */
537		.bus_format = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
538		.sensitivity = 65536
539	},
540	.regs = {
541		{ ET8EK8_REG_8BIT, 0x1239, 0x4F },
542		{ ET8EK8_REG_8BIT, 0x1238, 0x02 },
543		{ ET8EK8_REG_8BIT, 0x123B, 0x70 },
544		{ ET8EK8_REG_8BIT, 0x123A, 0x05 },
545		{ ET8EK8_REG_8BIT, 0x121B, 0x63 },
546		{ ET8EK8_REG_8BIT, 0x1220, 0x85 },
547		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
548		{ ET8EK8_REG_8BIT, 0x1222, 0x58 },
549		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
550		{ ET8EK8_REG_8BIT, 0x121D, 0x63 },
551		{ ET8EK8_REG_8BIT, 0x125D, 0x83 },
552		{ ET8EK8_REG_TERM, 0, 0}
553	}
554};
555
556struct et8ek8_meta_reglist meta_reglist = {
557	.version = "V14 03-June-2008",
558	.reglist = {
559		{ .ptr = &mode1_poweron_mode2_16vga_2592x1968_12_07fps },
560		{ .ptr = &mode1_16vga_2592x1968_13_12fps_dpcm10_8 },
561		{ .ptr = &mode3_4vga_1296x984_29_99fps_dpcm10_8 },
562		{ .ptr = &mode4_svga_864x656_29_88fps },
563		{ .ptr = &mode5_vga_648x492_29_93fps },
564		{ .ptr = &mode2_16vga_2592x1968_3_99fps },
565		{ .ptr = &mode_648x492_5fps },
566		{ .ptr = &mode3_4vga_1296x984_5fps },
567		{ .ptr = &mode_4vga_1296x984_25fps_dpcm10_8 },
568		{ .ptr = NULL }
569	}
570};