dw9768.c

  1// SPDX-License-Identifier: GPL-2.0
  2// Copyright (c) 2020 MediaTek Inc.
  3
  4#include <linux/delay.h>
  5#include <linux/i2c.h>
  6#include <linux/module.h>
  7#include <linux/pm_runtime.h>
  8#include <linux/regulator/consumer.h>
  9#include <media/v4l2-async.h>
 10#include <media/v4l2-ctrls.h>
 11#include <media/v4l2-device.h>
 12#include <media/v4l2-fwnode.h>
 13#include <media/v4l2-subdev.h>
 14
 15#define DW9768_NAME				"dw9768"
 16#define DW9768_MAX_FOCUS_POS			(1024 - 1)
 17/*
 18 * This sets the minimum granularity for the focus positions.
 19 * A value of 1 gives maximum accuracy for a desired focus position
 20 */
 21#define DW9768_FOCUS_STEPS			1
 22
 23/*
 24 * Ring control and Power control register
 25 * Bit[1] RING_EN
 26 * 0: Direct mode
 27 * 1: AAC mode (ringing control mode)
 28 * Bit[0] PD
 29 * 0: Normal operation mode
 30 * 1: Power down mode
 31 * DW9768 requires waiting time of Topr after PD reset takes place.
 32 */
 33#define DW9768_RING_PD_CONTROL_REG		0x02
 34#define DW9768_PD_MODE_OFF			0x00
 35#define DW9768_PD_MODE_EN			BIT(0)
 36#define DW9768_AAC_MODE_EN			BIT(1)
 37
 38/*
 39 * DW9768 separates two registers to control the VCM position.
 40 * One for MSB value, another is LSB value.
 41 * DAC_MSB: D[9:8] (ADD: 0x03)
 42 * DAC_LSB: D[7:0] (ADD: 0x04)
 43 * D[9:0] DAC data input: positive output current = D[9:0] / 1023 * 100[mA]
 44 */
 45#define DW9768_MSB_ADDR				0x03
 46#define DW9768_LSB_ADDR				0x04
 47#define DW9768_STATUS_ADDR			0x05
 48
 49/*
 50 * AAC mode control & prescale register
 51 * Bit[7:5] Namely AC[2:0], decide the VCM mode and operation time.
 52 * 001 AAC2 0.48 x Tvib
 53 * 010 AAC3 0.70 x Tvib
 54 * 011 AAC4 0.75 x Tvib
 55 * 101 AAC8 1.13 x Tvib
 56 * Bit[2:0] Namely PRESC[2:0], set the internal clock dividing rate as follow.
 57 * 000 2
 58 * 001 1
 59 * 010 1/2
 60 * 011 1/4
 61 * 100 8
 62 * 101 4
 63 */
 64#define DW9768_AAC_PRESC_REG			0x06
 65#define DW9768_AAC_MODE_SEL_MASK		GENMASK(7, 5)
 66#define DW9768_CLOCK_PRE_SCALE_SEL_MASK		GENMASK(2, 0)
 67
 68/*
 69 * VCM period of vibration register
 70 * Bit[5:0] Defined as VCM rising periodic time (Tvib) together with PRESC[2:0]
 71 * Tvib = (6.3ms + AACT[5:0] * 0.1ms) * Dividing Rate
 72 * Dividing Rate is the internal clock dividing rate that is defined at
 73 * PRESCALE register (ADD: 0x06)
 74 */
 75#define DW9768_AAC_TIME_REG			0x07
 76
 77/*
 78 * DW9768 requires waiting time (delay time) of t_OPR after power-up,
 79 * or in the case of PD reset taking place.
 80 */
 81#define DW9768_T_OPR_US				1000
 82#define DW9768_TVIB_MS_BASE10			(64 - 1)
 83#define DW9768_AAC_MODE_DEFAULT			2
 84#define DW9768_AAC_TIME_DEFAULT			0x20
 85#define DW9768_CLOCK_PRE_SCALE_DEFAULT		1
 86
 87/*
 88 * This acts as the minimum granularity of lens movement.
 89 * Keep this value power of 2, so the control steps can be
 90 * uniformly adjusted for gradual lens movement, with desired
 91 * number of control steps.
 92 */
 93#define DW9768_MOVE_STEPS			16
 94
 95static const char * const dw9768_supply_names[] = {
 96	"vin",	/* Digital I/O power */
 97	"vdd",	/* Digital core power */
 98};
 99
100/* dw9768 device structure */
101struct dw9768 {
102	struct regulator_bulk_data supplies[ARRAY_SIZE(dw9768_supply_names)];
103	struct v4l2_ctrl_handler ctrls;
104	struct v4l2_ctrl *focus;
105	struct v4l2_subdev sd;
106
107	u32 aac_mode;
108	u32 aac_timing;
109	u32 clock_presc;
110	u32 move_delay_us;
111};
112
113static inline struct dw9768 *sd_to_dw9768(struct v4l2_subdev *subdev)
114{
115	return container_of(subdev, struct dw9768, sd);
116}
117
118struct dw9768_aac_mode_ot_multi {
119	u32 aac_mode_enum;
120	u32 ot_multi_base100;
121};
122
123struct dw9768_clk_presc_dividing_rate {
124	u32 clk_presc_enum;
125	u32 dividing_rate_base100;
126};
127
128static const struct dw9768_aac_mode_ot_multi aac_mode_ot_multi[] = {
129	{1,  48},
130	{2,  70},
131	{3,  75},
132	{5, 113},
133};
134
135static const struct dw9768_clk_presc_dividing_rate presc_dividing_rate[] = {
136	{0, 200},
137	{1, 100},
138	{2,  50},
139	{3,  25},
140	{4, 800},
141	{5, 400},
142};
143
144static u32 dw9768_find_ot_multi(u32 aac_mode_param)
145{
146	u32 cur_ot_multi_base100 = 70;
147	unsigned int i;
148
149	for (i = 0; i < ARRAY_SIZE(aac_mode_ot_multi); i++) {
150		if (aac_mode_ot_multi[i].aac_mode_enum == aac_mode_param) {
151			cur_ot_multi_base100 =
152				aac_mode_ot_multi[i].ot_multi_base100;
153		}
154	}
155
156	return cur_ot_multi_base100;
157}
158
159static u32 dw9768_find_dividing_rate(u32 presc_param)
160{
161	u32 cur_clk_dividing_rate_base100 = 100;
162	unsigned int i;
163
164	for (i = 0; i < ARRAY_SIZE(presc_dividing_rate); i++) {
165		if (presc_dividing_rate[i].clk_presc_enum == presc_param) {
166			cur_clk_dividing_rate_base100 =
167				presc_dividing_rate[i].dividing_rate_base100;
168		}
169	}
170
171	return cur_clk_dividing_rate_base100;
172}
173
174/*
175 * DW9768_AAC_PRESC_REG & DW9768_AAC_TIME_REG determine VCM operation time.
176 * For current VCM mode: AAC3, Operation Time would be 0.70 x Tvib.
177 * Tvib = (6.3ms + AACT[5:0] * 0.1MS) * Dividing Rate.
178 * Below is calculation of the operation delay for each step.
179 */
180static inline u32 dw9768_cal_move_delay(u32 aac_mode_param, u32 presc_param,
181					u32 aac_timing_param)
182{
183	u32 Tvib_us;
184	u32 ot_multi_base100;
185	u32 clk_dividing_rate_base100;
186
187	ot_multi_base100 = dw9768_find_ot_multi(aac_mode_param);
188
189	clk_dividing_rate_base100 = dw9768_find_dividing_rate(presc_param);
190
191	Tvib_us = (DW9768_TVIB_MS_BASE10 + aac_timing_param) *
192		  clk_dividing_rate_base100;
193
194	return Tvib_us * ot_multi_base100 / 100;
195}
196
197static int dw9768_mod_reg(struct dw9768 *dw9768, u8 reg, u8 mask, u8 val)
198{
199	struct i2c_client *client = v4l2_get_subdevdata(&dw9768->sd);
200	int ret;
201
202	ret = i2c_smbus_read_byte_data(client, reg);
203	if (ret < 0)
204		return ret;
205
206	val = ((unsigned char)ret & ~mask) | (val & mask);
207
208	return i2c_smbus_write_byte_data(client, reg, val);
209}
210
211static int dw9768_set_dac(struct dw9768 *dw9768, u16 val)
212{
213	struct i2c_client *client = v4l2_get_subdevdata(&dw9768->sd);
214
215	/* Write VCM position to registers */
216	return i2c_smbus_write_word_swapped(client, DW9768_MSB_ADDR, val);
217}
218
219static int dw9768_init(struct dw9768 *dw9768)
220{
221	struct i2c_client *client = v4l2_get_subdevdata(&dw9768->sd);
222	int ret, val;
223
224	/* Reset DW9768_RING_PD_CONTROL_REG to default status 0x00 */
225	ret = i2c_smbus_write_byte_data(client, DW9768_RING_PD_CONTROL_REG,
226					DW9768_PD_MODE_OFF);
227	if (ret < 0)
228		return ret;
229
230	/*
231	 * DW9769 requires waiting delay time of t_OPR
232	 * after PD reset takes place.
233	 */
234	usleep_range(DW9768_T_OPR_US, DW9768_T_OPR_US + 100);
235
236	/* Set DW9768_RING_PD_CONTROL_REG to DW9768_AAC_MODE_EN(0x01) */
237	ret = i2c_smbus_write_byte_data(client, DW9768_RING_PD_CONTROL_REG,
238					DW9768_AAC_MODE_EN);
239	if (ret < 0)
240		return ret;
241
242	/* Set AAC mode */
243	ret = dw9768_mod_reg(dw9768, DW9768_AAC_PRESC_REG,
244			     DW9768_AAC_MODE_SEL_MASK,
245			     dw9768->aac_mode << 5);
246	if (ret < 0)
247		return ret;
248
249	/* Set clock presc */
250	if (dw9768->clock_presc != DW9768_CLOCK_PRE_SCALE_DEFAULT) {
251		ret = dw9768_mod_reg(dw9768, DW9768_AAC_PRESC_REG,
252				     DW9768_CLOCK_PRE_SCALE_SEL_MASK,
253				     dw9768->clock_presc);
254		if (ret < 0)
255			return ret;
256	}
257
258	/* Set AAC Timing */
259	if (dw9768->aac_timing != DW9768_AAC_TIME_DEFAULT) {
260		ret = i2c_smbus_write_byte_data(client, DW9768_AAC_TIME_REG,
261						dw9768->aac_timing);
262		if (ret < 0)
263			return ret;
264	}
265
266	for (val = dw9768->focus->val % DW9768_MOVE_STEPS;
267	     val <= dw9768->focus->val;
268	     val += DW9768_MOVE_STEPS) {
269		ret = dw9768_set_dac(dw9768, val);
270		if (ret) {
271			dev_err(&client->dev, "I2C failure: %d", ret);
272			return ret;
273		}
274		usleep_range(dw9768->move_delay_us,
275			     dw9768->move_delay_us + 1000);
276	}
277
278	return 0;
279}
280
281static int dw9768_release(struct dw9768 *dw9768)
282{
283	struct i2c_client *client = v4l2_get_subdevdata(&dw9768->sd);
284	int ret, val;
285
286	val = round_down(dw9768->focus->val, DW9768_MOVE_STEPS);
287	for ( ; val >= 0; val -= DW9768_MOVE_STEPS) {
288		ret = dw9768_set_dac(dw9768, val);
289		if (ret) {
290			dev_err(&client->dev, "I2C write fail: %d", ret);
291			return ret;
292		}
293		usleep_range(dw9768->move_delay_us,
294			     dw9768->move_delay_us + 1000);
295	}
296
297	ret = i2c_smbus_write_byte_data(client, DW9768_RING_PD_CONTROL_REG,
298					DW9768_PD_MODE_EN);
299	if (ret < 0)
300		return ret;
301
302	/*
303	 * DW9769 requires waiting delay time of t_OPR
304	 * after PD reset takes place.
305	 */
306	usleep_range(DW9768_T_OPR_US, DW9768_T_OPR_US + 100);
307
308	return 0;
309}
310
311static int dw9768_runtime_suspend(struct device *dev)
312{
313	struct v4l2_subdev *sd = dev_get_drvdata(dev);
314	struct dw9768 *dw9768 = sd_to_dw9768(sd);
315
316	dw9768_release(dw9768);
317	regulator_bulk_disable(ARRAY_SIZE(dw9768_supply_names),
318			       dw9768->supplies);
319
320	return 0;
321}
322
323static int dw9768_runtime_resume(struct device *dev)
324{
325	struct v4l2_subdev *sd = dev_get_drvdata(dev);
326	struct dw9768 *dw9768 = sd_to_dw9768(sd);
327	int ret;
328
329	ret = regulator_bulk_enable(ARRAY_SIZE(dw9768_supply_names),
330				    dw9768->supplies);
331	if (ret < 0) {
332		dev_err(dev, "failed to enable regulators\n");
333		return ret;
334	}
335
336	/*
337	 * The datasheet refers to t_OPR that needs to be waited before sending
338	 * I2C commands after power-up.
339	 */
340	usleep_range(DW9768_T_OPR_US, DW9768_T_OPR_US + 100);
341
342	ret = dw9768_init(dw9768);
343	if (ret < 0)
344		goto disable_regulator;
345
346	return 0;
347
348disable_regulator:
349	regulator_bulk_disable(ARRAY_SIZE(dw9768_supply_names),
350			       dw9768->supplies);
351
352	return ret;
353}
354
355static int dw9768_set_ctrl(struct v4l2_ctrl *ctrl)
356{
357	struct dw9768 *dw9768 = container_of(ctrl->handler,
358					     struct dw9768, ctrls);
359
360	if (ctrl->id == V4L2_CID_FOCUS_ABSOLUTE)
361		return dw9768_set_dac(dw9768, ctrl->val);
362
363	return 0;
364}
365
366static const struct v4l2_ctrl_ops dw9768_ctrl_ops = {
367	.s_ctrl = dw9768_set_ctrl,
368};
369
370static int dw9768_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
371{
372	return pm_runtime_resume_and_get(sd->dev);
373}
374
375static int dw9768_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
376{
377	pm_runtime_put_autosuspend(sd->dev);
378
379	return 0;
380}
381
382static const struct v4l2_subdev_internal_ops dw9768_int_ops = {
383	.open = dw9768_open,
384	.close = dw9768_close,
385};
386
387static const struct v4l2_subdev_ops dw9768_ops = { };
388
389static int dw9768_init_controls(struct dw9768 *dw9768)
390{
391	struct v4l2_ctrl_handler *hdl = &dw9768->ctrls;
392	const struct v4l2_ctrl_ops *ops = &dw9768_ctrl_ops;
393
394	v4l2_ctrl_handler_init(hdl, 1);
395
396	dw9768->focus = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FOCUS_ABSOLUTE, 0,
397					  DW9768_MAX_FOCUS_POS,
398					  DW9768_FOCUS_STEPS, 0);
399
400	if (hdl->error)
401		return hdl->error;
402
403	dw9768->sd.ctrl_handler = hdl;
404
405	return 0;
406}
407
408static int dw9768_probe(struct i2c_client *client)
409{
410	struct device *dev = &client->dev;
411	struct dw9768 *dw9768;
412	bool full_power;
413	unsigned int i;
414	int ret;
415
416	dw9768 = devm_kzalloc(dev, sizeof(*dw9768), GFP_KERNEL);
417	if (!dw9768)
418		return -ENOMEM;
419
420	/* Initialize subdev */
421	v4l2_i2c_subdev_init(&dw9768->sd, client, &dw9768_ops);
422
423	dw9768->aac_mode = DW9768_AAC_MODE_DEFAULT;
424	dw9768->aac_timing = DW9768_AAC_TIME_DEFAULT;
425	dw9768->clock_presc = DW9768_CLOCK_PRE_SCALE_DEFAULT;
426
427	/* Optional indication of AAC mode select */
428	fwnode_property_read_u32(dev_fwnode(dev), "dongwoon,aac-mode",
429				 &dw9768->aac_mode);
430
431	/* Optional indication of clock pre-scale select */
432	fwnode_property_read_u32(dev_fwnode(dev), "dongwoon,clock-presc",
433				 &dw9768->clock_presc);
434
435	/* Optional indication of AAC Timing */
436	fwnode_property_read_u32(dev_fwnode(dev), "dongwoon,aac-timing",
437				 &dw9768->aac_timing);
438
439	dw9768->move_delay_us = dw9768_cal_move_delay(dw9768->aac_mode,
440						      dw9768->clock_presc,
441						      dw9768->aac_timing);
442
443	for (i = 0; i < ARRAY_SIZE(dw9768_supply_names); i++)
444		dw9768->supplies[i].supply = dw9768_supply_names[i];
445
446	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dw9768_supply_names),
447				      dw9768->supplies);
448	if (ret) {
449		dev_err(dev, "failed to get regulators\n");
450		return ret;
451	}
452
453	/* Initialize controls */
454	ret = dw9768_init_controls(dw9768);
455	if (ret)
456		goto err_free_handler;
457
458	/* Initialize subdev */
459	dw9768->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
460	dw9768->sd.internal_ops = &dw9768_int_ops;
461
462	ret = media_entity_pads_init(&dw9768->sd.entity, 0, NULL);
463	if (ret < 0)
464		goto err_free_handler;
465
466	dw9768->sd.entity.function = MEDIA_ENT_F_LENS;
467
468	/*
469	 * Figure out whether we're going to power up the device here. Generally
470	 * this is done if CONFIG_PM is disabled in a DT system or the device is
471	 * to be powered on in an ACPI system. Similarly for power off in
472	 * remove.
473	 */
474	full_power = (is_acpi_node(dev_fwnode(dev)) &&
475		      acpi_dev_state_d0(dev)) ||
476		     (is_of_node(dev_fwnode(dev)) && !IS_ENABLED(CONFIG_PM));
477	if (full_power) {
478		ret = dw9768_runtime_resume(dev);
479		if (ret < 0) {
480			dev_err(dev, "failed to power on: %d\n", ret);
481			goto err_clean_entity;
482		}
483		pm_runtime_set_active(dev);
484	}
485
486	pm_runtime_enable(dev);
487	ret = v4l2_async_register_subdev(&dw9768->sd);
488	if (ret < 0) {
489		dev_err(dev, "failed to register V4L2 subdev: %d", ret);
490		goto err_power_off;
491	}
492
493	pm_runtime_set_autosuspend_delay(dev, 1000);
494	pm_runtime_use_autosuspend(dev);
495	pm_runtime_idle(dev);
496
497	return 0;
498
499err_power_off:
500	pm_runtime_disable(dev);
501	if (full_power) {
502		dw9768_runtime_suspend(dev);
503		pm_runtime_set_suspended(dev);
504	}
505err_clean_entity:
506	media_entity_cleanup(&dw9768->sd.entity);
507err_free_handler:
508	v4l2_ctrl_handler_free(&dw9768->ctrls);
509
510	return ret;
511}
512
513static void dw9768_remove(struct i2c_client *client)
514{
515	struct v4l2_subdev *sd = i2c_get_clientdata(client);
516	struct dw9768 *dw9768 = sd_to_dw9768(sd);
517	struct device *dev = &client->dev;
518
519	v4l2_async_unregister_subdev(&dw9768->sd);
520	v4l2_ctrl_handler_free(&dw9768->ctrls);
521	media_entity_cleanup(&dw9768->sd.entity);
522	pm_runtime_disable(dev);
523	if ((is_acpi_node(dev_fwnode(dev)) && acpi_dev_state_d0(dev)) ||
524	    (is_of_node(dev_fwnode(dev)) && !IS_ENABLED(CONFIG_PM))) {
525		dw9768_runtime_suspend(dev);
526		pm_runtime_set_suspended(dev);
527	}
528}
529
530static const struct of_device_id dw9768_of_table[] = {
531	{ .compatible = "dongwoon,dw9768" },
532	{ .compatible = "giantec,gt9769" },
533	{}
534};
535MODULE_DEVICE_TABLE(of, dw9768_of_table);
536
537static const struct dev_pm_ops dw9768_pm_ops = {
538	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
539				pm_runtime_force_resume)
540	SET_RUNTIME_PM_OPS(dw9768_runtime_suspend, dw9768_runtime_resume, NULL)
541};
542
543static struct i2c_driver dw9768_i2c_driver = {
544	.driver = {
545		.name = DW9768_NAME,
546		.pm = &dw9768_pm_ops,
547		.of_match_table = dw9768_of_table,
548	},
549	.probe = dw9768_probe,
550	.remove = dw9768_remove,
551};
552module_i2c_driver(dw9768_i2c_driver);
553
554MODULE_AUTHOR("Dongchun Zhu <dongchun.zhu@mediatek.com>");
555MODULE_DESCRIPTION("DW9768 VCM driver");
556MODULE_LICENSE("GPL v2");