ds90ub953.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2
  3#ifndef __MEDIA_I2C_DS90UB953_H__
  4#define __MEDIA_I2C_DS90UB953_H__
  5
  6#include <linux/types.h>
  7
  8#define UB953_REG_RESET_CTL			0x01
  9#define UB953_REG_RESET_CTL_DIGITAL_RESET_1	BIT(1)
 10#define UB953_REG_RESET_CTL_DIGITAL_RESET_0	BIT(0)
 11
 12#define UB953_REG_GENERAL_CFG			0x02
 13#define UB953_REG_GENERAL_CFG_CONT_CLK		BIT(6)
 14#define UB953_REG_GENERAL_CFG_CSI_LANE_SEL_SHIFT	4
 15#define UB953_REG_GENERAL_CFG_CSI_LANE_SEL_MASK	GENMASK(5, 4)
 16#define UB953_REG_GENERAL_CFG_CRC_TX_GEN_ENABLE	BIT(1)
 17#define UB953_REG_GENERAL_CFG_I2C_STRAP_MODE	BIT(0)
 18
 19#define UB953_REG_MODE_SEL			0x03
 20#define UB953_REG_MODE_SEL_MODE_DONE		BIT(3)
 21#define UB953_REG_MODE_SEL_MODE_OVERRIDE	BIT(4)
 22#define UB953_REG_MODE_SEL_MODE_MASK		GENMASK(2, 0)
 23
 24#define UB953_REG_CLKOUT_CTRL0			0x06
 25#define UB953_REG_CLKOUT_CTRL1			0x07
 26
 27#define UB953_REG_I2C_CONTROL2			0x0a
 28#define UB953_REG_I2C_CONTROL2_SDA_OUTPUT_SETUP_SHIFT	4
 29#define UB953_REG_I2C_CONTROL2_BUS_SPEEDUP	BIT(1)
 30
 31#define UB953_REG_SCL_HIGH_TIME			0x0b
 32#define UB953_REG_SCL_LOW_TIME			0x0c
 33
 34#define UB953_REG_LOCAL_GPIO_DATA		0x0d
 35#define UB953_REG_LOCAL_GPIO_DATA_GPIO_RMTEN(n)		BIT(4 + (n))
 36#define UB953_REG_LOCAL_GPIO_DATA_GPIO_OUT_SRC(n)	BIT(0 + (n))
 37
 38#define UB953_REG_GPIO_INPUT_CTRL		0x0e
 39#define UB953_REG_GPIO_INPUT_CTRL_OUT_EN(n)	BIT(4 + (n))
 40#define UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(n)	BIT(0 + (n))
 41
 42#define UB953_REG_BC_CTRL			0x49
 43#define UB953_REG_BC_CTRL_CRC_ERR_CLR		BIT(3)
 44
 45#define UB953_REG_REV_MASK_ID			0x50
 46#define UB953_REG_GENERAL_STATUS		0x52
 47
 48#define UB953_REG_GPIO_PIN_STS			0x53
 49#define UB953_REG_GPIO_PIN_STS_GPIO_STS(n)	BIT(0 + (n))
 50
 51#define UB953_REG_BIST_ERR_CNT			0x54
 52#define UB953_REG_CRC_ERR_CNT1			0x55
 53#define UB953_REG_CRC_ERR_CNT2			0x56
 54
 55#define UB953_REG_CSI_ERR_CNT			0x5c
 56#define UB953_REG_CSI_ERR_STATUS		0x5d
 57#define UB953_REG_CSI_ERR_DLANE01		0x5e
 58#define UB953_REG_CSI_ERR_DLANE23		0x5f
 59#define UB953_REG_CSI_ERR_CLK_LANE		0x60
 60#define UB953_REG_CSI_PKT_HDR_VC_ID		0x61
 61#define UB953_REG_PKT_HDR_WC_LSB		0x62
 62#define UB953_REG_PKT_HDR_WC_MSB		0x63
 63#define UB953_REG_CSI_ECC			0x64
 64
 65#define UB953_REG_IND_ACC_CTL			0xb0
 66#define UB953_REG_IND_ACC_ADDR			0xb1
 67#define UB953_REG_IND_ACC_DATA			0xb2
 68
 69#define UB953_REG_FPD3_RX_ID(n)			(0xf0 + (n))
 70#define UB953_REG_FPD3_RX_ID_LEN		6
 71
 72/* Indirect register blocks */
 73#define UB953_IND_TARGET_PAT_GEN		0x00
 74#define UB953_IND_TARGET_ANALOG			0x01
 75#define UB953_IND_TARGET_DIE_ID			0x02
 76
 77#define UB953_IND_PGEN_CTL			0x01
 78#define UB953_IND_PGEN_CTL_PGEN_ENABLE		BIT(0)
 79#define UB953_IND_PGEN_CFG			0x02
 80#define UB953_IND_PGEN_CSI_DI			0x03
 81#define UB953_IND_PGEN_LINE_SIZE1		0x04
 82#define UB953_IND_PGEN_LINE_SIZE0		0x05
 83#define UB953_IND_PGEN_BAR_SIZE1		0x06
 84#define UB953_IND_PGEN_BAR_SIZE0		0x07
 85#define UB953_IND_PGEN_ACT_LPF1			0x08
 86#define UB953_IND_PGEN_ACT_LPF0			0x09
 87#define UB953_IND_PGEN_TOT_LPF1			0x0a
 88#define UB953_IND_PGEN_TOT_LPF0			0x0b
 89#define UB953_IND_PGEN_LINE_PD1			0x0c
 90#define UB953_IND_PGEN_LINE_PD0			0x0d
 91#define UB953_IND_PGEN_VBP			0x0e
 92#define UB953_IND_PGEN_VFP			0x0f
 93#define UB953_IND_PGEN_COLOR(n)			(0x10 + (n)) /* n <= 15 */
 94
 95#define UB953_IND_ANA_TEMP_DYNAMIC_CFG		0x4b
 96#define UB953_IND_ANA_TEMP_DYNAMIC_CFG_OV	BIT(5)
 97#define UB953_IND_ANA_TEMP_STATIC_CFG		0x4c
 98#define UB953_IND_ANA_TEMP_STATIC_CFG_MASK	GENMASK(6, 4)
 99
100/* UB971 Registers */
101
102#define UB971_ENH_BC_CHK			0x4b
103
104#endif /* __MEDIA_I2C_DS90UB953_H__ */